1 /*- 2 * Copyright (c) 1997-2000 Nicolas Souchu 3 * Copyright (c) 2001 Alcove - Nicolas Souchu 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_ppc.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/interrupt.h> 39 #include <sys/module.h> 40 #include <sys/malloc.h> 41 #include <sys/mutex.h> 42 #include <sys/proc.h> 43 44 #include <machine/bus.h> 45 #include <machine/resource.h> 46 #include <sys/rman.h> 47 48 #ifdef __i386__ 49 #include <vm/vm.h> 50 #include <vm/pmap.h> 51 #include <machine/vmparam.h> 52 #endif 53 54 #include <dev/ppbus/ppbconf.h> 55 #include <dev/ppbus/ppb_msq.h> 56 57 #include <dev/ppc/ppcvar.h> 58 #include <dev/ppc/ppcreg.h> 59 60 #include "ppbus_if.h" 61 62 static void ppcintr(void *arg); 63 64 #define IO_LPTSIZE_EXTENDED 8 /* "Extended" LPT controllers */ 65 #define IO_LPTSIZE_NORMAL 4 /* "Normal" LPT controllers */ 66 67 #define LOG_PPC(function, ppc, string) \ 68 if (bootverbose) printf("%s: %s\n", function, string) 69 70 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev)) 71 72 /* 73 * We use critical enter/exit for the simple config locking needed to 74 * detect the devices. We just want to make sure that both of our writes 75 * happen without someone else also writing to those config registers. Since 76 * we just do this at startup, Giant keeps multiple threads from executing, 77 * and critical_enter() then is all that's needed to keep us from being preempted 78 * during the critical sequences with the hardware. 79 * 80 * Note: this doesn't prevent multiple threads from putting the chips into 81 * config mode, but since we only do that to detect the type at startup the 82 * extra overhead isn't needed since Giant protects us from multiple entry 83 * and no other code changes these registers. 84 */ 85 #define PPC_CONFIG_LOCK(ppc) critical_enter() 86 #define PPC_CONFIG_UNLOCK(ppc) critical_exit() 87 88 devclass_t ppc_devclass; 89 const char ppc_driver_name[] = "ppc"; 90 91 static char *ppc_models[] = { 92 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306", 93 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334", 94 "SMC FDC37C935", "PC87303", 0 95 }; 96 97 /* list of available modes */ 98 static char *ppc_avms[] = { 99 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only", 100 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only", 101 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP", 102 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0 103 }; 104 105 /* list of current executing modes 106 * Note that few modes do not actually exist. 107 */ 108 static char *ppc_modes[] = { 109 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP", 110 "EPP", "EPP", "EPP", "ECP", 111 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP", 112 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0 113 }; 114 115 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 }; 116 117 #ifdef __i386__ 118 /* 119 * BIOS printer list - used by BIOS probe. 120 */ 121 #define BIOS_PPC_PORTS 0x408 122 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS) 123 #define BIOS_MAX_PPC 4 124 #endif 125 126 /* 127 * ppc_ecp_sync() XXX 128 */ 129 int 130 ppc_ecp_sync(device_t dev) 131 { 132 int i, r; 133 struct ppc_data *ppc = DEVTOSOFTC(dev); 134 135 PPC_ASSERT_LOCKED(ppc); 136 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP)) 137 return 0; 138 139 r = r_ecr(ppc); 140 if ((r & 0xe0) != PPC_ECR_EPP) 141 return 0; 142 143 for (i = 0; i < 100; i++) { 144 r = r_ecr(ppc); 145 if (r & 0x1) 146 return 0; 147 DELAY(100); 148 } 149 150 device_printf(dev, "ECP sync failed as data still present in FIFO.\n"); 151 152 return 0; 153 } 154 155 /* 156 * ppc_detect_fifo() 157 * 158 * Detect parallel port FIFO 159 */ 160 static int 161 ppc_detect_fifo(struct ppc_data *ppc) 162 { 163 char ecr_sav; 164 char ctr_sav, ctr, cc; 165 short i; 166 167 /* save registers */ 168 ecr_sav = r_ecr(ppc); 169 ctr_sav = r_ctr(ppc); 170 171 /* enter ECP configuration mode, no interrupt, no DMA */ 172 w_ecr(ppc, 0xf4); 173 174 /* read PWord size - transfers in FIFO mode must be PWord aligned */ 175 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK); 176 177 /* XXX 16 and 32 bits implementations not supported */ 178 if (ppc->ppc_pword != PPC_PWORD_8) { 179 LOG_PPC(__func__, ppc, "PWord not supported"); 180 goto error; 181 } 182 183 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */ 184 ctr = r_ctr(ppc); 185 w_ctr(ppc, ctr | PCD); /* set direction to 1 */ 186 187 /* enter ECP test mode, no interrupt, no DMA */ 188 w_ecr(ppc, 0xd4); 189 190 /* flush the FIFO */ 191 for (i=0; i<1024; i++) { 192 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 193 break; 194 cc = r_fifo(ppc); 195 } 196 197 if (i >= 1024) { 198 LOG_PPC(__func__, ppc, "can't flush FIFO"); 199 goto error; 200 } 201 202 /* enable interrupts, no DMA */ 203 w_ecr(ppc, 0xd0); 204 205 /* determine readIntrThreshold 206 * fill the FIFO until serviceIntr is set 207 */ 208 for (i=0; i<1024; i++) { 209 w_fifo(ppc, (char)i); 210 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) { 211 /* readThreshold reached */ 212 ppc->ppc_rthr = i+1; 213 } 214 if (r_ecr(ppc) & PPC_FIFO_FULL) { 215 ppc->ppc_fifo = i+1; 216 break; 217 } 218 } 219 220 if (i >= 1024) { 221 LOG_PPC(__func__, ppc, "can't fill FIFO"); 222 goto error; 223 } 224 225 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */ 226 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */ 227 w_ecr(ppc, 0xd0); /* enable interrupts */ 228 229 /* determine writeIntrThreshold 230 * empty the FIFO until serviceIntr is set 231 */ 232 for (i=ppc->ppc_fifo; i>0; i--) { 233 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) { 234 LOG_PPC(__func__, ppc, "invalid data in FIFO"); 235 goto error; 236 } 237 if (r_ecr(ppc) & PPC_SERVICE_INTR) { 238 /* writeIntrThreshold reached */ 239 ppc->ppc_wthr = ppc->ppc_fifo - i+1; 240 } 241 /* if FIFO empty before the last byte, error */ 242 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) { 243 LOG_PPC(__func__, ppc, "data lost in FIFO"); 244 goto error; 245 } 246 } 247 248 /* FIFO must be empty after the last byte */ 249 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 250 LOG_PPC(__func__, ppc, "can't empty the FIFO"); 251 goto error; 252 } 253 254 w_ctr(ppc, ctr_sav); 255 w_ecr(ppc, ecr_sav); 256 257 return (0); 258 259 error: 260 w_ctr(ppc, ctr_sav); 261 w_ecr(ppc, ecr_sav); 262 263 return (EINVAL); 264 } 265 266 static int 267 ppc_detect_port(struct ppc_data *ppc) 268 { 269 270 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */ 271 w_dtr(ppc, 0xaa); 272 if (r_dtr(ppc) != 0xaa) 273 return (0); 274 275 return (1); 276 } 277 278 /* 279 * EPP timeout, according to the PC87332 manual 280 * Semantics of clearing EPP timeout bit. 281 * PC87332 - reading SPP_STR does it... 282 * SMC - write 1 to EPP timeout bit XXX 283 * Others - (?) write 0 to EPP timeout bit 284 */ 285 static void 286 ppc_reset_epp_timeout(struct ppc_data *ppc) 287 { 288 char r; 289 290 r = r_str(ppc); 291 w_str(ppc, r | 0x1); 292 w_str(ppc, r & 0xfe); 293 294 return; 295 } 296 297 static int 298 ppc_check_epp_timeout(struct ppc_data *ppc) 299 { 300 ppc_reset_epp_timeout(ppc); 301 302 return (!(r_str(ppc) & TIMEOUT)); 303 } 304 305 /* 306 * Configure current operating mode 307 */ 308 static int 309 ppc_generic_setmode(struct ppc_data *ppc, int mode) 310 { 311 u_char ecr = 0; 312 313 /* check if mode is available */ 314 if (mode && !(ppc->ppc_avm & mode)) 315 return (EINVAL); 316 317 /* if ECP mode, configure ecr register */ 318 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { 319 /* return to byte mode (keeping direction bit), 320 * no interrupt, no DMA to be able to change to 321 * ECP 322 */ 323 w_ecr(ppc, PPC_ECR_RESET); 324 ecr = PPC_DISABLE_INTR; 325 326 if (mode & PPB_EPP) 327 return (EINVAL); 328 else if (mode & PPB_ECP) 329 /* select ECP mode */ 330 ecr |= PPC_ECR_ECP; 331 else if (mode & PPB_PS2) 332 /* select PS2 mode with ECP */ 333 ecr |= PPC_ECR_PS2; 334 else 335 /* select COMPATIBLE/NIBBLE mode */ 336 ecr |= PPC_ECR_STD; 337 338 w_ecr(ppc, ecr); 339 } 340 341 ppc->ppc_mode = mode; 342 343 return (0); 344 } 345 346 /* 347 * The ppc driver is free to choose options like FIFO or DMA 348 * if ECP mode is available. 349 * 350 * The 'RAW' option allows the upper drivers to force the ppc mode 351 * even with FIFO, DMA available. 352 */ 353 static int 354 ppc_smclike_setmode(struct ppc_data *ppc, int mode) 355 { 356 u_char ecr = 0; 357 358 /* check if mode is available */ 359 if (mode && !(ppc->ppc_avm & mode)) 360 return (EINVAL); 361 362 /* if ECP mode, configure ecr register */ 363 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { 364 /* return to byte mode (keeping direction bit), 365 * no interrupt, no DMA to be able to change to 366 * ECP or EPP mode 367 */ 368 w_ecr(ppc, PPC_ECR_RESET); 369 ecr = PPC_DISABLE_INTR; 370 371 if (mode & PPB_EPP) 372 /* select EPP mode */ 373 ecr |= PPC_ECR_EPP; 374 else if (mode & PPB_ECP) 375 /* select ECP mode */ 376 ecr |= PPC_ECR_ECP; 377 else if (mode & PPB_PS2) 378 /* select PS2 mode with ECP */ 379 ecr |= PPC_ECR_PS2; 380 else 381 /* select COMPATIBLE/NIBBLE mode */ 382 ecr |= PPC_ECR_STD; 383 384 w_ecr(ppc, ecr); 385 } 386 387 ppc->ppc_mode = mode; 388 389 return (0); 390 } 391 392 #ifdef PPC_PROBE_CHIPSET 393 /* 394 * ppc_pc873xx_detect 395 * 396 * Probe for a Natsemi PC873xx-family part. 397 * 398 * References in this function are to the National Semiconductor 399 * PC87332 datasheet TL/C/11930, May 1995 revision. 400 */ 401 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0}; 402 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0}; 403 static int pc873xx_irqtab[] = {5, 7, 5, 0}; 404 405 static int pc873xx_regstab[] = { 406 PC873_FER, PC873_FAR, PC873_PTR, 407 PC873_FCR, PC873_PCR, PC873_PMC, 408 PC873_TUP, PC873_SID, PC873_PNP0, 409 PC873_PNP1, PC873_LPTBA, -1 410 }; 411 412 static char *pc873xx_rnametab[] = { 413 "FER", "FAR", "PTR", "FCR", "PCR", 414 "PMC", "TUP", "SID", "PNP0", "PNP1", 415 "LPTBA", NULL 416 }; 417 418 static int 419 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */ 420 { 421 static int index = 0; 422 int idport, irq; 423 int ptr, pcr, val, i; 424 425 while ((idport = pc873xx_basetab[index++])) { 426 427 /* XXX should check first to see if this location is already claimed */ 428 429 /* 430 * Pull the 873xx through the power-on ID cycle (2.2,1.). 431 * We can't use this to locate the chip as it may already have 432 * been used by the BIOS. 433 */ 434 (void)inb(idport); (void)inb(idport); 435 (void)inb(idport); (void)inb(idport); 436 437 /* 438 * Read the SID byte. Possible values are : 439 * 440 * 01010xxx PC87334 441 * 0001xxxx PC87332 442 * 01110xxx PC87306 443 * 00110xxx PC87303 444 */ 445 outb(idport, PC873_SID); 446 val = inb(idport + 1); 447 if ((val & 0xf0) == 0x10) { 448 ppc->ppc_model = NS_PC87332; 449 } else if ((val & 0xf8) == 0x70) { 450 ppc->ppc_model = NS_PC87306; 451 } else if ((val & 0xf8) == 0x50) { 452 ppc->ppc_model = NS_PC87334; 453 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the 454 documentation, but probing 455 yielded 0x40... */ 456 ppc->ppc_model = NS_PC87303; 457 } else { 458 if (bootverbose && (val != 0xff)) 459 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val); 460 continue ; /* not recognised */ 461 } 462 463 /* print registers */ 464 if (bootverbose) { 465 printf("PC873xx"); 466 for (i=0; pc873xx_regstab[i] != -1; i++) { 467 outb(idport, pc873xx_regstab[i]); 468 printf(" %s=0x%x", pc873xx_rnametab[i], 469 inb(idport + 1) & 0xff); 470 } 471 printf("\n"); 472 } 473 474 /* 475 * We think we have one. Is it enabled and where we want it to be? 476 */ 477 outb(idport, PC873_FER); 478 val = inb(idport + 1); 479 if (!(val & PC873_PPENABLE)) { 480 if (bootverbose) 481 printf("PC873xx parallel port disabled\n"); 482 continue; 483 } 484 outb(idport, PC873_FAR); 485 val = inb(idport + 1); 486 /* XXX we should create a driver instance for every port found */ 487 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) { 488 489 /* First try to change the port address to that requested... */ 490 491 switch (ppc->ppc_base) { 492 case 0x378: 493 val &= 0xfc; 494 break; 495 496 case 0x3bc: 497 val &= 0xfd; 498 break; 499 500 case 0x278: 501 val &= 0xfe; 502 break; 503 504 default: 505 val &= 0xfd; 506 break; 507 } 508 509 outb(idport, PC873_FAR); 510 outb(idport + 1, val); 511 outb(idport + 1, val); 512 513 /* Check for success by reading back the value we supposedly 514 wrote and comparing...*/ 515 516 outb(idport, PC873_FAR); 517 val = inb(idport + 1) & 0x3; 518 519 /* If we fail, report the failure... */ 520 521 if (pc873xx_porttab[val] != ppc->ppc_base) { 522 if (bootverbose) 523 printf("PC873xx at 0x%x not for driver at port 0x%x\n", 524 pc873xx_porttab[val], ppc->ppc_base); 525 } 526 continue; 527 } 528 529 outb(idport, PC873_PTR); 530 ptr = inb(idport + 1); 531 532 /* get irq settings */ 533 if (ppc->ppc_base == 0x378) 534 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5; 535 else 536 irq = pc873xx_irqtab[val]; 537 538 if (bootverbose) 539 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base); 540 541 /* 542 * Check if irq settings are correct 543 */ 544 if (irq != ppc->ppc_irq) { 545 /* 546 * If the chipset is not locked and base address is 0x378, 547 * we have another chance 548 */ 549 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) { 550 if (ppc->ppc_irq == 7) { 551 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 552 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 553 } else { 554 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 555 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 556 } 557 if (bootverbose) 558 printf("PC873xx irq set to %d\n", ppc->ppc_irq); 559 } else { 560 if (bootverbose) 561 printf("PC873xx sorry, can't change irq setting\n"); 562 } 563 } else { 564 if (bootverbose) 565 printf("PC873xx irq settings are correct\n"); 566 } 567 568 outb(idport, PC873_PCR); 569 pcr = inb(idport + 1); 570 571 if ((ptr & PC873_CFGLOCK) || !chipset_mode) { 572 if (bootverbose) 573 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked"); 574 575 ppc->ppc_avm |= PPB_NIBBLE; 576 if (bootverbose) 577 printf(", NIBBLE"); 578 579 if (pcr & PC873_EPPEN) { 580 ppc->ppc_avm |= PPB_EPP; 581 582 if (bootverbose) 583 printf(", EPP"); 584 585 if (pcr & PC873_EPP19) 586 ppc->ppc_epp = EPP_1_9; 587 else 588 ppc->ppc_epp = EPP_1_7; 589 590 if ((ppc->ppc_model == NS_PC87332) && bootverbose) { 591 outb(idport, PC873_PTR); 592 ptr = inb(idport + 1); 593 if (ptr & PC873_EPPRDIR) 594 printf(", Regular mode"); 595 else 596 printf(", Automatic mode"); 597 } 598 } else if (pcr & PC873_ECPEN) { 599 ppc->ppc_avm |= PPB_ECP; 600 if (bootverbose) 601 printf(", ECP"); 602 603 if (pcr & PC873_ECPCLK) { /* XXX */ 604 ppc->ppc_avm |= PPB_PS2; 605 if (bootverbose) 606 printf(", PS/2"); 607 } 608 } else { 609 outb(idport, PC873_PTR); 610 ptr = inb(idport + 1); 611 if (ptr & PC873_EXTENDED) { 612 ppc->ppc_avm |= PPB_SPP; 613 if (bootverbose) 614 printf(", SPP"); 615 } 616 } 617 } else { 618 if (bootverbose) 619 printf("PC873xx unlocked"); 620 621 if (chipset_mode & PPB_ECP) { 622 if ((chipset_mode & PPB_EPP) && bootverbose) 623 printf(", ECP+EPP not supported"); 624 625 pcr &= ~PC873_EPPEN; 626 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */ 627 outb(idport + 1, pcr); 628 outb(idport + 1, pcr); 629 630 if (bootverbose) 631 printf(", ECP"); 632 633 } else if (chipset_mode & PPB_EPP) { 634 pcr &= ~(PC873_ECPEN | PC873_ECPCLK); 635 pcr |= (PC873_EPPEN | PC873_EPP19); 636 outb(idport + 1, pcr); 637 outb(idport + 1, pcr); 638 639 ppc->ppc_epp = EPP_1_9; /* XXX */ 640 641 if (bootverbose) 642 printf(", EPP1.9"); 643 644 /* enable automatic direction turnover */ 645 if (ppc->ppc_model == NS_PC87332) { 646 outb(idport, PC873_PTR); 647 ptr = inb(idport + 1); 648 ptr &= ~PC873_EPPRDIR; 649 outb(idport + 1, ptr); 650 outb(idport + 1, ptr); 651 652 if (bootverbose) 653 printf(", Automatic mode"); 654 } 655 } else { 656 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN); 657 outb(idport + 1, pcr); 658 outb(idport + 1, pcr); 659 660 /* configure extended bit in PTR */ 661 outb(idport, PC873_PTR); 662 ptr = inb(idport + 1); 663 664 if (chipset_mode & PPB_PS2) { 665 ptr |= PC873_EXTENDED; 666 667 if (bootverbose) 668 printf(", PS/2"); 669 670 } else { 671 /* default to NIBBLE mode */ 672 ptr &= ~PC873_EXTENDED; 673 674 if (bootverbose) 675 printf(", NIBBLE"); 676 } 677 outb(idport + 1, ptr); 678 outb(idport + 1, ptr); 679 } 680 681 ppc->ppc_avm = chipset_mode; 682 } 683 684 if (bootverbose) 685 printf("\n"); 686 687 ppc->ppc_type = PPC_TYPE_GENERIC; 688 ppc_generic_setmode(ppc, chipset_mode); 689 690 return(chipset_mode); 691 } 692 return(-1); 693 } 694 695 /* 696 * ppc_smc37c66xgt_detect 697 * 698 * SMC FDC37C66xGT configuration. 699 */ 700 static int 701 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode) 702 { 703 int i; 704 u_char r; 705 int type = -1; 706 int csr = SMC66x_CSR; /* initial value is 0x3F0 */ 707 708 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 }; 709 710 711 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */ 712 713 /* 714 * Detection: enter configuration mode and read CRD register. 715 */ 716 PPC_CONFIG_LOCK(ppc); 717 outb(csr, SMC665_iCODE); 718 outb(csr, SMC665_iCODE); 719 PPC_CONFIG_UNLOCK(ppc); 720 721 outb(csr, 0xd); 722 if (inb(cio) == 0x65) { 723 type = SMC_37C665GT; 724 goto config; 725 } 726 727 for (i = 0; i < 2; i++) { 728 PPC_CONFIG_LOCK(ppc); 729 outb(csr, SMC666_iCODE); 730 outb(csr, SMC666_iCODE); 731 PPC_CONFIG_UNLOCK(ppc); 732 733 outb(csr, 0xd); 734 if (inb(cio) == 0x66) { 735 type = SMC_37C666GT; 736 break; 737 } 738 739 /* Another chance, CSR may be hard-configured to be at 0x370 */ 740 csr = SMC666_CSR; 741 } 742 743 config: 744 /* 745 * If chipset not found, do not continue. 746 */ 747 if (type == -1) { 748 outb(csr, 0xaa); /* end config mode */ 749 return (-1); 750 } 751 752 /* select CR1 */ 753 outb(csr, 0x1); 754 755 /* read the port's address: bits 0 and 1 of CR1 */ 756 r = inb(cio) & SMC_CR1_ADDR; 757 if (port_address[(int)r] != ppc->ppc_base) { 758 outb(csr, 0xaa); /* end config mode */ 759 return (-1); 760 } 761 762 ppc->ppc_model = type; 763 764 /* 765 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration 766 * If SPP mode is detected, try to set ECP+EPP mode 767 */ 768 769 if (bootverbose) { 770 outb(csr, 0x1); 771 device_printf(ppc->ppc_dev, "SMC registers CR1=0x%x", 772 inb(cio) & 0xff); 773 774 outb(csr, 0x4); 775 printf(" CR4=0x%x", inb(cio) & 0xff); 776 } 777 778 /* select CR1 */ 779 outb(csr, 0x1); 780 781 if (!chipset_mode) { 782 /* autodetect mode */ 783 784 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 785 if (type == SMC_37C666GT) { 786 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 787 if (bootverbose) 788 printf(" configuration hardwired, supposing " \ 789 "ECP+EPP SPP"); 790 791 } else 792 if ((inb(cio) & SMC_CR1_MODE) == 0) { 793 /* already in extended parallel port mode, read CR4 */ 794 outb(csr, 0x4); 795 r = (inb(cio) & SMC_CR4_EMODE); 796 797 switch (r) { 798 case SMC_SPP: 799 ppc->ppc_avm |= PPB_SPP; 800 if (bootverbose) 801 printf(" SPP"); 802 break; 803 804 case SMC_EPPSPP: 805 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 806 if (bootverbose) 807 printf(" EPP SPP"); 808 break; 809 810 case SMC_ECP: 811 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 812 if (bootverbose) 813 printf(" ECP SPP"); 814 break; 815 816 case SMC_ECPEPP: 817 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 818 if (bootverbose) 819 printf(" ECP+EPP SPP"); 820 break; 821 } 822 } else { 823 /* not an extended port mode */ 824 ppc->ppc_avm |= PPB_SPP; 825 if (bootverbose) 826 printf(" SPP"); 827 } 828 829 } else { 830 /* mode forced */ 831 ppc->ppc_avm = chipset_mode; 832 833 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 834 if (type == SMC_37C666GT) 835 goto end_detect; 836 837 r = inb(cio); 838 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) { 839 /* do not use ECP when the mode is not forced to */ 840 outb(cio, r | SMC_CR1_MODE); 841 if (bootverbose) 842 printf(" SPP"); 843 } else { 844 /* an extended mode is selected */ 845 outb(cio, r & ~SMC_CR1_MODE); 846 847 /* read CR4 register and reset mode field */ 848 outb(csr, 0x4); 849 r = inb(cio) & ~SMC_CR4_EMODE; 850 851 if (chipset_mode & PPB_ECP) { 852 if (chipset_mode & PPB_EPP) { 853 outb(cio, r | SMC_ECPEPP); 854 if (bootverbose) 855 printf(" ECP+EPP"); 856 } else { 857 outb(cio, r | SMC_ECP); 858 if (bootverbose) 859 printf(" ECP"); 860 } 861 } else { 862 /* PPB_EPP is set */ 863 outb(cio, r | SMC_EPPSPP); 864 if (bootverbose) 865 printf(" EPP SPP"); 866 } 867 } 868 ppc->ppc_avm = chipset_mode; 869 } 870 871 /* set FIFO threshold to 16 */ 872 if (ppc->ppc_avm & PPB_ECP) { 873 /* select CRA */ 874 outb(csr, 0xa); 875 outb(cio, 16); 876 } 877 878 end_detect: 879 880 if (bootverbose) 881 printf ("\n"); 882 883 if (ppc->ppc_avm & PPB_EPP) { 884 /* select CR4 */ 885 outb(csr, 0x4); 886 r = inb(cio); 887 888 /* 889 * Set the EPP protocol... 890 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7 891 */ 892 if (ppc->ppc_epp == EPP_1_9) 893 outb(cio, (r & ~SMC_CR4_EPPTYPE)); 894 else 895 outb(cio, (r | SMC_CR4_EPPTYPE)); 896 } 897 898 outb(csr, 0xaa); /* end config mode */ 899 900 ppc->ppc_type = PPC_TYPE_SMCLIKE; 901 ppc_smclike_setmode(ppc, chipset_mode); 902 903 return (chipset_mode); 904 } 905 906 /* 907 * SMC FDC37C935 configuration 908 * Found on many Alpha machines 909 */ 910 static int 911 ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode) 912 { 913 int type = -1; 914 915 PPC_CONFIG_LOCK(ppc); 916 outb(SMC935_CFG, 0x55); /* enter config mode */ 917 outb(SMC935_CFG, 0x55); 918 PPC_CONFIG_UNLOCK(ppc); 919 920 outb(SMC935_IND, SMC935_ID); /* check device id */ 921 if (inb(SMC935_DAT) == 0x2) 922 type = SMC_37C935; 923 924 if (type == -1) { 925 outb(SMC935_CFG, 0xaa); /* exit config mode */ 926 return (-1); 927 } 928 929 ppc->ppc_model = type; 930 931 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */ 932 outb(SMC935_DAT, 3); /* which is logical device 3 */ 933 934 /* set io port base */ 935 outb(SMC935_IND, SMC935_PORTHI); 936 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8)); 937 outb(SMC935_IND, SMC935_PORTLO); 938 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff)); 939 940 if (!chipset_mode) 941 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */ 942 else { 943 ppc->ppc_avm = chipset_mode; 944 outb(SMC935_IND, SMC935_PPMODE); 945 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */ 946 947 /* SPP + EPP or just plain SPP */ 948 if (chipset_mode & (PPB_SPP)) { 949 if (chipset_mode & PPB_EPP) { 950 if (ppc->ppc_epp == EPP_1_9) { 951 outb(SMC935_IND, SMC935_PPMODE); 952 outb(SMC935_DAT, SMC935_EPP19SPP); 953 } 954 if (ppc->ppc_epp == EPP_1_7) { 955 outb(SMC935_IND, SMC935_PPMODE); 956 outb(SMC935_DAT, SMC935_EPP17SPP); 957 } 958 } else { 959 outb(SMC935_IND, SMC935_PPMODE); 960 outb(SMC935_DAT, SMC935_SPP); 961 } 962 } 963 964 /* ECP + EPP or just plain ECP */ 965 if (chipset_mode & PPB_ECP) { 966 if (chipset_mode & PPB_EPP) { 967 if (ppc->ppc_epp == EPP_1_9) { 968 outb(SMC935_IND, SMC935_PPMODE); 969 outb(SMC935_DAT, SMC935_ECPEPP19); 970 } 971 if (ppc->ppc_epp == EPP_1_7) { 972 outb(SMC935_IND, SMC935_PPMODE); 973 outb(SMC935_DAT, SMC935_ECPEPP17); 974 } 975 } else { 976 outb(SMC935_IND, SMC935_PPMODE); 977 outb(SMC935_DAT, SMC935_ECP); 978 } 979 } 980 } 981 982 outb(SMC935_CFG, 0xaa); /* exit config mode */ 983 984 ppc->ppc_type = PPC_TYPE_SMCLIKE; 985 ppc_smclike_setmode(ppc, chipset_mode); 986 987 return (chipset_mode); 988 } 989 990 /* 991 * Winbond W83877F stuff 992 * 993 * EFER: extended function enable register 994 * EFIR: extended function index register 995 * EFDR: extended function data register 996 */ 997 #define efir ((efer == 0x250) ? 0x251 : 0x3f0) 998 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1) 999 1000 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 }; 1001 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 }; 1002 static int w83877f_keyiter[] = { 1, 2, 2, 1 }; 1003 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 }; 1004 1005 static int 1006 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode) 1007 { 1008 int i, j, efer; 1009 unsigned char r, hefere, hefras; 1010 1011 for (i = 0; i < 4; i ++) { 1012 /* first try to enable configuration registers */ 1013 efer = w83877f_efers[i]; 1014 1015 /* write the key to the EFER */ 1016 for (j = 0; j < w83877f_keyiter[i]; j ++) 1017 outb (efer, w83877f_keys[i]); 1018 1019 /* then check HEFERE and HEFRAS bits */ 1020 outb (efir, 0x0c); 1021 hefere = inb(efdr) & WINB_HEFERE; 1022 1023 outb (efir, 0x16); 1024 hefras = inb(efdr) & WINB_HEFRAS; 1025 1026 /* 1027 * HEFRAS HEFERE 1028 * 0 1 write 89h to 250h (power-on default) 1029 * 1 0 write 86h twice to 3f0h 1030 * 1 1 write 87h twice to 3f0h 1031 * 0 0 write 88h to 250h 1032 */ 1033 if ((hefere | hefras) == w83877f_hefs[i]) 1034 goto found; 1035 } 1036 1037 return (-1); /* failed */ 1038 1039 found: 1040 /* check base port address - read from CR23 */ 1041 outb(efir, 0x23); 1042 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */ 1043 return (-1); 1044 1045 /* read CHIP ID from CR9/bits0-3 */ 1046 outb(efir, 0x9); 1047 1048 switch (inb(efdr) & WINB_CHIPID) { 1049 case WINB_W83877F_ID: 1050 ppc->ppc_model = WINB_W83877F; 1051 break; 1052 1053 case WINB_W83877AF_ID: 1054 ppc->ppc_model = WINB_W83877AF; 1055 break; 1056 1057 default: 1058 ppc->ppc_model = WINB_UNKNOWN; 1059 } 1060 1061 if (bootverbose) { 1062 /* dump of registers */ 1063 device_printf(ppc->ppc_dev, "0x%x - ", w83877f_keys[i]); 1064 for (i = 0; i <= 0xd; i ++) { 1065 outb(efir, i); 1066 printf("0x%x ", inb(efdr)); 1067 } 1068 for (i = 0x10; i <= 0x17; i ++) { 1069 outb(efir, i); 1070 printf("0x%x ", inb(efdr)); 1071 } 1072 outb(efir, 0x1e); 1073 printf("0x%x ", inb(efdr)); 1074 for (i = 0x20; i <= 0x29; i ++) { 1075 outb(efir, i); 1076 printf("0x%x ", inb(efdr)); 1077 } 1078 printf("\n"); 1079 } 1080 1081 ppc->ppc_type = PPC_TYPE_GENERIC; 1082 1083 if (!chipset_mode) { 1084 /* autodetect mode */ 1085 1086 /* select CR0 */ 1087 outb(efir, 0x0); 1088 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1); 1089 1090 /* select CR9 */ 1091 outb(efir, 0x9); 1092 r |= (inb(efdr) & WINB_PRTMODS2); 1093 1094 switch (r) { 1095 case WINB_W83757: 1096 if (bootverbose) 1097 device_printf(ppc->ppc_dev, 1098 "W83757 compatible mode\n"); 1099 return (-1); /* generic or SMC-like */ 1100 1101 case WINB_EXTFDC: 1102 case WINB_EXTADP: 1103 case WINB_EXT2FDD: 1104 case WINB_JOYSTICK: 1105 if (bootverbose) 1106 device_printf(ppc->ppc_dev, 1107 "not in parallel port mode\n"); 1108 return (-1); 1109 1110 case (WINB_PARALLEL | WINB_EPP_SPP): 1111 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 1112 if (bootverbose) 1113 device_printf(ppc->ppc_dev, "EPP SPP\n"); 1114 break; 1115 1116 case (WINB_PARALLEL | WINB_ECP): 1117 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 1118 if (bootverbose) 1119 device_printf(ppc->ppc_dev, "ECP SPP\n"); 1120 break; 1121 1122 case (WINB_PARALLEL | WINB_ECP_EPP): 1123 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 1124 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1125 1126 if (bootverbose) 1127 device_printf(ppc->ppc_dev, "ECP+EPP SPP\n"); 1128 break; 1129 default: 1130 printf("%s: unknown case (0x%x)!\n", __func__, r); 1131 } 1132 1133 } else { 1134 /* mode forced */ 1135 1136 /* select CR9 and set PRTMODS2 bit */ 1137 outb(efir, 0x9); 1138 outb(efdr, inb(efdr) & ~WINB_PRTMODS2); 1139 1140 /* select CR0 and reset PRTMODSx bits */ 1141 outb(efir, 0x0); 1142 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1)); 1143 1144 if (chipset_mode & PPB_ECP) { 1145 if (chipset_mode & PPB_EPP) { 1146 outb(efdr, inb(efdr) | WINB_ECP_EPP); 1147 if (bootverbose) 1148 device_printf(ppc->ppc_dev, 1149 "ECP+EPP\n"); 1150 1151 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1152 1153 } else { 1154 outb(efdr, inb(efdr) | WINB_ECP); 1155 if (bootverbose) 1156 device_printf(ppc->ppc_dev, "ECP\n"); 1157 } 1158 } else { 1159 /* select EPP_SPP otherwise */ 1160 outb(efdr, inb(efdr) | WINB_EPP_SPP); 1161 if (bootverbose) 1162 device_printf(ppc->ppc_dev, "EPP SPP\n"); 1163 } 1164 ppc->ppc_avm = chipset_mode; 1165 } 1166 1167 /* exit configuration mode */ 1168 outb(efer, 0xaa); 1169 1170 switch (ppc->ppc_type) { 1171 case PPC_TYPE_SMCLIKE: 1172 ppc_smclike_setmode(ppc, chipset_mode); 1173 break; 1174 default: 1175 ppc_generic_setmode(ppc, chipset_mode); 1176 break; 1177 } 1178 1179 return (chipset_mode); 1180 } 1181 #endif 1182 1183 /* 1184 * ppc_generic_detect 1185 */ 1186 static int 1187 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode) 1188 { 1189 /* default to generic */ 1190 ppc->ppc_type = PPC_TYPE_GENERIC; 1191 1192 if (bootverbose) 1193 device_printf(ppc->ppc_dev, "SPP"); 1194 1195 /* first, check for ECP */ 1196 w_ecr(ppc, PPC_ECR_PS2); 1197 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) { 1198 ppc->ppc_dtm |= PPB_ECP | PPB_SPP; 1199 if (bootverbose) 1200 printf(" ECP "); 1201 1202 /* search for SMC style ECP+EPP mode */ 1203 w_ecr(ppc, PPC_ECR_EPP); 1204 } 1205 1206 /* try to reset EPP timeout bit */ 1207 if (ppc_check_epp_timeout(ppc)) { 1208 ppc->ppc_dtm |= PPB_EPP; 1209 1210 if (ppc->ppc_dtm & PPB_ECP) { 1211 /* SMC like chipset found */ 1212 ppc->ppc_model = SMC_LIKE; 1213 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1214 1215 if (bootverbose) 1216 printf(" ECP+EPP"); 1217 } else { 1218 if (bootverbose) 1219 printf(" EPP"); 1220 } 1221 } else { 1222 /* restore to standard mode */ 1223 w_ecr(ppc, PPC_ECR_STD); 1224 } 1225 1226 /* XXX try to detect NIBBLE and PS2 modes */ 1227 ppc->ppc_dtm |= PPB_NIBBLE; 1228 1229 if (chipset_mode) 1230 ppc->ppc_avm = chipset_mode; 1231 else 1232 ppc->ppc_avm = ppc->ppc_dtm; 1233 1234 if (bootverbose) 1235 printf("\n"); 1236 1237 switch (ppc->ppc_type) { 1238 case PPC_TYPE_SMCLIKE: 1239 ppc_smclike_setmode(ppc, chipset_mode); 1240 break; 1241 default: 1242 ppc_generic_setmode(ppc, chipset_mode); 1243 break; 1244 } 1245 1246 return (chipset_mode); 1247 } 1248 1249 /* 1250 * ppc_detect() 1251 * 1252 * mode is the mode suggested at boot 1253 */ 1254 static int 1255 ppc_detect(struct ppc_data *ppc, int chipset_mode) { 1256 1257 #ifdef PPC_PROBE_CHIPSET 1258 int i, mode; 1259 1260 /* list of supported chipsets */ 1261 int (*chipset_detect[])(struct ppc_data *, int) = { 1262 ppc_pc873xx_detect, 1263 ppc_smc37c66xgt_detect, 1264 ppc_w83877f_detect, 1265 ppc_smc37c935_detect, 1266 ppc_generic_detect, 1267 NULL 1268 }; 1269 #endif 1270 1271 /* if can't find the port and mode not forced return error */ 1272 if (!ppc_detect_port(ppc) && chipset_mode == 0) 1273 return (EIO); /* failed, port not present */ 1274 1275 /* assume centronics compatible mode is supported */ 1276 ppc->ppc_avm = PPB_COMPATIBLE; 1277 1278 #ifdef PPC_PROBE_CHIPSET 1279 /* we have to differenciate available chipset modes, 1280 * chipset running modes and IEEE-1284 operating modes 1281 * 1282 * after detection, the port must support running in compatible mode 1283 */ 1284 if (ppc->ppc_flags & 0x40) { 1285 if (bootverbose) 1286 printf("ppc: chipset forced to generic\n"); 1287 #endif 1288 1289 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode); 1290 1291 #ifdef PPC_PROBE_CHIPSET 1292 } else { 1293 for (i=0; chipset_detect[i] != NULL; i++) { 1294 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) { 1295 ppc->ppc_mode = mode; 1296 break; 1297 } 1298 } 1299 } 1300 #endif 1301 1302 /* configure/detect ECP FIFO */ 1303 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80)) 1304 ppc_detect_fifo(ppc); 1305 1306 return (0); 1307 } 1308 1309 /* 1310 * ppc_exec_microseq() 1311 * 1312 * Execute a microsequence. 1313 * Microsequence mechanism is supposed to handle fast I/O operations. 1314 */ 1315 int 1316 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq) 1317 { 1318 struct ppc_data *ppc = DEVTOSOFTC(dev); 1319 struct ppb_microseq *mi; 1320 char cc, *p; 1321 int i, iter, len; 1322 int error; 1323 1324 int reg; 1325 char mask; 1326 int accum = 0; 1327 char *ptr = NULL; 1328 1329 struct ppb_microseq *stack = NULL; 1330 1331 /* microsequence registers are equivalent to PC-like port registers */ 1332 1333 #define r_reg(reg,ppc) (bus_read_1((ppc)->res_ioport, reg)) 1334 #define w_reg(reg, ppc, byte) (bus_write_1((ppc)->res_ioport, reg, byte)) 1335 1336 #define INCR_PC (mi ++) /* increment program counter */ 1337 1338 PPC_ASSERT_LOCKED(ppc); 1339 mi = *p_msq; 1340 for (;;) { 1341 switch (mi->opcode) { 1342 case MS_OP_RSET: 1343 cc = r_reg(mi->arg[0].i, ppc); 1344 cc &= (char)mi->arg[2].i; /* clear mask */ 1345 cc |= (char)mi->arg[1].i; /* assert mask */ 1346 w_reg(mi->arg[0].i, ppc, cc); 1347 INCR_PC; 1348 break; 1349 1350 case MS_OP_RASSERT_P: 1351 reg = mi->arg[1].i; 1352 ptr = ppc->ppc_ptr; 1353 1354 if ((len = mi->arg[0].i) == MS_ACCUM) { 1355 accum = ppc->ppc_accum; 1356 for (; accum; accum--) 1357 w_reg(reg, ppc, *ptr++); 1358 ppc->ppc_accum = accum; 1359 } else 1360 for (i=0; i<len; i++) 1361 w_reg(reg, ppc, *ptr++); 1362 ppc->ppc_ptr = ptr; 1363 1364 INCR_PC; 1365 break; 1366 1367 case MS_OP_RFETCH_P: 1368 reg = mi->arg[1].i; 1369 mask = (char)mi->arg[2].i; 1370 ptr = ppc->ppc_ptr; 1371 1372 if ((len = mi->arg[0].i) == MS_ACCUM) { 1373 accum = ppc->ppc_accum; 1374 for (; accum; accum--) 1375 *ptr++ = r_reg(reg, ppc) & mask; 1376 ppc->ppc_accum = accum; 1377 } else 1378 for (i=0; i<len; i++) 1379 *ptr++ = r_reg(reg, ppc) & mask; 1380 ppc->ppc_ptr = ptr; 1381 1382 INCR_PC; 1383 break; 1384 1385 case MS_OP_RFETCH: 1386 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) & 1387 (char)mi->arg[1].i; 1388 INCR_PC; 1389 break; 1390 1391 case MS_OP_RASSERT: 1392 case MS_OP_DELAY: 1393 1394 /* let's suppose the next instr. is the same */ 1395 prefetch: 1396 for (;mi->opcode == MS_OP_RASSERT; INCR_PC) 1397 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i); 1398 1399 if (mi->opcode == MS_OP_DELAY) { 1400 DELAY(mi->arg[0].i); 1401 INCR_PC; 1402 goto prefetch; 1403 } 1404 break; 1405 1406 case MS_OP_ADELAY: 1407 if (mi->arg[0].i) { 1408 PPC_UNLOCK(ppc); 1409 pause("ppbdelay", mi->arg[0].i * (hz/1000)); 1410 PPC_LOCK(ppc); 1411 } 1412 INCR_PC; 1413 break; 1414 1415 case MS_OP_TRIG: 1416 reg = mi->arg[0].i; 1417 iter = mi->arg[1].i; 1418 p = (char *)mi->arg[2].p; 1419 1420 /* XXX delay limited to 255 us */ 1421 for (i=0; i<iter; i++) { 1422 w_reg(reg, ppc, *p++); 1423 DELAY((unsigned char)*p++); 1424 } 1425 INCR_PC; 1426 break; 1427 1428 case MS_OP_SET: 1429 ppc->ppc_accum = mi->arg[0].i; 1430 INCR_PC; 1431 break; 1432 1433 case MS_OP_DBRA: 1434 if (--ppc->ppc_accum > 0) 1435 mi += mi->arg[0].i; 1436 INCR_PC; 1437 break; 1438 1439 case MS_OP_BRSET: 1440 cc = r_str(ppc); 1441 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) 1442 mi += mi->arg[1].i; 1443 INCR_PC; 1444 break; 1445 1446 case MS_OP_BRCLEAR: 1447 cc = r_str(ppc); 1448 if ((cc & (char)mi->arg[0].i) == 0) 1449 mi += mi->arg[1].i; 1450 INCR_PC; 1451 break; 1452 1453 case MS_OP_BRSTAT: 1454 cc = r_str(ppc); 1455 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 1456 (char)mi->arg[0].i) 1457 mi += mi->arg[2].i; 1458 INCR_PC; 1459 break; 1460 1461 case MS_OP_C_CALL: 1462 /* 1463 * If the C call returns !0 then end the microseq. 1464 * The current state of ptr is passed to the C function 1465 */ 1466 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr))) 1467 return (error); 1468 1469 INCR_PC; 1470 break; 1471 1472 case MS_OP_PTR: 1473 ppc->ppc_ptr = (char *)mi->arg[0].p; 1474 INCR_PC; 1475 break; 1476 1477 case MS_OP_CALL: 1478 if (stack) 1479 panic("%s: too much calls", __func__); 1480 1481 if (mi->arg[0].p) { 1482 /* store the state of the actual 1483 * microsequence 1484 */ 1485 stack = mi; 1486 1487 /* jump to the new microsequence */ 1488 mi = (struct ppb_microseq *)mi->arg[0].p; 1489 } else 1490 INCR_PC; 1491 1492 break; 1493 1494 case MS_OP_SUBRET: 1495 /* retrieve microseq and pc state before the call */ 1496 mi = stack; 1497 1498 /* reset the stack */ 1499 stack = NULL; 1500 1501 /* XXX return code */ 1502 1503 INCR_PC; 1504 break; 1505 1506 case MS_OP_PUT: 1507 case MS_OP_GET: 1508 case MS_OP_RET: 1509 /* can't return to ppb level during the execution 1510 * of a submicrosequence */ 1511 if (stack) 1512 panic("%s: can't return to ppb level", 1513 __func__); 1514 1515 /* update pc for ppb level of execution */ 1516 *p_msq = mi; 1517 1518 /* return to ppb level of execution */ 1519 return (0); 1520 1521 default: 1522 panic("%s: unknown microsequence opcode 0x%x", 1523 __func__, mi->opcode); 1524 } 1525 } 1526 1527 /* unreached */ 1528 } 1529 1530 static void 1531 ppcintr(void *arg) 1532 { 1533 struct ppc_data *ppc = arg; 1534 u_char ctr, ecr, str; 1535 1536 /* 1537 * If we have any child interrupt handlers registered, let 1538 * them handle this interrupt. 1539 * 1540 * XXX: If DMA is in progress should we just complete that w/o 1541 * doing this? 1542 */ 1543 PPC_LOCK(ppc); 1544 if (ppc->ppc_intr_hook != NULL && 1545 ppc->ppc_intr_hook(ppc->ppc_intr_arg) == 0) { 1546 PPC_UNLOCK(ppc); 1547 return; 1548 } 1549 1550 str = r_str(ppc); 1551 ctr = r_ctr(ppc); 1552 ecr = r_ecr(ppc); 1553 1554 #if defined(PPC_DEBUG) && PPC_DEBUG > 1 1555 printf("![%x/%x/%x]", ctr, ecr, str); 1556 #endif 1557 1558 /* don't use ecp mode with IRQENABLE set */ 1559 if (ctr & IRQENABLE) { 1560 PPC_UNLOCK(ppc); 1561 return; 1562 } 1563 1564 /* interrupts are generated by nFault signal 1565 * only in ECP mode */ 1566 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) { 1567 /* check if ppc driver has programmed the 1568 * nFault interrupt */ 1569 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) { 1570 1571 w_ecr(ppc, ecr | PPC_nFAULT_INTR); 1572 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT; 1573 } else { 1574 /* shall be handled by underlying layers XXX */ 1575 PPC_UNLOCK(ppc); 1576 return; 1577 } 1578 } 1579 1580 if (ppc->ppc_irqstat & PPC_IRQ_DMA) { 1581 /* disable interrupts (should be done by hardware though) */ 1582 w_ecr(ppc, ecr | PPC_SERVICE_INTR); 1583 ppc->ppc_irqstat &= ~PPC_IRQ_DMA; 1584 ecr = r_ecr(ppc); 1585 1586 /* check if DMA completed */ 1587 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) { 1588 #ifdef PPC_DEBUG 1589 printf("a"); 1590 #endif 1591 /* stop DMA */ 1592 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA); 1593 ecr = r_ecr(ppc); 1594 1595 if (ppc->ppc_dmastat == PPC_DMA_STARTED) { 1596 #ifdef PPC_DEBUG 1597 printf("d"); 1598 #endif 1599 ppc->ppc_dmadone(ppc); 1600 ppc->ppc_dmastat = PPC_DMA_COMPLETE; 1601 1602 /* wakeup the waiting process */ 1603 wakeup(ppc); 1604 } 1605 } 1606 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) { 1607 1608 /* classic interrupt I/O */ 1609 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO; 1610 } 1611 PPC_UNLOCK(ppc); 1612 1613 return; 1614 } 1615 1616 int 1617 ppc_read(device_t dev, char *buf, int len, int mode) 1618 { 1619 return (EINVAL); 1620 } 1621 1622 int 1623 ppc_write(device_t dev, char *buf, int len, int how) 1624 { 1625 return (EINVAL); 1626 } 1627 1628 int 1629 ppc_reset_epp(device_t dev) 1630 { 1631 struct ppc_data *ppc = DEVTOSOFTC(dev); 1632 1633 PPC_ASSERT_LOCKED(ppc); 1634 ppc_reset_epp_timeout(ppc); 1635 1636 return 0; 1637 } 1638 1639 int 1640 ppc_setmode(device_t dev, int mode) 1641 { 1642 struct ppc_data *ppc = DEVTOSOFTC(dev); 1643 1644 PPC_ASSERT_LOCKED(ppc); 1645 switch (ppc->ppc_type) { 1646 case PPC_TYPE_SMCLIKE: 1647 return (ppc_smclike_setmode(ppc, mode)); 1648 break; 1649 1650 case PPC_TYPE_GENERIC: 1651 default: 1652 return (ppc_generic_setmode(ppc, mode)); 1653 break; 1654 } 1655 1656 /* not reached */ 1657 return (ENXIO); 1658 } 1659 1660 int 1661 ppc_probe(device_t dev, int rid) 1662 { 1663 #ifdef __i386__ 1664 static short next_bios_ppc = 0; 1665 #endif 1666 struct ppc_data *ppc; 1667 int error; 1668 rman_res_t port; 1669 1670 /* 1671 * Allocate the ppc_data structure. 1672 */ 1673 ppc = DEVTOSOFTC(dev); 1674 bzero(ppc, sizeof(struct ppc_data)); 1675 1676 ppc->rid_ioport = rid; 1677 1678 /* retrieve ISA parameters */ 1679 error = bus_get_resource(dev, SYS_RES_IOPORT, rid, &port, NULL); 1680 1681 #ifdef __i386__ 1682 /* 1683 * If port not specified, use bios list. 1684 */ 1685 if (error) { 1686 if ((next_bios_ppc < BIOS_MAX_PPC) && 1687 (*(BIOS_PORTS + next_bios_ppc) != 0)) { 1688 port = *(BIOS_PORTS + next_bios_ppc++); 1689 if (bootverbose) 1690 device_printf(dev, 1691 "parallel port found at 0x%jx\n", port); 1692 } else { 1693 device_printf(dev, "parallel port not found.\n"); 1694 return (ENXIO); 1695 } 1696 bus_set_resource(dev, SYS_RES_IOPORT, rid, port, 1697 IO_LPTSIZE_EXTENDED); 1698 } 1699 #endif 1700 1701 /* IO port is mandatory */ 1702 1703 /* Try "extended" IO port range...*/ 1704 ppc->res_ioport = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT, 1705 &ppc->rid_ioport, 1706 IO_LPTSIZE_EXTENDED, 1707 RF_ACTIVE); 1708 1709 if (ppc->res_ioport != 0) { 1710 if (bootverbose) 1711 device_printf(dev, "using extended I/O port range\n"); 1712 } else { 1713 /* Failed? If so, then try the "normal" IO port range... */ 1714 ppc->res_ioport = bus_alloc_resource_anywhere(dev, 1715 SYS_RES_IOPORT, 1716 &ppc->rid_ioport, 1717 IO_LPTSIZE_NORMAL, 1718 RF_ACTIVE); 1719 if (ppc->res_ioport != 0) { 1720 if (bootverbose) 1721 device_printf(dev, "using normal I/O port range\n"); 1722 } else { 1723 device_printf(dev, "cannot reserve I/O port range\n"); 1724 goto error; 1725 } 1726 } 1727 1728 ppc->ppc_base = rman_get_start(ppc->res_ioport); 1729 1730 ppc->ppc_flags = device_get_flags(dev); 1731 1732 if (!(ppc->ppc_flags & 0x20)) { 1733 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1734 &ppc->rid_irq, 1735 RF_SHAREABLE); 1736 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ, 1737 &ppc->rid_drq, 1738 RF_ACTIVE); 1739 } 1740 1741 if (ppc->res_irq) 1742 ppc->ppc_irq = rman_get_start(ppc->res_irq); 1743 if (ppc->res_drq) 1744 ppc->ppc_dmachan = rman_get_start(ppc->res_drq); 1745 1746 ppc->ppc_dev = dev; 1747 ppc->ppc_model = GENERIC; 1748 1749 ppc->ppc_mode = PPB_COMPATIBLE; 1750 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4; 1751 1752 ppc->ppc_type = PPC_TYPE_GENERIC; 1753 1754 /* 1755 * Try to detect the chipset and its mode. 1756 */ 1757 if (ppc_detect(ppc, ppc->ppc_flags & 0xf)) 1758 goto error; 1759 1760 return (0); 1761 1762 error: 1763 if (ppc->res_irq != 0) { 1764 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, 1765 ppc->res_irq); 1766 } 1767 if (ppc->res_ioport != 0) { 1768 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1769 ppc->res_ioport); 1770 } 1771 if (ppc->res_drq != 0) { 1772 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1773 ppc->res_drq); 1774 } 1775 return (ENXIO); 1776 } 1777 1778 int 1779 ppc_attach(device_t dev) 1780 { 1781 struct ppc_data *ppc = DEVTOSOFTC(dev); 1782 int error; 1783 1784 mtx_init(&ppc->ppc_lock, device_get_nameunit(dev), "ppc", MTX_DEF); 1785 1786 device_printf(dev, "%s chipset (%s) in %s mode%s\n", 1787 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm], 1788 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ? 1789 ppc_epp_protocol[ppc->ppc_epp] : ""); 1790 1791 if (ppc->ppc_fifo) 1792 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n", 1793 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr); 1794 1795 if (ppc->res_irq) { 1796 /* default to the tty mask for registration */ /* XXX */ 1797 error = bus_setup_intr(dev, ppc->res_irq, INTR_TYPE_TTY | 1798 INTR_MPSAFE, NULL, ppcintr, ppc, &ppc->intr_cookie); 1799 if (error) { 1800 device_printf(dev, 1801 "failed to register interrupt handler: %d\n", 1802 error); 1803 mtx_destroy(&ppc->ppc_lock); 1804 return (error); 1805 } 1806 } 1807 1808 /* add ppbus as a child of this isa to parallel bridge */ 1809 ppc->ppbus = device_add_child(dev, "ppbus", -1); 1810 1811 /* 1812 * Probe the ppbus and attach devices found. 1813 */ 1814 device_probe_and_attach(ppc->ppbus); 1815 1816 return (0); 1817 } 1818 1819 int 1820 ppc_detach(device_t dev) 1821 { 1822 struct ppc_data *ppc = DEVTOSOFTC(dev); 1823 1824 if (ppc->res_irq == 0) { 1825 return (ENXIO); 1826 } 1827 1828 /* detach & delete all children */ 1829 device_delete_children(dev); 1830 1831 if (ppc->res_irq != 0) { 1832 bus_teardown_intr(dev, ppc->res_irq, ppc->intr_cookie); 1833 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, 1834 ppc->res_irq); 1835 } 1836 if (ppc->res_ioport != 0) { 1837 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1838 ppc->res_ioport); 1839 } 1840 if (ppc->res_drq != 0) { 1841 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1842 ppc->res_drq); 1843 } 1844 1845 mtx_destroy(&ppc->ppc_lock); 1846 1847 return (0); 1848 } 1849 1850 u_char 1851 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte) 1852 { 1853 struct ppc_data *ppc = DEVTOSOFTC(ppcdev); 1854 1855 PPC_ASSERT_LOCKED(ppc); 1856 switch (iop) { 1857 case PPB_OUTSB_EPP: 1858 bus_write_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt); 1859 break; 1860 case PPB_OUTSW_EPP: 1861 bus_write_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt); 1862 break; 1863 case PPB_OUTSL_EPP: 1864 bus_write_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt); 1865 break; 1866 case PPB_INSB_EPP: 1867 bus_read_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt); 1868 break; 1869 case PPB_INSW_EPP: 1870 bus_read_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt); 1871 break; 1872 case PPB_INSL_EPP: 1873 bus_read_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt); 1874 break; 1875 case PPB_RDTR: 1876 return (r_dtr(ppc)); 1877 case PPB_RSTR: 1878 return (r_str(ppc)); 1879 case PPB_RCTR: 1880 return (r_ctr(ppc)); 1881 case PPB_REPP_A: 1882 return (r_epp_A(ppc)); 1883 case PPB_REPP_D: 1884 return (r_epp_D(ppc)); 1885 case PPB_RECR: 1886 return (r_ecr(ppc)); 1887 case PPB_RFIFO: 1888 return (r_fifo(ppc)); 1889 case PPB_WDTR: 1890 w_dtr(ppc, byte); 1891 break; 1892 case PPB_WSTR: 1893 w_str(ppc, byte); 1894 break; 1895 case PPB_WCTR: 1896 w_ctr(ppc, byte); 1897 break; 1898 case PPB_WEPP_A: 1899 w_epp_A(ppc, byte); 1900 break; 1901 case PPB_WEPP_D: 1902 w_epp_D(ppc, byte); 1903 break; 1904 case PPB_WECR: 1905 w_ecr(ppc, byte); 1906 break; 1907 case PPB_WFIFO: 1908 w_fifo(ppc, byte); 1909 break; 1910 default: 1911 panic("%s: unknown I/O operation", __func__); 1912 break; 1913 } 1914 1915 return (0); /* not significative */ 1916 } 1917 1918 int 1919 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val) 1920 { 1921 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus); 1922 1923 switch (index) { 1924 case PPC_IVAR_EPP_PROTO: 1925 PPC_ASSERT_LOCKED(ppc); 1926 *val = (u_long)ppc->ppc_epp; 1927 break; 1928 case PPC_IVAR_LOCK: 1929 *val = (uintptr_t)&ppc->ppc_lock; 1930 break; 1931 default: 1932 return (ENOENT); 1933 } 1934 1935 return (0); 1936 } 1937 1938 int 1939 ppc_write_ivar(device_t bus, device_t dev, int index, uintptr_t val) 1940 { 1941 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus); 1942 1943 switch (index) { 1944 case PPC_IVAR_INTR_HANDLER: 1945 PPC_ASSERT_LOCKED(ppc); 1946 if (dev != ppc->ppbus) 1947 return (EINVAL); 1948 if (val == 0) { 1949 ppc->ppc_intr_hook = NULL; 1950 break; 1951 } 1952 if (ppc->ppc_intr_hook != NULL) 1953 return (EBUSY); 1954 ppc->ppc_intr_hook = (void *)val; 1955 ppc->ppc_intr_arg = device_get_softc(dev); 1956 break; 1957 default: 1958 return (ENOENT); 1959 } 1960 1961 return (0); 1962 } 1963 1964 /* 1965 * We allow child devices to allocate an IRQ resource at rid 0 for their 1966 * interrupt handlers. 1967 */ 1968 struct resource * 1969 ppc_alloc_resource(device_t bus, device_t child, int type, int *rid, 1970 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 1971 { 1972 struct ppc_data *ppc = DEVTOSOFTC(bus); 1973 1974 switch (type) { 1975 case SYS_RES_IRQ: 1976 if (*rid == 0) 1977 return (ppc->res_irq); 1978 break; 1979 } 1980 return (NULL); 1981 } 1982 1983 int 1984 ppc_release_resource(device_t bus, device_t child, int type, int rid, 1985 struct resource *r) 1986 { 1987 #ifdef INVARIANTS 1988 struct ppc_data *ppc = DEVTOSOFTC(bus); 1989 #endif 1990 1991 switch (type) { 1992 case SYS_RES_IRQ: 1993 if (rid == 0) { 1994 KASSERT(r == ppc->res_irq, 1995 ("ppc child IRQ resource mismatch")); 1996 return (0); 1997 } 1998 break; 1999 } 2000 return (EINVAL); 2001 } 2002 2003 MODULE_DEPEND(ppc, ppbus, 1, 1, 1); 2004