1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2021 Intel Corporation */ 3 /* $FreeBSD$ */ 4 #ifndef ADF_GEN2_HW_DATA_H_ 5 #define ADF_GEN2_HW_DATA_H_ 6 7 #include "adf_accel_devices.h" 8 #include "adf_cfg_common.h" 9 10 /* Transport access */ 11 #define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL 12 #define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL 13 #define ADF_RING_CSR_RING_CONFIG 0x000 14 #define ADF_RING_CSR_RING_LBASE 0x040 15 #define ADF_RING_CSR_RING_UBASE 0x080 16 #define ADF_RING_CSR_RING_HEAD 0x0C0 17 #define ADF_RING_CSR_RING_TAIL 0x100 18 #define ADF_RING_CSR_E_STAT 0x14C 19 #define ADF_RING_CSR_INT_FLAG 0x170 20 #define ADF_RING_CSR_INT_SRCSEL 0x174 21 #define ADF_RING_CSR_INT_SRCSEL_2 0x178 22 #define ADF_RING_CSR_INT_COL_EN 0x17C 23 #define ADF_RING_CSR_INT_COL_CTL 0x180 24 #define ADF_RING_CSR_INT_FLAG_AND_COL 0x184 25 #define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000 26 #define ADF_RING_BUNDLE_SIZE 0x1000 27 #define ADF_GEN2_RX_RINGS_OFFSET 8 28 #define ADF_GEN2_TX_RINGS_MASK 0xFF 29 30 #define BUILD_RING_BASE_ADDR(addr, size) \ 31 (((addr) >> 6) & (GENMASK_ULL(63, 0) << (size))) 32 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ 33 ADF_CSR_RD(csr_base_addr, \ 34 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_RING_HEAD + \ 35 ((ring) << 2)) 36 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ 37 ADF_CSR_RD(csr_base_addr, \ 38 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_RING_TAIL + \ 39 ((ring) << 2)) 40 #define READ_CSR_E_STAT(csr_base_addr, bank) \ 41 ADF_CSR_RD(csr_base_addr, \ 42 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_E_STAT) 43 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ 44 ADF_CSR_WR(csr_base_addr, \ 45 (ADF_RING_BUNDLE_SIZE * (bank)) + \ 46 ADF_RING_CSR_RING_CONFIG + ((ring) << 2), \ 47 value) 48 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ 49 do { \ 50 u32 l_base = 0, u_base = 0; \ 51 l_base = (u32)((value)&0xFFFFFFFF); \ 52 u_base = (u32)(((value)&0xFFFFFFFF00000000ULL) >> 32); \ 53 ADF_CSR_WR(csr_base_addr, \ 54 (ADF_RING_BUNDLE_SIZE * (bank)) + \ 55 ADF_RING_CSR_RING_LBASE + ((ring) << 2), \ 56 l_base); \ 57 ADF_CSR_WR(csr_base_addr, \ 58 (ADF_RING_BUNDLE_SIZE * (bank)) + \ 59 ADF_RING_CSR_RING_UBASE + ((ring) << 2), \ 60 u_base); \ 61 } while (0) 62 63 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \ 64 ADF_CSR_WR(csr_base_addr, \ 65 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_RING_HEAD + \ 66 ((ring) << 2), \ 67 value) 68 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \ 69 ADF_CSR_WR(csr_base_addr, \ 70 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_RING_TAIL + \ 71 ((ring) << 2), \ 72 value) 73 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \ 74 ADF_CSR_WR(csr_base_addr, \ 75 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_INT_FLAG, \ 76 value) 77 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \ 78 do { \ 79 ADF_CSR_WR(csr_base_addr, \ 80 (ADF_RING_BUNDLE_SIZE * (bank)) + \ 81 ADF_RING_CSR_INT_SRCSEL, \ 82 ADF_BANK_INT_SRC_SEL_MASK_0); \ 83 ADF_CSR_WR(csr_base_addr, \ 84 (ADF_RING_BUNDLE_SIZE * (bank)) + \ 85 ADF_RING_CSR_INT_SRCSEL_2, \ 86 ADF_BANK_INT_SRC_SEL_MASK_X); \ 87 } while (0) 88 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \ 89 ADF_CSR_WR(csr_base_addr, \ 90 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_INT_COL_EN, \ 91 value) 92 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \ 93 ADF_CSR_WR(csr_base_addr, \ 94 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_INT_COL_CTL, \ 95 ADF_RING_CSR_INT_COL_CTL_ENABLE | (value)) 96 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \ 97 ADF_CSR_WR(csr_base_addr, \ 98 (ADF_RING_BUNDLE_SIZE * (bank)) + \ 99 ADF_RING_CSR_INT_FLAG_AND_COL, \ 100 value) 101 102 /* AE to function map */ 103 #define AE2FUNCTION_MAP_A_OFFSET (0x3A400 + 0x190) 104 #define AE2FUNCTION_MAP_B_OFFSET (0x3A400 + 0x310) 105 #define AE2FUNCTION_MAP_REG_SIZE 4 106 #define AE2FUNCTION_MAP_VALID BIT(7) 107 108 #define READ_CSR_AE2FUNCTION_MAP_A(pmisc_bar_addr, index) \ 109 ADF_CSR_RD(pmisc_bar_addr, \ 110 AE2FUNCTION_MAP_A_OFFSET + \ 111 AE2FUNCTION_MAP_REG_SIZE * (index)) 112 #define WRITE_CSR_AE2FUNCTION_MAP_A(pmisc_bar_addr, index, value) \ 113 ADF_CSR_WR(pmisc_bar_addr, \ 114 AE2FUNCTION_MAP_A_OFFSET + \ 115 AE2FUNCTION_MAP_REG_SIZE * (index), \ 116 value) 117 #define READ_CSR_AE2FUNCTION_MAP_B(pmisc_bar_addr, index) \ 118 ADF_CSR_RD(pmisc_bar_addr, \ 119 AE2FUNCTION_MAP_B_OFFSET + \ 120 AE2FUNCTION_MAP_REG_SIZE * (index)) 121 #define WRITE_CSR_AE2FUNCTION_MAP_B(pmisc_bar_addr, index, value) \ 122 ADF_CSR_WR(pmisc_bar_addr, \ 123 AE2FUNCTION_MAP_B_OFFSET + \ 124 AE2FUNCTION_MAP_REG_SIZE * (index), \ 125 value) 126 127 /* Admin Interface Offsets */ 128 #define ADF_ADMINMSGUR_OFFSET (0x3A000 + 0x574) 129 #define ADF_ADMINMSGLR_OFFSET (0x3A000 + 0x578) 130 #define ADF_MAILBOX_BASE_OFFSET 0x20970 131 132 /* Arbiter configuration */ 133 #define ADF_ARB_OFFSET 0x30000 134 #define ADF_ARB_WRK_2_SER_MAP_OFFSET 0x180 135 #define ADF_ARB_CONFIG (BIT(31) | BIT(6) | BIT(0)) 136 #define ADF_ARB_REG_SLOT 0x1000 137 #define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C 138 139 #define READ_CSR_RING_SRV_ARB_EN(csr_addr, index) \ 140 ADF_CSR_RD(csr_addr, \ 141 ADF_ARB_RINGSRVARBEN_OFFSET + (ADF_ARB_REG_SLOT * (index))) 142 143 #define WRITE_CSR_RING_SRV_ARB_EN(csr_addr, index, value) \ 144 ADF_CSR_WR(csr_addr, \ 145 ADF_ARB_RINGSRVARBEN_OFFSET + (ADF_ARB_REG_SLOT * (index)), \ 146 value) 147 148 /* Power gating */ 149 #define ADF_POWERGATE_DC BIT(23) 150 #define ADF_POWERGATE_PKE BIT(24) 151 152 /* Default ring mapping */ 153 #define ADF_GEN2_DEFAULT_RING_TO_SRV_MAP \ 154 (CRYPTO << ADF_CFG_SERV_RING_PAIR_0_SHIFT | \ 155 CRYPTO << ADF_CFG_SERV_RING_PAIR_1_SHIFT | \ 156 UNUSED << ADF_CFG_SERV_RING_PAIR_2_SHIFT | \ 157 COMP << ADF_CFG_SERV_RING_PAIR_3_SHIFT) 158 159 /* Error detection and correction */ 160 #define ADF_GEN2_AE_CTX_ENABLES(i) ((i)*0x1000 + 0x20818) 161 #define ADF_GEN2_AE_MISC_CONTROL(i) ((i)*0x1000 + 0x20960) 162 #define ADF_GEN2_ENABLE_AE_ECC_ERR BIT(28) 163 #define ADF_GEN2_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12)) 164 #define ADF_GEN2_UERRSSMSH(i) ((i)*0x4000 + 0x18) 165 #define ADF_GEN2_CERRSSMSH(i) ((i)*0x4000 + 0x10) 166 #define ADF_GEN2_ERRSSMSH_EN BIT(3) 167 168 #define ADF_NUM_HB_CNT_PER_AE (ADF_NUM_THREADS_PER_AE + ADF_NUM_PKE_STRAND) 169 170 void adf_gen2_init_hw_csr_info(struct adf_hw_csr_info *csr_info); 171 172 #endif 173