1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 /* $FreeBSD$ */ 4 #ifndef ADF_TRANSPORT_ACCESS_MACROS_H 5 #define ADF_TRANSPORT_ACCESS_MACROS_H 6 7 #include "adf_accel_devices.h" 8 #define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL 9 #define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL 10 #define ADF_BANK_INT_FLAG_CLEAR_MASK 0xFFFF 11 #define ADF_RING_CSR_RING_CONFIG 0x000 12 #define ADF_RING_CSR_RING_LBASE 0x040 13 #define ADF_RING_CSR_RING_UBASE 0x080 14 #define ADF_RING_CSR_RING_HEAD 0x0C0 15 #define ADF_RING_CSR_RING_TAIL 0x100 16 #define ADF_RING_CSR_E_STAT 0x14C 17 #define ADF_RING_CSR_INT_FLAG 0x170 18 #define ADF_RING_CSR_INT_SRCSEL 0x174 19 #define ADF_RING_CSR_INT_SRCSEL_2 0x178 20 #define ADF_RING_CSR_INT_COL_EN 0x17C 21 #define ADF_RING_CSR_INT_COL_CTL 0x180 22 #define ADF_RING_CSR_INT_FLAG_AND_COL 0x184 23 #define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000 24 #define ADF_RING_BUNDLE_SIZE 0x1000 25 #define ADF_RING_CONFIG_NEAR_FULL_WM 0x0A 26 #define ADF_RING_CONFIG_NEAR_EMPTY_WM 0x05 27 #define ADF_COALESCING_MIN_TIME 0x1FF 28 #define ADF_COALESCING_MAX_TIME 0xFFFFF 29 #define ADF_COALESCING_DEF_TIME 0x27FF 30 #define ADF_RING_NEAR_WATERMARK_512 0x08 31 #define ADF_RING_NEAR_WATERMARK_0 0x00 32 #define ADF_RING_EMPTY_SIG 0x7F7F7F7F 33 34 /* Valid internal ring size values */ 35 #define ADF_RING_SIZE_128 0x01 36 #define ADF_RING_SIZE_256 0x02 37 #define ADF_RING_SIZE_512 0x03 38 #define ADF_RING_SIZE_4K 0x06 39 #define ADF_RING_SIZE_16K 0x08 40 #define ADF_RING_SIZE_4M 0x10 41 #define ADF_MIN_RING_SIZE ADF_RING_SIZE_128 42 #define ADF_MAX_RING_SIZE ADF_RING_SIZE_4M 43 #define ADF_DEFAULT_RING_SIZE ADF_RING_SIZE_16K 44 45 /* Valid internal msg size values */ 46 #define ADF_MSG_SIZE_32 0x01 47 #define ADF_MSG_SIZE_64 0x02 48 #define ADF_MSG_SIZE_128 0x04 49 #define ADF_MIN_MSG_SIZE ADF_MSG_SIZE_32 50 #define ADF_MAX_MSG_SIZE ADF_MSG_SIZE_128 51 52 /* Size to bytes conversion macros for ring and msg size values */ 53 #define ADF_MSG_SIZE_TO_BYTES(SIZE) (SIZE << 5) 54 #define ADF_BYTES_TO_MSG_SIZE(SIZE) (SIZE >> 5) 55 #define ADF_SIZE_TO_RING_SIZE_IN_BYTES(SIZE) ((1 << (SIZE - 1)) << 7) 56 #define ADF_RING_SIZE_IN_BYTES_TO_SIZE(SIZE) ((1 << (SIZE - 1)) >> 7) 57 58 /* Set the response quota to a high number */ 59 #define ADF_NO_RESPONSE_QUOTA 0xFFFFFFFF 60 61 /* Minimum ring bufer size for memory allocation */ 62 #define ADF_RING_SIZE_BYTES_MIN(SIZE) \ 63 ((SIZE < ADF_SIZE_TO_RING_SIZE_IN_BYTES(ADF_RING_SIZE_4K)) ? \ 64 ADF_SIZE_TO_RING_SIZE_IN_BYTES(ADF_RING_SIZE_4K) : \ 65 SIZE) 66 #define ADF_RING_SIZE_MODULO(SIZE) (SIZE + 0x6) 67 #define ADF_SIZE_TO_POW(SIZE) \ 68 ((((SIZE & 0x4) >> 1) | ((SIZE & 0x4) >> 2) | SIZE) & ~0x4) 69 /* Max outstanding requests */ 70 #define ADF_MAX_INFLIGHTS(RING_SIZE, MSG_SIZE) \ 71 ((((1 << (RING_SIZE - 1)) << 3) >> ADF_SIZE_TO_POW(MSG_SIZE)) - 1) 72 #define BUILD_RING_CONFIG(size) \ 73 ((ADF_RING_NEAR_WATERMARK_0 << ADF_RING_CONFIG_NEAR_FULL_WM) | \ 74 (ADF_RING_NEAR_WATERMARK_0 << ADF_RING_CONFIG_NEAR_EMPTY_WM) | size) 75 #define BUILD_RESP_RING_CONFIG(size, watermark_nf, watermark_ne) \ 76 ((watermark_nf << ADF_RING_CONFIG_NEAR_FULL_WM) | \ 77 (watermark_ne << ADF_RING_CONFIG_NEAR_EMPTY_WM) | size) 78 #define BUILD_RING_BASE_ADDR(addr, size) \ 79 ((addr >> 6) & (0xFFFFFFFFFFFFFFFFULL << size)) 80 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ 81 ADF_CSR_RD(csr_base_addr, \ 82 (ADF_RING_BUNDLE_SIZE * bank) + ADF_RING_CSR_RING_HEAD + \ 83 (ring << 2)) 84 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ 85 ADF_CSR_RD(csr_base_addr, \ 86 (ADF_RING_BUNDLE_SIZE * bank) + ADF_RING_CSR_RING_TAIL + \ 87 (ring << 2)) 88 #define READ_CSR_E_STAT(csr_base_addr, bank) \ 89 ADF_CSR_RD(csr_base_addr, \ 90 (ADF_RING_BUNDLE_SIZE * bank) + ADF_RING_CSR_E_STAT) 91 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ 92 ADF_CSR_WR(csr_base_addr, \ 93 (ADF_RING_BUNDLE_SIZE * bank) + ADF_RING_CSR_RING_CONFIG + \ 94 (ring << 2), \ 95 value) 96 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ 97 do { \ 98 uint32_t l_base = 0, u_base = 0; \ 99 l_base = (uint32_t)(value & 0xFFFFFFFF); \ 100 u_base = (uint32_t)((value & 0xFFFFFFFF00000000ULL) >> 32); \ 101 ADF_CSR_WR(csr_base_addr, \ 102 (ADF_RING_BUNDLE_SIZE * bank) + \ 103 ADF_RING_CSR_RING_LBASE + (ring << 2), \ 104 l_base); \ 105 ADF_CSR_WR(csr_base_addr, \ 106 (ADF_RING_BUNDLE_SIZE * bank) + \ 107 ADF_RING_CSR_RING_UBASE + (ring << 2), \ 108 u_base); \ 109 } while (0) 110 static inline uint64_t 111 read_base(struct resource *csr_base_addr, uint32_t bank, uint32_t ring) 112 { 113 uint32_t l_base, u_base; 114 uint64_t addr; 115 116 l_base = ADF_CSR_RD(csr_base_addr, 117 (ADF_RING_BUNDLE_SIZE * bank) + 118 ADF_RING_CSR_RING_LBASE + (ring << 2)); 119 u_base = ADF_CSR_RD(csr_base_addr, 120 (ADF_RING_BUNDLE_SIZE * bank) + 121 ADF_RING_CSR_RING_UBASE + (ring << 2)); 122 123 addr = (uint64_t)l_base & 0x00000000FFFFFFFFULL; 124 addr |= (uint64_t)u_base << 32 & 0xFFFFFFFF00000000ULL; 125 126 return addr; 127 } 128 129 #define READ_CSR_RING_BASE(csr_base_addr, bank, ring) \ 130 read_base(csr_base_addr, bank, ring) 131 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \ 132 ADF_CSR_WR(csr_base_addr, \ 133 (ADF_RING_BUNDLE_SIZE * bank) + ADF_RING_CSR_RING_HEAD + \ 134 (ring << 2), \ 135 value) 136 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \ 137 ADF_CSR_WR(csr_base_addr, \ 138 (ADF_RING_BUNDLE_SIZE * bank) + ADF_RING_CSR_RING_TAIL + \ 139 (ring << 2), \ 140 value) 141 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \ 142 ADF_CSR_WR(csr_base_addr, \ 143 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_INT_FLAG, \ 144 value) 145 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \ 146 do { \ 147 ADF_CSR_WR(csr_base_addr, \ 148 (ADF_RING_BUNDLE_SIZE * bank) + \ 149 ADF_RING_CSR_INT_SRCSEL, \ 150 ADF_BANK_INT_SRC_SEL_MASK_0); \ 151 ADF_CSR_WR(csr_base_addr, \ 152 (ADF_RING_BUNDLE_SIZE * bank) + \ 153 ADF_RING_CSR_INT_SRCSEL_2, \ 154 ADF_BANK_INT_SRC_SEL_MASK_X); \ 155 } while (0) 156 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \ 157 ADF_CSR_WR(csr_base_addr, \ 158 (ADF_RING_BUNDLE_SIZE * bank) + ADF_RING_CSR_INT_COL_EN, \ 159 value) 160 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \ 161 ADF_CSR_WR(csr_base_addr, \ 162 (ADF_RING_BUNDLE_SIZE * bank) + ADF_RING_CSR_INT_COL_CTL, \ 163 ADF_RING_CSR_INT_COL_CTL_ENABLE | value) 164 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \ 165 ADF_CSR_WR(csr_base_addr, \ 166 (ADF_RING_BUNDLE_SIZE * bank) + \ 167 ADF_RING_CSR_INT_FLAG_AND_COL, \ 168 value) 169 #endif 170