1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 /** 4 ***************************************************************************** 5 * @file icp_qat_hw_2x_comp.h 6 * @defgroup ICP QAT HW accessors for using the for 2.x Compression Slice 7 * definitions 8 * @ingroup icp_qat_hw_2x_comp 9 * @description 10 * This file documents definitions for the QAT HW COMP SLICE 11 * 12 *****************************************************************************/ 13 14 #ifndef _ICP_QAT_HW_20_COMP_H_ 15 #define _ICP_QAT_HW_20_COMP_H_ 16 17 #include "icp_qat_hw_20_comp_defs.h" // For HW definitions 18 #include "icp_qat_fw.h" //For Set Field Macros. 19 20 #ifdef WIN32 21 #include <stdlib.h> // built in support for _byteswap_ulong 22 #define BYTE_SWAP_32 _byteswap_ulong 23 #else 24 #define BYTE_SWAP_32 __builtin_bswap32 25 #endif 26 27 /** 28 ***************************************************************************** 29 * @ingroup icp_qat_fw_comn 30 * 31 * @description 32 * Definition of the hw config csr. This representation has to be further 33 * processed by the corresponding config build function. 34 * 35 *****************************************************************************/ 36 typedef struct icp_qat_hw_comp_20_config_csr_lower_s { 37 // Fields programmable directly by the SW. 38 icp_qat_hw_comp_20_extended_delay_match_mode_t edmm; 39 icp_qat_hw_comp_20_hw_comp_format_t algo; 40 icp_qat_hw_comp_20_search_depth_t sd; 41 icp_qat_hw_comp_20_hbs_control_t hbs; 42 // Fields programmable directly by the FW. 43 // Block Drop enable. (Set by FW) 44 icp_qat_hw_comp_20_abd_t abd; 45 icp_qat_hw_comp_20_lllbd_ctrl_t lllbd; 46 // Advanced HW control (Set to default vals) 47 icp_qat_hw_comp_20_skip_hash_collision_t hash_col; 48 icp_qat_hw_comp_20_skip_hash_update_t hash_update; 49 icp_qat_hw_comp_20_byte_skip_t skip_ctrl; 50 51 } icp_qat_hw_comp_20_config_csr_lower_t; 52 53 /** 54 ***************************************************************************** 55 * @ingroup icp_qat_fw_comn 56 * 57 * @description 58 * Build the longword as expected by the HW 59 * 60 *****************************************************************************/ 61 static inline uint32_t 62 ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(icp_qat_hw_comp_20_config_csr_lower_t csr) 63 { 64 uint32_t val32 = 0; 65 // Programmable values 66 QAT_FIELD_SET(val32, 67 csr.algo, 68 ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_BITPOS, 69 ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_MASK); 70 71 QAT_FIELD_SET(val32, 72 csr.sd, 73 ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_BITPOS, 74 ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_MASK); 75 76 QAT_FIELD_SET( 77 val32, 78 csr.edmm, 79 ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_BITPOS, 80 ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_MASK); 81 82 QAT_FIELD_SET(val32, 83 csr.hbs, 84 ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS, 85 ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_MASK); 86 87 QAT_FIELD_SET(val32, 88 csr.lllbd, 89 ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS, 90 ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK); 91 92 QAT_FIELD_SET(val32, 93 csr.hash_col, 94 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_BITPOS, 95 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_MASK); 96 97 QAT_FIELD_SET(val32, 98 csr.hash_update, 99 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_BITPOS, 100 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_MASK); 101 102 QAT_FIELD_SET(val32, 103 csr.skip_ctrl, 104 ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_BITPOS, 105 ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_MASK); 106 // Default values. 107 108 QAT_FIELD_SET(val32, 109 csr.abd, 110 ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_BITPOS, 111 ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_MASK); 112 113 QAT_FIELD_SET(val32, 114 csr.lllbd, 115 ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS, 116 ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK); 117 118 return BYTE_SWAP_32(val32); 119 } 120 121 /** 122 ***************************************************************************** 123 * @ingroup icp_qat_fw_comn 124 * 125 * @description 126 * Definition of the hw config csr. This representation has to be further 127 * processed by the corresponding config build function. 128 * 129 *****************************************************************************/ 130 typedef struct icp_qat_hw_comp_20_config_csr_upper_s { 131 icp_qat_hw_comp_20_scb_control_t scb_ctrl; 132 icp_qat_hw_comp_20_rmb_control_t rmb_ctrl; 133 icp_qat_hw_comp_20_som_control_t som_ctrl; 134 icp_qat_hw_comp_20_skip_hash_rd_control_t skip_hash_ctrl; 135 icp_qat_hw_comp_20_scb_unload_control_t scb_unload_ctrl; 136 icp_qat_hw_comp_20_disable_token_fusion_control_t 137 disable_token_fusion_ctrl; 138 icp_qat_hw_comp_20_scb_mode_reset_mask_t scb_mode_reset; 139 uint16_t lazy; 140 uint16_t nice; 141 } icp_qat_hw_comp_20_config_csr_upper_t; 142 143 /** 144 ***************************************************************************** 145 * @ingroup icp_qat_fw_comn 146 * 147 * @description 148 * Build the longword as expected by the HW 149 * 150 *****************************************************************************/ 151 static inline uint32_t 152 ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(icp_qat_hw_comp_20_config_csr_upper_t csr) 153 { 154 uint32_t val32 = 0; 155 156 QAT_FIELD_SET(val32, 157 csr.scb_ctrl, 158 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_BITPOS, 159 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_MASK); 160 161 QAT_FIELD_SET(val32, 162 csr.rmb_ctrl, 163 ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_BITPOS, 164 ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_MASK); 165 166 QAT_FIELD_SET(val32, 167 csr.som_ctrl, 168 ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_BITPOS, 169 ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_MASK); 170 171 QAT_FIELD_SET(val32, 172 csr.skip_hash_ctrl, 173 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_BITPOS, 174 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_MASK); 175 176 QAT_FIELD_SET(val32, 177 csr.scb_unload_ctrl, 178 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_BITPOS, 179 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_MASK); 180 181 QAT_FIELD_SET( 182 val32, 183 csr.disable_token_fusion_ctrl, 184 ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_BITPOS, 185 ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_MASK); 186 187 QAT_FIELD_SET(val32, 188 csr.scb_mode_reset, 189 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_BITPOS, 190 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_MASK); 191 192 QAT_FIELD_SET(val32, 193 csr.lazy, 194 ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_BITPOS, 195 ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_MASK); 196 197 QAT_FIELD_SET(val32, 198 csr.nice, 199 ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_BITPOS, 200 ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_MASK); 201 202 return BYTE_SWAP_32(val32); 203 } 204 205 /** 206 ***************************************************************************** 207 * @ingroup icp_qat_fw_comn 208 * 209 * @description 210 * Definition of the hw config csr. This representation has to be further 211 * processed by the corresponding config build function. 212 * 213 *****************************************************************************/ 214 typedef struct icp_qat_hw_decomp_20_config_csr_lower_s { 215 /* Fields programmable directly by the SW. */ 216 icp_qat_hw_decomp_20_hbs_control_t hbs; 217 /* Advanced HW control (Set to default vals) */ 218 icp_qat_hw_decomp_20_hw_comp_format_t algo; 219 } icp_qat_hw_decomp_20_config_csr_lower_t; 220 221 /** 222 ***************************************************************************** 223 * @ingroup icp_qat_fw_comn 224 * 225 * @description 226 * Build the longword as expected by the HW 227 * 228 *****************************************************************************/ 229 static inline uint32_t 230 ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER( 231 icp_qat_hw_decomp_20_config_csr_lower_t csr) 232 { 233 uint32_t val32 = 0; 234 235 QAT_FIELD_SET(val32, 236 csr.hbs, 237 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS, 238 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_MASK); 239 240 QAT_FIELD_SET(val32, 241 csr.algo, 242 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_BITPOS, 243 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_MASK); 244 245 return BYTE_SWAP_32(val32); 246 } 247 248 /** 249 ***************************************************************************** 250 * @ingroup icp_qat_fw_comn 251 * 252 * @description 253 * Definition of the hw config csr. This representation has to be further 254 * processed by the corresponding config build function. 255 * 256 *****************************************************************************/ 257 typedef struct icp_qat_hw_decomp_20_config_csr_upper_s { 258 /* Advanced HW control (Set to default vals) */ 259 icp_qat_hw_decomp_20_speculative_decoder_control_t sdc; 260 icp_qat_hw_decomp_20_mini_cam_control_t mcc; 261 } icp_qat_hw_decomp_20_config_csr_upper_t; 262 263 /** 264 ***************************************************************************** 265 * @ingroup icp_qat_fw_comn 266 * 267 * @description 268 * Build the longword as expected by the HW 269 * 270 *****************************************************************************/ 271 static inline uint32_t 272 ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_UPPER( 273 icp_qat_hw_decomp_20_config_csr_upper_t csr) 274 { 275 uint32_t val32 = 0; 276 277 QAT_FIELD_SET( 278 val32, 279 csr.sdc, 280 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_BITPOS, 281 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_MASK); 282 283 QAT_FIELD_SET(val32, 284 csr.mcc, 285 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_BITPOS, 286 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_MASK); 287 288 return BYTE_SWAP_32(val32); 289 } 290 291 #endif /* ICP_QAT_HW__2X_COMP_H_ */ 292