1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 /* $FreeBSD$ */ 4 /** 5 ***************************************************************************** 6 * @file icp_qat_hw_2x_comp.h 7 * @defgroup ICP QAT HW accessors for using the for 2.x Compression Slice 8 * definitions 9 * @ingroup icp_qat_hw_2x_comp 10 * @description 11 * This file documents definitions for the QAT HW COMP SLICE 12 * 13 *****************************************************************************/ 14 15 #ifndef _ICP_QAT_HW_20_COMP_H_ 16 #define _ICP_QAT_HW_20_COMP_H_ 17 18 #include "icp_qat_hw_20_comp_defs.h" // For HW definitions 19 #include "icp_qat_fw.h" //For Set Field Macros. 20 21 #ifdef WIN32 22 #include <stdlib.h> // built in support for _byteswap_ulong 23 #define BYTE_SWAP_32 _byteswap_ulong 24 #else 25 #define BYTE_SWAP_32 __builtin_bswap32 26 #endif 27 28 /** 29 ***************************************************************************** 30 * @ingroup icp_qat_fw_comn 31 * 32 * @description 33 * Definition of the hw config csr. This representation has to be further 34 * processed by the corresponding config build function. 35 * 36 *****************************************************************************/ 37 typedef struct icp_qat_hw_comp_20_config_csr_lower_s { 38 // Fields programmable directly by the SW. 39 icp_qat_hw_comp_20_extended_delay_match_mode_t edmm; 40 icp_qat_hw_comp_20_hw_comp_format_t algo; 41 icp_qat_hw_comp_20_search_depth_t sd; 42 icp_qat_hw_comp_20_hbs_control_t hbs; 43 // Fields programmable directly by the FW. 44 // Block Drop enable. (Set by FW) 45 icp_qat_hw_comp_20_abd_t abd; 46 icp_qat_hw_comp_20_lllbd_ctrl_t lllbd; 47 // Advanced HW control (Set to default vals) 48 icp_qat_hw_comp_20_skip_hash_collision_t hash_col; 49 icp_qat_hw_comp_20_skip_hash_update_t hash_update; 50 icp_qat_hw_comp_20_byte_skip_t skip_ctrl; 51 52 } icp_qat_hw_comp_20_config_csr_lower_t; 53 54 /** 55 ***************************************************************************** 56 * @ingroup icp_qat_fw_comn 57 * 58 * @description 59 * Build the longword as expected by the HW 60 * 61 *****************************************************************************/ 62 static inline uint32_t 63 ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(icp_qat_hw_comp_20_config_csr_lower_t csr) 64 { 65 uint32_t val32 = 0; 66 // Programmable values 67 QAT_FIELD_SET(val32, 68 csr.algo, 69 ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_BITPOS, 70 ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_MASK); 71 72 QAT_FIELD_SET(val32, 73 csr.sd, 74 ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_BITPOS, 75 ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_MASK); 76 77 QAT_FIELD_SET( 78 val32, 79 csr.edmm, 80 ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_BITPOS, 81 ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_MASK); 82 83 QAT_FIELD_SET(val32, 84 csr.hbs, 85 ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS, 86 ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_MASK); 87 88 QAT_FIELD_SET(val32, 89 csr.lllbd, 90 ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS, 91 ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK); 92 93 QAT_FIELD_SET(val32, 94 csr.hash_col, 95 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_BITPOS, 96 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_MASK); 97 98 QAT_FIELD_SET(val32, 99 csr.hash_update, 100 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_BITPOS, 101 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_MASK); 102 103 QAT_FIELD_SET(val32, 104 csr.skip_ctrl, 105 ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_BITPOS, 106 ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_MASK); 107 // Default values. 108 109 QAT_FIELD_SET(val32, 110 csr.abd, 111 ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_BITPOS, 112 ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_MASK); 113 114 QAT_FIELD_SET(val32, 115 csr.lllbd, 116 ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS, 117 ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK); 118 119 return BYTE_SWAP_32(val32); 120 } 121 122 /** 123 ***************************************************************************** 124 * @ingroup icp_qat_fw_comn 125 * 126 * @description 127 * Definition of the hw config csr. This representation has to be further 128 * processed by the corresponding config build function. 129 * 130 *****************************************************************************/ 131 typedef struct icp_qat_hw_comp_20_config_csr_upper_s { 132 icp_qat_hw_comp_20_scb_control_t scb_ctrl; 133 icp_qat_hw_comp_20_rmb_control_t rmb_ctrl; 134 icp_qat_hw_comp_20_som_control_t som_ctrl; 135 icp_qat_hw_comp_20_skip_hash_rd_control_t skip_hash_ctrl; 136 icp_qat_hw_comp_20_scb_unload_control_t scb_unload_ctrl; 137 icp_qat_hw_comp_20_disable_token_fusion_control_t 138 disable_token_fusion_ctrl; 139 icp_qat_hw_comp_20_scb_mode_reset_mask_t scb_mode_reset; 140 uint16_t lazy; 141 uint16_t nice; 142 } icp_qat_hw_comp_20_config_csr_upper_t; 143 144 /** 145 ***************************************************************************** 146 * @ingroup icp_qat_fw_comn 147 * 148 * @description 149 * Build the longword as expected by the HW 150 * 151 *****************************************************************************/ 152 static inline uint32_t 153 ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(icp_qat_hw_comp_20_config_csr_upper_t csr) 154 { 155 uint32_t val32 = 0; 156 157 QAT_FIELD_SET(val32, 158 csr.scb_ctrl, 159 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_BITPOS, 160 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_MASK); 161 162 QAT_FIELD_SET(val32, 163 csr.rmb_ctrl, 164 ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_BITPOS, 165 ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_MASK); 166 167 QAT_FIELD_SET(val32, 168 csr.som_ctrl, 169 ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_BITPOS, 170 ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_MASK); 171 172 QAT_FIELD_SET(val32, 173 csr.skip_hash_ctrl, 174 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_BITPOS, 175 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_MASK); 176 177 QAT_FIELD_SET(val32, 178 csr.scb_unload_ctrl, 179 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_BITPOS, 180 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_MASK); 181 182 QAT_FIELD_SET( 183 val32, 184 csr.disable_token_fusion_ctrl, 185 ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_BITPOS, 186 ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_MASK); 187 188 QAT_FIELD_SET(val32, 189 csr.scb_mode_reset, 190 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_BITPOS, 191 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_MASK); 192 193 QAT_FIELD_SET(val32, 194 csr.lazy, 195 ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_BITPOS, 196 ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_MASK); 197 198 QAT_FIELD_SET(val32, 199 csr.nice, 200 ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_BITPOS, 201 ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_MASK); 202 203 return BYTE_SWAP_32(val32); 204 } 205 206 /** 207 ***************************************************************************** 208 * @ingroup icp_qat_fw_comn 209 * 210 * @description 211 * Definition of the hw config csr. This representation has to be further 212 * processed by the corresponding config build function. 213 * 214 *****************************************************************************/ 215 typedef struct icp_qat_hw_decomp_20_config_csr_lower_s { 216 /* Fields programmable directly by the SW. */ 217 icp_qat_hw_decomp_20_hbs_control_t hbs; 218 /* Advanced HW control (Set to default vals) */ 219 icp_qat_hw_decomp_20_hw_comp_format_t algo; 220 } icp_qat_hw_decomp_20_config_csr_lower_t; 221 222 /** 223 ***************************************************************************** 224 * @ingroup icp_qat_fw_comn 225 * 226 * @description 227 * Build the longword as expected by the HW 228 * 229 *****************************************************************************/ 230 static inline uint32_t 231 ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER( 232 icp_qat_hw_decomp_20_config_csr_lower_t csr) 233 { 234 uint32_t val32 = 0; 235 236 QAT_FIELD_SET(val32, 237 csr.hbs, 238 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS, 239 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_MASK); 240 241 QAT_FIELD_SET(val32, 242 csr.algo, 243 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_BITPOS, 244 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_MASK); 245 246 return BYTE_SWAP_32(val32); 247 } 248 249 /** 250 ***************************************************************************** 251 * @ingroup icp_qat_fw_comn 252 * 253 * @description 254 * Definition of the hw config csr. This representation has to be further 255 * processed by the corresponding config build function. 256 * 257 *****************************************************************************/ 258 typedef struct icp_qat_hw_decomp_20_config_csr_upper_s { 259 /* Advanced HW control (Set to default vals) */ 260 icp_qat_hw_decomp_20_speculative_decoder_control_t sdc; 261 icp_qat_hw_decomp_20_mini_cam_control_t mcc; 262 } icp_qat_hw_decomp_20_config_csr_upper_t; 263 264 /** 265 ***************************************************************************** 266 * @ingroup icp_qat_fw_comn 267 * 268 * @description 269 * Build the longword as expected by the HW 270 * 271 *****************************************************************************/ 272 static inline uint32_t 273 ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_UPPER( 274 icp_qat_hw_decomp_20_config_csr_upper_t csr) 275 { 276 uint32_t val32 = 0; 277 278 QAT_FIELD_SET( 279 val32, 280 csr.sdc, 281 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_BITPOS, 282 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_MASK); 283 284 QAT_FIELD_SET(val32, 285 csr.mcc, 286 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_BITPOS, 287 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_MASK); 288 289 return BYTE_SWAP_32(val32); 290 } 291 292 #endif /* ICP_QAT_HW__2X_COMP_H_ */ 293