1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 /* $FreeBSD$ */ 4 /* 5 **************************************************************************** 6 * @file icp_qat_hw_20_comp_defs.h, (autogenerated at 04-19-18 16:06) 7 * @defgroup icp_qat_hw_comp_20 8 * @ingroup icp_qat_hw_comp_20 9 * @description 10 * This file represents the HW configuration CSR definitions 11 **************************************************************************** 12 */ 13 14 #ifndef _ICP_QAT_HW_20_COMP_DEFS_H 15 #define _ICP_QAT_HW_20_COMP_DEFS_H 16 17 /*****************************************************************************/ 18 /* SCB Disabled - Set by FW, located in upper 32bit */ 19 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_BITPOS 31 20 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_MASK 0x1 21 /* 22 **************************************************************************** 23 * @ingroup icp_qat_hw_defs 24 * @description 25 * Enumeration of possible SCB_CONTROL field values 26 *****************************************************************************/ 27 typedef enum { 28 ICP_QAT_HW_COMP_20_SCB_CONTROL_ENABLE = 0x0, 29 /* Normal Mode using SCB (Default) */ 30 ICP_QAT_HW_COMP_20_SCB_CONTROL_DISABLE = 0x1, 31 /* Legacy CPM1.x Mode with SCB disabled. */ 32 } icp_qat_hw_comp_20_scb_control_t; 33 34 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_DEFAULT_VAL \ 35 ICP_QAT_HW_COMP_20_SCB_CONTROL_DISABLE 36 37 /*****************************************************************************/ 38 /* Reset Bit Mask Disabled - Set by FW , located in upper 32bit */ 39 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_BITPOS 30 40 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_MASK 0x1 41 /* 42 **************************************************************************** 43 * @ingroup icp_qat_hw_defs 44 * @description 45 * Enumeration of possible RMB_CONTROL field values 46 *****************************************************************************/ 47 typedef enum { 48 ICP_QAT_HW_COMP_20_RMB_CONTROL_RESET_ALL = 0x0, 49 /* Reset all data structures with a set_config command. (Set by FW) */ 50 ICP_QAT_HW_COMP_20_RMB_CONTROL_RESET_FC_ONLY = 0x1, 51 /* Reset only the Frequency Counters (LFCT) with a set_config command. 52 */ 53 } icp_qat_hw_comp_20_rmb_control_t; 54 55 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_DEFAULT_VAL \ 56 ICP_QAT_HW_COMP_20_RMB_CONTROL_RESET_ALL 57 58 /*****************************************************************************/ 59 /* Slice Operation Mode (SOM) - Set By FW, located in upper 32bit */ 60 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_BITPOS 28 61 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_MASK 0x3 62 /* 63 **************************************************************************** 64 * @ingroup icp_qat_hw_defs 65 * @description 66 * Enumeration of possible SOM_CONTROL field values 67 *****************************************************************************/ 68 typedef enum { 69 ICP_QAT_HW_COMP_20_SOM_CONTROL_NORMAL_MODE = 0x0, 70 /* Normal mode. */ 71 ICP_QAT_HW_COMP_20_SOM_CONTROL_REPLAY_MODE = 0x1, 72 /* Replay mode */ 73 ICP_QAT_HW_COMP_20_SOM_CONTROL_INPUT_CRC = 0x2, 74 /* Input CRC Mode */ 75 ICP_QAT_HW_COMP_20_SOM_CONTROL_RESERVED_MODE = 0x3, 76 /* Reserved. */ 77 } icp_qat_hw_comp_20_som_control_t; 78 79 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_DEFAULT_VAL \ 80 ICP_QAT_HW_COMP_20_SOM_CONTROL_NORMAL_MODE 81 82 /*****************************************************************************/ 83 /* Skip Hash Read (Set By FW) , located in upper 32bit */ 84 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_BITPOS 27 85 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_MASK 0x1 86 /* 87 **************************************************************************** 88 * @ingroup icp_qat_hw_defs 89 * @description 90 * Enumeration of possible SKIP_HASH_RD_CONTROL field values 91 *****************************************************************************/ 92 typedef enum { 93 ICP_QAT_HW_COMP_20_SKIP_HASH_RD_CONTROL_NO_SKIP = 0x0, 94 /* When set to 0, hash reads are not skipped. */ 95 ICP_QAT_HW_COMP_20_SKIP_HASH_RD_CONTROL_SKIP_HASH_READS = 0x1, 96 /* Hash reads are skipped. */ 97 } icp_qat_hw_comp_20_skip_hash_rd_control_t; 98 99 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_DEFAULT_VAL \ 100 ICP_QAT_HW_COMP_20_SKIP_HASH_RD_CONTROL_NO_SKIP 101 102 /*****************************************************************************/ 103 /* SCB Unload Disable, located in upper 32bit */ 104 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_BITPOS 26 105 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_MASK 0x1 106 /* 107 **************************************************************************** 108 * @ingroup icp_qat_hw_defs 109 * @description 110 * Enumeration of possible SCB_UNLOAD_CONTROL field values 111 *****************************************************************************/ 112 typedef enum { 113 ICP_QAT_HW_COMP_20_SCB_UNLOAD_CONTROL_UNLOAD = 0x0, 114 /* Unloads the LFCT and flushes the State Registers. */ 115 ICP_QAT_HW_COMP_20_SCB_UNLOAD_CONTROL_NO_UNLOAD = 0x1, 116 /* Does not unload the LFCT, but flushes the State Registers. */ 117 } icp_qat_hw_comp_20_scb_unload_control_t; 118 119 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_DEFAULT_VAL \ 120 ICP_QAT_HW_COMP_20_SCB_UNLOAD_CONTROL_UNLOAD 121 122 /*****************************************************************************/ 123 /* Disable token fusion, located in upper 32bit */ 124 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_BITPOS 21 125 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_MASK 0x1 126 /* 127 **************************************************************************** 128 * @ingroup icp_qat_hw_defs 129 * @description 130 * Enumeration of possible DISABLE_TOKEN_FUSION_CONTROL field values 131 *****************************************************************************/ 132 typedef enum { 133 ICP_QAT_HW_COMP_20_DISABLE_TOKEN_FUSION_CONTROL_ENABLE = 0x0, 134 /* Enables token fusion. */ 135 ICP_QAT_HW_COMP_20_DISABLE_TOKEN_FUSION_CONTROL_DISABLE = 0x1, 136 /* Disables token fusion. */ 137 } icp_qat_hw_comp_20_disable_token_fusion_control_t; 138 139 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_DEFAULT_VAL \ 140 ICP_QAT_HW_COMP_20_DISABLE_TOKEN_FUSION_CONTROL_ENABLE 141 142 /*****************************************************************************/ 143 /* SCB Mode Reset Mask (Set By FW) , located in upper 32bit */ 144 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_BITPOS 18 145 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_MASK 0x1 146 /* 147 **************************************************************************** 148 * @ingroup icp_qat_hw_defs 149 * @description 150 * Enumeration of possible SCB_MODE_RESET_MASK field values 151 *****************************************************************************/ 152 typedef enum { 153 ICP_QAT_HW_COMP_20_SCB_MODE_RESET_MASK_RESET_COUNTERS = 0x0, 154 /* iLZ77 mode: Reset LFCT, OBC */ 155 ICP_QAT_HW_COMP_20_SCB_MODE_RESET_MASK_RESET_COUNTERS_AND_HISTORY = 0x1, 156 /* iLZ77 mode: Reset LFCT, OBC, HB, HT */ 157 } icp_qat_hw_comp_20_scb_mode_reset_mask_t; 158 159 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_DEFAULT_VAL \ 160 ICP_QAT_HW_COMP_20_SCB_MODE_RESET_MASK_RESET_COUNTERS 161 162 /*****************************************************************************/ 163 /* Lazy - For iLZ77 and Static DEFLATE, Lazy = 102h , located in upper 164 * 32bit */ 165 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_BITPOS 9 166 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_MASK 0x1ff 167 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_DEFAULT_VAL 258 168 169 /*****************************************************************************/ 170 /* Nice - For iLZ77 and Static DEFLATE, Nice = 103h , located in upper 171 * 32bit */ 172 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_BITPOS 0 173 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_MASK 0x1ff 174 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_DEFAULT_VAL 259 175 176 /*****************************************************************************/ 177 /* History Buffer Size (Set By the Driver/ Application), located in lower 32bit 178 */ 179 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS 14 180 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_MASK 0x7 181 /* 182 **************************************************************************** 183 * @ingroup icp_qat_hw_defs 184 * @description 185 * Enumeration of possible HBS_CONTROL field values 186 *****************************************************************************/ 187 typedef enum { 188 ICP_QAT_HW_COMP_20_HBS_CONTROL_HBS_IS_32KB = 0x0, 189 /* 000b - 32KB */ 190 ICP_QAT_HW_COMP_20_HBS_CONTROL_HBS_IS_64KB = 0x1, 191 /* 001b - 64KB */ 192 } icp_qat_hw_comp_20_hbs_control_t; 193 194 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_DEFAULT_VAL \ 195 ICP_QAT_HW_COMP_20_HBS_CONTROL_HBS_IS_32KB 196 197 /*****************************************************************************/ 198 /* Adaptive Block Drop (Set By FW if Dynamic), located in lower 32bit */ 199 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_BITPOS 13 200 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_MASK 0x1 201 /* 202 **************************************************************************** 203 * @ingroup icp_qat_hw_defs 204 * @description 205 * Enumeration of possible ABD field values 206 *****************************************************************************/ 207 typedef enum { 208 ICP_QAT_HW_COMP_20_ABD_ABD_ENABLED = 0x0, 209 /* 0b - Feature enabled. */ 210 ICP_QAT_HW_COMP_20_ABD_ABD_DISABLED = 0x1, 211 /* 1b - Feature disabled. */ 212 } icp_qat_hw_comp_20_abd_t; 213 214 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_DEFAULT_VAL \ 215 ICP_QAT_HW_COMP_20_ABD_ABD_ENABLED 216 217 /*****************************************************************************/ 218 /* Literal+Length Limit Block Drop Block Drop, (Set By FW if Dynamic) , located 219 * in lower 32bit */ 220 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS 12 221 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK 0x1 222 /* 223 **************************************************************************** 224 * @ingroup icp_qat_hw_defs 225 * @description 226 * Enumeration of possible LLLBD_CTRL field values 227 *****************************************************************************/ 228 typedef enum { 229 ICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_ENABLED = 0x0, 230 /* 0b - Feature enabled. */ 231 ICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_DISABLED = 0x1, 232 /* 1b - Feature disabled. */ 233 } icp_qat_hw_comp_20_lllbd_ctrl_t; 234 235 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_DEFAULT_VAL \ 236 ICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_ENABLED 237 238 /*****************************************************************************/ 239 /* Search Depth (SD) (Set By Driver/Application), located in lower 32bit */ 240 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_BITPOS 8 241 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_MASK 0xf 242 /* 243 **************************************************************************** 244 * @ingroup icp_qat_hw_defs 245 * @description 246 * Enumeration of possible SEARCH_DEPTH field values 247 *****************************************************************************/ 248 typedef enum { 249 ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_1 = 0x1, 250 /* 0001b - Level 1 (search depth = 2^1 = 2) */ 251 ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_6 = 0x3, 252 /* 0011b - Level 6 (search depth = 2^3 = 8) */ 253 ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_9 = 0x4, 254 /* 0100b - Level 9 (search depth = 2^4 = 16) */ 255 } icp_qat_hw_comp_20_search_depth_t; 256 257 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_DEFAULT_VAL \ 258 ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_1 259 260 /*****************************************************************************/ 261 /* Compression Format (Set By Driver/Application. Also See CMD ID), located in 262 * lower 32bit */ 263 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_BITPOS 5 264 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_MASK 0x7 265 /* 266 **************************************************************************** 267 * @ingroup icp_qat_hw_defs 268 * @description 269 * Enumeration of possible HW_COMP_FORMAT field values 270 *****************************************************************************/ 271 typedef enum { 272 ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_ILZ77 = 0x0, 273 /* 000 - iLZ77. (Must set Min_Match = 3 bytes and HB size = 32KB.) */ 274 ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_DEFLATE = 0x1, 275 /* 001 - Static DEFLATE. (Must set Min_Match = 3 bytes and HB size = 276 32KB.) */ 277 } icp_qat_hw_comp_20_hw_comp_format_t; 278 279 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_DEFAULT_VAL \ 280 ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_DEFLATE 281 282 /*****************************************************************************/ 283 /* Skip Hash Collision (Set By FW to default value), located in lower 32bit */ 284 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_BITPOS 3 285 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_MASK 0x1 286 /* 287 **************************************************************************** 288 * @ingroup icp_qat_hw_defs 289 * @description 290 * Enumeration of possible SKIP_HASH_COLLISION field values 291 *****************************************************************************/ 292 typedef enum { 293 ICP_QAT_HW_COMP_20_SKIP_HASH_COLLISION_ALLOW = 0x0, 294 /* When set to 0, hash collisions are allowed. */ 295 ICP_QAT_HW_COMP_20_SKIP_HASH_COLLISION_DONT_ALLOW = 0x1, 296 /* When set to 0, hash collisions are allowed. */ 297 } icp_qat_hw_comp_20_skip_hash_collision_t; 298 299 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_DEFAULT_VAL \ 300 ICP_QAT_HW_COMP_20_SKIP_HASH_COLLISION_ALLOW 301 302 /*****************************************************************************/ 303 /* Skip Hash Update (Set By FW to default value) , located in lower 32bit */ 304 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_BITPOS 2 305 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_MASK 0x1 306 /* 307 **************************************************************************** 308 * @ingroup icp_qat_hw_defs 309 * @description 310 * Enumeration of possible SKIP_HASH_UPDATE field values 311 *****************************************************************************/ 312 typedef enum { 313 ICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_ALLOW = 0x0, 314 /* 0 - hash updates are not skipped. */ 315 ICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_DONT_ALLOW = 0x1, 316 /* 1 - hash updates are skipped. */ 317 } icp_qat_hw_comp_20_skip_hash_update_t; 318 319 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_DEFAULT_VAL \ 320 ICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_ALLOW 321 322 /*****************************************************************************/ 323 /* 3-Byte Match Skip (Set By FW to default value), located in lower 32bit */ 324 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_BITPOS 1 325 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_MASK 0x1 326 /* 327 **************************************************************************** 328 * @ingroup icp_qat_hw_defs 329 * @description 330 * Enumeration of possible BYTE_SKIP field values 331 *****************************************************************************/ 332 typedef enum { 333 ICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_TOKEN = 0x0, 334 /* 0 - Use 3-byte token */ 335 ICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_LITERAL = 0x1, 336 /* 0 - Use 3-byte literal */ 337 } icp_qat_hw_comp_20_byte_skip_t; 338 339 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_DEFAULT_VAL \ 340 ICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_TOKEN 341 342 /*****************************************************************************/ 343 /* Extended Delayed Match Mode enabled (Set By the Driver), located in lower 344 * 32bit */ 345 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_BITPOS 0 346 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_MASK 0x1 347 /* 348 **************************************************************************** 349 * @ingroup icp_qat_hw_defs 350 * @description 351 * Enumeration of possible EXTENDED_DELAY_MATCH_MODE field values 352 *****************************************************************************/ 353 typedef enum { 354 ICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_DISABLED = 0x0, 355 /* 0 - EXTENDED_DELAY_MATCH_MODE disabled */ 356 ICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_ENABLED = 0x1, 357 /* 1 - EXTENDED_DELAY_MATCH_MODE enabled */ 358 } icp_qat_hw_comp_20_extended_delay_match_mode_t; 359 360 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_DEFAULT_VAL \ 361 ICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_DISABLED 362 363 /*****************************************************************************/ 364 /* Speculative Decoder Disable (Set By the Driver/ Application), located in 365 * upper 32bit */ 366 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_BITPOS 31 367 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_MASK 0x1 368 /* 369 **************************************************************************** 370 * @ingroup icp_qat_hw_defs 371 * @description 372 * Enumeration of possible SPECULATIVE_DECODER_CONTROL field values 373 *****************************************************************************/ 374 typedef enum { 375 ICP_QAT_HW_DECOMP_20_SPECULATIVE_DECODER_CONTROL_ENABLE = 0x0, 376 /* 0b - Enabled */ 377 ICP_QAT_HW_DECOMP_20_SPECULATIVE_DECODER_CONTROL_DISABLE = 0x1, 378 /* 1b - Disabled */ 379 } icp_qat_hw_decomp_20_speculative_decoder_control_t; 380 381 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_DEFAULT_VAL \ 382 ICP_QAT_HW_DECOMP_20_SPECULATIVE_DECODER_CONTROL_ENABLE 383 384 /*****************************************************************************/ 385 /* Mini CAM Disable (Set By the Driver/ Application), located in upper 32bit */ 386 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_BITPOS 30 387 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_MASK 0x1 388 /* 389 **************************************************************************** 390 * @ingroup icp_qat_hw_defs 391 * @description 392 * Enumeration of possible MINI_CAM_CONTROL field values 393 *****************************************************************************/ 394 typedef enum { 395 ICP_QAT_HW_DECOMP_20_MINI_CAM_CONTROL_ENABLE = 0x0, 396 /* 0b - Enabled */ 397 ICP_QAT_HW_DECOMP_20_MINI_CAM_CONTROL_DISABLE = 0x1, 398 /* 1b - Disabled */ 399 } icp_qat_hw_decomp_20_mini_cam_control_t; 400 401 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_DEFAULT_VAL \ 402 ICP_QAT_HW_DECOMP_20_MINI_CAM_CONTROL_ENABLE 403 404 /*****************************************************************************/ 405 /* History Buffer Size (Set By the Driver/ Application), located in lower 32bit 406 */ 407 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS 14 408 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_MASK 0x7 409 /* 410 **************************************************************************** 411 * @ingroup icp_qat_hw_defs 412 * @description 413 * Enumeration of possible HBS_CONTROL field values 414 *****************************************************************************/ 415 typedef enum { 416 ICP_QAT_HW_DECOMP_20_HBS_CONTROL_HBS_IS_32KB = 0x0, 417 /* 000b - 32KB */ 418 } icp_qat_hw_decomp_20_hbs_control_t; 419 420 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_DEFAULT_VAL \ 421 ICP_QAT_HW_DECOMP_20_HBS_CONTROL_HBS_IS_32KB 422 423 /*****************************************************************************/ 424 /* Decompression Format (Set By Driver/Application. Also See CMD ID), located in 425 * lower 32bit */ 426 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_BITPOS 5 427 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_MASK 0x7 428 /* 429 **************************************************************************** 430 * @ingroup icp_qat_hw_defs 431 * @description 432 * Enumeration of possible HW_DECOMP_FORMAT field values 433 *****************************************************************************/ 434 typedef enum { 435 ICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_DEFLATE = 0x1, 436 /* 001 - Static DEFLATE. (Must set Min_Match = 3 bytes and HB size = 437 32KB.) */ 438 } icp_qat_hw_decomp_20_hw_comp_format_t; 439 440 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_DEFAULT_VAL \ 441 ICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_DEFLATE 442 443 #endif //_ICP_QAT_HW_20_COMP_DEFS_H 444