1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 /* $FreeBSD$ */ 4 /***************************************************************************** 5 * @file icp_accel_devices.h 6 * 7 * @defgroup Acceleration Driver Framework 8 * 9 * @ingroup icp_Adf 10 * 11 * @description 12 * This is the top level header file that contains the layout of the ADF 13 * icp_accel_dev_t structure and related macros/definitions. 14 * It can be used to dereference the icp_accel_dev_t *passed into upper 15 * layers. 16 * 17 *****************************************************************************/ 18 19 #ifndef ICP_ACCEL_DEVICES_H_ 20 #define ICP_ACCEL_DEVICES_H_ 21 22 #include "cpa.h" 23 #include "qat_utils.h" 24 #include "adf_accel_devices.h" 25 26 #define ADF_CFG_NO_INSTANCE 0xFFFFFFFF 27 28 #define ICP_DC_TX_RING_0 6 29 #define ICP_DC_TX_RING_1 7 30 #define ICP_RX_RINGS_OFFSET 8 31 #define ICP_RINGS_PER_BANK 16 32 33 /* Number of worker threads per AE */ 34 #define ICP_ARB_WRK_THREAD_TO_SARB 12 35 #define MAX_ACCEL_NAME_LEN 16 36 #define ADF_DEVICE_NAME_LENGTH 32 37 #define ADF_DEVICE_TYPE_LENGTH 8 38 39 #define ADF_CTL_DEVICE_NAME "/dev/qat_adf_ctl" 40 41 /** 42 ***************************************************************************** 43 * @ingroup icp_AdfAccelHandle 44 * 45 * @description 46 * Accelerator capabilities 47 * 48 *****************************************************************************/ 49 typedef enum { 50 ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = 0x01, 51 ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = 0x02, 52 ICP_ACCEL_CAPABILITIES_CIPHER = 0x04, 53 ICP_ACCEL_CAPABILITIES_AUTHENTICATION = 0x08, 54 ICP_ACCEL_CAPABILITIES_RESERVED_1 = 0x10, 55 ICP_ACCEL_CAPABILITIES_COMPRESSION = 0x20, 56 ICP_ACCEL_CAPABILITIES_DEPRECATED = 0x40, 57 ICP_ACCEL_CAPABILITIES_RANDOM_NUMBER = 0x80, 58 ICP_ACCEL_CAPABILITIES_CRYPTO_ZUC = 0x100, 59 ICP_ACCEL_CAPABILITIES_SHA3 = 0x200, 60 ICP_ACCEL_CAPABILITIES_KPT = 0x400, 61 ICP_ACCEL_CAPABILITIES_RL = 0x800, 62 ICP_ACCEL_CAPABILITIES_HKDF = 0x1000, 63 ICP_ACCEL_CAPABILITIES_ECEDMONT = 0x2000, 64 ICP_ACCEL_CAPABILITIES_EXT_ALGCHAIN = 0x4000, 65 ICP_ACCEL_CAPABILITIES_SHA3_EXT = 0x8000, 66 ICP_ACCEL_CAPABILITIES_AESGCM_SPC = 0x10000, 67 ICP_ACCEL_CAPABILITIES_CHACHA_POLY = 0x20000, 68 ICP_ACCEL_CAPABILITIES_SM2 = 0x40000, 69 ICP_ACCEL_CAPABILITIES_SM3 = 0x80000, 70 ICP_ACCEL_CAPABILITIES_SM4 = 0x100000, 71 ICP_ACCEL_CAPABILITIES_INLINE = 0x200000, 72 ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY = 0x400000, 73 ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64 = 0x800000, 74 ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION = 0x1000000, 75 ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION = 0x2000000, 76 ICP_ACCEL_CAPABILITIES_AES_V2 = 0x4000000, 77 ICP_ACCEL_CAPABILITIES_KPT2 = 0x8000000, 78 } icp_accel_capabilities_t; 79 80 /** 81 ***************************************************************************** 82 * @ingroup icp_AdfAccelHandle 83 * 84 * @description 85 * Device Configuration Data Structure 86 * 87 *****************************************************************************/ 88 89 typedef enum device_type_e { 90 DEVICE_UNKNOWN = 0, 91 DEVICE_DH895XCC, 92 DEVICE_DH895XCCVF, 93 DEVICE_C62X, 94 DEVICE_C62XVF, 95 DEVICE_C3XXX, 96 DEVICE_C3XXXVF, 97 DEVICE_200XX, 98 DEVICE_200XXVF, 99 DEVICE_C4XXX, 100 DEVICE_C4XXXVF, 101 DEVICE_GEN4 102 } device_type_t; 103 104 /* 105 * Enumeration on Service Type 106 */ 107 typedef enum adf_service_type_s { 108 ADF_SERVICE_CRYPTO, 109 ADF_SERVICE_COMPRESS, 110 ADF_SERVICE_MAX /* this is always the last one */ 111 } adf_service_type_t; 112 113 typedef struct accel_dev_s { 114 /* Some generic information */ 115 Cpa32U accelId; 116 Cpa8U *pAccelName; /* Name given to accelerator */ 117 Cpa32U aeMask; /* Acceleration Engine mask */ 118 device_type_t deviceType; /* Device Type */ 119 /* Device name for SAL */ 120 char deviceName[ADF_DEVICE_NAME_LENGTH + 1]; 121 Cpa32U accelCapabilitiesMask; /* Accelerator's capabilities 122 mask */ 123 Cpa32U dcExtendedFeatures; /* bit field of features */ 124 QatUtilsAtomic usageCounter; /* Usage counter. Prevents 125 shutting down the dev if not 0*/ 126 Cpa32U deviceMemAvail; /* Device memory for intermediate buffers */ 127 /* Component specific fields - cast to relevent layer */ 128 void *pRingInflight; /* For offload optimization */ 129 void *pSalHandle; /* For SAL*/ 130 void *pQatStats; /* For QATAL/SAL stats */ 131 void *ringInfoCallBack; /* Callback for user space 132 ring enabling */ 133 void *pShramConstants; /* Virtual address of Shram constants page */ 134 Cpa64U pShramConstantsDma; /* Bus address of Shram constants page */ 135 136 /* Status of ADF and registered subsystems */ 137 Cpa32U adfSubsystemStatus; 138 /* Physical processor to which the dev is connected */ 139 Cpa8U pkg_id; 140 enum dev_sku_info sku; 141 Cpa32U pciDevId; 142 Cpa8U devFileName[ADF_DEVICE_NAME_LENGTH]; 143 Cpa32S csrFileHdl; 144 Cpa32S ringFileHdl; 145 void *accel; 146 147 Cpa32U maxNumBanks; 148 Cpa32U maxNumRingsPerBank; 149 150 /* pointer to dynamic instance resource manager */ 151 void *pInstMgr; 152 void *banks; /* banks information */ 153 struct adf_accel_dev *accel_dev; 154 struct accel_dev_s *pPrev; 155 struct accel_dev_s *pNext; 156 } icp_accel_dev_t; 157 158 #endif /* ICP_ACCEL_HANDLE_H */ 159