1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 #include "adf_accel_devices.h" 4 #include "adf_gen4vf_hw_csr_data.h" 5 6 static u64 7 build_csr_ring_base_addr(dma_addr_t addr, u32 size) 8 { 9 return BUILD_RING_BASE_ADDR_GEN4(addr, size); 10 } 11 12 static u32 13 read_csr_ring_head(struct resource *csr_base_addr, u32 bank, u32 ring) 14 { 15 return READ_CSR_RING_HEAD_GEN4VF(csr_base_addr, bank, ring); 16 } 17 18 static void 19 write_csr_ring_head(struct resource *csr_base_addr, 20 u32 bank, 21 u32 ring, 22 u32 value) 23 { 24 WRITE_CSR_RING_HEAD_GEN4VF(csr_base_addr, bank, ring, value); 25 } 26 27 static u32 28 read_csr_ring_tail(struct resource *csr_base_addr, u32 bank, u32 ring) 29 { 30 return READ_CSR_RING_TAIL_GEN4VF(csr_base_addr, bank, ring); 31 } 32 33 static void 34 write_csr_ring_tail(struct resource *csr_base_addr, 35 u32 bank, 36 u32 ring, 37 u32 value) 38 { 39 WRITE_CSR_RING_TAIL_GEN4VF(csr_base_addr, bank, ring, value); 40 } 41 42 static u32 43 read_csr_e_stat(struct resource *csr_base_addr, u32 bank) 44 { 45 return READ_CSR_E_STAT_GEN4VF(csr_base_addr, bank); 46 } 47 48 static void 49 write_csr_ring_config(struct resource *csr_base_addr, 50 u32 bank, 51 u32 ring, 52 u32 value) 53 { 54 WRITE_CSR_RING_CONFIG_GEN4VF(csr_base_addr, bank, ring, value); 55 } 56 57 static dma_addr_t 58 read_csr_ring_base(struct resource *csr_base_addr, u32 bank, u32 ring) 59 { 60 return READ_CSR_RING_BASE_GEN4VF(csr_base_addr, bank, ring); 61 } 62 63 static void 64 write_csr_ring_base(struct resource *csr_base_addr, 65 u32 bank, 66 u32 ring, 67 dma_addr_t addr) 68 { 69 WRITE_CSR_RING_BASE_GEN4VF(csr_base_addr, bank, ring, addr); 70 } 71 72 static void 73 write_csr_int_flag(struct resource *csr_base_addr, u32 bank, u32 value) 74 { 75 WRITE_CSR_INT_FLAG_GEN4VF(csr_base_addr, bank, value); 76 } 77 78 static void 79 write_csr_int_srcsel(struct resource *csr_base_addr, u32 bank) 80 { 81 WRITE_CSR_INT_SRCSEL_GEN4VF(csr_base_addr, bank); 82 } 83 84 static void 85 write_csr_int_col_en(struct resource *csr_base_addr, u32 bank, u32 value) 86 { 87 WRITE_CSR_INT_COL_EN_GEN4VF(csr_base_addr, bank, value); 88 } 89 90 static void 91 write_csr_int_col_ctl(struct resource *csr_base_addr, u32 bank, u32 value) 92 { 93 WRITE_CSR_INT_COL_CTL_GEN4VF(csr_base_addr, bank, value); 94 } 95 96 static void 97 write_csr_int_flag_and_col(struct resource *csr_base_addr, u32 bank, u32 value) 98 { 99 WRITE_CSR_INT_FLAG_AND_COL_GEN4VF(csr_base_addr, bank, value); 100 } 101 102 static u32 103 read_csr_ring_srv_arb_en(struct resource *csr_base_addr, u32 bank) 104 { 105 return READ_CSR_RING_SRV_ARB_EN_GEN4VF(csr_base_addr, bank); 106 } 107 108 static void 109 write_csr_ring_srv_arb_en(struct resource *csr_base_addr, u32 bank, u32 value) 110 { 111 WRITE_CSR_RING_SRV_ARB_EN_GEN4VF(csr_base_addr, bank, value); 112 } 113 114 static u32 115 get_src_sel_mask(void) 116 { 117 return ADF_BANK_INT_SRC_SEL_MASK_GEN4; 118 } 119 120 static u32 121 get_int_col_ctl_enable_mask(void) 122 { 123 return ADF_RING_CSR_INT_COL_CTL_ENABLE; 124 } 125 126 static u32 127 get_bank_irq_mask(u32 irq_mask) 128 { 129 return 0x1; 130 } 131 132 void 133 gen4vf_init_hw_csr_info(struct adf_hw_csr_info *csr_info) 134 { 135 struct adf_hw_csr_ops *csr_ops = &csr_info->csr_ops; 136 137 csr_info->csr_addr_offset = ADF_RING_CSR_ADDR_OFFSET_GEN4VF; 138 csr_info->ring_bundle_size = ADF_RING_BUNDLE_SIZE_GEN4; 139 csr_info->bank_int_flag_clear_mask = ADF_BANK_INT_FLAG_CLEAR_MASK_GEN4; 140 csr_info->num_rings_per_int_srcsel = ADF_RINGS_PER_INT_SRCSEL_GEN4; 141 csr_info->arb_enable_mask = 0x1; 142 csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr; 143 csr_ops->read_csr_ring_head = read_csr_ring_head; 144 csr_ops->write_csr_ring_head = write_csr_ring_head; 145 csr_ops->read_csr_ring_tail = read_csr_ring_tail; 146 csr_ops->write_csr_ring_tail = write_csr_ring_tail; 147 csr_ops->read_csr_e_stat = read_csr_e_stat; 148 csr_ops->write_csr_ring_config = write_csr_ring_config; 149 csr_ops->read_csr_ring_base = read_csr_ring_base; 150 csr_ops->write_csr_ring_base = write_csr_ring_base; 151 csr_ops->write_csr_int_flag = write_csr_int_flag; 152 csr_ops->write_csr_int_srcsel = write_csr_int_srcsel; 153 csr_ops->write_csr_int_col_en = write_csr_int_col_en; 154 csr_ops->write_csr_int_col_ctl = write_csr_int_col_ctl; 155 csr_ops->write_csr_int_flag_and_col = write_csr_int_flag_and_col; 156 csr_ops->read_csr_ring_srv_arb_en = read_csr_ring_srv_arb_en; 157 csr_ops->write_csr_ring_srv_arb_en = write_csr_ring_srv_arb_en; 158 csr_ops->get_src_sel_mask = get_src_sel_mask; 159 csr_ops->get_int_col_ctl_enable_mask = get_int_col_ctl_enable_mask; 160 csr_ops->get_bank_irq_mask = get_bank_irq_mask; 161 } 162