1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 /* $FreeBSD$ */ 4 #ifndef ADF_200XX_HW_DATA_H_ 5 #define ADF_200XX_HW_DATA_H_ 6 7 /* PCIe configuration space */ 8 #define ADF_200XX_PMISC_BAR 0 9 #define ADF_200XX_ETR_BAR 1 10 #define ADF_200XX_RX_RINGS_OFFSET 8 11 #define ADF_200XX_TX_RINGS_MASK 0xFF 12 #define ADF_200XX_MAX_ACCELERATORS 3 13 #define ADF_200XX_MAX_ACCELENGINES 6 14 #define ADF_200XX_ACCELERATORS_REG_OFFSET 16 15 #define ADF_200XX_ACCELERATORS_MASK 0x7 16 #define ADF_200XX_ACCELENGINES_MASK 0x3F 17 #define ADF_200XX_ETR_MAX_BANKS 16 18 #define ADF_200XX_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28) 19 #define ADF_200XX_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30) 20 #define ADF_200XX_SMIA0_MASK 0xFFFF 21 #define ADF_200XX_SMIA1_MASK 0x1 22 #define ADF_200XX_SOFTSTRAP_CSR_OFFSET 0x2EC 23 #define ADF_200XX_POWERGATE_PKE BIT(24) 24 #define ADF_200XX_POWERGATE_CY BIT(23) 25 26 #define ADF_200XX_PFIEERRUNCSTSR 0x280 27 28 /* Error detection and correction */ 29 #define ADF_200XX_AE_CTX_ENABLES(i) ((i)*0x1000 + 0x20818) 30 #define ADF_200XX_AE_MISC_CONTROL(i) ((i)*0x1000 + 0x20960) 31 #define ADF_200XX_ENABLE_AE_ECC_ERR BIT(28) 32 #define ADF_200XX_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12)) 33 #define ADF_200XX_UERRSSMSH(i) (i * 0x4000 + 0x18) 34 #define ADF_200XX_CERRSSMSH(i) (i * 0x4000 + 0x10) 35 #define ADF_200XX_ERRSSMSH_EN BIT(3) 36 #define ADF_200XX_ERRSOU3 (0x3A000 + 0x0C) 37 #define ADF_200XX_ERRSOU5 (0x3A000 + 0xD8) 38 39 /* BIT(2) enables the logging of push/pull data errors. */ 40 #define ADF_200XX_PPERR_EN (BIT(2)) 41 42 /* Mask for VF2PF interrupts */ 43 #define ADF_200XX_VF2PF1_16 (0xFFFF << 9) 44 #define ADF_200XX_ERRSOU3_VF2PF(errsou3) (((errsou3)&0x01FFFE00) >> 9) 45 #define ADF_200XX_ERRMSK3_VF2PF(vf_mask) (((vf_mask)&0xFFFF) << 9) 46 47 /* Masks for correctable error interrupts. */ 48 #define ADF_200XX_ERRMSK0_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0)) 49 #define ADF_200XX_ERRMSK1_CERR (BIT(8) | BIT(0)) 50 #define ADF_200XX_ERRMSK5_CERR (0) 51 52 /* Masks for uncorrectable error interrupts. */ 53 #define ADF_200XX_ERRMSK0_UERR (BIT(25) | BIT(17) | BIT(9) | BIT(1)) 54 #define ADF_200XX_ERRMSK1_UERR (BIT(9) | BIT(1)) 55 #define ADF_200XX_ERRMSK3_UERR \ 56 (BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(0)) 57 #define ADF_200XX_ERRMSK5_UERR (BIT(16)) 58 59 /* RI CPP control */ 60 #define ADF_200XX_RICPPINTCTL (0x3A000 + 0x110) 61 /* 62 * BIT(2) enables error detection and reporting on the RI Parity Error. 63 * BIT(1) enables error detection and reporting on the RI CPP Pull interface. 64 * BIT(0) enables error detection and reporting on the RI CPP Push interface. 65 */ 66 #define ADF_200XX_RICPP_EN (BIT(2) | BIT(1) | BIT(0)) 67 68 /* TI CPP control */ 69 #define ADF_200XX_TICPPINTCTL (0x3A400 + 0x138) 70 /* 71 * BIT(3) enables error detection and reporting on the ETR Parity Error. 72 * BIT(2) enables error detection and reporting on the TI Parity Error. 73 * BIT(1) enables error detection and reporting on the TI CPP Pull interface. 74 * BIT(0) enables error detection and reporting on the TI CPP Push interface. 75 */ 76 #define ADF_200XX_TICPP_EN (BIT(3) | BIT(2) | BIT(1) | BIT(0)) 77 78 /* CFC Uncorrectable Errors */ 79 #define ADF_200XX_CPP_CFC_ERR_CTRL (0x30000 + 0xC00) 80 /* 81 * BIT(1) enables interrupt. 82 * BIT(0) enables detecting and logging of push/pull data errors. 83 */ 84 #define ADF_200XX_CPP_CFC_UE (BIT(1) | BIT(0)) 85 86 #define ADF_200XX_SLICEPWRDOWN(i) ((i)*0x4000 + 0x2C) 87 /* Enabling PKE4-PKE0. */ 88 #define ADF_200XX_MMP_PWR_UP_MSK \ 89 (BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16)) 90 91 /* CPM Uncorrectable Errors */ 92 #define ADF_200XX_INTMASKSSM(i) ((i)*0x4000 + 0x0) 93 /* Disabling interrupts for correctable errors. */ 94 #define ADF_200XX_INTMASKSSM_UERR \ 95 (BIT(11) | BIT(9) | BIT(7) | BIT(5) | BIT(3) | BIT(1)) 96 97 /* MMP */ 98 /* BIT(3) enables correction. */ 99 #define ADF_200XX_CERRSSMMMP_EN (BIT(3)) 100 101 /* BIT(3) enables logging. */ 102 #define ADF_200XX_UERRSSMMMP_EN (BIT(3)) 103 104 #define ADF_200XX_PF2VF_OFFSET(i) (0x3A000 + 0x280 + ((i)*0x04)) 105 #define ADF_200XX_VINTMSK_OFFSET(i) (0x3A000 + 0x200 + ((i)*0x04)) 106 107 /* Arbiter configuration */ 108 #define ADF_200XX_ARB_OFFSET 0x30000 109 #define ADF_200XX_ARB_WRK_2_SER_MAP_OFFSET 0x180 110 #define ADF_200XX_ARB_WQCFG_OFFSET 0x100 111 112 /* Admin Interface Reg Offset */ 113 #define ADF_200XX_ADMINMSGUR_OFFSET (0x3A000 + 0x574) 114 #define ADF_200XX_ADMINMSGLR_OFFSET (0x3A000 + 0x578) 115 #define ADF_200XX_MAILBOX_BASE_OFFSET 0x20970 116 117 /* Firmware Binary */ 118 #define ADF_200XX_FW "qat_200xx_fw" 119 #define ADF_200XX_MMP "qat_200xx_mmp_fw" 120 121 void adf_init_hw_data_200xx(struct adf_hw_device_data *hw_data); 122 void adf_clean_hw_data_200xx(struct adf_hw_device_data *hw_data); 123 124 #define ADF_200XX_AE_FREQ (685 * 1000000) 125 #define ADF_200XX_MIN_AE_FREQ (333 * 1000000) 126 #define ADF_200XX_MAX_AE_FREQ (685 * 1000000) 127 128 #endif 129