1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007 - 2022 Intel Corporation */
3 /* $FreeBSD$ */
4 #ifndef ADF_4XXX_HW_DATA_H_
5 #define ADF_4XXX_HW_DATA_H_
6 
7 #include <adf_accel_devices.h>
8 
9 /* PCIe configuration space */
10 #define ADF_4XXX_SRAM_BAR 0
11 #define ADF_4XXX_PMISC_BAR 1
12 #define ADF_4XXX_ETR_BAR 2
13 #define ADF_4XXX_RX_RINGS_OFFSET 1
14 #define ADF_4XXX_TX_RINGS_MASK 0x1
15 #define ADF_4XXX_MAX_ACCELERATORS 1
16 #define ADF_4XXX_MAX_ACCELENGINES 9
17 #define ADF_4XXX_BAR_MASK (BIT(0) | BIT(2) | BIT(4))
18 
19 /* 2 Accel units dedicated to services and */
20 /* 1 Accel unit dedicated to Admin AE */
21 #define ADF_4XXX_MAX_ACCELUNITS 3
22 
23 /* Physical function fuses */
24 #define ADF_4XXX_FUSECTL0_OFFSET (0x2C8)
25 #define ADF_4XXX_FUSECTL1_OFFSET (0x2CC)
26 #define ADF_4XXX_FUSECTL2_OFFSET (0x2D0)
27 #define ADF_4XXX_FUSECTL3_OFFSET (0x2D4)
28 #define ADF_4XXX_FUSECTL4_OFFSET (0x2D8)
29 #define ADF_4XXX_FUSECTL5_OFFSET (0x2DC)
30 
31 #define ADF_4XXX_ACCELERATORS_MASK (0x1)
32 #define ADF_4XXX_ACCELENGINES_MASK (0x1FF)
33 #define ADF_4XXX_ADMIN_AE_MASK (0x100)
34 
35 #define ADF_4XXX_ETR_MAX_BANKS 64
36 
37 /* MSIX interrupt */
38 #define ADF_4XXX_SMIAPF_RP_X0_MASK_OFFSET (0x41A040)
39 #define ADF_4XXX_SMIAPF_RP_X1_MASK_OFFSET (0x41A044)
40 #define ADF_4XXX_SMIAPF_MASK_OFFSET (0x41A084)
41 #define ADF_4XXX_MSIX_RTTABLE_OFFSET(i) (0x409000 + ((i)*0x04))
42 
43 /* Bank and ring configuration */
44 #define ADF_4XXX_NUM_RINGS_PER_BANK 2
45 
46 /* Error source registers */
47 #define ADF_4XXX_ERRSOU0 (0x41A200)
48 #define ADF_4XXX_ERRSOU1 (0x41A204)
49 #define ADF_4XXX_ERRSOU2 (0x41A208)
50 #define ADF_4XXX_ERRSOU3 (0x41A20C)
51 
52 /* Error source mask registers */
53 #define ADF_4XXX_ERRMSK0 (0x41A210)
54 #define ADF_4XXX_ERRMSK1 (0x41A214)
55 #define ADF_4XXX_ERRMSK2 (0x41A218)
56 #define ADF_4XXX_ERRMSK3 (0x41A21C)
57 
58 #define ADF_4XXX_VFLNOTIFY BIT(7)
59 
60 /* Arbiter configuration */
61 #define ADF_4XXX_ARB_CONFIG (BIT(31) | BIT(6) | BIT(0))
62 #define ADF_4XXX_ARB_OFFSET (0x0)
63 #define ADF_4XXX_ARB_WRK_2_SER_MAP_OFFSET (0x400)
64 
65 /* Admin Interface Reg Offset */
66 #define ADF_4XXX_ADMINMSGUR_OFFSET (0x500574)
67 #define ADF_4XXX_ADMINMSGLR_OFFSET (0x500578)
68 #define ADF_4XXX_MAILBOX_BASE_OFFSET (0x600970)
69 
70 /* Power management */
71 #define ADF_4XXX_PM_POLL_DELAY_US 20
72 #define ADF_4XXX_PM_POLL_TIMEOUT_US USEC_PER_SEC
73 #define ADF_4XXX_PM_STATUS (0x50A00C)
74 #define ADF_4XXX_PM_INTERRUPT (0x50A028)
75 #define ADF_4XXX_PM_DRV_ACTIVE BIT(20)
76 #define ADF_4XXX_PM_INIT_STATE BIT(21)
77 /* Power management source in ERRSOU2 and ERRMSK2 */
78 #define ADF_4XXX_PM_SOU BIT(18)
79 
80 /* Firmware Binaries */
81 #define ADF_4XXX_FW "qat_4xxx_fw"
82 #define ADF_4XXX_MMP "qat_4xxx_mmp_fw"
83 #define ADF_4XXX_DC_OBJ "qat_4xxx_dc.bin"
84 #define ADF_4XXX_SYM_OBJ "qat_4xxx_sym.bin"
85 #define ADF_4XXX_ASYM_OBJ "qat_4xxx_asym.bin"
86 #define ADF_4XXX_ADMIN_OBJ "qat_4xxx_admin.bin"
87 
88 /* Only 3 types of images can be loaded including the admin image */
89 #define ADF_4XXX_MAX_OBJ 3
90 
91 #define ADF_4XXX_AE_FREQ (1000 * 1000000)
92 #define ADF_4XXX_KPT_COUNTER_FREQ (100 * 1000000)
93 
94 #define ADF_4XXX_MIN_AE_FREQ (9 * 1000000)
95 #define ADF_4XXX_MAX_AE_FREQ (1100 * 1000000)
96 
97 /* qat_4xxx fuse bits are different from old GENs, redefine them */
98 enum icp_qat_4xxx_slice_mask {
99 	ICP_ACCEL_4XXX_MASK_CIPHER_SLICE = BIT(0),
100 	ICP_ACCEL_4XXX_MASK_AUTH_SLICE = BIT(1),
101 	ICP_ACCEL_4XXX_MASK_PKE_SLICE = BIT(2),
102 	ICP_ACCEL_4XXX_MASK_COMPRESS_SLICE = BIT(3),
103 	ICP_ACCEL_4XXX_MASK_UCS_SLICE = BIT(4),
104 	ICP_ACCEL_4XXX_MASK_EIA3_SLICE = BIT(5),
105 	ICP_ACCEL_4XXX_MASK_SMX_SLICE = BIT(6),
106 };
107 
108 void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data);
109 void adf_clean_hw_data_4xxx(struct adf_hw_device_data *hw_data);
110 
111 #endif
112