1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 /* $FreeBSD$ */ 4 #ifndef ADF_C3XXX_HW_DATA_H_ 5 #define ADF_C3XXX_HW_DATA_H_ 6 7 /* PCIe configuration space */ 8 #define ADF_C3XXX_PMISC_BAR 0 9 #define ADF_C3XXX_ETR_BAR 1 10 #define ADF_C3XXX_RX_RINGS_OFFSET 8 11 #define ADF_C3XXX_TX_RINGS_MASK 0xFF 12 #define ADF_C3XXX_MAX_ACCELERATORS 3 13 #define ADF_C3XXX_MAX_ACCELENGINES 6 14 #define ADF_C3XXX_ACCELERATORS_REG_OFFSET 16 15 #define ADF_C3XXX_ACCELERATORS_MASK 0x7 16 #define ADF_C3XXX_ACCELENGINES_MASK 0x3F 17 #define ADF_C3XXX_ETR_MAX_BANKS 16 18 #define ADF_C3XXX_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28) 19 #define ADF_C3XXX_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30) 20 #define ADF_C3XXX_SMIA0_MASK 0xFFFF 21 #define ADF_C3XXX_SMIA1_MASK 0x1 22 #define ADF_C3XXX_SOFTSTRAP_CSR_OFFSET 0x2EC 23 #define ADF_C3XXX_POWERGATE_PKE BIT(24) 24 #define ADF_C3XXX_POWERGATE_CY BIT(23) 25 26 /* Error detection and correction */ 27 #define ADF_C3XXX_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818) 28 #define ADF_C3XXX_AE_MISC_CONTROL(i) (i * 0x1000 + 0x20960) 29 #define ADF_C3XXX_ENABLE_AE_ECC_ERR BIT(28) 30 #define ADF_C3XXX_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12)) 31 #define ADF_C3XXX_UERRSSMSH(i) (i * 0x4000 + 0x18) 32 #define ADF_C3XXX_CERRSSMSH(i) (i * 0x4000 + 0x10) 33 #define ADF_C3XXX_ERRSSMSH_EN BIT(3) 34 #define ADF_C3XXX_ERRSOU3 (0x3A000 + 0x0C) 35 #define ADF_C3XXX_ERRSOU5 (0x3A000 + 0xD8) 36 37 /* BIT(2) enables the logging of push/pull data errors. */ 38 #define ADF_C3XXX_PPERR_EN (BIT(2)) 39 40 /* Mask for VF2PF interrupts */ 41 #define ADF_C3XXX_VF2PF1_16 (0xFFFF << 9) 42 #define ADF_C3XXX_ERRSOU3_VF2PF(errsou3) (((errsou3)&0x01FFFE00) >> 9) 43 #define ADF_C3XXX_ERRMSK3_VF2PF(vf_mask) (((vf_mask)&0xFFFF) << 9) 44 45 /* Masks for correctable error interrupts. */ 46 #define ADF_C3XXX_ERRMSK0_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0)) 47 #define ADF_C3XXX_ERRMSK1_CERR (BIT(8) | BIT(0)) 48 #define ADF_C3XXX_ERRMSK5_CERR (0) 49 50 /* Masks for uncorrectable error interrupts. */ 51 #define ADF_C3XXX_ERRMSK0_UERR (BIT(25) | BIT(17) | BIT(9) | BIT(1)) 52 #define ADF_C3XXX_ERRMSK1_UERR (BIT(9) | BIT(1)) 53 #define ADF_C3XXX_ERRMSK3_UERR \ 54 (BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(0)) 55 #define ADF_C3XXX_ERRMSK5_UERR (BIT(16)) 56 57 /* RI CPP control */ 58 #define ADF_C3XXX_RICPPINTCTL (0x3A000 + 0x110) 59 /* 60 * BIT(2) enables error detection and reporting on the RI Parity Error. 61 * BIT(1) enables error detection and reporting on the RI CPP Pull interface. 62 * BIT(0) enables error detection and reporting on the RI CPP Push interface. 63 */ 64 #define ADF_C3XXX_RICPP_EN (BIT(2) | BIT(1) | BIT(0)) 65 66 /* TI CPP control */ 67 #define ADF_C3XXX_TICPPINTCTL (0x3A400 + 0x138) 68 /* 69 * BIT(3) enables error detection and reporting on the ETR Parity Error. 70 * BIT(2) enables error detection and reporting on the TI Parity Error. 71 * BIT(1) enables error detection and reporting on the TI CPP Pull interface. 72 * BIT(0) enables error detection and reporting on the TI CPP Push interface. 73 */ 74 #define ADF_C3XXX_TICPP_EN (BIT(3) | BIT(2) | BIT(1) | BIT(0)) 75 76 /* CFC Uncorrectable Errors */ 77 #define ADF_C3XXX_CPP_CFC_ERR_CTRL (0x30000 + 0xC00) 78 /* 79 * BIT(1) enables interrupt. 80 * BIT(0) enables detecting and logging of push/pull data errors. 81 */ 82 #define ADF_C3XXX_CPP_CFC_UE (BIT(1) | BIT(0)) 83 84 #define ADF_C3XXX_SLICEPWRDOWN(i) ((i)*0x4000 + 0x2C) 85 /* Enabling PKE4-PKE0. */ 86 #define ADF_C3XXX_MMP_PWR_UP_MSK \ 87 (BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16)) 88 89 /* CPM Uncorrectable Errors */ 90 #define ADF_C3XXX_INTMASKSSM(i) ((i)*0x4000 + 0x0) 91 /* Disabling interrupts for correctable errors. */ 92 #define ADF_C3XXX_INTMASKSSM_UERR \ 93 (BIT(11) | BIT(9) | BIT(7) | BIT(5) | BIT(3) | BIT(1)) 94 95 /* MMP */ 96 /* BIT(3) enables correction. */ 97 #define ADF_C3XXX_CERRSSMMMP_EN (BIT(3)) 98 99 #define ADF_C3X_CLK_PER_SEC (343 * 1000000) 100 /* BIT(3) enables logging. */ 101 #define ADF_C3XXX_UERRSSMMMP_EN (BIT(3)) 102 103 #define ADF_C3XXX_PF2VF_OFFSET(i) (0x3A000 + 0x280 + ((i)*0x04)) 104 #define ADF_C3XXX_VINTMSK_OFFSET(i) (0x3A000 + 0x200 + ((i)*0x04)) 105 106 /* Arbiter configuration */ 107 #define ADF_C3XXX_ARB_OFFSET 0x30000 108 #define ADF_C3XXX_ARB_WRK_2_SER_MAP_OFFSET 0x180 109 #define ADF_C3XXX_ARB_WQCFG_OFFSET 0x100 110 111 /* Admin Interface Reg Offset */ 112 #define ADF_C3XXX_ADMINMSGUR_OFFSET (0x3A000 + 0x574) 113 #define ADF_C3XXX_ADMINMSGLR_OFFSET (0x3A000 + 0x578) 114 #define ADF_C3XXX_MAILBOX_BASE_OFFSET 0x20970 115 116 /* Firmware Binary */ 117 #define ADF_C3XXX_FW "qat_c3xxx_fw" 118 #define ADF_C3XXX_MMP "qat_c3xxx_mmp_fw" 119 120 void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data); 121 void adf_clean_hw_data_c3xxx(struct adf_hw_device_data *hw_data); 122 123 #define ADF_C3XXX_AE_FREQ (685 * 1000000) 124 #define ADF_C3XXX_MIN_AE_FREQ (320 * 1000000) 125 #define ADF_C3XXX_MAX_AE_FREQ (685 * 1000000) 126 127 #endif 128