1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 /* $FreeBSD$ */ 4 #ifndef ADF_C4XXX_HW_DATA_H_ 5 #define ADF_C4XXX_HW_DATA_H_ 6 7 #include <adf_accel_devices.h> 8 9 /* PCIe configuration space */ 10 #define ADF_C4XXX_SRAM_BAR 0 11 #define ADF_C4XXX_PMISC_BAR 1 12 #define ADF_C4XXX_ETR_BAR 2 13 #define ADF_C4XXX_RX_RINGS_OFFSET 4 14 #define ADF_C4XXX_TX_RINGS_MASK 0xF 15 16 #define ADF_C4XXX_MAX_ACCELERATORS 12 17 #define ADF_C4XXX_MAX_ACCELUNITS 6 18 #define ADF_C4XXX_MAX_ACCELENGINES 32 19 #define ADF_C4XXX_ACCELERATORS_REG_OFFSET 16 20 21 /* Soft straps offsets */ 22 #define ADF_C4XXX_SOFTSTRAPPULL0_OFFSET (0x344) 23 #define ADF_C4XXX_SOFTSTRAPPULL1_OFFSET (0x348) 24 #define ADF_C4XXX_SOFTSTRAPPULL2_OFFSET (0x34C) 25 26 /* Physical function fuses offsets */ 27 #define ADF_C4XXX_FUSECTL0_OFFSET (0x350) 28 #define ADF_C4XXX_FUSECTL1_OFFSET (0x354) 29 #define ADF_C4XXX_FUSECTL2_OFFSET (0x358) 30 31 #define ADF_C4XXX_FUSE_PKE_MASK (0xFFF000) 32 #define ADF_C4XXX_FUSE_COMP_MASK (0x000FFF) 33 #define ADF_C4XXX_FUSE_PROD_SKU_MASK BIT(31) 34 35 #define ADF_C4XXX_LEGFUSE_BASE_SKU_MASK (BIT(2) | BIT(3)) 36 37 #define ADF_C4XXX_FUSE_DISABLE_INLINE_INGRESS BIT(12) 38 #define ADF_C4XXX_FUSE_DISABLE_INLINE_EGRESS BIT(13) 39 #define ADF_C4XXX_FUSE_DISABLE_INLINE_MASK \ 40 (ADF_C4XXX_FUSE_DISABLE_INLINE_INGRESS | \ 41 ADF_C4XXX_FUSE_DISABLE_INLINE_EGRESS) 42 43 #define ADF_C4XXX_ACCELERATORS_MASK (0xFFF) 44 #define ADF_C4XXX_ACCELENGINES_MASK (0xFFFFFFFF) 45 46 #define ADF_C4XXX_ETR_MAX_BANKS 128 47 #define ADF_C4XXX_SMIAPF0_MASK_OFFSET (0x60000 + 0x20) 48 #define ADF_C4XXX_SMIAPF1_MASK_OFFSET (0x60000 + 0x24) 49 #define ADF_C4XXX_SMIAPF2_MASK_OFFSET (0x60000 + 0x28) 50 #define ADF_C4XXX_SMIAPF3_MASK_OFFSET (0x60000 + 0x2C) 51 #define ADF_C4XXX_SMIAPF4_MASK_OFFSET (0x60000 + 0x30) 52 #define ADF_C4XXX_SMIA0_MASK 0xFFFFFFFF 53 #define ADF_C4XXX_SMIA1_MASK 0xFFFFFFFF 54 #define ADF_C4XXX_SMIA2_MASK 0xFFFFFFFF 55 #define ADF_C4XXX_SMIA3_MASK 0xFFFFFFFF 56 #define ADF_C4XXX_SMIA4_MASK 0x1 57 /* Bank and ring configuration */ 58 #define ADF_C4XXX_NUM_RINGS_PER_BANK 8 59 /* Error detection and correction */ 60 #define ADF_C4XXX_AE_CTX_ENABLES(i) (0x40818 + ((i)*0x1000)) 61 #define ADF_C4XXX_AE_MISC_CONTROL(i) (0x40960 + ((i)*0x1000)) 62 #define ADF_C4XXX_ENABLE_AE_ECC_ERR BIT(28) 63 #define ADF_C4XXX_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12)) 64 #define ADF_C4XXX_UERRSSMSH(i) (0x18 + ((i)*0x4000)) 65 #define ADF_C4XXX_UERRSSMSH_INTS_CLEAR_MASK (~BIT(0) ^ BIT(16)) 66 #define ADF_C4XXX_CERRSSMSH(i) (0x10 + ((i)*0x4000)) 67 #define ADF_C4XXX_CERRSSMSH_INTS_CLEAR_MASK (~BIT(0)) 68 #define ADF_C4XXX_ERRSSMSH_EN BIT(3) 69 #define ADF_C4XXX_PF2VF_OFFSET(i) (0x62400 + ((i)*0x04)) 70 #define ADF_C4XXX_VINTMSK_OFFSET(i) (0x62200 + ((i)*0x04)) 71 72 /* Doorbell interrupt detection in ERRSOU11 */ 73 #define ADF_C4XXX_DOORBELL_INT_SRC BIT(10) 74 75 /* Doorbell interrupt register definitions */ 76 #define ADF_C4XXX_ETH_DOORBELL_INT (0x60108) 77 78 /* Clear <3:0> in ETH_DOORBELL_INT */ 79 #define ADF_C4XXX_ETH_DOORBELL_MASK 0xF 80 81 /* Doorbell register definitions */ 82 #define ADF_C4XXX_NUM_ETH_DOORBELL_REGS (4) 83 #define ADF_C4XXX_ETH_DOORBELL(i) (0x61500 + ((i)*0x04)) 84 85 /* Error source registers */ 86 #define ADF_C4XXX_ERRSOU0 (0x60000 + 0x40) 87 #define ADF_C4XXX_ERRSOU1 (0x60000 + 0x44) 88 #define ADF_C4XXX_ERRSOU2 (0x60000 + 0x48) 89 #define ADF_C4XXX_ERRSOU3 (0x60000 + 0x4C) 90 #define ADF_C4XXX_ERRSOU4 (0x60000 + 0x50) 91 #define ADF_C4XXX_ERRSOU5 (0x60000 + 0x54) 92 #define ADF_C4XXX_ERRSOU6 (0x60000 + 0x58) 93 #define ADF_C4XXX_ERRSOU7 (0x60000 + 0x5C) 94 #define ADF_C4XXX_ERRSOU8 (0x60000 + 0x60) 95 #define ADF_C4XXX_ERRSOU9 (0x60000 + 0x64) 96 #define ADF_C4XXX_ERRSOU10 (0x60000 + 0x68) 97 #define ADF_C4XXX_ERRSOU11 (0x60000 + 0x6C) 98 99 /* Error source mask registers */ 100 #define ADF_C4XXX_ERRMSK0 (0x60000 + 0xC0) 101 #define ADF_C4XXX_ERRMSK1 (0x60000 + 0xC4) 102 #define ADF_C4XXX_ERRMSK2 (0x60000 + 0xC8) 103 #define ADF_C4XXX_ERRMSK3 (0x60000 + 0xCC) 104 #define ADF_C4XXX_ERRMSK4 (0x60000 + 0xD0) 105 #define ADF_C4XXX_ERRMSK5 (0x60000 + 0xD4) 106 #define ADF_C4XXX_ERRMSK6 (0x60000 + 0xD8) 107 #define ADF_C4XXX_ERRMSK7 (0x60000 + 0xDC) 108 #define ADF_C4XXX_ERRMSK8 (0x60000 + 0xE0) 109 #define ADF_C4XXX_ERRMSK9 (0x60000 + 0xE4) 110 #define ADF_C4XXX_ERRMSK10 (0x60000 + 0xE8) 111 #define ADF_C4XXX_ERRMSK11 (0x60000 + 0xEC) 112 113 /* Slice Hang enabling related registers */ 114 #define ADF_C4XXX_SHINTMASKSSM (0x1018) 115 #define ADF_C4XXX_SSMWDTL (0x54) 116 #define ADF_C4XXX_SSMWDTH (0x5C) 117 #define ADF_C4XXX_SSMWDTPKEL (0x58) 118 #define ADF_C4XXX_SSMWDTPKEH (0x60) 119 #define ADF_C4XXX_SLICEHANGSTATUS (0x4C) 120 #define ADF_C4XXX_IASLICEHANGSTATUS (0x50) 121 122 #define ADF_C4XXX_SHINTMASKSSM_VAL (0x00) 123 124 /* Set default value of Slice Hang watchdogs in clock cycles */ 125 #define ADF_C4XXX_SSM_WDT_64BIT_DEFAULT_VALUE 0x3D0900 126 #define ADF_C4XXX_SSM_WDT_PKE_64BIT_DEFAULT_VALUE 0x3000000 127 128 /* Return interrupt accelerator source mask */ 129 #define ADF_C4XXX_IRQ_SRC_MASK(accel) (1 << (accel)) 130 131 /* Return address of SHINTMASKSSM register for a given accelerator */ 132 #define ADF_C4XXX_SHINTMASKSSM_OFFSET(accel) \ 133 (ADF_C4XXX_SHINTMASKSSM + ((accel)*0x4000)) 134 135 /* Return address of SSMWDTL register for a given accelerator */ 136 #define ADF_C4XXX_SSMWDTL_OFFSET(accel) (ADF_C4XXX_SSMWDTL + ((accel)*0x4000)) 137 138 /* Return address of SSMWDTH register for a given accelerator */ 139 #define ADF_C4XXX_SSMWDTH_OFFSET(accel) (ADF_C4XXX_SSMWDTH + ((accel)*0x4000)) 140 141 /* Return address of SSMWDTPKEL register for a given accelerator */ 142 #define ADF_C4XXX_SSMWDTPKEL_OFFSET(accel) \ 143 (ADF_C4XXX_SSMWDTPKEL + ((accel)*0x4000)) 144 145 /* Return address of SSMWDTPKEH register for a given accelerator */ 146 #define ADF_C4XXX_SSMWDTPKEH_OFFSET(accel) \ 147 (ADF_C4XXX_SSMWDTPKEH + ((accel)*0x4000)) 148 149 /* Return address of SLICEHANGSTATUS register for a given accelerator */ 150 #define ADF_C4XXX_SLICEHANGSTATUS_OFFSET(accel) \ 151 (ADF_C4XXX_SLICEHANGSTATUS + ((accel)*0x4000)) 152 153 /* Return address of IASLICEHANGSTATUS register for a given accelerator */ 154 #define ADF_C4XXX_IASLICEHANGSTATUS_OFFSET(accel) \ 155 (ADF_C4XXX_IASLICEHANGSTATUS + ((accel)*0x4000)) 156 157 /* RAS enabling related registers */ 158 #define ADF_C4XXX_SSMFEATREN (0x2010) 159 #define ADF_C4XXX_SSMSOFTERRORPARITY_MASK (0x1008) 160 161 /* Return address of SSMFEATREN register for given accel */ 162 #define ADF_C4XXX_GET_SSMFEATREN_OFFSET(accel) \ 163 (ADF_C4XXX_SSMFEATREN + ((accel)*0x4000)) 164 165 /* Return address of SSMSOFTERRORPARITY_MASK register for given accel */ 166 #define ADF_C4XXX_GET_SSMSOFTERRORPARITY_MASK_OFFSET(accel) \ 167 (ADF_C4XXX_SSMSOFTERRORPARITY_MASK + ((accel)*0x4000)) 168 169 /* RAS enabling related registers values to be written */ 170 #define ADF_C4XXX_SSMFEATREN_VAL (0xFD) 171 #define ADF_C4XXX_SSMSOFTERRORPARITY_MASK_VAL (0x00) 172 173 /* Enable VF2PF interrupt in ERRMSK4 to ERRMSK7 */ 174 #define ADF_C4XXX_VF2PF0_31 0x0 175 #define ADF_C4XXX_VF2PF32_63 0x0 176 #define ADF_C4XXX_VF2PF64_95 0x0 177 #define ADF_C4XXX_VF2PF96_127 0x0 178 179 /* AEx Correctable Error Mask in ERRMSK8 */ 180 #define ADF_C4XXX_ERRMSK8_COERR 0x0 181 #define ADF_C4XXX_ERRSOU8_MECORR_MASK BIT(0) 182 #define ADF_C4XXX_HI_ME_COR_ERRLOG (0x60104) 183 #define ADF_C4XXX_HI_ME_COR_ERRLOG_ENABLE (0x61600) 184 #define ADF_C4XXX_HI_ME_COR_ERRLOG_ENABLE_MASK (0xFFFFFFFF) 185 #define ADF_C4XXX_HI_ME_COR_ERRLOG_SIZE_IN_BITS (32) 186 187 /* Group of registers related to ERRSOU9 handling 188 * 189 * AEx Uncorrectable Error Mask in ERRMSK9 190 * CPP Command Parity Errors Mask in ERRMSK9 191 * RI Memory Parity Errors Mask in ERRMSK9 192 * TI Memory Parity Errors Mask in ERRMSK9 193 */ 194 #define ADF_C4XXX_ERRMSK9_IRQ_MASK 0x0 195 #define ADF_C4XXX_ME_UNCORR_ERROR BIT(0) 196 #define ADF_C4XXX_CPP_CMD_PAR_ERR BIT(1) 197 #define ADF_C4XXX_RI_MEM_PAR_ERR BIT(2) 198 #define ADF_C4XXX_TI_MEM_PAR_ERR BIT(3) 199 200 #define ADF_C4XXX_ERRSOU9_ERROR_MASK \ 201 (ADF_C4XXX_ME_UNCORR_ERROR | ADF_C4XXX_CPP_CMD_PAR_ERR | \ 202 ADF_C4XXX_RI_MEM_PAR_ERR | ADF_C4XXX_TI_MEM_PAR_ERR) 203 204 #define ADF_C4XXX_HI_ME_UNCERR_LOG (0x60100) 205 #define ADF_C4XXX_HI_ME_UNCERR_LOG_ENABLE (0x61608) 206 #define ADF_C4XXX_HI_ME_UNCERR_LOG_ENABLE_MASK (0xFFFFFFFF) 207 #define ADF_C4XXX_HI_ME_UNCOR_ERRLOG_BITS (32) 208 209 /* HI CPP Agents Command parity Error Log 210 * CSR name: hicppagentcmdparerrlog 211 */ 212 #define ADF_C4XXX_HI_CPP_AGENT_CMD_PAR_ERR_LOG (0x6010C) 213 #define ADF_C4XXX_HI_CPP_AGENT_CMD_PAR_ERR_LOG_ENABLE (0x61604) 214 #define ADF_C4XXX_HI_CPP_AGENT_CMD_PAR_ERR_LOG_ENABLE_MASK (0xFFFFFFFF) 215 #define ADF_C4XXX_TI_CMD_PAR_ERR BIT(0) 216 #define ADF_C4XXX_RI_CMD_PAR_ERR BIT(1) 217 #define ADF_C4XXX_ICI_CMD_PAR_ERR BIT(2) 218 #define ADF_C4XXX_ICE_CMD_PAR_ERR BIT(3) 219 #define ADF_C4XXX_ARAM_CMD_PAR_ERR BIT(4) 220 #define ADF_C4XXX_CFC_CMD_PAR_ERR BIT(5) 221 #define ADF_C4XXX_SSM_CMD_PAR_ERR(value) (((u32)(value) >> 6) & 0xFFF) 222 223 /* RI Memory Parity Error Status Register 224 * CSR name: rimem_parerr_sts 225 */ 226 #define ADF_C4XXX_RI_MEM_PAR_ERR_STS (0x61610) 227 #define ADF_C4XXX_RI_MEM_PAR_ERR_EN0 (0x61614) 228 #define ADF_C4XXX_RI_MEM_PAR_ERR_FERR (0x61618) 229 #define ADF_C4XXX_RI_MEM_PAR_ERR_EN0_MASK (0x7FFFFF) 230 #define ADF_C4XXX_RI_MEM_MSIX_TBL_INT_MASK (BIT(22)) 231 #define ADF_C4XXX_RI_MEM_PAR_ERR_STS_MASK \ 232 (ADF_C4XXX_RI_MEM_PAR_ERR_EN0_MASK ^ ADF_C4XXX_RI_MEM_MSIX_TBL_INT_MASK) 233 234 /* TI Memory Parity Error Status Register 235 * CSR name: ti_mem_par_err_sts0, ti_mem_par_err_sts1 236 */ 237 #define ADF_C4XXX_TI_MEM_PAR_ERR_STS0 (0x68604) 238 #define ADF_C4XXX_TI_MEM_PAR_ERR_EN0 (0x68608) 239 #define ADF_C4XXX_TI_MEM_PAR_ERR_EN0_MASK (0xFFFFFFFF) 240 #define ADF_C4XXX_TI_MEM_PAR_ERR_STS1 (0x68610) 241 #define ADF_C4XXX_TI_MEM_PAR_ERR_EN1 (0x68614) 242 #define ADF_C4XXX_TI_MEM_PAR_ERR_EN1_MASK (0x7FFFF) 243 #define ADF_C4XXX_TI_MEM_PAR_ERR_STS1_MASK (ADF_C4XXX_TI_MEM_PAR_ERR_EN1_MASK) 244 #define ADF_C4XXX_TI_MEM_PAR_ERR_FIRST_ERROR (0x68618) 245 246 /* Enable SSM<11:0> in ERRMSK10 */ 247 #define ADF_C4XXX_ERRMSK10_SSM_ERR 0x0 248 #define ADF_C4XXX_ERRSOU10_RAS_MASK 0x1FFF 249 #define ADF_C4XXX_ERRSOU10_PUSHPULL_MASK BIT(12) 250 251 #define ADF_C4XXX_IASTATSSM_UERRSSMSH_MASK BIT(0) 252 #define ADF_C4XXX_IASTATSSM_CERRSSMSH_MASK BIT(1) 253 #define ADF_C4XXX_IASTATSSM_UERRSSMMMP0_MASK BIT(2) 254 #define ADF_C4XXX_IASTATSSM_CERRSSMMMP0_MASK BIT(3) 255 #define ADF_C4XXX_IASTATSSM_UERRSSMMMP1_MASK BIT(4) 256 #define ADF_C4XXX_IASTATSSM_CERRSSMMMP1_MASK BIT(5) 257 #define ADF_C4XXX_IASTATSSM_UERRSSMMMP2_MASK BIT(6) 258 #define ADF_C4XXX_IASTATSSM_CERRSSMMMP2_MASK BIT(7) 259 #define ADF_C4XXX_IASTATSSM_UERRSSMMMP3_MASK BIT(8) 260 #define ADF_C4XXX_IASTATSSM_CERRSSMMMP3_MASK BIT(9) 261 #define ADF_C4XXX_IASTATSSM_UERRSSMMMP4_MASK BIT(10) 262 #define ADF_C4XXX_IASTATSSM_CERRSSMMMP4_MASK BIT(11) 263 #define ADF_C4XXX_IASTATSSM_PPERR_MASK BIT(12) 264 #define ADF_C4XXX_IASTATSSM_SPPPAR_ERR_MASK BIT(14) 265 #define ADF_C4XXX_IASTATSSM_CPPPAR_ERR_MASK BIT(15) 266 #define ADF_C4XXX_IASTATSSM_RFPAR_ERR_MASK BIT(16) 267 268 #define ADF_C4XXX_IAINTSTATSSM(i) ((i)*0x4000 + 0x206C) 269 #define ADF_C4XXX_IASTATSSM_MASK 0x1DFFF 270 #define ADF_C4XXX_IASTATSSM_CLR_MASK 0xFFFE2000 271 #define ADF_C4XXX_IASTATSSM_BITS 17 272 #define ADF_C4XXX_IASTATSSM_SLICE_HANG_ERR_BIT 13 273 #define ADF_C4XXX_IASTATSSM_SPP_PAR_ERR_BIT 14 274 #define ADF_C4XXX_IASTATSSM_CPP_PAR_ERR_BIT 15 275 276 /* Accelerator Interrupt Mask (SSM) 277 * CSR name: intmaskssm[0..11] 278 * Returns address of INTMASKSSM register for a given accel. 279 * This register is used to unmask SSM interrupts to host 280 * reported by ERRSOU10. 281 */ 282 #define ADF_C4XXX_GET_INTMASKSSM_OFFSET(accel) ((accel)*0x4000) 283 284 /* Base address of SPP parity error mask register 285 * CSR name: sppparerrmsk[0..11] 286 */ 287 #define ADF_C4XXX_SPPPARERRMSK_OFFSET (0x2028) 288 289 /* Returns address of SPPPARERRMSK register for a given accel. 290 * This register is used to unmask SPP parity errors interrupts to host 291 * reported by ERRSOU10. 292 */ 293 #define ADF_C4XXX_GET_SPPPARERRMSK_OFFSET(accel) \ 294 (ADF_C4XXX_SPPPARERRMSK_OFFSET + ((accel)*0x4000)) 295 296 #define ADF_C4XXX_EXPRPSSMCPR0(i) ((i)*0x4000 + 0x400) 297 #define ADF_C4XXX_EXPRPSSMXLT0(i) ((i)*0x4000 + 0x500) 298 #define ADF_C4XXX_EXPRPSSMCPR1(i) ((i)*0x4000 + 0x1400) 299 #define ADF_C4XXX_EXPRPSSMXLT1(i) ((i)*0x4000 + 0x1500) 300 301 #define ADF_C4XXX_EXPRPSSM_FATAL_MASK BIT(2) 302 #define ADF_C4XXX_EXPRPSSM_SOFT_MASK BIT(3) 303 304 #define ADF_C4XXX_PPERR_INTS_CLEAR_MASK BIT(0) 305 306 #define ADF_C4XXX_SSMSOFTERRORPARITY(i) ((i)*0x4000 + 0x1000) 307 #define ADF_C4XXX_SSMCPPERR(i) ((i)*0x4000 + 0x2030) 308 309 /* ethernet doorbell in ERRMSK11 310 * timisc in ERRMSK11 311 * rimisc in ERRMSK11 312 * ppmiscerr in ERRMSK11 313 * cerr in ERRMSK11 314 * uerr in ERRMSK11 315 * ici in ERRMSK11 316 * ice in ERRMSK11 317 */ 318 #define ADF_C4XXX_ERRMSK11_ERR 0x0 319 /* 320 * BIT(7) disables ICI interrupt 321 * BIT(8) disables ICE interrupt 322 */ 323 #define ADF_C4XXX_ERRMSK11_ERR_DISABLE_ICI_ICE_INTR (BIT(7) | BIT(8)) 324 325 /* RAS mask for errors reported by ERRSOU11 */ 326 #define ADF_C4XXX_ERRSOU11_ERROR_MASK (0x1FF) 327 #define ADF_C4XXX_TI_MISC BIT(0) 328 #define ADF_C4XXX_RI_PUSH_PULL_PAR_ERR BIT(1) 329 #define ADF_C4XXX_TI_PUSH_PULL_PAR_ERR BIT(2) 330 #define ADF_C4XXX_ARAM_CORR_ERR BIT(3) 331 #define ADF_C4XXX_ARAM_UNCORR_ERR BIT(4) 332 #define ADF_C4XXX_TI_PULL_PAR_ERR BIT(5) 333 #define ADF_C4XXX_RI_PUSH_PAR_ERR BIT(6) 334 #define ADF_C4XXX_INLINE_INGRESS_INTR BIT(7) 335 #define ADF_C4XXX_INLINE_EGRESS_INTR BIT(8) 336 337 /* TI Misc error status */ 338 #define ADF_C4XXX_TI_MISC_STS (0x6854C) 339 #define ADF_C4XXX_TI_MISC_ERR_MASK (BIT(0)) 340 #define ADF_C4XXX_GET_TI_MISC_ERR_TYPE(status) ((status) >> 1 & 0x3) 341 #define ADF_C4XXX_TI_BME_RESP_ORDER_ERR (0x1) 342 #define ADF_C4XXX_TI_RESP_ORDER_ERR (0x2) 343 344 /* RI CPP interface status register */ 345 #define ADF_C4XXX_RI_CPP_INT_STS (0x61118) 346 #define ADF_C4XXX_RI_CPP_INT_STS_PUSH_ERR BIT(0) 347 #define ADF_C4XXX_RI_CPP_INT_STS_PULL_ERR BIT(1) 348 #define ADF_C4XXX_RI_CPP_INT_STS_PUSH_DATA_PAR_ERR BIT(2) 349 #define ADF_C4XXX_GET_CPP_BUS_FROM_STS(status) ((status) >> 31 & 0x1) 350 351 /* RI CPP interface control register. */ 352 #define ADF_C4XXX_RICPPINTCTL (0x61000 + 0x004) 353 /* 354 * BIT(3) enables error parity checking on CPP. 355 * BIT(2) enables error detection and reporting on the RI Parity Error. 356 * BIT(1) enables error detection and reporting on the RI CPP Pull interface. 357 * BIT(0) enables error detection and reporting on the RI CPP Push interface. 358 */ 359 #define ADF_C4XXX_RICPP_EN (BIT(3) | BIT(2) | BIT(1) | BIT(0)) 360 361 /* TI CPP interface status register */ 362 #define ADF_C4XXX_TI_CPP_INT_STS (0x6853C) 363 #define ADF_C4XXX_TI_CPP_INT_STS_PUSH_ERR BIT(0) 364 #define ADF_C4XXX_TI_CPP_INT_STS_PULL_ERR BIT(1) 365 #define ADF_C4XXX_TI_CPP_INT_STS_PUSH_DATA_PAR_ERR BIT(2) 366 367 #define ADF_C4XXX_TICPPINTCTL (0x68000 + 0x538) 368 /* 369 * BIT(4) enables 'stop and scream' feature for TI RF. 370 * BIT(3) enables CPP command and pull data parity checking. 371 * BIT(2) enables data parity error detection and reporting on the TI CPP 372 * Pull interface. 373 * BIT(1) enables error detection and reporting on the TI CPP Pull interface. 374 * BIT(0) enables error detection and reporting on the TI CPP Push interface. 375 */ 376 #define ADF_C4XXX_TICPP_EN (BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)) 377 378 /* CPP error control and logging register */ 379 #define ADF_C4XXX_CPP_CFC_ERR_CTRL (0x70000 + 0xC00) 380 381 /* 382 * BIT(1) enables generation of irqs to the PCIe endpoint 383 * for the errors specified in CPP_CFC_ERR_STATUS 384 * BIT(0) enables detecting and logging of push/pull data errors. 385 */ 386 #define ADF_C4XXX_CPP_CFC_UE (BIT(1) | BIT(0)) 387 388 /* ARAM error interrupt enable registers */ 389 #define ADF_C4XXX_ARAMCERR (0x101700) 390 #define ADF_C4XXX_ARAMUERR (0x101704) 391 #define ADF_C4XXX_CPPMEMTGTERR (0x101710) 392 #define ADF_C4XXX_ARAM_CORR_ERR_MASK (BIT(0)) 393 #define ADF_C4XXX_ARAM_UNCORR_ERR_MASK (BIT(0)) 394 #define ADF_C4XXX_CLEAR_CSR_BIT(csr, bit_num) ((csr) &= ~(BIT(bit_num))) 395 396 /* ARAM correctable errors defined in ARAMCERR 397 * Bit<3> Enable fixing and logging correctable errors by hardware. 398 * Bit<26> Enable interrupt to host for ARAM correctable errors. 399 */ 400 #define ADF_C4XXX_ARAM_CERR (BIT(3) | BIT(26)) 401 402 /* ARAM correctable errors defined in ARAMUERR 403 * Bit<3> Enable detection and logging of ARAM uncorrectable errors. 404 * Bit<19> Enable interrupt to host for ARAM uncorrectable errors. 405 */ 406 #define ADF_C4XXX_ARAM_UERR (BIT(3) | BIT(19)) 407 408 /* Misc memory target error registers in CPPMEMTGTERR 409 * Bit<2> CPP memory push/pull error enable bit 410 * Bit<7> RI push/pull error enable bit 411 * Bit<8> ARAM pull data parity check bit 412 * Bit<9> RAS push error enable bit 413 */ 414 #define ADF_C4XXX_TGT_UERR (BIT(9) | BIT(8) | BIT(7) | BIT(2)) 415 416 /* Slice power down register */ 417 #define ADF_C4XXX_SLICEPWRDOWN(i) (((i)*0x4000) + 0x2C) 418 419 /* Enabling PKE0 to PKE4. */ 420 #define ADF_C4XXX_MMP_PWR_UP_MSK \ 421 (BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16)) 422 423 /* Error registers for MMP0-MMP4. */ 424 #define ADF_C4XXX_MAX_MMP (5) 425 426 #define ADF_C4XXX_MMP_BASE(i) ((i)*0x1000 % 0x3800) 427 #define ADF_C4XXX_CERRSSMMMP(i, n) ((i)*0x4000 + ADF_C4XXX_MMP_BASE(n) + 0x380) 428 #define ADF_C4XXX_UERRSSMMMP(i, n) ((i)*0x4000 + ADF_C4XXX_MMP_BASE(n) + 0x388) 429 #define ADF_C4XXX_UERRSSMMMPAD(i, n) \ 430 ((i)*0x4000 + ADF_C4XXX_MMP_BASE(n) + 0x38C) 431 #define ADF_C4XXX_INTMASKSSM(i) ((i)*0x4000 + 0x0) 432 433 #define ADF_C4XXX_UERRSSMMMP_INTS_CLEAR_MASK ((BIT(16) | BIT(0))) 434 #define ADF_C4XXX_CERRSSMMMP_INTS_CLEAR_MASK BIT(0) 435 436 /* Bit<3> enables logging of MMP uncorrectable errors */ 437 #define ADF_C4XXX_UERRSSMMMP_EN BIT(3) 438 439 /* Bit<3> enables logging of MMP correctable errors */ 440 #define ADF_C4XXX_CERRSSMMMP_EN BIT(3) 441 442 #define ADF_C4XXX_ERRMSK_VF2PF_OFFSET(i) (ADF_C4XXX_ERRMSK4 + ((i)*0x04)) 443 444 /* RAM base address registers */ 445 #define ADF_C4XXX_RAMBASEADDRHI 0x71020 446 447 #define ADF_C4XXX_NUM_ARAM_ENTRIES 8 448 449 /* ARAM region sizes in bytes */ 450 #define ADF_C4XXX_1MB_SIZE (1024 * 1024) 451 #define ADF_C4XXX_2MB_ARAM_SIZE (2 * ADF_C4XXX_1MB_SIZE) 452 #define ADF_C4XXX_4MB_ARAM_SIZE (4 * ADF_C4XXX_1MB_SIZE) 453 #define ADF_C4XXX_DEFAULT_MMP_REGION_SIZE (1024 * 256) 454 #define ADF_C4XXX_DEFAULT_SKM_REGION_SIZE (1024 * 256) 455 #define ADF_C4XXX_AU_COMPR_INTERM_SIZE (1024 * 128 * 2 * 2) 456 #define ADF_C4XXX_DEF_ASYM_MASK 0x1 457 458 /* Arbiter configuration */ 459 #define ADF_C4XXX_ARB_OFFSET 0x80000 460 #define ADF_C4XXX_ARB_WQCFG_OFFSET 0x200 461 462 /* Admin Interface Reg Offset */ 463 #define ADF_C4XXX_ADMINMSGUR_OFFSET (0x60000 + 0x8000 + 0x400 + 0x174) 464 #define ADF_C4XXX_ADMINMSGLR_OFFSET (0x60000 + 0x8000 + 0x400 + 0x178) 465 #define ADF_C4XXX_MAILBOX_BASE_OFFSET 0x40970 466 467 /* AE to function mapping */ 468 #define ADF_C4XXX_AE2FUNC_REG_PER_AE 8 469 #define ADF_C4XXX_AE2FUNC_MAP_OFFSET 0x68800 470 #define ADF_C4XXX_AE2FUNC_MAP_REG_SIZE 4 471 #define ADF_C4XXX_AE2FUNC_MAP_VALID BIT(8) 472 473 /* Enable each of the units on the chip */ 474 #define ADF_C4XXX_GLOBAL_CLK_ENABLE_GENERIC 0x7096C 475 #define ADF_C4XXX_GLOBAL_CLK_ENABLE_GENERIC_DISABLE_ALL 0x0 476 #define ADF_C4XXX_GLOBAL_CLK_ENABLE_GENERIC_ICE_ENABLE BIT(4) 477 #define ADF_C4XXX_GLOBAL_CLK_ENABLE_GENERIC_ICI_ENABLE BIT(3) 478 #define ADF_C4XXX_GLOBAL_CLK_ENABLE_GENERIC_ARAM BIT(2) 479 480 /* Clock is fully sets up after some delay */ 481 #define ADF_C4XXX_GLOBAL_CLK_ENABLE_GENERIC_RESTART_DELAY 10 482 #define ADF_C4XXX_GLOBAL_CLK_RESTART_LOOP 10 483 484 /* Reset each of the PPC units on the chip */ 485 #define ADF_C4XXX_IXP_RESET_GENERIC 0x70940 486 #define ADF_C4XXX_IXP_RESET_GENERIC_OUT_OF_RESET_TRIGGER 0x0 487 #define ADF_C4XXX_IXP_RESET_GENERIC_INLINE_INGRESS BIT(4) 488 #define ADF_C4XXX_IXP_RESET_GENERIC_INLINE_EGRESS BIT(3) 489 #define ADF_C4XXX_IXP_RESET_GENERIC_ARAM BIT(2) 490 491 /* Default accel unit configuration */ 492 #define ADF_C4XXX_NUM_CY_AU \ 493 { \ 494 [DEV_SKU_1] = 4, [DEV_SKU_1_CY] = 6, [DEV_SKU_2] = 3, \ 495 [DEV_SKU_2_CY] = 4, [DEV_SKU_3] = 1, [DEV_SKU_3_CY] = 2, \ 496 [DEV_SKU_UNKNOWN] = 0 \ 497 } 498 #define ADF_C4XXX_NUM_DC_AU \ 499 { \ 500 [DEV_SKU_1] = 2, [DEV_SKU_1_CY] = 0, [DEV_SKU_2] = 1, \ 501 [DEV_SKU_2_CY] = 0, [DEV_SKU_3] = 1, [DEV_SKU_3_CY] = 0, \ 502 [DEV_SKU_UNKNOWN] = 0 \ 503 } 504 505 #define ADF_C4XXX_NUM_ACCEL_PER_AU 2 506 #define ADF_C4XXX_NUM_INLINE_AU \ 507 { \ 508 [DEV_SKU_1] = 0, [DEV_SKU_1_CY] = 0, [DEV_SKU_2] = 0, \ 509 [DEV_SKU_2_CY] = 0, [DEV_SKU_3] = 0, [DEV_SKU_3_CY] = 0, \ 510 [DEV_SKU_UNKNOWN] = 0 \ 511 } 512 #define ADF_C4XXX_6_AE 6 513 #define ADF_C4XXX_4_AE 4 514 #define ADF_C4XXX_100 100 515 #define ADF_C4XXX_ROUND_LIMIT 5 516 #define ADF_C4XXX_PERCENTAGE "%" 517 518 #define ADF_C4XXX_ARB_CY 0x12222222 519 #define ADF_C4XXX_ARB_DC 0x00000888 520 521 /* Default accel firmware maximal object*/ 522 #define ADF_C4XXX_MAX_OBJ 4 523 524 /* Default 4 partitions for services */ 525 #define ADF_C4XXX_PART_ASYM 0 526 #define ADF_C4XXX_PART_SYM 1 527 #define ADF_C4XXX_PART_UNUSED 2 528 #define ADF_C4XXX_PART_DC 3 529 #define ADF_C4XXX_PARTS_PER_GRP 16 530 531 #define ADF_C4XXX_PARTITION_LUT_OFFSET 0x81000 532 #define ADF_C4XXX_WRKTHD2PARTMAP 0x82000 533 #define ADF_C4XXX_WQM_SIZE 0x4 534 535 #define ADF_C4XXX_DEFAULT_PARTITIONS \ 536 (ADF_C4XXX_PART_ASYM | ADF_C4XXX_PART_SYM << 8 | \ 537 ADF_C4XXX_PART_UNUSED << 16 | ADF_C4XXX_PART_DC << 24) 538 539 /* SKU configurations */ 540 #define ADF_C4XXX_HIGH_SKU_AES 32 541 #define ADF_C4XXX_MED_SKU_AES 24 542 #define ADF_C4XXX_LOW_SKU_AES 12 543 544 #define READ_CSR_WQM(csr_addr, csr_offset, index) \ 545 ADF_CSR_RD(csr_addr, (csr_offset) + ((index)*ADF_C4XXX_WQM_SIZE)) 546 547 #define WRITE_CSR_WQM(csr_addr, csr_offset, index, value) \ 548 ADF_CSR_WR(csr_addr, (csr_offset) + ((index)*ADF_C4XXX_WQM_SIZE), value) 549 550 /* Firmware Binary */ 551 #define ADF_C4XXX_FW "qat_c4xxx_fw" 552 #define ADF_C4XXX_MMP "qat_c4xxx_mmp_fw" 553 #define ADF_C4XXX_INLINE_OBJ "qat_c4xxx_inline.bin" 554 #define ADF_C4XXX_DC_OBJ "qat_c4xxx_dc.bin" 555 #define ADF_C4XXX_CY_OBJ "qat_c4xxx_cy.bin" 556 #define ADF_C4XXX_SYM_OBJ "qat_c4xxx_sym.bin" 557 558 void adf_init_hw_data_c4xxx(struct adf_hw_device_data *hw_data); 559 void adf_clean_hw_data_c4xxx(struct adf_hw_device_data *hw_data); 560 int adf_init_arb_c4xxx(struct adf_accel_dev *accel_dev); 561 void adf_exit_arb_c4xxx(struct adf_accel_dev *accel_dev); 562 563 #define ADF_C4XXX_AE_FREQ (800 * 1000000) 564 #define ADF_C4XXX_MIN_AE_FREQ (571 * 1000000) 565 #define ADF_C4XXX_MAX_AE_FREQ (800 * 1000000) 566 567 int c4xxx_init_ae_config(struct adf_accel_dev *accel_dev); 568 void c4xxx_exit_ae_config(struct adf_accel_dev *accel_dev); 569 void remove_oid(struct adf_accel_dev *accel_dev, struct sysctl_oid *oid); 570 #endif 571