1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 #include "adf_c4xxx_ras.h" 4 #include "adf_accel_devices.h" 5 #include "adf_c4xxx_hw_data.h" 6 #include <adf_dev_err.h> 7 #include "adf_c4xxx_inline.h" 8 9 #define ADF_RAS_STR_LEN 64 10 11 static int adf_sysctl_read_ras_correctable(SYSCTL_HANDLER_ARGS) 12 { 13 struct adf_accel_dev *accel_dev = arg1; 14 unsigned long counter = 0; 15 16 if (accel_dev->ras_counters) 17 counter = atomic_read(&accel_dev->ras_counters[ADF_RAS_CORR]); 18 19 return SYSCTL_OUT(req, &counter, sizeof(counter)); 20 } 21 22 static int adf_sysctl_read_ras_uncorrectable(SYSCTL_HANDLER_ARGS) 23 { 24 struct adf_accel_dev *accel_dev = arg1; 25 unsigned long counter = 0; 26 27 if (accel_dev->ras_counters) 28 counter = atomic_read(&accel_dev->ras_counters[ADF_RAS_UNCORR]); 29 30 return SYSCTL_OUT(req, &counter, sizeof(counter)); 31 } 32 33 static int adf_sysctl_read_ras_fatal(SYSCTL_HANDLER_ARGS) 34 { 35 struct adf_accel_dev *accel_dev = arg1; 36 unsigned long counter = 0; 37 38 if (accel_dev->ras_counters) 39 counter = atomic_read(&accel_dev->ras_counters[ADF_RAS_FATAL]); 40 41 return SYSCTL_OUT(req, &counter, sizeof(counter)); 42 } 43 44 static int adf_sysctl_write_ras_reset(SYSCTL_HANDLER_ARGS) 45 { 46 struct adf_accel_dev *accel_dev = arg1; 47 int value = 0; 48 int ret = SYSCTL_IN(req, &value, sizeof(value)); 49 50 if (!ret && value != 0 && accel_dev->ras_counters) { 51 } 52 53 return SYSCTL_OUT(req, &value, sizeof(value)); 54 } 55 56 int 57 adf_init_ras(struct adf_accel_dev *accel_dev) 58 { 59 struct sysctl_ctx_list *qat_sysctl_ctx; 60 struct sysctl_oid *qat_sysctl_tree; 61 struct sysctl_oid *ras_corr; 62 struct sysctl_oid *ras_uncor; 63 struct sysctl_oid *ras_fat; 64 struct sysctl_oid *ras_res; 65 int i; 66 67 accel_dev->ras_counters = kcalloc(ADF_RAS_ERRORS, 68 sizeof(*accel_dev->ras_counters), 69 GFP_KERNEL); 70 if (!accel_dev->ras_counters) 71 return -ENOMEM; 72 73 for (i = 0; i < ADF_RAS_ERRORS; ++i) 74 75 qat_sysctl_ctx = 76 device_get_sysctl_ctx(accel_dev->accel_pci_dev.pci_dev); 77 qat_sysctl_tree = 78 device_get_sysctl_tree(accel_dev->accel_pci_dev.pci_dev); 79 ras_corr = SYSCTL_ADD_OID(qat_sysctl_ctx, 80 SYSCTL_CHILDREN(qat_sysctl_tree), 81 OID_AUTO, 82 "ras_correctable", 83 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_DYN, 84 accel_dev, 85 0, 86 adf_sysctl_read_ras_correctable, 87 "LU", 88 "QAT RAS correctable"); 89 accel_dev->ras_correctable = ras_corr; 90 if (!accel_dev->ras_correctable) { 91 device_printf(GET_DEV(accel_dev), 92 "Failed to register ras_correctable sysctl\n"); 93 return -EINVAL; 94 } 95 ras_uncor = SYSCTL_ADD_OID(qat_sysctl_ctx, 96 SYSCTL_CHILDREN(qat_sysctl_tree), 97 OID_AUTO, 98 "ras_uncorrectable", 99 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_DYN, 100 accel_dev, 101 0, 102 adf_sysctl_read_ras_uncorrectable, 103 "LU", 104 "QAT RAS uncorrectable"); 105 accel_dev->ras_uncorrectable = ras_uncor; 106 if (!accel_dev->ras_uncorrectable) { 107 device_printf(GET_DEV(accel_dev), 108 "Failed to register ras_uncorrectable sysctl\n"); 109 return -EINVAL; 110 } 111 112 ras_fat = SYSCTL_ADD_OID(qat_sysctl_ctx, 113 SYSCTL_CHILDREN(qat_sysctl_tree), 114 OID_AUTO, 115 "ras_fatal", 116 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_DYN, 117 accel_dev, 118 0, 119 adf_sysctl_read_ras_fatal, 120 "LU", 121 "QAT RAS fatal"); 122 accel_dev->ras_fatal = ras_fat; 123 if (!accel_dev->ras_fatal) { 124 device_printf(GET_DEV(accel_dev), 125 "Failed to register ras_fatal sysctl\n"); 126 return -EINVAL; 127 } 128 129 ras_res = SYSCTL_ADD_OID(qat_sysctl_ctx, 130 SYSCTL_CHILDREN(qat_sysctl_tree), 131 OID_AUTO, 132 "ras_reset", 133 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_DYN, 134 accel_dev, 135 0, 136 adf_sysctl_write_ras_reset, 137 "I", 138 "QAT RAS reset"); 139 accel_dev->ras_reset = ras_res; 140 if (!accel_dev->ras_reset) { 141 device_printf(GET_DEV(accel_dev), 142 "Failed to register ras_reset sysctl\n"); 143 return -EINVAL; 144 } 145 146 return 0; 147 } 148 149 void 150 adf_exit_ras(struct adf_accel_dev *accel_dev) 151 { 152 if (accel_dev->ras_counters) { 153 remove_oid(accel_dev, accel_dev->ras_correctable); 154 remove_oid(accel_dev, accel_dev->ras_uncorrectable); 155 remove_oid(accel_dev, accel_dev->ras_fatal); 156 remove_oid(accel_dev, accel_dev->ras_reset); 157 158 accel_dev->ras_correctable = NULL; 159 accel_dev->ras_uncorrectable = NULL; 160 accel_dev->ras_fatal = NULL; 161 accel_dev->ras_reset = NULL; 162 163 kfree(accel_dev->ras_counters); 164 accel_dev->ras_counters = NULL; 165 } 166 } 167 168 static inline void 169 adf_log_source_iastatssm(struct adf_accel_dev *accel_dev, 170 struct resource *pmisc, 171 u32 iastatssm, 172 u32 accel_num) 173 { 174 if (iastatssm & ADF_C4XXX_IASTATSSM_UERRSSMSH_MASK) 175 device_printf( 176 GET_DEV(accel_dev), 177 "Uncorrectable error shared memory detected in accel: %u\n", 178 accel_num); 179 180 if (iastatssm & ADF_C4XXX_IASTATSSM_CERRSSMSH_MASK) 181 device_printf( 182 GET_DEV(accel_dev), 183 "Correctable error shared memory detected in accel: %u\n", 184 accel_num); 185 186 if (iastatssm & ADF_C4XXX_IASTATSSM_UERRSSMMMP0_MASK) 187 device_printf( 188 GET_DEV(accel_dev), 189 "Uncorrectable error MMP0 detected in accel: %u\n", 190 accel_num); 191 192 if (iastatssm & ADF_C4XXX_IASTATSSM_CERRSSMMMP0_MASK) 193 device_printf(GET_DEV(accel_dev), 194 "Correctable error MMP0 detected in accel: %u\n", 195 accel_num); 196 197 if (iastatssm & ADF_C4XXX_IASTATSSM_UERRSSMMMP1_MASK) 198 device_printf( 199 GET_DEV(accel_dev), 200 "Uncorrectable error MMP1 detected in accel: %u\n", 201 accel_num); 202 203 if (iastatssm & ADF_C4XXX_IASTATSSM_CERRSSMMMP1_MASK) 204 device_printf(GET_DEV(accel_dev), 205 "Correctable error MMP1 detected in accel: %u\n", 206 accel_num); 207 208 if (iastatssm & ADF_C4XXX_IASTATSSM_UERRSSMMMP2_MASK) 209 device_printf( 210 GET_DEV(accel_dev), 211 "Uncorrectable error MMP2 detected in accel: %u\n", 212 accel_num); 213 214 if (iastatssm & ADF_C4XXX_IASTATSSM_CERRSSMMMP2_MASK) 215 device_printf(GET_DEV(accel_dev), 216 "Correctable error MMP2 detected in accel: %u\n", 217 accel_num); 218 219 if (iastatssm & ADF_C4XXX_IASTATSSM_UERRSSMMMP3_MASK) 220 device_printf( 221 GET_DEV(accel_dev), 222 "Uncorrectable error MMP3 detected in accel: %u\n", 223 accel_num); 224 225 if (iastatssm & ADF_C4XXX_IASTATSSM_CERRSSMMMP3_MASK) 226 device_printf(GET_DEV(accel_dev), 227 "Correctable error MMP3 detected in accel: %u\n", 228 accel_num); 229 230 if (iastatssm & ADF_C4XXX_IASTATSSM_UERRSSMMMP4_MASK) 231 device_printf( 232 GET_DEV(accel_dev), 233 "Uncorrectable error MMP4 detected in accel: %u\n", 234 accel_num); 235 236 if (iastatssm & ADF_C4XXX_IASTATSSM_CERRSSMMMP4_MASK) 237 device_printf(GET_DEV(accel_dev), 238 "Correctable error MMP4 detected in accel: %u\n", 239 accel_num); 240 241 if (iastatssm & ADF_C4XXX_IASTATSSM_PPERR_MASK) 242 device_printf( 243 GET_DEV(accel_dev), 244 "Uncorrectable error Push or Pull detected in accel: %u\n", 245 accel_num); 246 247 if (iastatssm & ADF_C4XXX_IASTATSSM_CPPPAR_ERR_MASK) 248 device_printf( 249 GET_DEV(accel_dev), 250 "Uncorrectable CPP parity error detected in accel: %u\n", 251 accel_num); 252 253 if (iastatssm & ADF_C4XXX_IASTATSSM_RFPAR_ERR_MASK) 254 device_printf( 255 GET_DEV(accel_dev), 256 "Uncorrectable SSM RF parity error detected in accel: %u\n", 257 accel_num); 258 } 259 260 static inline void 261 adf_clear_source_statssm(struct adf_accel_dev *accel_dev, 262 struct resource *pmisc, 263 u32 statssm, 264 u32 accel_num) 265 { 266 if (statssm & ADF_C4XXX_IASTATSSM_UERRSSMSH_MASK) 267 adf_csr_fetch_and_and(pmisc, 268 ADF_C4XXX_UERRSSMSH(accel_num), 269 ADF_C4XXX_UERRSSMSH_INTS_CLEAR_MASK); 270 271 if (statssm & ADF_C4XXX_IASTATSSM_CERRSSMSH_MASK) 272 adf_csr_fetch_and_and(pmisc, 273 ADF_C4XXX_CERRSSMSH(accel_num), 274 ADF_C4XXX_CERRSSMSH_INTS_CLEAR_MASK); 275 276 if (statssm & ADF_C4XXX_IASTATSSM_UERRSSMMMP0_MASK) 277 adf_csr_fetch_and_and(pmisc, 278 ADF_C4XXX_UERRSSMMMP(accel_num, 0), 279 ~ADF_C4XXX_UERRSSMMMP_INTS_CLEAR_MASK); 280 281 if (statssm & ADF_C4XXX_IASTATSSM_CERRSSMMMP0_MASK) 282 adf_csr_fetch_and_and(pmisc, 283 ADF_C4XXX_CERRSSMMMP(accel_num, 0), 284 ~ADF_C4XXX_CERRSSMMMP_INTS_CLEAR_MASK); 285 286 if (statssm & ADF_C4XXX_IASTATSSM_UERRSSMMMP1_MASK) 287 adf_csr_fetch_and_and(pmisc, 288 ADF_C4XXX_UERRSSMMMP(accel_num, 1), 289 ~ADF_C4XXX_UERRSSMMMP_INTS_CLEAR_MASK); 290 291 if (statssm & ADF_C4XXX_IASTATSSM_CERRSSMMMP1_MASK) 292 adf_csr_fetch_and_and(pmisc, 293 ADF_C4XXX_CERRSSMMMP(accel_num, 1), 294 ~ADF_C4XXX_CERRSSMMMP_INTS_CLEAR_MASK); 295 296 if (statssm & ADF_C4XXX_IASTATSSM_UERRSSMMMP2_MASK) 297 adf_csr_fetch_and_and(pmisc, 298 ADF_C4XXX_UERRSSMMMP(accel_num, 2), 299 ~ADF_C4XXX_UERRSSMMMP_INTS_CLEAR_MASK); 300 301 if (statssm & ADF_C4XXX_IASTATSSM_CERRSSMMMP2_MASK) 302 adf_csr_fetch_and_and(pmisc, 303 ADF_C4XXX_CERRSSMMMP(accel_num, 2), 304 ~ADF_C4XXX_CERRSSMMMP_INTS_CLEAR_MASK); 305 306 if (statssm & ADF_C4XXX_IASTATSSM_UERRSSMMMP3_MASK) 307 adf_csr_fetch_and_and(pmisc, 308 ADF_C4XXX_UERRSSMMMP(accel_num, 3), 309 ~ADF_C4XXX_UERRSSMMMP_INTS_CLEAR_MASK); 310 311 if (statssm & ADF_C4XXX_IASTATSSM_CERRSSMMMP3_MASK) 312 adf_csr_fetch_and_and(pmisc, 313 ADF_C4XXX_CERRSSMMMP(accel_num, 3), 314 ~ADF_C4XXX_CERRSSMMMP_INTS_CLEAR_MASK); 315 316 if (statssm & ADF_C4XXX_IASTATSSM_UERRSSMMMP4_MASK) 317 adf_csr_fetch_and_and(pmisc, 318 ADF_C4XXX_UERRSSMMMP(accel_num, 4), 319 ~ADF_C4XXX_UERRSSMMMP_INTS_CLEAR_MASK); 320 321 if (statssm & ADF_C4XXX_IASTATSSM_CERRSSMMMP4_MASK) 322 adf_csr_fetch_and_and(pmisc, 323 ADF_C4XXX_CERRSSMMMP(accel_num, 4), 324 ~ADF_C4XXX_CERRSSMMMP_INTS_CLEAR_MASK); 325 326 if (statssm & ADF_C4XXX_IASTATSSM_PPERR_MASK) 327 adf_csr_fetch_and_and(pmisc, 328 ADF_PPERR(accel_num), 329 ~ADF_C4XXX_PPERR_INTS_CLEAR_MASK); 330 331 if (statssm & ADF_C4XXX_IASTATSSM_RFPAR_ERR_MASK) 332 adf_csr_fetch_and_or(pmisc, 333 ADF_C4XXX_SSMSOFTERRORPARITY(accel_num), 334 0UL); 335 336 if (statssm & ADF_C4XXX_IASTATSSM_CPPPAR_ERR_MASK) 337 adf_csr_fetch_and_or(pmisc, 338 ADF_C4XXX_SSMCPPERR(accel_num), 339 0UL); 340 } 341 342 static inline void 343 adf_process_errsou8(struct adf_accel_dev *accel_dev, struct resource *pmisc) 344 { 345 int i; 346 u32 mecorrerr = ADF_CSR_RD(pmisc, ADF_C4XXX_HI_ME_COR_ERRLOG); 347 const unsigned long tmp_mecorrerr = mecorrerr; 348 349 /* For each correctable error in ME increment RAS counter */ 350 for_each_set_bit(i, 351 &tmp_mecorrerr, 352 ADF_C4XXX_HI_ME_COR_ERRLOG_SIZE_IN_BITS) 353 { 354 atomic_inc(&accel_dev->ras_counters[ADF_RAS_CORR]); 355 device_printf(GET_DEV(accel_dev), 356 "Correctable error detected in AE%d\n", 357 i); 358 } 359 360 /* Clear interrupt from errsou8 (RW1C) */ 361 ADF_CSR_WR(pmisc, ADF_C4XXX_HI_ME_COR_ERRLOG, mecorrerr); 362 } 363 364 static inline void 365 adf_handle_ae_uncorr_err(struct adf_accel_dev *accel_dev, 366 struct resource *pmisc) 367 { 368 int i; 369 u32 me_uncorr_err = ADF_CSR_RD(pmisc, ADF_C4XXX_HI_ME_UNCERR_LOG); 370 const unsigned long tmp_me_uncorr_err = me_uncorr_err; 371 372 /* For each uncorrectable fatal error in AE increment RAS error 373 * counter. 374 */ 375 for_each_set_bit(i, 376 &tmp_me_uncorr_err, 377 ADF_C4XXX_HI_ME_UNCOR_ERRLOG_BITS) 378 { 379 atomic_inc(&accel_dev->ras_counters[ADF_RAS_FATAL]); 380 device_printf(GET_DEV(accel_dev), 381 "Uncorrectable error detected in AE%d\n", 382 i); 383 } 384 385 /* Clear interrupt from me_uncorr_err (RW1C) */ 386 ADF_CSR_WR(pmisc, ADF_C4XXX_HI_ME_UNCERR_LOG, me_uncorr_err); 387 } 388 389 static inline void 390 adf_handle_ri_mem_par_err(struct adf_accel_dev *accel_dev, 391 struct resource *pmisc, 392 bool *reset_required) 393 { 394 u32 ri_mem_par_err_sts = 0; 395 u32 ri_mem_par_err_ferr = 0; 396 397 ri_mem_par_err_sts = ADF_CSR_RD(pmisc, ADF_C4XXX_RI_MEM_PAR_ERR_STS); 398 399 ri_mem_par_err_ferr = ADF_CSR_RD(pmisc, ADF_C4XXX_RI_MEM_PAR_ERR_FERR); 400 401 if (ri_mem_par_err_sts & ADF_C4XXX_RI_MEM_PAR_ERR_STS_MASK) { 402 atomic_inc(&accel_dev->ras_counters[ADF_RAS_UNCORR]); 403 device_printf( 404 GET_DEV(accel_dev), 405 "Uncorrectable RI memory parity error detected.\n"); 406 } 407 408 if (ri_mem_par_err_sts & ADF_C4XXX_RI_MEM_MSIX_TBL_INT_MASK) { 409 atomic_inc(&accel_dev->ras_counters[ADF_RAS_FATAL]); 410 device_printf( 411 GET_DEV(accel_dev), 412 "Uncorrectable fatal MSIX table parity error detected.\n"); 413 *reset_required = true; 414 } 415 416 device_printf(GET_DEV(accel_dev), 417 "ri_mem_par_err_sts=0x%X\tri_mem_par_err_ferr=%u\n", 418 ri_mem_par_err_sts, 419 ri_mem_par_err_ferr); 420 421 ADF_CSR_WR(pmisc, ADF_C4XXX_RI_MEM_PAR_ERR_STS, ri_mem_par_err_sts); 422 } 423 424 static inline void 425 adf_handle_ti_mem_par_err(struct adf_accel_dev *accel_dev, 426 struct resource *pmisc) 427 { 428 u32 ti_mem_par_err_sts0 = 0; 429 u32 ti_mem_par_err_sts1 = 0; 430 u32 ti_mem_par_err_ferr = 0; 431 432 ti_mem_par_err_sts0 = ADF_CSR_RD(pmisc, ADF_C4XXX_TI_MEM_PAR_ERR_STS0); 433 ti_mem_par_err_sts1 = ADF_CSR_RD(pmisc, ADF_C4XXX_TI_MEM_PAR_ERR_STS1); 434 ti_mem_par_err_ferr = 435 ADF_CSR_RD(pmisc, ADF_C4XXX_TI_MEM_PAR_ERR_FIRST_ERROR); 436 437 atomic_inc(&accel_dev->ras_counters[ADF_RAS_FATAL]); 438 ti_mem_par_err_sts1 &= ADF_C4XXX_TI_MEM_PAR_ERR_STS1_MASK; 439 440 device_printf(GET_DEV(accel_dev), 441 "Uncorrectable TI memory parity error detected.\n"); 442 device_printf(GET_DEV(accel_dev), 443 "ti_mem_par_err_sts0=0x%X\tti_mem_par_err_sts1=0x%X\t" 444 "ti_mem_par_err_ferr=0x%X\n", 445 ti_mem_par_err_sts0, 446 ti_mem_par_err_sts1, 447 ti_mem_par_err_ferr); 448 449 ADF_CSR_WR(pmisc, ADF_C4XXX_TI_MEM_PAR_ERR_STS0, ti_mem_par_err_sts0); 450 ADF_CSR_WR(pmisc, ADF_C4XXX_TI_MEM_PAR_ERR_STS1, ti_mem_par_err_sts1); 451 } 452 453 static inline void 454 adf_log_fatal_cmd_par_err(struct adf_accel_dev *accel_dev, char *err_type) 455 { 456 atomic_inc(&accel_dev->ras_counters[ADF_RAS_FATAL]); 457 device_printf(GET_DEV(accel_dev), 458 "Fatal error detected: %s command parity\n", 459 err_type); 460 } 461 462 static inline void 463 adf_handle_host_cpp_par_err(struct adf_accel_dev *accel_dev, 464 struct resource *pmisc) 465 { 466 u32 host_cpp_par_err = 0; 467 468 host_cpp_par_err = 469 ADF_CSR_RD(pmisc, ADF_C4XXX_HI_CPP_AGENT_CMD_PAR_ERR_LOG); 470 471 if (host_cpp_par_err & ADF_C4XXX_TI_CMD_PAR_ERR) 472 adf_log_fatal_cmd_par_err(accel_dev, "TI"); 473 474 if (host_cpp_par_err & ADF_C4XXX_RI_CMD_PAR_ERR) 475 adf_log_fatal_cmd_par_err(accel_dev, "RI"); 476 477 if (host_cpp_par_err & ADF_C4XXX_ICI_CMD_PAR_ERR) 478 adf_log_fatal_cmd_par_err(accel_dev, "ICI"); 479 480 if (host_cpp_par_err & ADF_C4XXX_ICE_CMD_PAR_ERR) 481 adf_log_fatal_cmd_par_err(accel_dev, "ICE"); 482 483 if (host_cpp_par_err & ADF_C4XXX_ARAM_CMD_PAR_ERR) 484 adf_log_fatal_cmd_par_err(accel_dev, "ARAM"); 485 486 if (host_cpp_par_err & ADF_C4XXX_CFC_CMD_PAR_ERR) 487 adf_log_fatal_cmd_par_err(accel_dev, "CFC"); 488 489 if (ADF_C4XXX_SSM_CMD_PAR_ERR(host_cpp_par_err)) 490 adf_log_fatal_cmd_par_err(accel_dev, "SSM"); 491 492 /* Clear interrupt from host_cpp_par_err (RW1C) */ 493 ADF_CSR_WR(pmisc, 494 ADF_C4XXX_HI_CPP_AGENT_CMD_PAR_ERR_LOG, 495 host_cpp_par_err); 496 } 497 498 static inline void 499 adf_process_errsou9(struct adf_accel_dev *accel_dev, 500 struct resource *pmisc, 501 u32 errsou, 502 bool *reset_required) 503 { 504 if (errsou & ADF_C4XXX_ME_UNCORR_ERROR) { 505 adf_handle_ae_uncorr_err(accel_dev, pmisc); 506 507 /* Notify caller that function level reset is required. */ 508 *reset_required = true; 509 } 510 511 if (errsou & ADF_C4XXX_CPP_CMD_PAR_ERR) { 512 adf_handle_host_cpp_par_err(accel_dev, pmisc); 513 *reset_required = true; 514 } 515 516 /* RI memory parity errors are uncorrectable non-fatal errors 517 * with exception of bit 22 MSIX table parity error, which should 518 * be treated as fatal error, followed by device restart. 519 */ 520 if (errsou & ADF_C4XXX_RI_MEM_PAR_ERR) 521 adf_handle_ri_mem_par_err(accel_dev, pmisc, reset_required); 522 523 if (errsou & ADF_C4XXX_TI_MEM_PAR_ERR) { 524 adf_handle_ti_mem_par_err(accel_dev, pmisc); 525 *reset_required = true; 526 } 527 } 528 529 static inline void 530 adf_process_exprpssmcpr(struct adf_accel_dev *accel_dev, 531 struct resource *pmisc, 532 u32 accel) 533 { 534 u32 exprpssmcpr; 535 536 /* CPR0 */ 537 exprpssmcpr = ADF_CSR_RD(pmisc, ADF_C4XXX_EXPRPSSMCPR0(accel)); 538 if (exprpssmcpr & ADF_C4XXX_EXPRPSSM_FATAL_MASK) { 539 device_printf(GET_DEV(accel_dev), 540 "Uncorrectable error CPR0 detected in accel %u\n", 541 accel); 542 atomic_inc(&accel_dev->ras_counters[ADF_RAS_UNCORR]); 543 } 544 if (exprpssmcpr & ADF_C4XXX_EXPRPSSM_SOFT_MASK) { 545 device_printf(GET_DEV(accel_dev), 546 "Correctable error CPR0 detected in accel %u\n", 547 accel); 548 atomic_inc(&accel_dev->ras_counters[ADF_RAS_CORR]); 549 } 550 ADF_CSR_WR(pmisc, ADF_C4XXX_EXPRPSSMCPR0(accel), 0); 551 552 /* CPR1 */ 553 exprpssmcpr = ADF_CSR_RD(pmisc, ADF_C4XXX_EXPRPSSMCPR1(accel)); 554 if (exprpssmcpr & ADF_C4XXX_EXPRPSSM_FATAL_MASK) { 555 device_printf(GET_DEV(accel_dev), 556 "Uncorrectable error CPR1 detected in accel %u\n", 557 accel); 558 atomic_inc(&accel_dev->ras_counters[ADF_RAS_UNCORR]); 559 } 560 if (exprpssmcpr & ADF_C4XXX_EXPRPSSM_SOFT_MASK) { 561 device_printf(GET_DEV(accel_dev), 562 "Correctable error CPR1 detected in accel %u\n", 563 accel); 564 atomic_inc(&accel_dev->ras_counters[ADF_RAS_CORR]); 565 } 566 ADF_CSR_WR(pmisc, ADF_C4XXX_EXPRPSSMCPR1(accel), 0); 567 } 568 569 static inline void 570 adf_process_exprpssmxlt(struct adf_accel_dev *accel_dev, 571 struct resource *pmisc, 572 u32 accel) 573 { 574 u32 exprpssmxlt; 575 576 /* XTL0 */ 577 exprpssmxlt = ADF_CSR_RD(pmisc, ADF_C4XXX_EXPRPSSMXLT0(accel)); 578 if (exprpssmxlt & ADF_C4XXX_EXPRPSSM_FATAL_MASK) { 579 device_printf(GET_DEV(accel_dev), 580 "Uncorrectable error XLT0 detected in accel %u\n", 581 accel); 582 atomic_inc(&accel_dev->ras_counters[ADF_RAS_UNCORR]); 583 } 584 if (exprpssmxlt & ADF_C4XXX_EXPRPSSM_SOFT_MASK) { 585 device_printf(GET_DEV(accel_dev), 586 "Correctable error XLT0 detected in accel %u\n", 587 accel); 588 atomic_inc(&accel_dev->ras_counters[ADF_RAS_CORR]); 589 } 590 ADF_CSR_WR(pmisc, ADF_C4XXX_EXPRPSSMXLT0(accel), 0); 591 592 /* XTL1 */ 593 exprpssmxlt = ADF_CSR_RD(pmisc, ADF_C4XXX_EXPRPSSMXLT1(accel)); 594 if (exprpssmxlt & ADF_C4XXX_EXPRPSSM_FATAL_MASK) { 595 device_printf(GET_DEV(accel_dev), 596 "Uncorrectable error XLT1 detected in accel %u\n", 597 accel); 598 atomic_inc(&accel_dev->ras_counters[ADF_RAS_UNCORR]); 599 } 600 if (exprpssmxlt & ADF_C4XXX_EXPRPSSM_SOFT_MASK) { 601 device_printf(GET_DEV(accel_dev), 602 "Correctable error XLT1 detected in accel %u\n", 603 accel); 604 atomic_inc(&accel_dev->ras_counters[ADF_RAS_CORR]); 605 } 606 ADF_CSR_WR(pmisc, ADF_C4XXX_EXPRPSSMXLT0(accel), 0); 607 } 608 609 static inline void 610 adf_process_spp_par_err(struct adf_accel_dev *accel_dev, 611 struct resource *pmisc, 612 u32 accel, 613 bool *reset_required) 614 { 615 /* All SPP parity errors are treated as uncorrectable fatal errors */ 616 atomic_inc(&accel_dev->ras_counters[ADF_RAS_FATAL]); 617 *reset_required = true; 618 device_printf(GET_DEV(accel_dev), 619 "Uncorrectable fatal SPP parity error detected\n"); 620 } 621 622 static inline void 623 adf_process_statssm(struct adf_accel_dev *accel_dev, 624 struct resource *pmisc, 625 u32 accel, 626 bool *reset_required) 627 { 628 u32 i; 629 u32 statssm = ADF_CSR_RD(pmisc, ADF_INTSTATSSM(accel)); 630 u32 iastatssm = ADF_CSR_RD(pmisc, ADF_C4XXX_IAINTSTATSSM(accel)); 631 bool type; 632 const unsigned long tmp_iastatssm = iastatssm; 633 634 /* First collect all errors */ 635 for_each_set_bit(i, &tmp_iastatssm, ADF_C4XXX_IASTATSSM_BITS) 636 { 637 if (i == ADF_C4XXX_IASTATSSM_SLICE_HANG_ERR_BIT) { 638 /* Slice Hang error is being handled in 639 * separate function adf_check_slice_hang_c4xxx(), 640 * which also increments RAS counters for 641 * SliceHang error. 642 */ 643 continue; 644 } 645 if (i == ADF_C4XXX_IASTATSSM_SPP_PAR_ERR_BIT) { 646 adf_process_spp_par_err(accel_dev, 647 pmisc, 648 accel, 649 reset_required); 650 continue; 651 } 652 653 type = (i % 2) ? ADF_RAS_CORR : ADF_RAS_UNCORR; 654 if (i == ADF_C4XXX_IASTATSSM_CPP_PAR_ERR_BIT) 655 type = ADF_RAS_UNCORR; 656 657 atomic_inc(&accel_dev->ras_counters[type]); 658 } 659 660 /* If iastatssm is set, we need to log the error */ 661 if (iastatssm & ADF_C4XXX_IASTATSSM_MASK) 662 adf_log_source_iastatssm(accel_dev, pmisc, iastatssm, accel); 663 /* If statssm is set, we need to clear the error sources */ 664 if (statssm & ADF_C4XXX_IASTATSSM_MASK) 665 adf_clear_source_statssm(accel_dev, pmisc, statssm, accel); 666 /* Clear the iastatssm after clearing error sources */ 667 if (iastatssm & ADF_C4XXX_IASTATSSM_MASK) 668 adf_csr_fetch_and_and(pmisc, 669 ADF_C4XXX_IAINTSTATSSM(accel), 670 ADF_C4XXX_IASTATSSM_CLR_MASK); 671 } 672 673 static inline void 674 adf_process_errsou10(struct adf_accel_dev *accel_dev, 675 struct resource *pmisc, 676 u32 errsou, 677 u32 num_accels, 678 bool *reset_required) 679 { 680 int accel; 681 const unsigned long tmp_errsou = errsou; 682 683 for_each_set_bit(accel, &tmp_errsou, num_accels) 684 { 685 adf_process_statssm(accel_dev, pmisc, accel, reset_required); 686 adf_process_exprpssmcpr(accel_dev, pmisc, accel); 687 adf_process_exprpssmxlt(accel_dev, pmisc, accel); 688 } 689 } 690 691 /* ERRSOU 11 */ 692 static inline void 693 adf_handle_ti_misc_err(struct adf_accel_dev *accel_dev, struct resource *pmisc) 694 { 695 u32 ti_misc_sts = 0; 696 u32 err_type = 0; 697 698 ti_misc_sts = ADF_CSR_RD(pmisc, ADF_C4XXX_TI_MISC_STS); 699 dev_dbg(GET_DEV(accel_dev), "ti_misc_sts = 0x%X\n", ti_misc_sts); 700 701 if (ti_misc_sts & ADF_C4XXX_TI_MISC_ERR_MASK) { 702 atomic_inc(&accel_dev->ras_counters[ADF_RAS_UNCORR]); 703 704 /* If TI misc error occurred then check its type */ 705 err_type = ADF_C4XXX_GET_TI_MISC_ERR_TYPE(ti_misc_sts); 706 if (err_type == ADF_C4XXX_TI_BME_RESP_ORDER_ERR) { 707 device_printf( 708 GET_DEV(accel_dev), 709 "Uncorrectable non-fatal BME response order error.\n"); 710 711 } else if (err_type == ADF_C4XXX_TI_RESP_ORDER_ERR) { 712 device_printf( 713 GET_DEV(accel_dev), 714 "Uncorrectable non-fatal response order error.\n"); 715 } 716 717 /* Clear the interrupt and allow the next error to be 718 * logged. 719 */ 720 ADF_CSR_WR(pmisc, ADF_C4XXX_TI_MISC_STS, BIT(0)); 721 } 722 } 723 724 static inline void 725 adf_handle_ri_push_pull_par_err(struct adf_accel_dev *accel_dev, 726 struct resource *pmisc) 727 { 728 u32 ri_cpp_int_sts = 0; 729 u32 err_clear_mask = 0; 730 731 ri_cpp_int_sts = ADF_CSR_RD(pmisc, ADF_C4XXX_RI_CPP_INT_STS); 732 dev_dbg(GET_DEV(accel_dev), "ri_cpp_int_sts = 0x%X\n", ri_cpp_int_sts); 733 734 if (ri_cpp_int_sts & ADF_C4XXX_RI_CPP_INT_STS_PUSH_ERR) { 735 atomic_inc(&accel_dev->ras_counters[ADF_RAS_UNCORR]); 736 device_printf( 737 GET_DEV(accel_dev), 738 "CPP%d: Uncorrectable non-fatal RI push error detected.\n", 739 ADF_C4XXX_GET_CPP_BUS_FROM_STS(ri_cpp_int_sts)); 740 741 err_clear_mask |= ADF_C4XXX_RI_CPP_INT_STS_PUSH_ERR; 742 } 743 744 if (ri_cpp_int_sts & ADF_C4XXX_RI_CPP_INT_STS_PULL_ERR) { 745 atomic_inc(&accel_dev->ras_counters[ADF_RAS_UNCORR]); 746 device_printf( 747 GET_DEV(accel_dev), 748 "CPP%d: Uncorrectable non-fatal RI pull error detected.\n", 749 ADF_C4XXX_GET_CPP_BUS_FROM_STS(ri_cpp_int_sts)); 750 751 err_clear_mask |= ADF_C4XXX_RI_CPP_INT_STS_PULL_ERR; 752 } 753 754 /* Clear the interrupt for handled errors and allow the next error 755 * to be logged. 756 */ 757 ADF_CSR_WR(pmisc, ADF_C4XXX_RI_CPP_INT_STS, err_clear_mask); 758 } 759 760 static inline void 761 adf_handle_ti_push_pull_par_err(struct adf_accel_dev *accel_dev, 762 struct resource *pmisc) 763 { 764 u32 ti_cpp_int_sts = 0; 765 u32 err_clear_mask = 0; 766 767 ti_cpp_int_sts = ADF_CSR_RD(pmisc, ADF_C4XXX_TI_CPP_INT_STS); 768 dev_dbg(GET_DEV(accel_dev), "ti_cpp_int_sts = 0x%X\n", ti_cpp_int_sts); 769 770 if (ti_cpp_int_sts & ADF_C4XXX_TI_CPP_INT_STS_PUSH_ERR) { 771 atomic_inc(&accel_dev->ras_counters[ADF_RAS_UNCORR]); 772 device_printf( 773 GET_DEV(accel_dev), 774 "CPP%d: Uncorrectable non-fatal TI push error detected.\n", 775 ADF_C4XXX_GET_CPP_BUS_FROM_STS(ti_cpp_int_sts)); 776 777 err_clear_mask |= ADF_C4XXX_TI_CPP_INT_STS_PUSH_ERR; 778 } 779 780 if (ti_cpp_int_sts & ADF_C4XXX_TI_CPP_INT_STS_PULL_ERR) { 781 atomic_inc(&accel_dev->ras_counters[ADF_RAS_UNCORR]); 782 device_printf( 783 GET_DEV(accel_dev), 784 "CPP%d: Uncorrectable non-fatal TI pull error detected.\n", 785 ADF_C4XXX_GET_CPP_BUS_FROM_STS(ti_cpp_int_sts)); 786 787 err_clear_mask |= ADF_C4XXX_TI_CPP_INT_STS_PULL_ERR; 788 } 789 790 /* Clear the interrupt for handled errors and allow the next error 791 * to be logged. 792 */ 793 ADF_CSR_WR(pmisc, ADF_C4XXX_TI_CPP_INT_STS, err_clear_mask); 794 } 795 796 static inline void 797 adf_handle_aram_corr_err(struct adf_accel_dev *accel_dev, 798 struct resource *aram_base_addr) 799 { 800 u32 aram_cerr = 0; 801 802 aram_cerr = ADF_CSR_RD(aram_base_addr, ADF_C4XXX_ARAMCERR); 803 dev_dbg(GET_DEV(accel_dev), "aram_cerr = 0x%X\n", aram_cerr); 804 805 if (aram_cerr & ADF_C4XXX_ARAM_CORR_ERR_MASK) { 806 atomic_inc(&accel_dev->ras_counters[ADF_RAS_CORR]); 807 device_printf(GET_DEV(accel_dev), 808 "Correctable ARAM error detected.\n"); 809 } 810 811 /* Clear correctable ARAM error interrupt. */ 812 ADF_C4XXX_CLEAR_CSR_BIT(aram_cerr, 0); 813 ADF_CSR_WR(aram_base_addr, ADF_C4XXX_ARAMCERR, aram_cerr); 814 } 815 816 static inline void 817 adf_handle_aram_uncorr_err(struct adf_accel_dev *accel_dev, 818 struct resource *aram_base_addr) 819 { 820 u32 aram_uerr = 0; 821 822 aram_uerr = ADF_CSR_RD(aram_base_addr, ADF_C4XXX_ARAMUERR); 823 dev_dbg(GET_DEV(accel_dev), "aram_uerr = 0x%X\n", aram_uerr); 824 825 if (aram_uerr & ADF_C4XXX_ARAM_UNCORR_ERR_MASK) { 826 atomic_inc(&accel_dev->ras_counters[ADF_RAS_UNCORR]); 827 device_printf(GET_DEV(accel_dev), 828 "Uncorrectable non-fatal ARAM error detected.\n"); 829 } 830 831 /* Clear uncorrectable ARAM error interrupt. */ 832 ADF_C4XXX_CLEAR_CSR_BIT(aram_uerr, 0); 833 ADF_CSR_WR(aram_base_addr, ADF_C4XXX_ARAMUERR, aram_uerr); 834 } 835 836 static inline void 837 adf_handle_ti_pull_par_err(struct adf_accel_dev *accel_dev, 838 struct resource *pmisc) 839 { 840 u32 ti_cpp_int_sts = 0; 841 842 ti_cpp_int_sts = ADF_CSR_RD(pmisc, ADF_C4XXX_TI_CPP_INT_STS); 843 dev_dbg(GET_DEV(accel_dev), "ti_cpp_int_sts = 0x%X\n", ti_cpp_int_sts); 844 845 if (ti_cpp_int_sts & ADF_C4XXX_TI_CPP_INT_STS_PUSH_DATA_PAR_ERR) { 846 atomic_inc(&accel_dev->ras_counters[ADF_RAS_UNCORR]); 847 device_printf( 848 GET_DEV(accel_dev), 849 "CPP%d: Uncorrectable non-fatal TI pull data parity error detected.\n", 850 ADF_C4XXX_GET_CPP_BUS_FROM_STS(ti_cpp_int_sts)); 851 } 852 853 /* Clear the interrupt and allow the next error to be logged. */ 854 ADF_CSR_WR(pmisc, 855 ADF_C4XXX_TI_CPP_INT_STS, 856 ADF_C4XXX_TI_CPP_INT_STS_PUSH_DATA_PAR_ERR); 857 } 858 859 static inline void 860 adf_handle_ri_push_par_err(struct adf_accel_dev *accel_dev, 861 struct resource *pmisc) 862 { 863 u32 ri_cpp_int_sts = 0; 864 865 ri_cpp_int_sts = ADF_CSR_RD(pmisc, ADF_C4XXX_RI_CPP_INT_STS); 866 dev_dbg(GET_DEV(accel_dev), "ri_cpp_int_sts = 0x%X\n", ri_cpp_int_sts); 867 868 if (ri_cpp_int_sts & ADF_C4XXX_RI_CPP_INT_STS_PUSH_DATA_PAR_ERR) { 869 atomic_inc(&accel_dev->ras_counters[ADF_RAS_UNCORR]); 870 device_printf( 871 GET_DEV(accel_dev), 872 "CPP%d: Uncorrectable non-fatal RI push data parity error detected.\n", 873 ADF_C4XXX_GET_CPP_BUS_FROM_STS(ri_cpp_int_sts)); 874 } 875 876 /* Clear the interrupt and allow the next error to be logged. */ 877 ADF_CSR_WR(pmisc, 878 ADF_C4XXX_RI_CPP_INT_STS, 879 ADF_C4XXX_RI_CPP_INT_STS_PUSH_DATA_PAR_ERR); 880 } 881 882 static inline void 883 adf_log_inln_err(struct adf_accel_dev *accel_dev, 884 u32 offset, 885 u8 ras_type, 886 char *msg) 887 { 888 if (ras_type >= ADF_RAS_ERRORS) { 889 device_printf(GET_DEV(accel_dev), 890 "Invalid ras type %u\n", 891 ras_type); 892 return; 893 } 894 895 if (offset == ADF_C4XXX_INLINE_INGRESS_OFFSET) { 896 if (ras_type == ADF_RAS_CORR) 897 dev_dbg(GET_DEV(accel_dev), "Detect ici %s\n", msg); 898 else 899 device_printf(GET_DEV(accel_dev), 900 "Detect ici %s\n", 901 msg); 902 } else { 903 if (ras_type == ADF_RAS_CORR) 904 dev_dbg(GET_DEV(accel_dev), "Detect ice %s\n", msg); 905 else 906 device_printf(GET_DEV(accel_dev), 907 "Detect ice %s\n", 908 msg); 909 } 910 atomic_inc(&accel_dev->ras_counters[ras_type]); 911 } 912 913 static inline void 914 adf_handle_parser_uerr(struct adf_accel_dev *accel_dev, 915 struct resource *aram_base_addr, 916 u32 offset, 917 bool *reset_required) 918 { 919 u32 reg_val = 0; 920 921 reg_val = ADF_CSR_RD(aram_base_addr, ADF_C4XXX_IC_PARSER_UERR + offset); 922 if (reg_val & ADF_C4XXX_PARSER_UERR_INTR) { 923 /* Mask inten */ 924 reg_val &= ~ADF_C4XXX_PARSER_DESC_UERR_INTR_ENA; 925 ADF_CSR_WR(aram_base_addr, 926 ADF_C4XXX_IC_PARSER_UERR + offset, 927 reg_val); 928 929 /* Fatal error then increase RAS error counter 930 * and reset CPM 931 */ 932 adf_log_inln_err(accel_dev, 933 offset, 934 ADF_RAS_FATAL, 935 "parser uncorr fatal err"); 936 *reset_required = true; 937 } 938 } 939 940 static inline void 941 adf_handle_mac_intr(struct adf_accel_dev *accel_dev, 942 struct resource *aram_base_addr, 943 u32 offset, 944 bool *reset_required) 945 { 946 u64 reg_val; 947 948 reg_val = ADF_CSR_RD64(aram_base_addr, ADF_C4XXX_MAC_IP + offset); 949 950 /* Handle the MAC interrupts masked out in MAC_IM */ 951 if (reg_val & ADF_C4XXX_MAC_ERROR_TX_UNDERRUN) 952 adf_log_inln_err(accel_dev, 953 offset, 954 ADF_RAS_CORR, 955 "err tx underrun"); 956 957 if (reg_val & ADF_C4XXX_MAC_ERROR_TX_FCS) 958 adf_log_inln_err(accel_dev, offset, ADF_RAS_CORR, "err tx fcs"); 959 960 if (reg_val & ADF_C4XXX_MAC_ERROR_TX_DATA_CORRUPT) 961 adf_log_inln_err(accel_dev, 962 offset, 963 ADF_RAS_CORR, 964 "err tx data corrupt"); 965 966 if (reg_val & ADF_C4XXX_MAC_ERROR_RX_OVERRUN) { 967 *reset_required = true; 968 adf_log_inln_err(accel_dev, 969 offset, 970 ADF_RAS_FATAL, 971 "err rx overrun fatal err"); 972 } 973 974 if (reg_val & ADF_C4XXX_MAC_ERROR_RX_RUNT) { 975 *reset_required = true; 976 adf_log_inln_err(accel_dev, 977 offset, 978 ADF_RAS_FATAL, 979 "err rx runt fatal err"); 980 } 981 982 if (reg_val & ADF_C4XXX_MAC_ERROR_RX_UNDERSIZE) { 983 *reset_required = true; 984 adf_log_inln_err(accel_dev, 985 offset, 986 ADF_RAS_FATAL, 987 "err rx undersize fatal err"); 988 } 989 990 if (reg_val & ADF_C4XXX_MAC_ERROR_RX_JABBER) { 991 *reset_required = true; 992 adf_log_inln_err(accel_dev, 993 offset, 994 ADF_RAS_FATAL, 995 "err rx jabber fatal err"); 996 } 997 998 if (reg_val & ADF_C4XXX_MAC_ERROR_RX_OVERSIZE) { 999 *reset_required = true; 1000 adf_log_inln_err(accel_dev, 1001 offset, 1002 ADF_RAS_FATAL, 1003 "err rx oversize fatal err"); 1004 } 1005 1006 if (reg_val & ADF_C4XXX_MAC_ERROR_RX_FCS) 1007 adf_log_inln_err(accel_dev, offset, ADF_RAS_CORR, "err rx fcs"); 1008 1009 if (reg_val & ADF_C4XXX_MAC_ERROR_RX_FRAME) 1010 adf_log_inln_err(accel_dev, 1011 offset, 1012 ADF_RAS_CORR, 1013 "err rx frame"); 1014 1015 if (reg_val & ADF_C4XXX_MAC_ERROR_RX_CODE) 1016 adf_log_inln_err(accel_dev, 1017 offset, 1018 ADF_RAS_CORR, 1019 "err rx code"); 1020 1021 if (reg_val & ADF_C4XXX_MAC_ERROR_RX_PREAMBLE) 1022 adf_log_inln_err(accel_dev, 1023 offset, 1024 ADF_RAS_CORR, 1025 "err rx preamble"); 1026 1027 if (reg_val & ADF_C4XXX_MAC_RX_LINK_UP) 1028 adf_log_inln_err(accel_dev, offset, ADF_RAS_CORR, "rx link up"); 1029 1030 if (reg_val & ADF_C4XXX_MAC_INVALID_SPEED) 1031 adf_log_inln_err(accel_dev, 1032 offset, 1033 ADF_RAS_CORR, 1034 "invalid speed"); 1035 1036 if (reg_val & ADF_C4XXX_MAC_PIA_RX_FIFO_OVERRUN) { 1037 *reset_required = true; 1038 adf_log_inln_err(accel_dev, 1039 offset, 1040 ADF_RAS_FATAL, 1041 "pia rx fifo overrun fatal err"); 1042 } 1043 1044 if (reg_val & ADF_C4XXX_MAC_PIA_TX_FIFO_OVERRUN) { 1045 *reset_required = true; 1046 adf_log_inln_err(accel_dev, 1047 offset, 1048 ADF_RAS_FATAL, 1049 "pia tx fifo overrun fatal err"); 1050 } 1051 1052 if (reg_val & ADF_C4XXX_MAC_PIA_TX_FIFO_UNDERRUN) { 1053 *reset_required = true; 1054 adf_log_inln_err(accel_dev, 1055 offset, 1056 ADF_RAS_FATAL, 1057 "pia tx fifo underrun fatal err"); 1058 } 1059 1060 /* Clear the interrupt and allow the next error to be logged. */ 1061 ADF_CSR_WR64(aram_base_addr, ADF_C4XXX_MAC_IP + offset, reg_val); 1062 } 1063 1064 static inline bool 1065 adf_handle_rf_par_err(struct adf_accel_dev *accel_dev, 1066 struct resource *aram_base_addr, 1067 u32 rf_par_addr, 1068 u32 rf_par_msk, 1069 u32 offset, 1070 char *msg) 1071 { 1072 u32 reg_val; 1073 unsigned long intr_status; 1074 int i; 1075 char strbuf[ADF_C4XXX_MAX_STR_LEN]; 1076 1077 /* Handle rf parity error */ 1078 reg_val = ADF_CSR_RD(aram_base_addr, rf_par_addr + offset); 1079 intr_status = reg_val & rf_par_msk; 1080 if (intr_status) { 1081 for_each_set_bit(i, &intr_status, ADF_C4XXX_RF_PAR_ERR_BITS) 1082 { 1083 if (i % 2 == 0) 1084 snprintf(strbuf, 1085 sizeof(strbuf), 1086 "%s mul par %u uncorr fatal err", 1087 msg, 1088 RF_PAR_MUL_MAP(i)); 1089 1090 else 1091 snprintf(strbuf, 1092 sizeof(strbuf), 1093 "%s par %u uncorr fatal err", 1094 msg, 1095 RF_PAR_MAP(i)); 1096 1097 adf_log_inln_err(accel_dev, 1098 offset, 1099 ADF_RAS_FATAL, 1100 strbuf); 1101 } 1102 1103 /* Clear the interrupt and allow the next error to be logged. */ 1104 ADF_CSR_WR(aram_base_addr, rf_par_addr + offset, reg_val); 1105 return true; 1106 } 1107 return false; 1108 } 1109 1110 static inline void 1111 adf_handle_cd_rf_par_err(struct adf_accel_dev *accel_dev, 1112 struct resource *aram_base_addr, 1113 u32 offset, 1114 bool *reset_required) 1115 { 1116 /* Handle reg_cd_rf_parity_err[1] */ 1117 *reset_required |= 1118 adf_handle_rf_par_err(accel_dev, 1119 aram_base_addr, 1120 ADF_C4XXX_IC_CD_RF_PARITY_ERR_1, 1121 ADF_C4XXX_CD_RF_PAR_ERR_1_INTR, 1122 offset, 1123 "cd rf par[1]:") ? 1124 true : 1125 false; 1126 } 1127 1128 static inline void 1129 adf_handle_inln_rf_par_err(struct adf_accel_dev *accel_dev, 1130 struct resource *aram_base_addr, 1131 u32 offset, 1132 bool *reset_required) 1133 { 1134 /* Handle reg_inln_rf_parity_err[0] */ 1135 *reset_required |= 1136 adf_handle_rf_par_err(accel_dev, 1137 aram_base_addr, 1138 ADF_C4XXX_IC_INLN_RF_PARITY_ERR_0, 1139 ADF_C4XXX_INLN_RF_PAR_ERR_0_INTR, 1140 offset, 1141 "inln rf par[0]:") ? 1142 true : 1143 false; 1144 1145 /* Handle reg_inln_rf_parity_err[1] */ 1146 *reset_required |= 1147 adf_handle_rf_par_err(accel_dev, 1148 aram_base_addr, 1149 ADF_C4XXX_IC_INLN_RF_PARITY_ERR_1, 1150 ADF_C4XXX_INLN_RF_PAR_ERR_1_INTR, 1151 offset, 1152 "inln rf par[1]:") ? 1153 true : 1154 false; 1155 1156 /* Handle reg_inln_rf_parity_err[2] */ 1157 *reset_required |= 1158 adf_handle_rf_par_err(accel_dev, 1159 aram_base_addr, 1160 ADF_C4XXX_IC_INLN_RF_PARITY_ERR_2, 1161 ADF_C4XXX_INLN_RF_PAR_ERR_2_INTR, 1162 offset, 1163 "inln rf par[2]:") ? 1164 true : 1165 false; 1166 1167 /* Handle reg_inln_rf_parity_err[5] */ 1168 *reset_required |= 1169 adf_handle_rf_par_err(accel_dev, 1170 aram_base_addr, 1171 ADF_C4XXX_IC_INLN_RF_PARITY_ERR_5, 1172 ADF_C4XXX_INLN_RF_PAR_ERR_5_INTR, 1173 offset, 1174 "inln rf par[5]:") ? 1175 true : 1176 false; 1177 } 1178 1179 static inline void 1180 adf_handle_congest_mngt_intr(struct adf_accel_dev *accel_dev, 1181 struct resource *aram_base_addr, 1182 u32 offset, 1183 bool *reset_required) 1184 { 1185 u32 reg_val; 1186 1187 reg_val = ADF_CSR_RD(aram_base_addr, 1188 ADF_C4XXX_IC_CONGESTION_MGMT_INT + offset); 1189 1190 /* A mis-configuration of CPM, a mis-configuration of the Ethernet 1191 * Complex or that the traffic profile has deviated from that for 1192 * which the resources were configured 1193 */ 1194 if (reg_val & ADF_C4XXX_CONGESTION_MGMT_CTPB_GLOBAL_CROSSED) { 1195 adf_log_inln_err( 1196 accel_dev, 1197 offset, 1198 ADF_RAS_FATAL, 1199 "congestion mgmt ctpb global crossed fatal err"); 1200 *reset_required = true; 1201 } 1202 1203 if (reg_val & ADF_C4XXX_CONGESTION_MGMT_XOFF_CIRQ_OUT) { 1204 adf_log_inln_err(accel_dev, 1205 offset, 1206 ADF_RAS_CORR, 1207 "congestion mgmt XOFF cirq out err"); 1208 } 1209 1210 if (reg_val & ADF_C4XXX_CONGESTION_MGMT_XOFF_CIRQ_IN) { 1211 adf_log_inln_err(accel_dev, 1212 offset, 1213 ADF_RAS_CORR, 1214 "congestion mgmt XOFF cirq in err"); 1215 } 1216 1217 /* Clear the interrupt and allow the next error to be logged */ 1218 ADF_CSR_WR(aram_base_addr, 1219 ADF_C4XXX_IC_CONGESTION_MGMT_INT + offset, 1220 reg_val); 1221 } 1222 1223 static inline void 1224 adf_handle_inline_intr(struct adf_accel_dev *accel_dev, 1225 struct resource *aram_base_addr, 1226 u32 csr_offset, 1227 bool *reset_required) 1228 { 1229 adf_handle_cd_rf_par_err(accel_dev, 1230 aram_base_addr, 1231 csr_offset, 1232 reset_required); 1233 1234 adf_handle_parser_uerr(accel_dev, 1235 aram_base_addr, 1236 csr_offset, 1237 reset_required); 1238 1239 adf_handle_inln_rf_par_err(accel_dev, 1240 aram_base_addr, 1241 csr_offset, 1242 reset_required); 1243 1244 adf_handle_congest_mngt_intr(accel_dev, 1245 aram_base_addr, 1246 csr_offset, 1247 reset_required); 1248 1249 adf_handle_mac_intr(accel_dev, 1250 aram_base_addr, 1251 csr_offset, 1252 reset_required); 1253 } 1254 1255 static inline void 1256 adf_process_errsou11(struct adf_accel_dev *accel_dev, 1257 struct resource *pmisc, 1258 u32 errsou, 1259 bool *reset_required) 1260 { 1261 struct resource *aram_base_addr = 1262 (&GET_BARS(accel_dev)[ADF_C4XXX_SRAM_BAR])->virt_addr; 1263 1264 if (errsou & ADF_C4XXX_TI_MISC) 1265 adf_handle_ti_misc_err(accel_dev, pmisc); 1266 1267 if (errsou & ADF_C4XXX_RI_PUSH_PULL_PAR_ERR) 1268 adf_handle_ri_push_pull_par_err(accel_dev, pmisc); 1269 1270 if (errsou & ADF_C4XXX_TI_PUSH_PULL_PAR_ERR) 1271 adf_handle_ti_push_pull_par_err(accel_dev, pmisc); 1272 1273 if (errsou & ADF_C4XXX_ARAM_CORR_ERR) 1274 adf_handle_aram_corr_err(accel_dev, aram_base_addr); 1275 1276 if (errsou & ADF_C4XXX_ARAM_UNCORR_ERR) 1277 adf_handle_aram_uncorr_err(accel_dev, aram_base_addr); 1278 1279 if (errsou & ADF_C4XXX_TI_PULL_PAR_ERR) 1280 adf_handle_ti_pull_par_err(accel_dev, pmisc); 1281 1282 if (errsou & ADF_C4XXX_RI_PUSH_PAR_ERR) 1283 adf_handle_ri_push_par_err(accel_dev, pmisc); 1284 1285 if (errsou & ADF_C4XXX_INLINE_INGRESS_INTR) 1286 adf_handle_inline_intr(accel_dev, 1287 aram_base_addr, 1288 ADF_C4XXX_INLINE_INGRESS_OFFSET, 1289 reset_required); 1290 1291 if (errsou & ADF_C4XXX_INLINE_EGRESS_INTR) 1292 adf_handle_inline_intr(accel_dev, 1293 aram_base_addr, 1294 ADF_C4XXX_INLINE_EGRESS_OFFSET, 1295 reset_required); 1296 } 1297 1298 bool 1299 adf_ras_interrupts(struct adf_accel_dev *accel_dev, bool *reset_required) 1300 { 1301 u32 errsou = 0; 1302 bool handled = false; 1303 struct adf_hw_device_data *hw_data = accel_dev->hw_device; 1304 u32 num_accels = hw_data->get_num_accels(hw_data); 1305 struct resource *pmisc = 1306 (&GET_BARS(accel_dev)[ADF_C4XXX_PMISC_BAR])->virt_addr; 1307 1308 if (unlikely(!reset_required)) { 1309 device_printf(GET_DEV(accel_dev), 1310 "Invalid pointer reset_required\n"); 1311 return false; 1312 } 1313 1314 /* errsou8 */ 1315 errsou = ADF_CSR_RD(pmisc, ADF_C4XXX_ERRSOU8); 1316 if (errsou & ADF_C4XXX_ERRSOU8_MECORR_MASK) { 1317 adf_process_errsou8(accel_dev, pmisc); 1318 handled = true; 1319 } 1320 1321 /* errsou9 */ 1322 errsou = ADF_CSR_RD(pmisc, ADF_C4XXX_ERRSOU9); 1323 if (errsou & ADF_C4XXX_ERRSOU9_ERROR_MASK) { 1324 adf_process_errsou9(accel_dev, pmisc, errsou, reset_required); 1325 handled = true; 1326 } 1327 1328 /* errsou10 */ 1329 errsou = ADF_CSR_RD(pmisc, ADF_C4XXX_ERRSOU10); 1330 if (errsou & ADF_C4XXX_ERRSOU10_RAS_MASK) { 1331 adf_process_errsou10( 1332 accel_dev, pmisc, errsou, num_accels, reset_required); 1333 handled = true; 1334 } 1335 1336 /* errsou11 */ 1337 errsou = ADF_CSR_RD(pmisc, ADF_C4XXX_ERRSOU11); 1338 if (errsou & ADF_C4XXX_ERRSOU11_ERROR_MASK) { 1339 adf_process_errsou11(accel_dev, pmisc, errsou, reset_required); 1340 handled = true; 1341 } 1342 1343 return handled; 1344 } 1345