1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 /* $FreeBSD$ */ 4 #ifndef ADF_C62X_HW_DATA_H_ 5 #define ADF_C62X_HW_DATA_H_ 6 7 /* PCIe configuration space */ 8 #define ADF_C62X_SRAM_BAR 0 9 #define ADF_C62X_PMISC_BAR 1 10 #define ADF_C62X_ETR_BAR 2 11 #define ADF_C62X_RX_RINGS_OFFSET 8 12 #define ADF_C62X_TX_RINGS_MASK 0xFF 13 #define ADF_C62X_MAX_ACCELERATORS 5 14 #define ADF_C62X_MAX_ACCELENGINES 10 15 #define ADF_C62X_ACCELERATORS_REG_OFFSET 16 16 #define ADF_C62X_ACCELERATORS_MASK 0x1F 17 #define ADF_C62X_ACCELENGINES_MASK 0x3FF 18 #define ADF_C62X_ETR_MAX_BANKS 16 19 #define ADF_C62X_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28) 20 #define ADF_C62X_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30) 21 #define ADF_C62X_SMIA0_MASK 0xFFFF 22 #define ADF_C62X_SMIA1_MASK 0x1 23 #define ADF_C62X_SOFTSTRAP_CSR_OFFSET 0x2EC 24 #define ADF_C62X_POWERGATE_PKE BIT(24) 25 #define ADF_C62X_POWERGATE_DC BIT(23) 26 27 /* Error detection and correction */ 28 #define ADF_C62X_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818) 29 #define ADF_C62X_AE_MISC_CONTROL(i) (i * 0x1000 + 0x20960) 30 #define ADF_C62X_ENABLE_AE_ECC_ERR BIT(28) 31 #define ADF_C62X_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12)) 32 #define ADF_C62X_UERRSSMSH(i) (i * 0x4000 + 0x18) 33 #define ADF_C62X_CERRSSMSH(i) (i * 0x4000 + 0x10) 34 #define ADF_C62X_ERRSOU3 (0x3A000 + 0x0C) 35 #define ADF_C62X_ERRSOU5 (0x3A000 + 0xD8) 36 #define ADF_C62X_ERRSSMSH_EN (BIT(3)) 37 /* BIT(2) enables the logging of push/pull data errors. */ 38 #define ADF_C62X_PPERR_EN (BIT(2)) 39 40 /* Mask for VF2PF interrupts */ 41 #define ADF_C62X_VF2PF1_16 (0xFFFF << 9) 42 #define ADF_C62X_ERRSOU3_VF2PF(errsou3) (((errsou3)&0x01FFFE00) >> 9) 43 #define ADF_C62X_ERRMSK3_VF2PF(vf_mask) (((vf_mask)&0xFFFF) << 9) 44 45 /* Masks for correctable error interrupts. */ 46 #define ADF_C62X_ERRMSK0_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0)) 47 #define ADF_C62X_ERRMSK1_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0)) 48 #define ADF_C62X_ERRMSK3_CERR (BIT(7)) 49 #define ADF_C62X_ERRMSK4_CERR (BIT(8) | BIT(0)) 50 #define ADF_C62X_ERRMSK5_CERR (0) 51 52 /* Masks for uncorrectable error interrupts. */ 53 #define ADF_C62X_ERRMSK0_UERR (BIT(25) | BIT(17) | BIT(9) | BIT(1)) 54 #define ADF_C62X_ERRMSK1_UERR (BIT(25) | BIT(17) | BIT(9) | BIT(1)) 55 #define ADF_C62X_ERRMSK3_UERR \ 56 (BIT(8) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(0)) 57 #define ADF_C62X_ERRMSK4_UERR (BIT(9) | BIT(1)) 58 #define ADF_C62X_ERRMSK5_UERR (BIT(18) | BIT(17) | BIT(16)) 59 60 /* RI CPP control */ 61 #define ADF_C62X_RICPPINTCTL (0x3A000 + 0x110) 62 /* 63 * BIT(2) enables error detection and reporting on the RI Parity Error. 64 * BIT(1) enables error detection and reporting on the RI CPP Pull interface. 65 * BIT(0) enables error detection and reporting on the RI CPP Push interface. 66 */ 67 #define ADF_C62X_RICPP_EN (BIT(2) | BIT(1) | BIT(0)) 68 69 /* TI CPP control */ 70 #define ADF_C62X_TICPPINTCTL (0x3A400 + 0x138) 71 /* 72 * BIT(4) enables parity error detection and reporting on the Secure RAM. 73 * BIT(3) enables error detection and reporting on the ETR Parity Error. 74 * BIT(2) enables error detection and reporting on the TI Parity Error. 75 * BIT(1) enables error detection and reporting on the TI CPP Pull interface. 76 * BIT(0) enables error detection and reporting on the TI CPP Push interface. 77 */ 78 #define ADF_C62X_TICPP_EN (BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)) 79 80 /* CFC Uncorrectable Errors */ 81 #define ADF_C62X_CPP_CFC_ERR_CTRL (0x30000 + 0xC00) 82 /* 83 * BIT(1) enables interrupt. 84 * BIT(0) enables detecting and logging of push/pull data errors. 85 */ 86 #define ADF_C62X_CPP_CFC_UE (BIT(1) | BIT(0)) 87 88 #define ADF_C62X_PF2VF_OFFSET(i) (0x3A000 + 0x280 + ((i)*0x04)) 89 #define ADF_C62X_VINTMSK_OFFSET(i) (0x3A000 + 0x200 + ((i)*0x04)) 90 91 /* Arbiter configuration */ 92 #define ADF_C62X_ARB_OFFSET 0x30000 93 #define ADF_C62X_ARB_WRK_2_SER_MAP_OFFSET 0x180 94 #define ADF_C62X_ARB_WQCFG_OFFSET 0x100 95 96 /* Admin Interface Reg Offset */ 97 #define ADF_C62X_ADMINMSGUR_OFFSET (0x3A000 + 0x574) 98 #define ADF_C62X_ADMINMSGLR_OFFSET (0x3A000 + 0x578) 99 #define ADF_C62X_MAILBOX_BASE_OFFSET 0x20970 100 101 /* Firmware Binary */ 102 #define ADF_C62X_FW "qat_c62x_fw" 103 #define ADF_C62X_MMP "qat_c62x_mmp_fw" 104 105 void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data); 106 void adf_clean_hw_data_c62x(struct adf_hw_device_data *hw_data); 107 108 #define ADF_C62X_AE_FREQ (685 * 1000000) 109 110 #define ADF_C62X_MIN_AE_FREQ (533 * 1000000) 111 #define ADF_C62X_MAX_AE_FREQ (800 * 1000000) 112 113 #define ADF_C62X_THREADS_ON_ENGINE 8 114 #define ADF_C62X_MAX_SERVICES 4 115 #define ADF_C62X_DEF_ASYM_MASK 0x03 116 117 #endif 118