1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 #ifndef ADF_C62X_HW_DATA_H_ 4 #define ADF_C62X_HW_DATA_H_ 5 6 /* PCIe configuration space */ 7 #define ADF_C62X_SRAM_BAR 0 8 #define ADF_C62X_PMISC_BAR 1 9 #define ADF_C62X_ETR_BAR 2 10 #define ADF_C62X_RX_RINGS_OFFSET 8 11 #define ADF_C62X_TX_RINGS_MASK 0xFF 12 #define ADF_C62X_MAX_ACCELERATORS 5 13 #define ADF_C62X_MAX_ACCELENGINES 10 14 #define ADF_C62X_ACCELERATORS_REG_OFFSET 16 15 #define ADF_C62X_ACCELERATORS_MASK 0x1F 16 #define ADF_C62X_ACCELENGINES_MASK 0x3FF 17 #define ADF_C62X_ETR_MAX_BANKS 16 18 #define ADF_C62X_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28) 19 #define ADF_C62X_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30) 20 #define ADF_C62X_SMIA0_MASK 0xFFFF 21 #define ADF_C62X_SMIA1_MASK 0x1 22 #define ADF_C62X_SOFTSTRAP_CSR_OFFSET 0x2EC 23 #define ADF_C62X_POWERGATE_PKE BIT(24) 24 #define ADF_C62X_POWERGATE_DC BIT(23) 25 26 /* Error detection and correction */ 27 #define ADF_C62X_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818) 28 #define ADF_C62X_AE_MISC_CONTROL(i) (i * 0x1000 + 0x20960) 29 #define ADF_C62X_ENABLE_AE_ECC_ERR BIT(28) 30 #define ADF_C62X_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12)) 31 #define ADF_C62X_UERRSSMSH(i) (i * 0x4000 + 0x18) 32 #define ADF_C62X_CERRSSMSH(i) (i * 0x4000 + 0x10) 33 #define ADF_C62X_ERRSOU3 (0x3A000 + 0x0C) 34 #define ADF_C62X_ERRSOU5 (0x3A000 + 0xD8) 35 #define ADF_C62X_ERRSSMSH_EN (BIT(3)) 36 /* BIT(2) enables the logging of push/pull data errors. */ 37 #define ADF_C62X_PPERR_EN (BIT(2)) 38 39 /* Mask for VF2PF interrupts */ 40 #define ADF_C62X_VF2PF1_16 (0xFFFF << 9) 41 #define ADF_C62X_ERRSOU3_VF2PF(errsou3) (((errsou3)&0x01FFFE00) >> 9) 42 #define ADF_C62X_ERRMSK3_VF2PF(vf_mask) (((vf_mask)&0xFFFF) << 9) 43 44 /* Masks for correctable error interrupts. */ 45 #define ADF_C62X_ERRMSK0_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0)) 46 #define ADF_C62X_ERRMSK1_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0)) 47 #define ADF_C62X_ERRMSK3_CERR (BIT(7)) 48 #define ADF_C62X_ERRMSK4_CERR (BIT(8) | BIT(0)) 49 #define ADF_C62X_ERRMSK5_CERR (0) 50 51 /* Masks for uncorrectable error interrupts. */ 52 #define ADF_C62X_ERRMSK0_UERR (BIT(25) | BIT(17) | BIT(9) | BIT(1)) 53 #define ADF_C62X_ERRMSK1_UERR (BIT(25) | BIT(17) | BIT(9) | BIT(1)) 54 #define ADF_C62X_ERRMSK3_UERR \ 55 (BIT(8) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(0)) 56 #define ADF_C62X_ERRMSK4_UERR (BIT(9) | BIT(1)) 57 #define ADF_C62X_ERRMSK5_UERR (BIT(18) | BIT(17) | BIT(16)) 58 59 /* RI CPP control */ 60 #define ADF_C62X_RICPPINTCTL (0x3A000 + 0x110) 61 /* 62 * BIT(2) enables error detection and reporting on the RI Parity Error. 63 * BIT(1) enables error detection and reporting on the RI CPP Pull interface. 64 * BIT(0) enables error detection and reporting on the RI CPP Push interface. 65 */ 66 #define ADF_C62X_RICPP_EN (BIT(2) | BIT(1) | BIT(0)) 67 68 /* TI CPP control */ 69 #define ADF_C62X_TICPPINTCTL (0x3A400 + 0x138) 70 /* 71 * BIT(4) enables parity error detection and reporting on the Secure RAM. 72 * BIT(3) enables error detection and reporting on the ETR Parity Error. 73 * BIT(2) enables error detection and reporting on the TI Parity Error. 74 * BIT(1) enables error detection and reporting on the TI CPP Pull interface. 75 * BIT(0) enables error detection and reporting on the TI CPP Push interface. 76 */ 77 #define ADF_C62X_TICPP_EN (BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)) 78 79 /* CFC Uncorrectable Errors */ 80 #define ADF_C62X_CPP_CFC_ERR_CTRL (0x30000 + 0xC00) 81 /* 82 * BIT(1) enables interrupt. 83 * BIT(0) enables detecting and logging of push/pull data errors. 84 */ 85 #define ADF_C62X_CPP_CFC_UE (BIT(1) | BIT(0)) 86 87 #define ADF_C62X_PF2VF_OFFSET(i) (0x3A000 + 0x280 + ((i)*0x04)) 88 #define ADF_C62X_VINTMSK_OFFSET(i) (0x3A000 + 0x200 + ((i)*0x04)) 89 90 /* Arbiter configuration */ 91 #define ADF_C62X_ARB_OFFSET 0x30000 92 #define ADF_C62X_ARB_WRK_2_SER_MAP_OFFSET 0x180 93 #define ADF_C62X_ARB_WQCFG_OFFSET 0x100 94 95 /* Admin Interface Reg Offset */ 96 #define ADF_C62X_ADMINMSGUR_OFFSET (0x3A000 + 0x574) 97 #define ADF_C62X_ADMINMSGLR_OFFSET (0x3A000 + 0x578) 98 #define ADF_C62X_MAILBOX_BASE_OFFSET 0x20970 99 100 /* Firmware Binary */ 101 #define ADF_C62X_FW "qat_c62x_fw" 102 #define ADF_C62X_MMP "qat_c62x_mmp_fw" 103 104 void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data); 105 void adf_clean_hw_data_c62x(struct adf_hw_device_data *hw_data); 106 107 #define ADF_C62X_AE_FREQ (685 * 1000000) 108 109 #define ADF_C62X_MIN_AE_FREQ (533 * 1000000) 110 #define ADF_C62X_MAX_AE_FREQ (800 * 1000000) 111 112 #define ADF_C62X_THREADS_ON_ENGINE 8 113 #define ADF_C62X_MAX_SERVICES 4 114 #define ADF_C62X_DEF_ASYM_MASK 0x03 115 116 #endif 117