1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 /* $FreeBSD$ */ 4 #ifndef ADF_DH895x_HW_DATA_H_ 5 #define ADF_DH895x_HW_DATA_H_ 6 7 /* PCIe configuration space */ 8 #define ADF_DH895XCC_SRAM_BAR 0 9 #define ADF_DH895XCC_PMISC_BAR 1 10 #define ADF_DH895XCC_ETR_BAR 2 11 #define ADF_DH895XCC_RX_RINGS_OFFSET 8 12 #define ADF_DH895XCC_TX_RINGS_MASK 0xFF 13 #define ADF_DH895XCC_FUSECTL_SKU_MASK 0x300000 14 #define ADF_DH895XCC_FUSECTL_SKU_SHIFT 20 15 #define ADF_DH895XCC_FUSECTL_SKU_1 0x0 16 #define ADF_DH895XCC_FUSECTL_SKU_2 0x1 17 #define ADF_DH895XCC_FUSECTL_SKU_3 0x2 18 #define ADF_DH895XCC_FUSECTL_SKU_4 0x3 19 #define ADF_DH895XCC_MAX_ACCELERATORS 6 20 #define ADF_DH895XCC_MAX_ACCELENGINES 12 21 #define ADF_DH895XCC_ACCELERATORS_REG_OFFSET 13 22 #define ADF_DH895XCC_ACCELERATORS_MASK 0x3F 23 #define ADF_DH895XCC_ACCELENGINES_MASK 0xFFF 24 #define ADF_DH895XCC_ETR_MAX_BANKS 32 25 #define ADF_DH895XCC_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28) 26 #define ADF_DH895XCC_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30) 27 #define ADF_DH895XCC_SMIA0_MASK 0xFFFFFFFF 28 #define ADF_DH895XCC_SMIA1_MASK 0x1 29 /* Error detection and correction */ 30 #define ADF_DH895XCC_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818) 31 #define ADF_DH895XCC_AE_MISC_CONTROL(i) (i * 0x1000 + 0x20960) 32 #define ADF_DH895XCC_ENABLE_AE_ECC_ERR BIT(28) 33 #define ADF_DH895XCC_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12)) 34 #define ADF_DH895XCC_UERRSSMSH(i) (i * 0x4000 + 0x18) 35 #define ADF_DH895XCC_CERRSSMSH(i) (i * 0x4000 + 0x10) 36 #define ADF_DH895XCC_ERRSSMSH_EN BIT(3) 37 #define ADF_DH895XCC_ERRSOU3 (0x3A000 + 0x0C) 38 #define ADF_DH895XCC_ERRSOU5 (0x3A000 + 0xD8) 39 /* BIT(2) enables the logging of push/pull data errors. */ 40 #define ADF_DH895XCC_PPERR_EN (BIT(2)) 41 42 /* Masks for VF2PF interrupts */ 43 #define ADF_DH895XCC_VF2PF1_16 (0xFFFF << 9) 44 #define ADF_DH895XCC_VF2PF17_32 (0xFFFF) 45 #define ADF_DH895XCC_ERRSOU3_VF2PF_L(errsou3) (((errsou3)&0x01FFFE00) >> 9) 46 #define ADF_DH895XCC_ERRSOU5_VF2PF_U(errsou5) (((errsou5)&0x0000FFFF) << 16) 47 #define ADF_DH895XCC_ERRMSK3_VF2PF_L(vf_mask) (((vf_mask)&0xFFFF) << 9) 48 #define ADF_DH895XCC_ERRMSK5_VF2PF_U(vf_mask) ((vf_mask) >> 16) 49 50 /* Masks for correctable error interrupts. */ 51 #define ADF_DH895XCC_ERRMSK0_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0)) 52 #define ADF_DH895XCC_ERRMSK1_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0)) 53 #define ADF_DH895XCC_ERRMSK3_CERR (BIT(7)) 54 #define ADF_DH895XCC_ERRMSK4_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0)) 55 #define ADF_DH895XCC_ERRMSK5_CERR (0) 56 57 /* Masks for uncorrectable error interrupts. */ 58 #define ADF_DH895XCC_ERRMSK0_UERR (BIT(25) | BIT(17) | BIT(9) | BIT(1)) 59 #define ADF_DH895XCC_ERRMSK1_UERR (BIT(25) | BIT(17) | BIT(9) | BIT(1)) 60 #define ADF_DH895XCC_ERRMSK3_UERR \ 61 (BIT(8) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(0)) 62 #define ADF_DH895XCC_ERRMSK4_UERR (BIT(25) | BIT(17) | BIT(9) | BIT(1)) 63 #define ADF_DH895XCC_ERRMSK5_UERR (BIT(19) | BIT(18) | BIT(17) | BIT(16)) 64 65 /* RI CPP control */ 66 #define ADF_DH895XCC_RICPPINTCTL (0x3A000 + 0x110) 67 /* 68 * BIT(1) enables error detection and reporting on the RI CPP Pull interface. 69 * BIT(0) enables error detection and reporting on the RI CPP Push interface. 70 */ 71 #define ADF_DH895XCC_RICPP_EN (BIT(1) | BIT(0)) 72 73 /* TI CPP control */ 74 #define ADF_DH895XCC_TICPPINTCTL (0x3A400 + 0x138) 75 /* 76 * BIT(1) enables error detection and reporting on the TI CPP Pull interface. 77 * BIT(0) enables error detection and reporting on the TI CPP Push interface. 78 */ 79 #define ADF_DH895XCC_TICPP_EN (BIT(1) | BIT(0)) 80 81 /* CFC Uncorrectable Errors */ 82 #define ADF_DH895XCC_CPP_SHAC_ERR_CTRL (0x30000 + 0xC00) 83 /* 84 * BIT(1) enables interrupt. 85 * BIT(0) enables detecting and logging of push/pull data errors. 86 */ 87 #define ADF_DH895XCC_CPP_SHAC_UE (BIT(1) | BIT(0)) 88 89 /* Correctable SecureRAM Error Reg */ 90 #define ADF_DH895XCC_ESRAMCERR (0x3AC00 + 0x00) 91 /* BIT(3) enables fixing and logging of correctable errors. */ 92 #define ADF_DH895XCC_ESRAM_CERR (BIT(3)) 93 94 /* Uncorrectable SecureRAM Error Reg */ 95 #define ADF_DH895XCC_ESRAMUERR (ADF_SECRAMUERR) 96 /* 97 * BIT(17) enables interrupt. 98 * BIT(3) enables detecting and logging of uncorrectable errors. 99 */ 100 #define ADF_DH895XCC_ESRAM_UERR (BIT(17) | BIT(3)) 101 102 /* Miscellaneous Memory Target Errors Register */ 103 /* 104 * BIT(3) enables detecting and logging push/pull data errors. 105 * BIT(2) enables interrupt. 106 */ 107 #define ADF_DH895XCC_TGT_UERR (BIT(3) | BIT(2)) 108 109 #define ADF_DH895XCC_SLICEPWRDOWN(i) ((i)*0x4000 + 0x2C) 110 /* Enabling PKE4-PKE0. */ 111 #define ADF_DH895XCC_MMP_PWR_UP_MSK (BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3)) 112 113 /* CPM Uncorrectable Errors */ 114 #define ADF_DH895XCC_INTMASKSSM(i) ((i)*0x4000 + 0x0) 115 /* Disabling interrupts for correctable errors. */ 116 #define ADF_DH895XCC_INTMASKSSM_UERR \ 117 (BIT(11) | BIT(9) | BIT(7) | BIT(5) | BIT(3) | BIT(1)) 118 119 /* MMP */ 120 /* BIT(3) enables correction. */ 121 #define ADF_DH895XCC_CERRSSMMMP_EN (BIT(3)) 122 123 /* BIT(3) enables logging. */ 124 #define ADF_DH895XCC_UERRSSMMMP_EN (BIT(3)) 125 126 #define ADF_DH895XCC_PF2VF_OFFSET(i) (0x3A000 + 0x280 + ((i)*0x04)) 127 #define ADF_DH895XCC_VINTMSK_OFFSET(i) (0x3A000 + 0x200 + ((i)*0x04)) 128 129 /* Arbiter configuration */ 130 #define ADF_DH895XCC_ARB_OFFSET 0x30000 131 #define ADF_DH895XCC_ARB_WRK_2_SER_MAP_OFFSET 0x180 132 #define ADF_DH895XCC_ARB_WQCFG_OFFSET 0x100 133 134 /* Admin Interface Reg Offset */ 135 #define ADF_DH895XCC_ADMINMSGUR_OFFSET (0x3A000 + 0x574) 136 #define ADF_DH895XCC_ADMINMSGLR_OFFSET (0x3A000 + 0x578) 137 #define ADF_DH895XCC_MAILBOX_BASE_OFFSET 0x20970 138 139 /* FW names */ 140 #define ADF_DH895XCC_FW "qat_dh895xcc_fw" 141 #define ADF_DH895XCC_MMP "qat_dh895xcc_mmp_fw" 142 143 void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data); 144 void adf_clean_hw_data_dh895xcc(struct adf_hw_device_data *hw_data); 145 #define ADF_DH895XCC_AE_FREQ (933 * 1000000) 146 #endif 147