1 /*- 2 * Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/bus.h> 30 #include <sys/lock.h> 31 #include <sys/mutex.h> 32 #include <sys/rman.h> 33 #include <machine/bus.h> 34 35 #include <dev/extres/clk/clk.h> 36 #include <dev/extres/clk/clk_div.h> 37 #include <dev/extres/clk/clk_fixed.h> 38 #include <dev/extres/clk/clk_mux.h> 39 40 #include "qcom_clk_freqtbl.h" 41 #include "qcom_clk_apssdiv.h" 42 43 #include "clkdev_if.h" 44 45 /* 46 * This is a combination gate, divisor/PLL configuration 47 * for the APSS CPU clock. 48 */ 49 50 #if 0 51 #define DPRINTF(dev, msg...) device_printf(dev, "cpufreq_dt: " msg); 52 #else 53 #define DPRINTF(dev, msg...) 54 #endif 55 56 struct qcom_clk_apssdiv_sc { 57 struct clknode *clknode; 58 uint32_t div_offset; 59 uint32_t div_width; 60 uint32_t div_shift; 61 uint32_t enable_offset; 62 uint32_t enable_shift; 63 const struct qcom_clk_freq_tbl *freq_tbl; 64 }; 65 66 static uint64_t 67 qcom_clk_apssdiv_calc_rate(struct clknode *clk, uint64_t freq, uint32_t cdiv) 68 { 69 uint32_t pre_div; 70 71 /* 72 * The divisor isn't a linear map with a linear pre-divisor. 73 */ 74 if (cdiv > 10) { 75 pre_div = (cdiv + 1) * 2; 76 } else { 77 pre_div = cdiv + 12; 78 } 79 /* 80 * Multiplier is a fixed "2" here. 81 */ 82 return (freq * 2L) / pre_div; 83 } 84 85 static int 86 qcom_clk_apssdiv_recalc(struct clknode *clk, uint64_t *freq) 87 { 88 struct qcom_clk_apssdiv_sc *sc; 89 uint32_t reg, cdiv; 90 91 sc = clknode_get_softc(clk); 92 93 if (freq == NULL || *freq == 0) { 94 printf("%s: called; NULL or 0 frequency\n", __func__); 95 return (ENXIO); 96 } 97 98 CLKDEV_DEVICE_LOCK(clknode_get_device(sc->clknode)); 99 CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->div_offset, ®); 100 CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode)); 101 cdiv = (reg >> sc->div_shift) & ((1U << sc->div_width) - 1); 102 103 DPRINTF(clknode_get_device(sc->clknode), 104 "%s: called; cdiv=0x%x, freq=%llu\n", __func__, cdiv, *freq); 105 106 *freq = qcom_clk_apssdiv_calc_rate(clk, *freq, cdiv); 107 108 DPRINTF(clknode_get_device(sc->clknode), 109 "%s: called; freq is %llu\n", __func__, *freq); 110 return (0); 111 } 112 113 #if 0 114 static bool 115 qcom_clk_apssdiv_get_gate_locked(struct qcom_clk_apssdiv_sc *sc) 116 { 117 uint32_t reg; 118 119 if (sc->enable_offset == 0) 120 return (false); 121 122 CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->enable_offset, 123 ®); 124 125 return (!! (reg & (1U << sc->enable_shift))); 126 } 127 #endif 128 129 static int 130 qcom_clk_apssdiv_init(struct clknode *clk, device_t dev) 131 { 132 133 /* 134 * There's only a single parent here for an fixed divisor, 135 * so just set it to 0; the caller doesn't need to supply it. 136 * 137 * Note that the freqtbl entries have an upstream clock, 138 * but the APSS div/gate only has a single upstream and we 139 * don't program anything else specific in here. 140 */ 141 clknode_init_parent_idx(clk, 0); 142 143 return (0); 144 } 145 146 static int 147 qcom_clk_apssdiv_set_gate(struct clknode *clk, bool enable) 148 { 149 struct qcom_clk_apssdiv_sc *sc; 150 uint32_t reg; 151 152 sc = clknode_get_softc(clk); 153 154 if (sc->enable_offset == 0) { 155 return (ENXIO); 156 } 157 158 DPRINTF(clknode_get_device(sc->clknode), 159 "%s: called; enable=%d\n", __func__, enable); 160 161 CLKDEV_DEVICE_LOCK(clknode_get_device(sc->clknode)); 162 CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->enable_offset, 163 ®); 164 if (enable) { 165 reg |= (1U << sc->enable_shift); 166 } else { 167 reg &= ~(1U << sc->enable_shift); 168 } 169 CLKDEV_WRITE_4(clknode_get_device(sc->clknode), sc->enable_offset, 170 reg); 171 CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode)); 172 173 return (0); 174 } 175 176 /* 177 * Set frequency 178 * 179 * fin - the parent frequency, if exists 180 * fout - starts as the requested frequency, ends with the configured 181 * or dry-run frequency 182 * Flags - CLK_SET_DRYRUN, CLK_SET_ROUND_UP, CLK_SET_ROUND_DOWN 183 * retval - 0, ERANGE 184 */ 185 static int 186 qcom_clk_apssdiv_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout, 187 int flags, int *stop) 188 { 189 const struct qcom_clk_freq_tbl *f; 190 struct qcom_clk_apssdiv_sc *sc; 191 uint64_t f_freq; 192 uint32_t reg; 193 194 sc = clknode_get_softc(clk); 195 196 /* There are no further PLLs to set in this chain */ 197 *stop = 1; 198 199 /* Search the table for a suitable frequency */ 200 f = qcom_clk_freq_tbl_lookup(sc->freq_tbl, *fout); 201 if (f == NULL) { 202 return (ERANGE); 203 } 204 205 /* 206 * Calculate what the resultant frequency would be based on the 207 * parent PLL. 208 */ 209 f_freq = qcom_clk_apssdiv_calc_rate(clk, fin, f->pre_div); 210 211 DPRINTF(clknode_get_device(sc->clknode), 212 "%s: dryrun: %d, fin=%llu fout=%llu f_freq=%llu pre_div=%u" 213 " target_freq=%llu\n", 214 __func__, 215 !! (flags & CLK_SET_DRYRUN), 216 fin, *fout, f_freq, f->pre_div, f->freq); 217 218 if (flags & CLK_SET_DRYRUN) { 219 *fout = f_freq; 220 return (0); 221 } 222 223 /* 224 * Program in the new pre-divisor. 225 */ 226 CLKDEV_DEVICE_LOCK(clknode_get_device(sc->clknode)); 227 CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->div_offset, ®); 228 reg &= ~(((1U << sc->div_width) - 1) << sc->div_shift); 229 reg |= (f->pre_div << sc->div_shift); 230 CLKDEV_WRITE_4(clknode_get_device(sc->clknode), sc->div_offset, reg); 231 CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode)); 232 233 /* 234 * The linux driver notes there's no status/completion bit to poll. 235 * So sleep for a bit and hope that's enough time for it to 236 * settle. 237 */ 238 DELAY(1); 239 240 *fout = f_freq; 241 242 return (0); 243 } 244 245 static clknode_method_t qcom_clk_apssdiv_methods[] = { 246 /* Device interface */ 247 CLKNODEMETHOD(clknode_init, qcom_clk_apssdiv_init), 248 CLKNODEMETHOD(clknode_recalc_freq, qcom_clk_apssdiv_recalc), 249 CLKNODEMETHOD(clknode_set_gate, qcom_clk_apssdiv_set_gate), 250 CLKNODEMETHOD(clknode_set_freq, qcom_clk_apssdiv_set_freq), 251 CLKNODEMETHOD_END 252 }; 253 254 DEFINE_CLASS_1(qcom_clk_apssdiv, qcom_clk_apssdiv_class, 255 qcom_clk_apssdiv_methods, sizeof(struct qcom_clk_apssdiv_sc), 256 clknode_class); 257 258 int 259 qcom_clk_apssdiv_register(struct clkdom *clkdom, 260 struct qcom_clk_apssdiv_def *clkdef) 261 { 262 struct clknode *clk; 263 struct qcom_clk_apssdiv_sc *sc; 264 265 clk = clknode_create(clkdom, &qcom_clk_apssdiv_class, &clkdef->clkdef); 266 if (clk == NULL) 267 return (1); 268 269 sc = clknode_get_softc(clk); 270 sc->clknode = clk; 271 272 sc->div_offset = clkdef->div_offset; 273 sc->div_width = clkdef->div_width; 274 sc->div_shift = clkdef->div_shift; 275 sc->freq_tbl = clkdef->freq_tbl; 276 sc->enable_offset = clkdef->enable_offset; 277 sc->enable_shift = clkdef->enable_shift; 278 279 clknode_register(clkdom, clk); 280 281 return (0); 282 } 283