1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __COMMON_HSI__ 32 #define __COMMON_HSI__ 33 /********************************/ 34 /* PROTOCOL COMMON FW CONSTANTS */ 35 /********************************/ 36 37 /* Temporarily here should be added to HSI automatically by resource allocation tool.*/ 38 #define T_TEST_AGG_INT_TEMP 6 39 #define M_TEST_AGG_INT_TEMP 8 40 #define U_TEST_AGG_INT_TEMP 6 41 #define X_TEST_AGG_INT_TEMP 14 42 #define Y_TEST_AGG_INT_TEMP 4 43 #define P_TEST_AGG_INT_TEMP 4 44 45 #define X_FINAL_CLEANUP_AGG_INT 1 46 47 #define EVENT_RING_PAGE_SIZE_BYTES 4096 48 49 #define NUM_OF_GLOBAL_QUEUES 128 50 #define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64 51 52 #define ISCSI_CDU_TASK_SEG_TYPE 0 53 #define FCOE_CDU_TASK_SEG_TYPE 0 54 #define RDMA_CDU_TASK_SEG_TYPE 1 55 56 #define FW_ASSERT_GENERAL_ATTN_IDX 32 57 58 #define MAX_PINNED_CCFC 32 59 60 #define EAGLE_ENG1_WORKAROUND_NIG_FLOWCTRL_MODE 3 61 62 /* Queue Zone sizes in bytes */ 63 #define TSTORM_QZONE_SIZE 8 /*tstorm_scsi_queue_zone*/ 64 #define MSTORM_QZONE_SIZE 16 /*mstorm_eth_queue_zone. Used only for RX producer of VFs in backward compatibility mode.*/ 65 #define USTORM_QZONE_SIZE 8 /*ustorm_eth_queue_zone*/ 66 #define XSTORM_QZONE_SIZE 8 /*xstorm_eth_queue_zone*/ 67 #define YSTORM_QZONE_SIZE 0 68 #define PSTORM_QZONE_SIZE 0 69 70 #define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7 /*Log of mstorm default VF zone size.*/ 71 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16 /*Maximum number of RX queues that can be allocated to VF by default*/ 72 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48 /*Maximum number of RX queues that can be allocated to VF with doubled VF zone size. Up to 96 VF supported in this mode*/ 73 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112 /*Maximum number of RX queues that can be allocated to VF with 4 VF zone size. Up to 48 VF supported in this mode*/ 74 75 76 /********************************/ 77 /* CORE (LIGHT L2) FW CONSTANTS */ 78 /********************************/ 79 80 #define CORE_LL2_MAX_RAMROD_PER_CON 8 81 #define CORE_LL2_TX_BD_PAGE_SIZE_BYTES 4096 82 #define CORE_LL2_RX_BD_PAGE_SIZE_BYTES 4096 83 #define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES 4096 84 #define CORE_LL2_RX_NUM_NEXT_PAGE_BDS 1 85 86 #define CORE_LL2_TX_MAX_BDS_PER_PACKET 12 87 88 #define CORE_SPQE_PAGE_SIZE_BYTES 4096 89 90 /* 91 * Usually LL2 queues are opened in pairs � TX-RX. 92 * There is a hard restriction on number of RX queues (limited by Tstorm RAM) and TX counters (Pstorm RAM). 93 * Number of TX queues is almost unlimited. 94 * The constants are different so as to allow asymmetric LL2 connections 95 */ 96 97 #define MAX_NUM_LL2_RX_QUEUES 48 98 #define MAX_NUM_LL2_TX_STATS_COUNTERS 48 99 100 101 /////////////////////////////////////////////////////////////////////////////////////////////////// 102 // Include firmware verison number only- do not add constants here to avoid redundunt compilations 103 /////////////////////////////////////////////////////////////////////////////////////////////////// 104 105 106 #define FW_MAJOR_VERSION 8 107 #define FW_MINOR_VERSION 30 108 #define FW_REVISION_VERSION 0 109 #define FW_ENGINEERING_VERSION 0 110 111 /***********************/ 112 /* COMMON HW CONSTANTS */ 113 /***********************/ 114 115 /* PCI functions */ 116 #define MAX_NUM_PORTS_BB (2) 117 #define MAX_NUM_PORTS_K2 (4) 118 #define MAX_NUM_PORTS_E5 (MAX_NUM_PORTS_K2) 119 #define MAX_NUM_PORTS (MAX_NUM_PORTS_E5) 120 121 #define MAX_NUM_PFS_BB (8) 122 #define MAX_NUM_PFS_K2 (16) 123 #define MAX_NUM_PFS_E5 (MAX_NUM_PFS_K2) 124 #define MAX_NUM_PFS (MAX_NUM_PFS_E5) 125 #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */ 126 127 #define MAX_NUM_VFS_BB (120) 128 #define MAX_NUM_VFS_K2 (192) 129 #define MAX_NUM_VFS_E4 (MAX_NUM_VFS_K2) 130 #define MAX_NUM_VFS_E5 (240) 131 #define COMMON_MAX_NUM_VFS (MAX_NUM_VFS_E5) 132 133 #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB) 134 #define MAX_NUM_FUNCTIONS_K2 (MAX_NUM_PFS_K2 + MAX_NUM_VFS_K2) 135 #define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + MAX_NUM_VFS_E4) 136 137 /* in both BB and K2, the VF number starts from 16. so for arrays containing all */ 138 /* possible PFs and VFs - we need a constant for this size */ 139 #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB) 140 #define MAX_FUNCTION_NUMBER_K2 (MAX_NUM_PFS + MAX_NUM_VFS_K2) 141 #define MAX_FUNCTION_NUMBER_E4 (MAX_NUM_PFS + MAX_NUM_VFS_E4) 142 #define MAX_FUNCTION_NUMBER_E5 (MAX_NUM_PFS + MAX_NUM_VFS_E5) 143 #define COMMON_MAX_FUNCTION_NUMBER (MAX_NUM_PFS + MAX_NUM_VFS_E5) 144 145 #define MAX_NUM_VPORTS_K2 (208) 146 #define MAX_NUM_VPORTS_BB (160) 147 #define MAX_NUM_VPORTS_E4 (MAX_NUM_VPORTS_K2) 148 #define MAX_NUM_VPORTS_E5 (256) 149 #define COMMON_MAX_NUM_VPORTS (MAX_NUM_VPORTS_E5) 150 151 #define MAX_NUM_L2_QUEUES_K2 (320) 152 #define MAX_NUM_L2_QUEUES_BB (256) 153 #define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_K2) 154 155 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */ 156 #define NUM_PHYS_TCS_4PORT_K2 (4) 157 #define NUM_PHYS_TCS_4PORT_E5 (6) 158 #define NUM_OF_PHYS_TCS (8) 159 #define PURE_LB_TC NUM_OF_PHYS_TCS 160 #define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1) 161 #define NUM_TCS_4PORT_E5 (NUM_PHYS_TCS_4PORT_E5 + 1) 162 #define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1) 163 164 /* Num of possible traffic priority values */ 165 #define NUM_OF_PRIO (8) 166 167 /* CIDs */ 168 #define NUM_OF_CONNECTION_TYPES_E4 (8) 169 #define NUM_OF_CONNECTION_TYPES_E5 (16) 170 #define NUM_OF_TASK_TYPES (8) 171 #define NUM_OF_LCIDS (320) 172 #define NUM_OF_LTIDS (320) 173 174 /* Clock values */ 175 #define MASTER_CLK_FREQ_E4 (375e6) 176 #define STORM_CLK_FREQ_E4 (1000e6) 177 #define CLK25M_CLK_FREQ_E4 (25e6) 178 179 #define STORM_CLK_DUAL_CORE_FREQ_E5 (3000e6) 180 181 /* Global PXP windows (GTT) */ 182 #define NUM_OF_GTT 19 183 #define GTT_DWORD_SIZE_BITS 10 184 #define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2) 185 #define GTT_DWORD_SIZE (1 << GTT_DWORD_SIZE_BITS) 186 187 /* Tools Version */ 188 #define TOOLS_VERSION 10 189 /*****************/ 190 /* CDU CONSTANTS */ 191 /*****************/ 192 193 #define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17) 194 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff) 195 196 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12) 197 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff) 198 199 #define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0) 200 #define CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT (1) 201 #define CDU_CONTEXT_VALIDATION_CFG_USE_TYPE (2) 202 #define CDU_CONTEXT_VALIDATION_CFG_USE_REGION (3) 203 #define CDU_CONTEXT_VALIDATION_CFG_USE_CID (4) 204 #define CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE (5) 205 206 207 /*****************/ 208 /* DQ CONSTANTS */ 209 /*****************/ 210 211 /* DEMS */ 212 #define DQ_DEMS_LEGACY 0 213 #define DQ_DEMS_TOE_MORE_TO_SEND 3 214 #define DQ_DEMS_TOE_LOCAL_ADV_WND 4 215 #define DQ_DEMS_ROCE_CQ_CONS 7 216 217 /* XCM agg val selection (HW) */ 218 #define DQ_XCM_AGG_VAL_SEL_WORD2 0 219 #define DQ_XCM_AGG_VAL_SEL_WORD3 1 220 #define DQ_XCM_AGG_VAL_SEL_WORD4 2 221 #define DQ_XCM_AGG_VAL_SEL_WORD5 3 222 #define DQ_XCM_AGG_VAL_SEL_REG3 4 223 #define DQ_XCM_AGG_VAL_SEL_REG4 5 224 #define DQ_XCM_AGG_VAL_SEL_REG5 6 225 #define DQ_XCM_AGG_VAL_SEL_REG6 7 226 227 /* XCM agg val selection (FW) */ 228 #define DQ_XCM_CORE_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 229 #define DQ_XCM_CORE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 230 #define DQ_XCM_CORE_SPQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 231 #define DQ_XCM_ETH_EDPM_NUM_BDS_CMD DQ_XCM_AGG_VAL_SEL_WORD2 232 #define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 233 #define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 234 #define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5 235 #define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 236 #define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 237 #define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5 238 #define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 239 #define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 240 #define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 241 #define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6 242 #define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 243 #define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 244 #define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 245 #define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4 246 247 /* UCM agg val selection (HW) */ 248 #define DQ_UCM_AGG_VAL_SEL_WORD0 0 249 #define DQ_UCM_AGG_VAL_SEL_WORD1 1 250 #define DQ_UCM_AGG_VAL_SEL_WORD2 2 251 #define DQ_UCM_AGG_VAL_SEL_WORD3 3 252 #define DQ_UCM_AGG_VAL_SEL_REG0 4 253 #define DQ_UCM_AGG_VAL_SEL_REG1 5 254 #define DQ_UCM_AGG_VAL_SEL_REG2 6 255 #define DQ_UCM_AGG_VAL_SEL_REG3 7 256 257 /* UCM agg val selection (FW) */ 258 #define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2 259 #define DQ_UCM_ETH_PMD_RX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD3 260 #define DQ_UCM_ROCE_CQ_CONS_CMD DQ_UCM_AGG_VAL_SEL_REG0 261 #define DQ_UCM_ROCE_CQ_PROD_CMD DQ_UCM_AGG_VAL_SEL_REG2 262 263 /* TCM agg val selection (HW) */ 264 #define DQ_TCM_AGG_VAL_SEL_WORD0 0 265 #define DQ_TCM_AGG_VAL_SEL_WORD1 1 266 #define DQ_TCM_AGG_VAL_SEL_WORD2 2 267 #define DQ_TCM_AGG_VAL_SEL_WORD3 3 268 #define DQ_TCM_AGG_VAL_SEL_REG1 4 269 #define DQ_TCM_AGG_VAL_SEL_REG2 5 270 #define DQ_TCM_AGG_VAL_SEL_REG6 6 271 #define DQ_TCM_AGG_VAL_SEL_REG9 7 272 273 /* TCM agg val selection (FW) */ 274 #define DQ_TCM_L2B_BD_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD1 275 #define DQ_TCM_ROCE_RQ_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD0 276 277 /* XCM agg counter flag selection (HW) */ 278 #define DQ_XCM_AGG_FLG_SHIFT_BIT14 0 279 #define DQ_XCM_AGG_FLG_SHIFT_BIT15 1 280 #define DQ_XCM_AGG_FLG_SHIFT_CF12 2 281 #define DQ_XCM_AGG_FLG_SHIFT_CF13 3 282 #define DQ_XCM_AGG_FLG_SHIFT_CF18 4 283 #define DQ_XCM_AGG_FLG_SHIFT_CF19 5 284 #define DQ_XCM_AGG_FLG_SHIFT_CF22 6 285 #define DQ_XCM_AGG_FLG_SHIFT_CF23 7 286 287 /* XCM agg counter flag selection (FW) */ 288 #define DQ_XCM_CORE_DQ_CF_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF18) 289 #define DQ_XCM_CORE_TERMINATE_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 290 #define DQ_XCM_CORE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 291 #define DQ_XCM_ETH_DQ_CF_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF18) 292 #define DQ_XCM_ETH_TERMINATE_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 293 #define DQ_XCM_ETH_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 294 #define DQ_XCM_ETH_TPH_EN_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23) 295 #define DQ_XCM_FCOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 296 #define DQ_XCM_ISCSI_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 297 #define DQ_XCM_ISCSI_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 298 #define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23) 299 #define DQ_XCM_TOE_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 300 #define DQ_XCM_TOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 301 302 /* UCM agg counter flag selection (HW) */ 303 #define DQ_UCM_AGG_FLG_SHIFT_CF0 0 304 #define DQ_UCM_AGG_FLG_SHIFT_CF1 1 305 #define DQ_UCM_AGG_FLG_SHIFT_CF3 2 306 #define DQ_UCM_AGG_FLG_SHIFT_CF4 3 307 #define DQ_UCM_AGG_FLG_SHIFT_CF5 4 308 #define DQ_UCM_AGG_FLG_SHIFT_CF6 5 309 #define DQ_UCM_AGG_FLG_SHIFT_RULE0EN 6 310 #define DQ_UCM_AGG_FLG_SHIFT_RULE1EN 7 311 312 /* UCM agg counter flag selection (FW) */ 313 #define DQ_UCM_ETH_PMD_TX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 314 #define DQ_UCM_ETH_PMD_RX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 315 #define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 316 #define DQ_UCM_ROCE_CQ_ARM_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 317 #define DQ_UCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF3) 318 #define DQ_UCM_TOE_SLOW_PATH_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 319 #define DQ_UCM_TOE_DQ_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 320 321 /* TCM agg counter flag selection (HW) */ 322 #define DQ_TCM_AGG_FLG_SHIFT_CF0 0 323 #define DQ_TCM_AGG_FLG_SHIFT_CF1 1 324 #define DQ_TCM_AGG_FLG_SHIFT_CF2 2 325 #define DQ_TCM_AGG_FLG_SHIFT_CF3 3 326 #define DQ_TCM_AGG_FLG_SHIFT_CF4 4 327 #define DQ_TCM_AGG_FLG_SHIFT_CF5 5 328 #define DQ_TCM_AGG_FLG_SHIFT_CF6 6 329 #define DQ_TCM_AGG_FLG_SHIFT_CF7 7 330 331 /* TCM agg counter flag selection (FW) */ 332 #define DQ_TCM_FCOE_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 333 #define DQ_TCM_FCOE_DUMMY_TIMER_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF2) 334 #define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 335 #define DQ_TCM_ISCSI_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 336 #define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 337 #define DQ_TCM_TOE_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 338 #define DQ_TCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 339 #define DQ_TCM_IWARP_POST_RQ_CF_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 340 341 /* PWM address mapping */ 342 #define DQ_PWM_OFFSET_DPM_BASE 0x0 343 #define DQ_PWM_OFFSET_DPM_END 0x27 344 #define DQ_PWM_OFFSET_XCM16_BASE 0x40 345 #define DQ_PWM_OFFSET_XCM32_BASE 0x44 346 #define DQ_PWM_OFFSET_UCM16_BASE 0x48 347 #define DQ_PWM_OFFSET_UCM32_BASE 0x4C 348 #define DQ_PWM_OFFSET_UCM16_4 0x50 349 #define DQ_PWM_OFFSET_TCM16_BASE 0x58 350 #define DQ_PWM_OFFSET_TCM32_BASE 0x5C 351 #define DQ_PWM_OFFSET_XCM_FLAGS 0x68 352 #define DQ_PWM_OFFSET_UCM_FLAGS 0x69 353 #define DQ_PWM_OFFSET_TCM_FLAGS 0x6B 354 355 #define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2) 356 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE) 357 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT (DQ_PWM_OFFSET_UCM16_4) 358 #define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT (DQ_PWM_OFFSET_UCM16_BASE + 2) 359 #define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS) 360 #define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1) 361 #define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3) 362 363 #define DQ_REGION_SHIFT (12) 364 365 /* DPM */ 366 #define DQ_DPM_WQE_BUFF_SIZE (320) 367 368 // Conn type ranges 369 #define DQ_CONN_TYPE_RANGE_SHIFT (4) 370 371 /*****************/ 372 /* QM CONSTANTS */ 373 /*****************/ 374 375 /* number of TX queues in the QM */ 376 #define MAX_QM_TX_QUEUES_K2 512 377 #define MAX_QM_TX_QUEUES_BB 448 378 #define MAX_QM_TX_QUEUES_E5 MAX_QM_TX_QUEUES_K2 379 #define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2 380 381 /* number of Other queues in the QM */ 382 #define MAX_QM_OTHER_QUEUES_BB 64 383 #define MAX_QM_OTHER_QUEUES_K2 128 384 #define MAX_QM_OTHER_QUEUES_E5 MAX_QM_OTHER_QUEUES_K2 385 #define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2 386 387 /* number of queues in a PF queue group */ 388 #define QM_PF_QUEUE_GROUP_SIZE 8 389 390 /* the size of a single queue element in bytes */ 391 #define QM_PQ_ELEMENT_SIZE 4 392 393 /* base number of Tx PQs in the CM PQ representation. 394 should be used when storing PQ IDs in CM PQ registers and context */ 395 #define CM_TX_PQ_BASE 0x200 396 397 /* number of global Vport/QCN rate limiters */ 398 #define MAX_QM_GLOBAL_RLS 256 399 400 /* QM registers data */ 401 #define QM_LINE_CRD_REG_WIDTH 16 402 #define QM_LINE_CRD_REG_SIGN_BIT (1 << (QM_LINE_CRD_REG_WIDTH - 1)) 403 #define QM_BYTE_CRD_REG_WIDTH 24 404 #define QM_BYTE_CRD_REG_SIGN_BIT (1 << (QM_BYTE_CRD_REG_WIDTH - 1)) 405 #define QM_WFQ_CRD_REG_WIDTH 32 406 #define QM_WFQ_CRD_REG_SIGN_BIT (1 << (QM_WFQ_CRD_REG_WIDTH - 1)) 407 #define QM_RL_CRD_REG_WIDTH 32 408 #define QM_RL_CRD_REG_SIGN_BIT (1 << (QM_RL_CRD_REG_WIDTH - 1)) 409 410 /*****************/ 411 /* CAU CONSTANTS */ 412 /*****************/ 413 414 #define CAU_FSM_ETH_RX 0 415 #define CAU_FSM_ETH_TX 1 416 417 /* Number of Protocol Indices per Status Block */ 418 #define PIS_PER_SB_E4 12 419 #define PIS_PER_SB_E5 8 420 #define MAX_PIS_PER_SB OSAL_MAX_T(u8, PIS_PER_SB_E4, PIS_PER_SB_E5) 421 422 423 #define CAU_HC_STOPPED_STATE 3 /* fsm is stopped or not valid for this sb */ 424 #define CAU_HC_DISABLE_STATE 4 /* fsm is working without interrupt coalescing for this sb*/ 425 #define CAU_HC_ENABLE_STATE 0 /* fsm is working with interrupt coalescing for this sb*/ 426 427 428 /*****************/ 429 /* IGU CONSTANTS */ 430 /*****************/ 431 432 #define MAX_SB_PER_PATH_K2 (368) 433 #define MAX_SB_PER_PATH_BB (288) 434 #define MAX_SB_PER_PATH_E5 (512) 435 #define MAX_TOT_SB_PER_PATH MAX_SB_PER_PATH_E5 436 437 #define MAX_SB_PER_PF_MIMD 129 438 #define MAX_SB_PER_PF_SIMD 64 439 #define MAX_SB_PER_VF 64 440 441 /* Memory addresses on the BAR for the IGU Sub Block */ 442 #define IGU_MEM_BASE 0x0000 443 444 #define IGU_MEM_MSIX_BASE 0x0000 445 #define IGU_MEM_MSIX_UPPER 0x0101 446 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff 447 448 #define IGU_MEM_PBA_MSIX_BASE 0x0200 449 #define IGU_MEM_PBA_MSIX_UPPER 0x0202 450 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff 451 452 #define IGU_CMD_INT_ACK_BASE 0x0400 453 #define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + MAX_TOT_SB_PER_PATH - 1) 454 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff 455 456 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0 457 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1 458 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2 459 460 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3 461 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4 462 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5 463 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6 464 465 #define IGU_CMD_PROD_UPD_BASE 0x0600 466 #define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE + MAX_TOT_SB_PER_PATH - 1) 467 #define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff 468 469 /*****************/ 470 /* PXP CONSTANTS */ 471 /*****************/ 472 473 /* Bars for Blocks */ 474 #define PXP_BAR_GRC 0 475 #define PXP_BAR_TSDM 0 476 #define PXP_BAR_USDM 0 477 #define PXP_BAR_XSDM 0 478 #define PXP_BAR_MSDM 0 479 #define PXP_BAR_YSDM 0 480 #define PXP_BAR_PSDM 0 481 #define PXP_BAR_IGU 0 482 #define PXP_BAR_DQ 1 483 484 /* PTT and GTT */ 485 #define PXP_PER_PF_ENTRY_SIZE 8 486 #define PXP_NUM_GLOBAL_WINDOWS 243 487 #define PXP_GLOBAL_ENTRY_SIZE 4 488 #define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4 489 #define PXP_PF_WINDOW_ADMIN_START 0 490 #define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000 491 #define PXP_PF_WINDOW_ADMIN_END (PXP_PF_WINDOW_ADMIN_START + PXP_PF_WINDOW_ADMIN_LENGTH - 1) 492 #define PXP_PF_WINDOW_ADMIN_PER_PF_START 0 493 #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH (PXP_NUM_PF_WINDOWS * PXP_PER_PF_ENTRY_SIZE) 494 #define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1) 495 #define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200 496 #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH (PXP_NUM_GLOBAL_WINDOWS * PXP_GLOBAL_ENTRY_SIZE) 497 #define PXP_PF_WINDOW_ADMIN_GLOBAL_END (PXP_PF_WINDOW_ADMIN_GLOBAL_START + PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1) 498 #define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0 499 #define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4 500 #define PXP_PF_ME_OPAQUE_ADDR 0x1f8 501 #define PXP_PF_ME_CONCRETE_ADDR 0x1fc 502 503 #define PXP_NUM_PF_WINDOWS 12 504 505 #define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000 506 #define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS 507 #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000 508 #define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) 509 #define PXP_EXTERNAL_BAR_PF_WINDOW_END (PXP_EXTERNAL_BAR_PF_WINDOW_START + PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1) 510 511 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START (PXP_EXTERNAL_BAR_PF_WINDOW_END + 1) 512 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM PXP_NUM_GLOBAL_WINDOWS 513 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000 514 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE) 515 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1) 516 517 /* PF BAR */ 518 #define PXP_BAR0_START_GRC 0x0000 519 #define PXP_BAR0_GRC_LENGTH 0x1C00000 520 #define PXP_BAR0_END_GRC (PXP_BAR0_START_GRC + PXP_BAR0_GRC_LENGTH - 1) 521 522 #define PXP_BAR0_START_IGU 0x1C00000 523 #define PXP_BAR0_IGU_LENGTH 0x10000 524 #define PXP_BAR0_END_IGU (PXP_BAR0_START_IGU + PXP_BAR0_IGU_LENGTH - 1) 525 526 #define PXP_BAR0_START_TSDM 0x1C80000 527 #define PXP_BAR0_SDM_LENGTH 0x40000 528 #define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000 529 #define PXP_BAR0_END_TSDM (PXP_BAR0_START_TSDM + PXP_BAR0_SDM_LENGTH - 1) 530 531 #define PXP_BAR0_START_MSDM 0x1D00000 532 #define PXP_BAR0_END_MSDM (PXP_BAR0_START_MSDM + PXP_BAR0_SDM_LENGTH - 1) 533 534 #define PXP_BAR0_START_USDM 0x1D80000 535 #define PXP_BAR0_END_USDM (PXP_BAR0_START_USDM + PXP_BAR0_SDM_LENGTH - 1) 536 537 #define PXP_BAR0_START_XSDM 0x1E00000 538 #define PXP_BAR0_END_XSDM (PXP_BAR0_START_XSDM + PXP_BAR0_SDM_LENGTH - 1) 539 540 #define PXP_BAR0_START_YSDM 0x1E80000 541 #define PXP_BAR0_END_YSDM (PXP_BAR0_START_YSDM + PXP_BAR0_SDM_LENGTH - 1) 542 543 #define PXP_BAR0_START_PSDM 0x1F00000 544 #define PXP_BAR0_END_PSDM (PXP_BAR0_START_PSDM + PXP_BAR0_SDM_LENGTH - 1) 545 546 #define PXP_BAR0_FIRST_INVALID_ADDRESS (PXP_BAR0_END_PSDM + 1) 547 548 /* VF BAR */ 549 #define PXP_VF_BAR0 0 550 551 #define PXP_VF_BAR0_START_GRC 0x3E00 552 #define PXP_VF_BAR0_GRC_LENGTH 0x200 553 #define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + PXP_VF_BAR0_GRC_LENGTH - 1) 554 555 #define PXP_VF_BAR0_START_IGU 0 556 #define PXP_VF_BAR0_IGU_LENGTH 0x3000 557 #define PXP_VF_BAR0_END_IGU (PXP_VF_BAR0_START_IGU + PXP_VF_BAR0_IGU_LENGTH - 1) 558 559 #define PXP_VF_BAR0_START_DQ 0x3000 560 #define PXP_VF_BAR0_DQ_LENGTH 0x200 561 #define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0 562 #define PXP_VF_BAR0_ME_OPAQUE_ADDRESS (PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_OPAQUE_OFFSET) 563 #define PXP_VF_BAR0_ME_CONCRETE_ADDRESS (PXP_VF_BAR0_ME_OPAQUE_ADDRESS + 4) 564 #define PXP_VF_BAR0_END_DQ (PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_LENGTH - 1) 565 566 #define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200 567 #define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200 568 #define PXP_VF_BAR0_END_TSDM_ZONE_B (PXP_VF_BAR0_START_TSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 569 570 #define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400 571 #define PXP_VF_BAR0_END_MSDM_ZONE_B (PXP_VF_BAR0_START_MSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 572 573 #define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600 574 #define PXP_VF_BAR0_END_USDM_ZONE_B (PXP_VF_BAR0_START_USDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 575 576 #define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800 577 #define PXP_VF_BAR0_END_XSDM_ZONE_B (PXP_VF_BAR0_START_XSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 578 579 #define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00 580 #define PXP_VF_BAR0_END_YSDM_ZONE_B (PXP_VF_BAR0_START_YSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 581 582 #define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00 583 #define PXP_VF_BAR0_END_PSDM_ZONE_B (PXP_VF_BAR0_START_PSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 584 585 #define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000 586 #define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000 587 588 #define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32 589 590 #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12 591 #define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024 592 593 // ILT Records 594 #define PXP_NUM_ILT_RECORDS_BB 7600 595 #define PXP_NUM_ILT_RECORDS_K2 11000 596 #define MAX_NUM_ILT_RECORDS OSAL_MAX_T(u16, PXP_NUM_ILT_RECORDS_BB,PXP_NUM_ILT_RECORDS_K2) 597 598 599 // Host Interface 600 #define PXP_QUEUES_ZONE_MAX_NUM 320 601 602 603 604 605 /*****************/ 606 /* PRM CONSTANTS */ 607 /*****************/ 608 #define PRM_DMA_PAD_BYTES_NUM 2 609 /*****************/ 610 /* SDMs CONSTANTS */ 611 /*****************/ 612 613 614 #define SDM_OP_GEN_TRIG_NONE 0 615 #define SDM_OP_GEN_TRIG_WAKE_THREAD 1 616 #define SDM_OP_GEN_TRIG_AGG_INT 2 617 #define SDM_OP_GEN_TRIG_LOADER 4 618 #define SDM_OP_GEN_TRIG_INDICATE_ERROR 6 619 #define SDM_OP_GEN_TRIG_INC_ORDER_CNT 9 620 621 ///////////////////////////////////////////////////////////// 622 // Completion types 623 ///////////////////////////////////////////////////////////// 624 625 #define SDM_COMP_TYPE_NONE 0 626 #define SDM_COMP_TYPE_WAKE_THREAD 1 627 #define SDM_COMP_TYPE_AGG_INT 2 628 #define SDM_COMP_TYPE_CM 3 // Send direct message to local CM and/or remote CMs. Destinations are defined by vector in CompParams. 629 #define SDM_COMP_TYPE_LOADER 4 630 #define SDM_COMP_TYPE_PXP 5 // Send direct message to PXP (like "internal write" command) to write to remote Storm RAM via remote SDM 631 #define SDM_COMP_TYPE_INDICATE_ERROR 6 // Indicate error per thread 632 #define SDM_COMP_TYPE_RELEASE_THREAD 7 // Obsolete in E5 633 #define SDM_COMP_TYPE_RAM 8 // Write to local RAM as a completion 634 #define SDM_COMP_TYPE_INC_ORDER_CNT 9 // Applicable only for E4 635 636 /******************/ 637 /* PBF CONSTANTS */ 638 /******************/ 639 640 /* Number of PBF command queue lines. Each line is 32B. */ 641 #define PBF_MAX_CMD_LINES_E4 3328 642 #define PBF_MAX_CMD_LINES_E5 5280 643 644 /* Number of BTB blocks. Each block is 256B. */ 645 #define BTB_MAX_BLOCKS 1440 646 647 /*****************/ 648 /* PRS CONSTANTS */ 649 /*****************/ 650 651 #define PRS_GFT_CAM_LINES_NO_MATCH 31 652 653 /* 654 * Async data KCQ CQE 655 */ 656 struct async_data 657 { 658 __le32 cid /* Context ID of the connection */; 659 __le16 itid /* Task Id of the task (for error that happened on a a task) */; 660 u8 error_code /* error code - relevant only if the opcode indicates its an error */; 661 u8 fw_debug_param /* internal fw debug parameter */; 662 }; 663 664 665 /* 666 * Interrupt coalescing TimeSet 667 */ 668 struct coalescing_timeset 669 { 670 u8 value; 671 #define COALESCING_TIMESET_TIMESET_MASK 0x7F /* Interrupt coalescing TimeSet (timeout_ticks = TimeSet shl (TimerRes+1)) */ 672 #define COALESCING_TIMESET_TIMESET_SHIFT 0 673 #define COALESCING_TIMESET_VALID_MASK 0x1 /* Only if this flag is set, timeset will take effect */ 674 #define COALESCING_TIMESET_VALID_SHIFT 7 675 }; 676 677 678 struct common_queue_zone 679 { 680 __le16 ring_drv_data_consumer; 681 __le16 reserved; 682 }; 683 684 685 /* 686 * ETH Rx producers data 687 */ 688 struct eth_rx_prod_data 689 { 690 __le16 bd_prod /* BD producer. */; 691 __le16 cqe_prod /* CQE producer. */; 692 }; 693 694 695 struct regpair 696 { 697 __le32 lo /* low word for reg-pair */; 698 __le32 hi /* high word for reg-pair */; 699 }; 700 701 /* 702 * Event Ring VF-PF Channel data 703 */ 704 struct vf_pf_channel_eqe_data 705 { 706 struct regpair msg_addr /* VF-PF message address */; 707 }; 708 709 struct iscsi_eqe_data 710 { 711 __le32 cid /* Context ID of the connection */; 712 __le16 conn_id /* Task Id of the task (for error that happened on a a task) */; 713 u8 error_code /* error code - relevant only if the opcode indicates its an error */; 714 u8 error_pdu_opcode_reserved; 715 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F /* The processed PDUs opcode on which happened the error - updated for specific error codes, by defualt=0xFF */ 716 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT 0 717 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK 0x1 /* Indication for driver is the error_pdu_opcode field has valid value */ 718 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT 6 719 #define ISCSI_EQE_DATA_RESERVED0_MASK 0x1 720 #define ISCSI_EQE_DATA_RESERVED0_SHIFT 7 721 }; 722 723 /* 724 * RoCE Destroy Event Data 725 */ 726 struct rdma_eqe_destroy_qp 727 { 728 __le32 cid /* Dedicated field RoCE destroy QP event */; 729 u8 reserved[4]; 730 }; 731 732 /* 733 * RDMA Event Data Union 734 */ 735 union rdma_eqe_data 736 { 737 struct regpair async_handle /* Host handle for the Async Completions */; 738 struct rdma_eqe_destroy_qp rdma_destroy_qp_data /* RoCE Destroy Event Data */; 739 }; 740 741 /* 742 * Event Ring malicious VF data 743 */ 744 struct malicious_vf_eqe_data 745 { 746 u8 vf_id /* Malicious VF ID */; 747 u8 err_id /* Malicious VF error */; 748 __le16 reserved[3]; 749 }; 750 751 /* 752 * Event Ring initial cleanup data 753 */ 754 struct initial_cleanup_eqe_data 755 { 756 u8 vf_id /* VF ID */; 757 u8 reserved[7]; 758 }; 759 760 /* 761 * Event Data Union 762 */ 763 union event_ring_data 764 { 765 u8 bytes[8] /* Byte Array */; 766 struct vf_pf_channel_eqe_data vf_pf_channel /* VF-PF Channel data */; 767 struct iscsi_eqe_data iscsi_info /* Dedicated fields to iscsi data */; 768 union rdma_eqe_data rdma_data /* Dedicated field for RDMA data */; 769 struct malicious_vf_eqe_data malicious_vf /* Malicious VF data */; 770 struct initial_cleanup_eqe_data vf_init_cleanup /* VF Initial Cleanup data */; 771 }; 772 773 774 /* 775 * Event Ring Entry 776 */ 777 struct event_ring_entry 778 { 779 u8 protocol_id /* Event Protocol ID */; 780 u8 opcode /* Event Opcode */; 781 __le16 reserved0 /* Reserved */; 782 __le16 echo /* Echo value from ramrod data on the host */; 783 u8 fw_return_code /* FW return code for SP ramrods */; 784 u8 flags; 785 #define EVENT_RING_ENTRY_ASYNC_MASK 0x1 /* 0: synchronous EQE - a completion of SP message. 1: asynchronous EQE */ 786 #define EVENT_RING_ENTRY_ASYNC_SHIFT 0 787 #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F 788 #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1 789 union event_ring_data data; 790 }; 791 792 793 794 795 796 /* 797 * Multi function mode 798 */ 799 enum mf_mode 800 { 801 ERROR_MODE /* Unsupported mode */, 802 MF_OVLAN /* Multi function based on outer VLAN */, 803 MF_NPAR /* Multi function based on MAC address (NIC partitioning) */, 804 MAX_MF_MODE 805 }; 806 807 808 /* 809 * Per-protocol connection types 810 */ 811 enum protocol_type 812 { 813 PROTOCOLID_ISCSI /* iSCSI */, 814 PROTOCOLID_FCOE /* FCoE */, 815 PROTOCOLID_ROCE /* RoCE */, 816 PROTOCOLID_CORE /* Core (light L2, slow path core) */, 817 PROTOCOLID_ETH /* Ethernet */, 818 PROTOCOLID_IWARP /* iWARP */, 819 PROTOCOLID_TOE /* TOE */, 820 PROTOCOLID_PREROCE /* Pre (tapeout) RoCE */, 821 PROTOCOLID_COMMON /* ProtocolCommon */, 822 PROTOCOLID_TCP /* TCP */, 823 MAX_PROTOCOL_TYPE 824 }; 825 826 827 828 829 /* 830 * Ustorm Queue Zone 831 */ 832 struct ustorm_eth_queue_zone 833 { 834 struct coalescing_timeset int_coalescing_timeset /* Rx interrupt coalescing TimeSet */; 835 u8 reserved[3]; 836 }; 837 838 839 struct ustorm_queue_zone 840 { 841 struct ustorm_eth_queue_zone eth; 842 struct common_queue_zone common; 843 }; 844 845 846 847 /* 848 * status block structure 849 */ 850 struct cau_pi_entry 851 { 852 __le32 prod; 853 #define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF /* A per protocol indexPROD value. */ 854 #define CAU_PI_ENTRY_PROD_VAL_SHIFT 0 855 #define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F /* This value determines the TimeSet that the PI is associated with */ 856 #define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16 857 #define CAU_PI_ENTRY_FSM_SEL_MASK 0x1 /* Select the FSM within the SB */ 858 #define CAU_PI_ENTRY_FSM_SEL_SHIFT 23 859 #define CAU_PI_ENTRY_RESERVED_MASK 0xFF /* Select the FSM within the SB */ 860 #define CAU_PI_ENTRY_RESERVED_SHIFT 24 861 }; 862 863 864 /* 865 * status block structure 866 */ 867 struct cau_sb_entry 868 { 869 __le32 data; 870 #define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF /* The SB PROD index which is sent to the IGU. */ 871 #define CAU_SB_ENTRY_SB_PROD_SHIFT 0 872 #define CAU_SB_ENTRY_STATE0_MASK 0xF /* RX state */ 873 #define CAU_SB_ENTRY_STATE0_SHIFT 24 874 #define CAU_SB_ENTRY_STATE1_MASK 0xF /* TX state */ 875 #define CAU_SB_ENTRY_STATE1_SHIFT 28 876 __le32 params; 877 #define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F /* Indicates the RX TimeSet that this SB is associated with. */ 878 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0 879 #define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F /* Indicates the TX TimeSet that this SB is associated with. */ 880 #define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7 881 #define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3 /* This value will determine the RX FSM timer resolution in ticks */ 882 #define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14 883 #define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3 /* This value will determine the TX FSM timer resolution in ticks */ 884 #define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16 885 #define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF 886 #define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18 887 #define CAU_SB_ENTRY_VF_VALID_MASK 0x1 888 #define CAU_SB_ENTRY_VF_VALID_SHIFT 26 889 #define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF 890 #define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27 891 #define CAU_SB_ENTRY_TPH_MASK 0x1 /* If set then indicates that the TPH STAG is equal to the SB number. Otherwise the STAG will be equal to all ones. */ 892 #define CAU_SB_ENTRY_TPH_SHIFT 31 893 }; 894 895 896 /* 897 * core doorbell data 898 */ 899 struct core_db_data 900 { 901 u8 params; 902 #define CORE_DB_DATA_DEST_MASK 0x3 /* destination of doorbell (use enum db_dest) */ 903 #define CORE_DB_DATA_DEST_SHIFT 0 904 #define CORE_DB_DATA_AGG_CMD_MASK 0x3 /* aggregative command to CM (use enum db_agg_cmd_sel) */ 905 #define CORE_DB_DATA_AGG_CMD_SHIFT 2 906 #define CORE_DB_DATA_BYPASS_EN_MASK 0x1 /* enable QM bypass */ 907 #define CORE_DB_DATA_BYPASS_EN_SHIFT 4 908 #define CORE_DB_DATA_RESERVED_MASK 0x1 909 #define CORE_DB_DATA_RESERVED_SHIFT 5 910 #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3 /* aggregative value selection */ 911 #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6 912 u8 agg_flags /* bit for every DQ counter flags in CM context that DQ can increment */; 913 __le16 spq_prod; 914 }; 915 916 917 /* 918 * Enum of doorbell aggregative command selection 919 */ 920 enum db_agg_cmd_sel 921 { 922 DB_AGG_CMD_NOP /* No operation */, 923 DB_AGG_CMD_SET /* Set the value */, 924 DB_AGG_CMD_ADD /* Add the value */, 925 DB_AGG_CMD_MAX /* Set max of current and new value */, 926 MAX_DB_AGG_CMD_SEL 927 }; 928 929 930 /* 931 * Enum of doorbell destination 932 */ 933 enum db_dest 934 { 935 DB_DEST_XCM /* TX doorbell to XCM */, 936 DB_DEST_UCM /* RX doorbell to UCM */, 937 DB_DEST_TCM /* RX doorbell to TCM */, 938 DB_NUM_DESTINATIONS, 939 MAX_DB_DEST 940 }; 941 942 943 /* 944 * Enum of doorbell DPM types 945 */ 946 enum db_dpm_type 947 { 948 DPM_LEGACY /* Legacy DPM- to Xstorm RAM */, 949 DPM_RDMA /* RDMA DPM (only RoCE in E4) - to NIG */, 950 DPM_L2_INLINE /* L2 DPM inline- to PBF, with packet data on doorbell */, 951 DPM_L2_BD /* L2 DPM with BD- to PBF, with TX BD data on doorbell */, 952 MAX_DB_DPM_TYPE 953 }; 954 955 956 /* 957 * Structure for doorbell data, in L2 DPM mode, for the first doorbell in a DPM burst 958 */ 959 struct db_l2_dpm_data 960 { 961 __le16 icid /* internal CID */; 962 __le16 bd_prod /* bd producer value to update */; 963 __le32 params; 964 #define DB_L2_DPM_DATA_SIZE_MASK 0x3F /* Size in QWORD-s of the DPM burst */ 965 #define DB_L2_DPM_DATA_SIZE_SHIFT 0 966 #define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3 /* Type of DPM transaction (DPM_L2_INLINE or DPM_L2_BD) (use enum db_dpm_type) */ 967 #define DB_L2_DPM_DATA_DPM_TYPE_SHIFT 6 968 #define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF /* number of BD-s */ 969 #define DB_L2_DPM_DATA_NUM_BDS_SHIFT 8 970 #define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF /* size of the packet to be transmitted in bytes */ 971 #define DB_L2_DPM_DATA_PKT_SIZE_SHIFT 16 972 #define DB_L2_DPM_DATA_RESERVED0_MASK 0x1 973 #define DB_L2_DPM_DATA_RESERVED0_SHIFT 27 974 #define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7 /* In DPM_L2_BD mode: the number of SGE-s */ 975 #define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28 976 #define DB_L2_DPM_DATA_GFS_SRC_EN_MASK 0x1 /* Flag indicating whether to enable GFS search */ 977 #define DB_L2_DPM_DATA_GFS_SRC_EN_SHIFT 31 978 }; 979 980 981 /* 982 * Structure for SGE in a DPM doorbell of type DPM_L2_BD 983 */ 984 struct db_l2_dpm_sge 985 { 986 struct regpair addr /* Single continuous buffer */; 987 __le16 nbytes /* Number of bytes in this BD. */; 988 __le16 bitfields; 989 #define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF /* The TPH STAG index value */ 990 #define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0 991 #define DB_L2_DPM_SGE_RESERVED0_MASK 0x3 992 #define DB_L2_DPM_SGE_RESERVED0_SHIFT 9 993 #define DB_L2_DPM_SGE_ST_VALID_MASK 0x1 /* Indicate if ST hint is requested or not */ 994 #define DB_L2_DPM_SGE_ST_VALID_SHIFT 11 995 #define DB_L2_DPM_SGE_RESERVED1_MASK 0xF 996 #define DB_L2_DPM_SGE_RESERVED1_SHIFT 12 997 __le32 reserved2; 998 }; 999 1000 1001 /* 1002 * Structure for doorbell address, in legacy mode 1003 */ 1004 struct db_legacy_addr 1005 { 1006 __le32 addr; 1007 #define DB_LEGACY_ADDR_RESERVED0_MASK 0x3 1008 #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0 1009 #define DB_LEGACY_ADDR_DEMS_MASK 0x7 /* doorbell extraction mode specifier- 0 if not used */ 1010 #define DB_LEGACY_ADDR_DEMS_SHIFT 2 1011 #define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF /* internal CID */ 1012 #define DB_LEGACY_ADDR_ICID_SHIFT 5 1013 }; 1014 1015 1016 /* 1017 * Structure for doorbell address, in PWM mode 1018 */ 1019 struct db_pwm_addr 1020 { 1021 __le32 addr; 1022 #define DB_PWM_ADDR_RESERVED0_MASK 0x7 1023 #define DB_PWM_ADDR_RESERVED0_SHIFT 0 1024 #define DB_PWM_ADDR_OFFSET_MASK 0x7F /* Offset in PWM address space */ 1025 #define DB_PWM_ADDR_OFFSET_SHIFT 3 1026 #define DB_PWM_ADDR_WID_MASK 0x3 /* Window ID */ 1027 #define DB_PWM_ADDR_WID_SHIFT 10 1028 #define DB_PWM_ADDR_DPI_MASK 0xFFFF /* Doorbell page ID */ 1029 #define DB_PWM_ADDR_DPI_SHIFT 12 1030 #define DB_PWM_ADDR_RESERVED1_MASK 0xF 1031 #define DB_PWM_ADDR_RESERVED1_SHIFT 28 1032 }; 1033 1034 1035 /* 1036 * Parameters to RDMA firmware, passed in EDPM doorbell 1037 */ 1038 struct db_rdma_dpm_params 1039 { 1040 __le32 params; 1041 #define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F /* Size in QWORD-s of the DPM burst */ 1042 #define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0 1043 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3 /* Type of DPM transacation (DPM_RDMA) (use enum db_dpm_type) */ 1044 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT 6 1045 #define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF /* opcode for RDMA operation */ 1046 #define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT 8 1047 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF /* the size of the WQE payload in bytes */ 1048 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16 1049 #define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1 1050 #define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27 1051 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1 /* RoCE completion flag */ 1052 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 28 1053 #define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1 /* RoCE S flag */ 1054 #define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29 1055 #define DB_RDMA_DPM_PARAMS_RESERVED1_MASK 0x1 1056 #define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT 30 1057 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1 /* Connection type is iWARP */ 1058 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31 1059 }; 1060 1061 /* 1062 * Structure for doorbell data, in RDMA DPM mode, for the first doorbell in a DPM burst 1063 */ 1064 struct db_rdma_dpm_data 1065 { 1066 __le16 icid /* internal CID */; 1067 __le16 prod_val /* aggregated value to update */; 1068 struct db_rdma_dpm_params params /* parametes passed to RDMA firmware */; 1069 }; 1070 1071 1072 1073 /* 1074 * Igu interrupt command 1075 */ 1076 enum igu_int_cmd 1077 { 1078 IGU_INT_ENABLE=0, 1079 IGU_INT_DISABLE=1, 1080 IGU_INT_NOP=2, 1081 IGU_INT_NOP2=3, 1082 MAX_IGU_INT_CMD 1083 }; 1084 1085 1086 /* 1087 * IGU producer or consumer update command 1088 */ 1089 struct igu_prod_cons_update 1090 { 1091 __le32 sb_id_and_flags; 1092 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF 1093 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0 1094 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1 1095 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24 1096 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3 /* interrupt enable/disable/nop (use enum igu_int_cmd) */ 1097 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25 1098 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1 /* (use enum igu_seg_access) */ 1099 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27 1100 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1 1101 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28 1102 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3 1103 #define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29 1104 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1 /* must always be set cleared (use enum command_type_bit) */ 1105 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31 1106 __le32 reserved1; 1107 }; 1108 1109 1110 /* 1111 * Igu segments access for default status block only 1112 */ 1113 enum igu_seg_access 1114 { 1115 IGU_SEG_ACCESS_REG=0, 1116 IGU_SEG_ACCESS_ATTN=1, 1117 MAX_IGU_SEG_ACCESS 1118 }; 1119 1120 1121 /* 1122 * Enumeration for L3 type field of parsing_and_err_flags. L3Type: 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled according to the last-ethertype) 1123 */ 1124 enum l3_type 1125 { 1126 e_l3_type_unknown, 1127 e_l3_type_ipv4, 1128 e_l3_type_ipv6, 1129 MAX_L3_TYPE 1130 }; 1131 1132 1133 /* 1134 * Enumeration for l4Protocol field of parsing_and_err_flags. L4-protocol 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and its not the first fragment, the protocol-type should be set to none. 1135 */ 1136 enum l4_protocol 1137 { 1138 e_l4_protocol_none, 1139 e_l4_protocol_tcp, 1140 e_l4_protocol_udp, 1141 MAX_L4_PROTOCOL 1142 }; 1143 1144 1145 /* 1146 * Parsing and error flags field. 1147 */ 1148 struct parsing_and_err_flags 1149 { 1150 __le16 flags; 1151 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3 /* L3Type: 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled according to the last-ethertype) (use enum l3_type) */ 1152 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0 1153 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3 /* L4-protocol 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and its not the first fragment, the protocol-type should be set to none. (use enum l4_protocol) */ 1154 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2 1155 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1 /* Set if the packet is IPv4/IPv6 fragment. */ 1156 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4 1157 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1 /* corresponds to the same 8021q tag that is selected for 8021q-tag fiel. This flag should be set if the tag appears in the packet, regardless of its value. */ 1158 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5 1159 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1 /* Set if L4 checksum was calculated. taken from the EOP descriptor. */ 1160 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6 1161 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1 /* Set for PTP packet. */ 1162 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7 1163 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1 /* Set if PTP timestamp recorded. */ 1164 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8 1165 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1 /* Set if either version-mismatch or hdr-len-error or ipv4-cksm is set or ipv6 ver mismatch */ 1166 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9 1167 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1 /* Set if L4 checksum validation failed. Valid only if L4 checksum was calculated. */ 1168 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10 1169 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1 /* Set if GRE/VXLAN/GENEVE tunnel detected. */ 1170 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11 1171 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1 /* This flag should be set if the tag appears in the packet tunnel header, regardless of its value.. */ 1172 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12 1173 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1 /* Set if either tunnel-ipv4-version-mismatch or tunnel-ipv4-hdr-len-error or tunnel-ipv4-cksm is set or tunneling ipv6 ver mismatch */ 1174 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13 1175 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1 /* taken from the EOP descriptor. */ 1176 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14 1177 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1 /* Set if tunnel L4 checksum validation failed. Valid only if tunnel L4 checksum was calculated. */ 1178 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15 1179 }; 1180 1181 1182 /* 1183 * Parsing error flags bitmap. 1184 */ 1185 struct parsing_err_flags 1186 { 1187 __le16 flags; 1188 #define PARSING_ERR_FLAGS_MAC_ERROR_MASK 0x1 /* MAC error indication */ 1189 #define PARSING_ERR_FLAGS_MAC_ERROR_SHIFT 0 1190 #define PARSING_ERR_FLAGS_TRUNC_ERROR_MASK 0x1 /* truncation error indication */ 1191 #define PARSING_ERR_FLAGS_TRUNC_ERROR_SHIFT 1 1192 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_MASK 0x1 /* packet too small indication */ 1193 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_SHIFT 2 1194 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_MASK 0x1 /* Header Missing Tag */ 1195 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_SHIFT 3 1196 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_MASK 0x1 /* from frame cracker output */ 1197 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_SHIFT 4 1198 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_MASK 0x1 /* from frame cracker output */ 1199 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_SHIFT 5 1200 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_MASK 0x1 /* set this error if: 1. total-len is smaller than hdr-len 2. total-ip-len indicates number that is bigger than real packet length 3. tunneling: total-ip-length of the outer header points to offset that is smaller than the one pointed to by the total-ip-len of the inner hdr. */ 1201 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_SHIFT 6 1202 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_MASK 0x1 /* from frame cracker output */ 1203 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_SHIFT 7 1204 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_MASK 0x1 /* from frame cracker output. for either TCP or UDP */ 1205 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_SHIFT 8 1206 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_MASK 0x1 /* from frame cracker output */ 1207 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_SHIFT 9 1208 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_MASK 0x1 /* cksm calculated and value isnt 0xffff or L4-cksm-wasnt-calculated for any reason, like: udp/ipv4 checksum is 0 etc. */ 1209 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_SHIFT 10 1210 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_MASK 0x1 /* from frame cracker output */ 1211 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_SHIFT 11 1212 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_MASK 0x1 /* from frame cracker output */ 1213 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_SHIFT 12 1214 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_MASK 0x1 /* set if geneve option size was over 32 byte */ 1215 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_SHIFT 13 1216 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_MASK 0x1 /* from frame cracker output */ 1217 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_SHIFT 14 1218 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_MASK 0x1 /* from frame cracker output */ 1219 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_SHIFT 15 1220 }; 1221 1222 1223 /* 1224 * Pb context 1225 */ 1226 struct pb_context 1227 { 1228 __le32 crc[4]; 1229 }; 1230 1231 1232 /* 1233 * Concrete Function ID. 1234 */ 1235 struct pxp_concrete_fid 1236 { 1237 __le16 fid; 1238 #define PXP_CONCRETE_FID_PFID_MASK 0xF /* Parent PFID */ 1239 #define PXP_CONCRETE_FID_PFID_SHIFT 0 1240 #define PXP_CONCRETE_FID_PORT_MASK 0x3 /* port number */ 1241 #define PXP_CONCRETE_FID_PORT_SHIFT 4 1242 #define PXP_CONCRETE_FID_PATH_MASK 0x1 /* path number */ 1243 #define PXP_CONCRETE_FID_PATH_SHIFT 6 1244 #define PXP_CONCRETE_FID_VFVALID_MASK 0x1 1245 #define PXP_CONCRETE_FID_VFVALID_SHIFT 7 1246 #define PXP_CONCRETE_FID_VFID_MASK 0xFF 1247 #define PXP_CONCRETE_FID_VFID_SHIFT 8 1248 }; 1249 1250 1251 /* 1252 * Concrete Function ID. 1253 */ 1254 struct pxp_pretend_concrete_fid 1255 { 1256 __le16 fid; 1257 #define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF /* Parent PFID */ 1258 #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0 1259 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7 /* port number. Only when part of ME register. */ 1260 #define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4 1261 #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1 1262 #define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7 1263 #define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF 1264 #define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8 1265 }; 1266 1267 /* 1268 * Function ID. 1269 */ 1270 union pxp_pretend_fid 1271 { 1272 struct pxp_pretend_concrete_fid concrete_fid; 1273 __le16 opaque_fid; 1274 }; 1275 1276 /* 1277 * Pxp Pretend Command Register. 1278 */ 1279 struct pxp_pretend_cmd 1280 { 1281 union pxp_pretend_fid fid; 1282 __le16 control; 1283 #define PXP_PRETEND_CMD_PATH_MASK 0x1 1284 #define PXP_PRETEND_CMD_PATH_SHIFT 0 1285 #define PXP_PRETEND_CMD_USE_PORT_MASK 0x1 1286 #define PXP_PRETEND_CMD_USE_PORT_SHIFT 1 1287 #define PXP_PRETEND_CMD_PORT_MASK 0x3 1288 #define PXP_PRETEND_CMD_PORT_SHIFT 2 1289 #define PXP_PRETEND_CMD_RESERVED0_MASK 0xF 1290 #define PXP_PRETEND_CMD_RESERVED0_SHIFT 4 1291 #define PXP_PRETEND_CMD_RESERVED1_MASK 0xF 1292 #define PXP_PRETEND_CMD_RESERVED1_SHIFT 8 1293 #define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1 /* is pretend mode? */ 1294 #define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12 1295 #define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1 /* is pretend mode? */ 1296 #define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13 1297 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1 /* is pretend mode? */ 1298 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14 1299 #define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1 /* is fid concrete? */ 1300 #define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15 1301 }; 1302 1303 1304 1305 1306 /* 1307 * PTT Record in PXP Admin Window. 1308 */ 1309 struct pxp_ptt_entry 1310 { 1311 __le32 offset; 1312 #define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF 1313 #define PXP_PTT_ENTRY_OFFSET_SHIFT 0 1314 #define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF 1315 #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23 1316 struct pxp_pretend_cmd pretend; 1317 }; 1318 1319 1320 /* 1321 * VF Zone A Permission Register. 1322 */ 1323 struct pxp_vf_zone_a_permission 1324 { 1325 __le32 control; 1326 #define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF 1327 #define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0 1328 #define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1 1329 #define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8 1330 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F 1331 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9 1332 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF 1333 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16 1334 }; 1335 1336 1337 /* 1338 * Rdif context 1339 */ 1340 struct rdif_task_context 1341 { 1342 __le32 initialRefTag; 1343 __le16 appTagValue; 1344 __le16 appTagMask; 1345 u8 flags0; 1346 #define RDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1 1347 #define RDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0 1348 #define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1 1349 #define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1 1350 #define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1 /* 0 = IP checksum, 1 = CRC */ 1351 #define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2 1352 #define RDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1 1353 #define RDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3 1354 #define RDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3 /* 1/2/3 - Protection Type */ 1355 #define RDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4 1356 #define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 /* 0=0x0000, 1=0xffff */ 1357 #define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1358 #define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1 /* Keep reference tag constant */ 1359 #define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 7 1360 u8 partialDifData[7]; 1361 __le16 partialCrcValue; 1362 __le16 partialChecksumValue; 1363 __le32 offsetInIO; 1364 __le16 flags1; 1365 #define RDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1 1366 #define RDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0 1367 #define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1 1368 #define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1 1369 #define RDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1 1370 #define RDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2 1371 #define RDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1 1372 #define RDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3 1373 #define RDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1 1374 #define RDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4 1375 #define RDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1 1376 #define RDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5 1377 #define RDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */ 1378 #define RDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6 1379 #define RDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3 /* 0=None, 1=DIF, 2=DIX */ 1380 #define RDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9 1381 #define RDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1 /* DIF tag right at the beginning of DIF interval */ 1382 #define RDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11 1383 #define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1 1384 #define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12 1385 #define RDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1 /* 0=None, 1=DIF */ 1386 #define RDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13 1387 #define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1 /* Forward application tag with mask */ 1388 #define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 14 1389 #define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1 /* Forward reference tag with mask */ 1390 #define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 15 1391 __le16 state; 1392 #define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_MASK 0xF 1393 #define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_SHIFT 0 1394 #define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_MASK 0xF 1395 #define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_SHIFT 4 1396 #define RDIF_TASK_CONTEXT_ERRORINIO_MASK 0x1 1397 #define RDIF_TASK_CONTEXT_ERRORINIO_SHIFT 8 1398 #define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1 1399 #define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9 1400 #define RDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF /* mask for refernce tag handling */ 1401 #define RDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 10 1402 #define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3 1403 #define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14 1404 __le32 reserved2; 1405 }; 1406 1407 1408 1409 /* 1410 * RSS hash type 1411 */ 1412 enum rss_hash_type 1413 { 1414 RSS_HASH_TYPE_DEFAULT=0, 1415 RSS_HASH_TYPE_IPV4=1, 1416 RSS_HASH_TYPE_TCP_IPV4=2, 1417 RSS_HASH_TYPE_IPV6=3, 1418 RSS_HASH_TYPE_TCP_IPV6=4, 1419 RSS_HASH_TYPE_UDP_IPV4=5, 1420 RSS_HASH_TYPE_UDP_IPV6=6, 1421 MAX_RSS_HASH_TYPE 1422 }; 1423 1424 1425 /* 1426 * status block structure 1427 */ 1428 struct status_block_e4 1429 { 1430 __le16 pi_array[PIS_PER_SB_E4]; 1431 __le32 sb_num; 1432 #define STATUS_BLOCK_E4_SB_NUM_MASK 0x1FF 1433 #define STATUS_BLOCK_E4_SB_NUM_SHIFT 0 1434 #define STATUS_BLOCK_E4_ZERO_PAD_MASK 0x7F 1435 #define STATUS_BLOCK_E4_ZERO_PAD_SHIFT 9 1436 #define STATUS_BLOCK_E4_ZERO_PAD2_MASK 0xFFFF 1437 #define STATUS_BLOCK_E4_ZERO_PAD2_SHIFT 16 1438 __le32 prod_index; 1439 #define STATUS_BLOCK_E4_PROD_INDEX_MASK 0xFFFFFF 1440 #define STATUS_BLOCK_E4_PROD_INDEX_SHIFT 0 1441 #define STATUS_BLOCK_E4_ZERO_PAD3_MASK 0xFF 1442 #define STATUS_BLOCK_E4_ZERO_PAD3_SHIFT 24 1443 }; 1444 1445 1446 /* 1447 * status block structure 1448 */ 1449 struct status_block_e5 1450 { 1451 __le16 pi_array[PIS_PER_SB_E5]; 1452 __le32 sb_num; 1453 #define STATUS_BLOCK_E5_SB_NUM_MASK 0x1FF 1454 #define STATUS_BLOCK_E5_SB_NUM_SHIFT 0 1455 #define STATUS_BLOCK_E5_ZERO_PAD_MASK 0x7F 1456 #define STATUS_BLOCK_E5_ZERO_PAD_SHIFT 9 1457 #define STATUS_BLOCK_E5_ZERO_PAD2_MASK 0xFFFF 1458 #define STATUS_BLOCK_E5_ZERO_PAD2_SHIFT 16 1459 __le32 prod_index; 1460 #define STATUS_BLOCK_E5_PROD_INDEX_MASK 0xFFFFFF 1461 #define STATUS_BLOCK_E5_PROD_INDEX_SHIFT 0 1462 #define STATUS_BLOCK_E5_ZERO_PAD3_MASK 0xFF 1463 #define STATUS_BLOCK_E5_ZERO_PAD3_SHIFT 24 1464 }; 1465 1466 1467 /* 1468 * Tdif context 1469 */ 1470 struct tdif_task_context 1471 { 1472 __le32 initialRefTag; 1473 __le16 appTagValue; 1474 __le16 appTagMask; 1475 __le16 partialCrcValueB; 1476 __le16 partialChecksumValueB; 1477 __le16 stateB; 1478 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_MASK 0xF 1479 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_SHIFT 0 1480 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_MASK 0xF 1481 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_SHIFT 4 1482 #define TDIF_TASK_CONTEXT_ERRORINIOB_MASK 0x1 1483 #define TDIF_TASK_CONTEXT_ERRORINIOB_SHIFT 8 1484 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1 1485 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9 1486 #define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F 1487 #define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10 1488 u8 reserved1; 1489 u8 flags0; 1490 #define TDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1 1491 #define TDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0 1492 #define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1 1493 #define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1 1494 #define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1 /* 0 = IP checksum, 1 = CRC */ 1495 #define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2 1496 #define TDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1 1497 #define TDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3 1498 #define TDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3 /* 1/2/3 - Protection Type */ 1499 #define TDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4 1500 #define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 /* 0=0x0000, 1=0xffff */ 1501 #define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1502 #define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1 1503 #define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7 1504 __le32 flags1; 1505 #define TDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1 1506 #define TDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0 1507 #define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1 1508 #define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1 1509 #define TDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1 1510 #define TDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2 1511 #define TDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1 1512 #define TDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3 1513 #define TDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1 1514 #define TDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4 1515 #define TDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1 1516 #define TDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5 1517 #define TDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */ 1518 #define TDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6 1519 #define TDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3 /* 0=None, 1=DIF, 2=DIX */ 1520 #define TDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9 1521 #define TDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1 /* DIF tag right at the beginning of DIF interval */ 1522 #define TDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11 1523 #define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1 /* reserved */ 1524 #define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12 1525 #define TDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1 /* 0=None, 1=DIF */ 1526 #define TDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13 1527 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_MASK 0xF 1528 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_SHIFT 14 1529 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_MASK 0xF 1530 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_SHIFT 18 1531 #define TDIF_TASK_CONTEXT_ERRORINIOA_MASK 0x1 1532 #define TDIF_TASK_CONTEXT_ERRORINIOA_SHIFT 22 1533 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_MASK 0x1 1534 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_SHIFT 23 1535 #define TDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF /* mask for refernce tag handling */ 1536 #define TDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 24 1537 #define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1 /* Forward application tag with mask */ 1538 #define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 28 1539 #define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1 /* Forward reference tag with mask */ 1540 #define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 29 1541 #define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1 /* Keep reference tag constant */ 1542 #define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 30 1543 #define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1 1544 #define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31 1545 __le32 offsetInIOB; 1546 __le16 partialCrcValueA; 1547 __le16 partialChecksumValueA; 1548 __le32 offsetInIOA; 1549 u8 partialDifDataA[8]; 1550 u8 partialDifDataB[8]; 1551 }; 1552 1553 1554 /* 1555 * Timers context 1556 */ 1557 struct timers_context 1558 { 1559 __le32 logical_client_0; 1560 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0x7FFFFFF /* Expiration time of logical client 0 */ 1561 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0 1562 #define TIMERS_CONTEXT_RESERVED0_MASK 0x1 1563 #define TIMERS_CONTEXT_RESERVED0_SHIFT 27 1564 #define TIMERS_CONTEXT_VALIDLC0_MASK 0x1 /* Valid bit of logical client 0 */ 1565 #define TIMERS_CONTEXT_VALIDLC0_SHIFT 28 1566 #define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1 /* Active bit of logical client 0 */ 1567 #define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29 1568 #define TIMERS_CONTEXT_RESERVED1_MASK 0x3 1569 #define TIMERS_CONTEXT_RESERVED1_SHIFT 30 1570 __le32 logical_client_1; 1571 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0x7FFFFFF /* Expiration time of logical client 1 */ 1572 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0 1573 #define TIMERS_CONTEXT_RESERVED2_MASK 0x1 1574 #define TIMERS_CONTEXT_RESERVED2_SHIFT 27 1575 #define TIMERS_CONTEXT_VALIDLC1_MASK 0x1 /* Valid bit of logical client 1 */ 1576 #define TIMERS_CONTEXT_VALIDLC1_SHIFT 28 1577 #define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1 /* Active bit of logical client 1 */ 1578 #define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29 1579 #define TIMERS_CONTEXT_RESERVED3_MASK 0x3 1580 #define TIMERS_CONTEXT_RESERVED3_SHIFT 30 1581 __le32 logical_client_2; 1582 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0x7FFFFFF /* Expiration time of logical client 2 */ 1583 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0 1584 #define TIMERS_CONTEXT_RESERVED4_MASK 0x1 1585 #define TIMERS_CONTEXT_RESERVED4_SHIFT 27 1586 #define TIMERS_CONTEXT_VALIDLC2_MASK 0x1 /* Valid bit of logical client 2 */ 1587 #define TIMERS_CONTEXT_VALIDLC2_SHIFT 28 1588 #define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1 /* Active bit of logical client 2 */ 1589 #define TIMERS_CONTEXT_ACTIVELC2_SHIFT 29 1590 #define TIMERS_CONTEXT_RESERVED5_MASK 0x3 1591 #define TIMERS_CONTEXT_RESERVED5_SHIFT 30 1592 __le32 host_expiration_fields; 1593 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0x7FFFFFF /* Expiration time on host (closest one) */ 1594 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0 1595 #define TIMERS_CONTEXT_RESERVED6_MASK 0x1 1596 #define TIMERS_CONTEXT_RESERVED6_SHIFT 27 1597 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1 /* Valid bit of host expiration */ 1598 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT 28 1599 #define TIMERS_CONTEXT_RESERVED7_MASK 0x7 1600 #define TIMERS_CONTEXT_RESERVED7_SHIFT 29 1601 }; 1602 1603 1604 /* 1605 * Enum for next_protocol field of tunnel_parsing_flags 1606 */ 1607 enum tunnel_next_protocol 1608 { 1609 e_unknown=0, 1610 e_l2=1, 1611 e_ipv4=2, 1612 e_ipv6=3, 1613 MAX_TUNNEL_NEXT_PROTOCOL 1614 }; 1615 1616 #endif /* __COMMON_HSI__ */ 1617