1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __ECORE_HSI_COMMON__ 32 #define __ECORE_HSI_COMMON__ 33 /********************************/ 34 /* Add include to common target */ 35 /********************************/ 36 #include "common_hsi.h" 37 38 /* 39 * opcodes for the event ring 40 */ 41 enum common_event_opcode 42 { 43 COMMON_EVENT_PF_START, 44 COMMON_EVENT_PF_STOP, 45 COMMON_EVENT_VF_START, 46 COMMON_EVENT_VF_STOP, 47 COMMON_EVENT_VF_PF_CHANNEL, 48 COMMON_EVENT_VF_FLR, 49 COMMON_EVENT_PF_UPDATE, 50 COMMON_EVENT_MALICIOUS_VF, 51 COMMON_EVENT_RL_UPDATE, 52 COMMON_EVENT_EMPTY, 53 MAX_COMMON_EVENT_OPCODE 54 }; 55 56 /* 57 * Common Ramrod Command IDs 58 */ 59 enum common_ramrod_cmd_id 60 { 61 COMMON_RAMROD_UNUSED, 62 COMMON_RAMROD_PF_START /* PF Function Start Ramrod */, 63 COMMON_RAMROD_PF_STOP /* PF Function Stop Ramrod */, 64 COMMON_RAMROD_VF_START /* VF Function Start */, 65 COMMON_RAMROD_VF_STOP /* VF Function Stop Ramrod */, 66 COMMON_RAMROD_PF_UPDATE /* PF update Ramrod */, 67 COMMON_RAMROD_RL_UPDATE /* QCN/DCQCN RL update Ramrod */, 68 COMMON_RAMROD_EMPTY /* Empty Ramrod */, 69 MAX_COMMON_RAMROD_CMD_ID 70 }; 71 72 /* 73 * How ll2 should deal with packet upon errors 74 */ 75 enum core_error_handle 76 { 77 LL2_DROP_PACKET /* If error occurs drop packet */, 78 LL2_DO_NOTHING /* If error occurs do nothing */, 79 LL2_ASSERT /* If error occurs assert */, 80 MAX_CORE_ERROR_HANDLE 81 }; 82 83 /* 84 * opcodes for the event ring 85 */ 86 enum core_event_opcode 87 { 88 CORE_EVENT_TX_QUEUE_START, 89 CORE_EVENT_TX_QUEUE_STOP, 90 CORE_EVENT_RX_QUEUE_START, 91 CORE_EVENT_RX_QUEUE_STOP, 92 CORE_EVENT_RX_QUEUE_FLUSH, 93 CORE_EVENT_TX_QUEUE_UPDATE, 94 MAX_CORE_EVENT_OPCODE 95 }; 96 97 /* 98 * The L4 pseudo checksum mode for Core 99 */ 100 enum core_l4_pseudo_checksum_mode 101 { 102 CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH /* Pseudo Checksum on packet is calculated with the correct packet length. */, 103 CORE_L4_PSEUDO_CSUM_ZERO_LENGTH /* Pseudo Checksum on packet is calculated with zero length. */, 104 MAX_CORE_L4_PSEUDO_CHECKSUM_MODE 105 }; 106 107 /* 108 * Light-L2 RX Producers in Tstorm RAM 109 */ 110 struct core_ll2_port_stats 111 { 112 struct regpair gsi_invalid_hdr; 113 struct regpair gsi_invalid_pkt_length; 114 struct regpair gsi_unsupported_pkt_typ; 115 struct regpair gsi_crcchksm_error; 116 }; 117 118 /* 119 * Ethernet TX Per Queue Stats 120 */ 121 struct core_ll2_pstorm_per_queue_stat 122 { 123 struct regpair sent_ucast_bytes /* number of total bytes sent without errors */; 124 struct regpair sent_mcast_bytes /* number of total bytes sent without errors */; 125 struct regpair sent_bcast_bytes /* number of total bytes sent without errors */; 126 struct regpair sent_ucast_pkts /* number of total packets sent without errors */; 127 struct regpair sent_mcast_pkts /* number of total packets sent without errors */; 128 struct regpair sent_bcast_pkts /* number of total packets sent without errors */; 129 }; 130 131 /* 132 * Light-L2 RX Producers in Tstorm RAM 133 */ 134 struct core_ll2_rx_prod 135 { 136 __le16 bd_prod /* BD Producer */; 137 __le16 cqe_prod /* CQE Producer */; 138 __le32 reserved; 139 }; 140 141 struct core_ll2_tstorm_per_queue_stat 142 { 143 struct regpair packet_too_big_discard /* Number of packets discarded because they are bigger than MTU */; 144 struct regpair no_buff_discard /* Number of packets discarded due to lack of host buffers */; 145 }; 146 147 struct core_ll2_ustorm_per_queue_stat 148 { 149 struct regpair rcv_ucast_bytes; 150 struct regpair rcv_mcast_bytes; 151 struct regpair rcv_bcast_bytes; 152 struct regpair rcv_ucast_pkts; 153 struct regpair rcv_mcast_pkts; 154 struct regpair rcv_bcast_pkts; 155 }; 156 157 /* 158 * Core Ramrod Command IDs (light L2) 159 */ 160 enum core_ramrod_cmd_id 161 { 162 CORE_RAMROD_UNUSED, 163 CORE_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */, 164 CORE_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */, 165 CORE_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */, 166 CORE_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */, 167 CORE_RAMROD_RX_QUEUE_FLUSH /* RX Flush queue Ramrod */, 168 CORE_RAMROD_TX_QUEUE_UPDATE /* TX Queue Update Ramrod */, 169 MAX_CORE_RAMROD_CMD_ID 170 }; 171 172 /* 173 * Core RX CQE Type for Light L2 174 */ 175 enum core_roce_flavor_type 176 { 177 CORE_ROCE, 178 CORE_RROCE, 179 MAX_CORE_ROCE_FLAVOR_TYPE 180 }; 181 182 /* 183 * Specifies how ll2 should deal with packets errors: packet_too_big and no_buff 184 */ 185 struct core_rx_action_on_error 186 { 187 u8 error_type; 188 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3 /* ll2 how to handle error packet_too_big (use enum core_error_handle) */ 189 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0 190 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3 /* ll2 how to handle error with no_buff (use enum core_error_handle) */ 191 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2 192 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF 193 #define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4 194 }; 195 196 /* 197 * Core RX BD for Light L2 198 */ 199 struct core_rx_bd 200 { 201 struct regpair addr; 202 __le16 reserved[4]; 203 }; 204 205 /* 206 * Core RX CM offload BD for Light L2 207 */ 208 struct core_rx_bd_with_buff_len 209 { 210 struct regpair addr; 211 __le16 buff_length; 212 __le16 reserved[3]; 213 }; 214 215 /* 216 * Core RX CM offload BD for Light L2 217 */ 218 union core_rx_bd_union 219 { 220 struct core_rx_bd rx_bd /* Core Rx Bd static buffer size */; 221 struct core_rx_bd_with_buff_len rx_bd_with_len /* Core Rx Bd with dynamic buffer length */; 222 }; 223 224 /* 225 * Opaque Data for Light L2 RX CQE . 226 */ 227 struct core_rx_cqe_opaque_data 228 { 229 __le32 data[2] /* Opaque CQE Data */; 230 }; 231 232 /* 233 * Core RX CQE Type for Light L2 234 */ 235 enum core_rx_cqe_type 236 { 237 CORE_RX_CQE_ILLIGAL_TYPE /* Bad RX Cqe type */, 238 CORE_RX_CQE_TYPE_REGULAR /* Regular Core RX CQE */, 239 CORE_RX_CQE_TYPE_GSI_OFFLOAD /* Fp Gsi offload RX CQE */, 240 CORE_RX_CQE_TYPE_SLOW_PATH /* Slow path Core RX CQE */, 241 MAX_CORE_RX_CQE_TYPE 242 }; 243 244 /* 245 * Core RX CQE for Light L2 . 246 */ 247 struct core_rx_fast_path_cqe 248 { 249 u8 type /* CQE type (use enum core_rx_cqe_type) */; 250 u8 placement_offset /* Offset (in bytes) of the packet from start of the buffer */; 251 struct parsing_and_err_flags parse_flags /* Parsing and error flags from the parser */; 252 __le16 packet_length /* Total packet length (from the parser) */; 253 __le16 vlan /* 802.1q VLAN tag */; 254 struct core_rx_cqe_opaque_data opaque_data /* Opaque Data */; 255 struct parsing_err_flags err_flags /* bit- map: each bit represents a specific error. errors indications are provided by the cracker. see spec for detailed description */; 256 __le16 reserved0; 257 __le32 reserved1[3]; 258 }; 259 260 /* 261 * Core Rx CM offload CQE . 262 */ 263 struct core_rx_gsi_offload_cqe 264 { 265 u8 type /* CQE type (use enum core_rx_cqe_type) */; 266 u8 data_length_error /* set if gsi data is bigger than buff */; 267 struct parsing_and_err_flags parse_flags /* Parsing and error flags from the parser */; 268 __le16 data_length /* Total packet length (from the parser) */; 269 __le16 vlan /* 802.1q VLAN tag */; 270 __le32 src_mac_addrhi /* hi 4 bytes source mac address */; 271 __le16 src_mac_addrlo /* lo 2 bytes of source mac address */; 272 __le16 qp_id /* These are the lower 16 bit of QP id in RoCE BTH header */; 273 __le32 src_qp /* Source QP from DETH header */; 274 __le32 reserved[3]; 275 }; 276 277 /* 278 * Core RX CQE for Light L2 . 279 */ 280 struct core_rx_slow_path_cqe 281 { 282 u8 type /* CQE type (use enum core_rx_cqe_type) */; 283 u8 ramrod_cmd_id; 284 __le16 echo; 285 struct core_rx_cqe_opaque_data opaque_data /* Opaque Data */; 286 __le32 reserved1[5]; 287 }; 288 289 /* 290 * Core RX CM offload BD for Light L2 291 */ 292 union core_rx_cqe_union 293 { 294 struct core_rx_fast_path_cqe rx_cqe_fp /* Fast path CQE */; 295 struct core_rx_gsi_offload_cqe rx_cqe_gsi /* GSI offload CQE */; 296 struct core_rx_slow_path_cqe rx_cqe_sp /* Slow path CQE */; 297 }; 298 299 /* 300 * Ramrod data for rx queue start ramrod 301 */ 302 struct core_rx_start_ramrod_data 303 { 304 struct regpair bd_base /* bd address of the first bd page */; 305 struct regpair cqe_pbl_addr /* Base address on host of CQE PBL */; 306 __le16 mtu /* Maximum transmission unit */; 307 __le16 sb_id /* Status block ID */; 308 u8 sb_index /* index of the protocol index */; 309 u8 complete_cqe_flg /* post completion to the CQE ring if set */; 310 u8 complete_event_flg /* post completion to the event ring if set */; 311 u8 drop_ttl0_flg /* drop packet with ttl0 if set */; 312 __le16 num_of_pbl_pages /* Num of pages in CQE PBL */; 313 u8 inner_vlan_stripping_en /* if set, 802.1q tags will be removed and copied to CQE */; 314 u8 report_outer_vlan /* if set and inner vlan does not exist, the outer vlan will copied to CQE as inner vlan. should be used in MF_OVLAN mode only. */; 315 u8 queue_id /* Light L2 RX Queue ID */; 316 u8 main_func_queue /* Is this the main queue for the PF */; 317 u8 mf_si_bcast_accept_all /* Duplicate broadcast packets to LL2 main queue in mf_si mode. Valid if main_func_queue is set. */; 318 u8 mf_si_mcast_accept_all /* Duplicate multicast packets to LL2 main queue in mf_si mode. Valid if main_func_queue is set. */; 319 struct core_rx_action_on_error action_on_error /* Specifies how ll2 should deal with packets errors: packet_too_big and no_buff */; 320 u8 gsi_offload_flag /* set when in GSI offload mode on ROCE connection */; 321 u8 reserved[6]; 322 }; 323 324 /* 325 * Ramrod data for rx queue stop ramrod 326 */ 327 struct core_rx_stop_ramrod_data 328 { 329 u8 complete_cqe_flg /* post completion to the CQE ring if set */; 330 u8 complete_event_flg /* post completion to the event ring if set */; 331 u8 queue_id /* Light L2 RX Queue ID */; 332 u8 reserved1; 333 __le16 reserved2[2]; 334 }; 335 336 /* 337 * Flags for Core TX BD 338 */ 339 struct core_tx_bd_data 340 { 341 __le16 as_bitfield; 342 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1 /* Do not allow additional VLAN manipulations on this packet (DCB) */ 343 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0 344 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1 /* Insert VLAN into packet. Cannot be set for LB packets (tx_dst == CORE_TX_DEST_LB) */ 345 #define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1 346 #define CORE_TX_BD_DATA_START_BD_MASK 0x1 /* This is the first BD of the packet (for debug) */ 347 #define CORE_TX_BD_DATA_START_BD_SHIFT 2 348 #define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1 /* Calculate the IP checksum for the packet */ 349 #define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3 350 #define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1 /* Calculate the L4 checksum for the packet */ 351 #define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4 352 #define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1 /* Packet is IPv6 with extensions */ 353 #define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5 354 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1 /* If IPv6+ext, and if l4_csum is 1, than this field indicates L4 protocol: 0-TCP, 1-UDP */ 355 #define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6 356 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1 /* The pseudo checksum mode to place in the L4 checksum field. Required only when IPv6+ext and l4_csum is set. (use enum core_l4_pseudo_checksum_mode) */ 357 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7 358 #define CORE_TX_BD_DATA_NBDS_MASK 0xF /* Number of BDs that make up one packet - width wide enough to present CORE_LL2_TX_MAX_BDS_PER_PACKET */ 359 #define CORE_TX_BD_DATA_NBDS_SHIFT 8 360 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1 /* Use roce_flavor enum - Differentiate between Roce flavors is valid when connType is ROCE (use enum core_roce_flavor_type) */ 361 #define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12 362 #define CORE_TX_BD_DATA_IP_LEN_MASK 0x1 /* Calculate ip length */ 363 #define CORE_TX_BD_DATA_IP_LEN_SHIFT 13 364 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK 0x1 /* disables the STAG insertion, relevant only in MF OVLAN mode. */ 365 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_SHIFT 14 366 #define CORE_TX_BD_DATA_RESERVED0_MASK 0x1 367 #define CORE_TX_BD_DATA_RESERVED0_SHIFT 15 368 }; 369 370 /* 371 * Core TX BD for Light L2 372 */ 373 struct core_tx_bd 374 { 375 struct regpair addr /* Buffer Address */; 376 __le16 nbytes /* Number of Bytes in Buffer */; 377 __le16 nw_vlan_or_lb_echo /* Network packets: VLAN to insert to packet (if insertion flag set) LoopBack packets: echo data to pass to Rx */; 378 struct core_tx_bd_data bd_data /* BD flags */; 379 __le16 bitfield1; 380 #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF /* L4 Header Offset from start of packet (in Words). This is needed if both l4_csum and ipv6_ext are set */ 381 #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0 382 #define CORE_TX_BD_TX_DST_MASK 0x3 /* Packet destination - Network, Loopback or Drop (use enum core_tx_dest) */ 383 #define CORE_TX_BD_TX_DST_SHIFT 14 384 }; 385 386 /* 387 * Light L2 TX Destination 388 */ 389 enum core_tx_dest 390 { 391 CORE_TX_DEST_NW /* TX Destination to the Network */, 392 CORE_TX_DEST_LB /* TX Destination to the Loopback */, 393 CORE_TX_DEST_RESERVED, 394 CORE_TX_DEST_DROP /* TX Drop */, 395 MAX_CORE_TX_DEST 396 }; 397 398 /* 399 * Ramrod data for tx queue start ramrod 400 */ 401 struct core_tx_start_ramrod_data 402 { 403 struct regpair pbl_base_addr /* Address of the pbl page */; 404 __le16 mtu /* Maximum transmission unit */; 405 __le16 sb_id /* Status block ID */; 406 u8 sb_index /* Status block protocol index */; 407 u8 stats_en /* Statistics Enable */; 408 u8 stats_id /* Statistics Counter ID */; 409 u8 conn_type /* connection type that loaded ll2 (use enum protocol_type) */; 410 __le16 pbl_size /* Number of BD pages pointed by PBL */; 411 __le16 qm_pq_id /* QM PQ ID */; 412 u8 gsi_offload_flag /* set when in GSI offload mode on ROCE connection */; 413 u8 resrved[3]; 414 }; 415 416 /* 417 * Ramrod data for tx queue stop ramrod 418 */ 419 struct core_tx_stop_ramrod_data 420 { 421 __le32 reserved0[2]; 422 }; 423 424 /* 425 * Ramrod data for tx queue update ramrod 426 */ 427 struct core_tx_update_ramrod_data 428 { 429 u8 update_qm_pq_id_flg /* Flag to Update QM PQ ID */; 430 u8 reserved0; 431 __le16 qm_pq_id /* Updated QM PQ ID */; 432 __le32 reserved1[1]; 433 }; 434 435 /* 436 * Enum flag for what type of DCB data to update 437 */ 438 enum dcb_dscp_update_mode 439 { 440 DONT_UPDATE_DCB_DSCP /* use when no change should be done to DCB data */, 441 UPDATE_DCB /* use to update only L2 (vlan) priority */, 442 UPDATE_DSCP /* use to update only IP DSCP */, 443 UPDATE_DCB_DSCP /* update vlan pri and DSCP */, 444 MAX_DCB_DSCP_UPDATE_MODE 445 }; 446 447 /* 448 * The core storm context for the Ystorm 449 */ 450 struct ystorm_core_conn_st_ctx 451 { 452 __le32 reserved[4]; 453 }; 454 455 /* 456 * The core storm context for the Pstorm 457 */ 458 struct pstorm_core_conn_st_ctx 459 { 460 __le32 reserved[4]; 461 }; 462 463 /* 464 * Core Slowpath Connection storm context of Xstorm 465 */ 466 struct xstorm_core_conn_st_ctx 467 { 468 __le32 spq_base_lo /* SPQ Ring Base Address low dword */; 469 __le32 spq_base_hi /* SPQ Ring Base Address high dword */; 470 struct regpair consolid_base_addr /* Consolidation Ring Base Address */; 471 __le16 spq_cons /* SPQ Ring Consumer */; 472 __le16 consolid_cons /* Consolidation Ring Consumer */; 473 __le32 reserved0[55] /* Pad to 15 cycles */; 474 }; 475 476 struct e4_xstorm_core_conn_ag_ctx 477 { 478 u8 reserved0 /* cdu_validation */; 479 u8 state /* state */; 480 u8 flags0; 481 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 482 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 483 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 484 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1 485 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 486 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2 487 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 488 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 489 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 490 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4 491 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 492 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5 493 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 494 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6 495 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 496 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7 497 u8 flags1; 498 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 499 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0 500 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 501 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1 502 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 503 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2 504 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 505 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3 506 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 507 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4 508 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 509 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5 510 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 511 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 512 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 513 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 514 u8 flags2; 515 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 516 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0 517 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 518 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2 519 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 520 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4 521 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 522 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6 523 u8 flags3; 524 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 525 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0 526 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 527 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2 528 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 529 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4 530 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 531 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6 532 u8 flags4; 533 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 534 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0 535 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 536 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2 537 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 538 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4 539 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 540 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6 541 u8 flags5; 542 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 543 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0 544 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 545 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2 546 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 547 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4 548 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 549 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6 550 u8 flags6; 551 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3 /* cf16 */ 552 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0 553 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 554 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2 555 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 556 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4 557 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 558 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 559 u8 flags7; 560 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 561 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 562 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 563 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2 564 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 565 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 566 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 567 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6 568 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 569 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7 570 u8 flags8; 571 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 572 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0 573 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 574 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1 575 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 576 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2 577 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 578 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3 579 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 580 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4 581 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 582 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5 583 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 584 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6 585 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 586 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7 587 u8 flags9; 588 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 589 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0 590 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 591 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1 592 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 593 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2 594 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 595 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3 596 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 597 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4 598 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 599 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5 600 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1 /* cf16en */ 601 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6 602 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 603 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7 604 u8 flags10; 605 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 606 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 607 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 608 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 609 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 610 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 611 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 612 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3 613 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 614 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 615 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 616 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5 617 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 618 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6 619 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 620 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7 621 u8 flags11; 622 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 623 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0 624 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 625 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1 626 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 627 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 628 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 629 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3 630 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 631 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4 632 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 633 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5 634 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 635 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 636 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 637 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7 638 u8 flags12; 639 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 640 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0 641 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 642 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1 643 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 644 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 645 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 646 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 647 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 648 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4 649 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 650 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5 651 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 652 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6 653 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 654 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7 655 u8 flags13; 656 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 657 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0 658 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 659 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1 660 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 661 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 662 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 663 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 664 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 665 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 666 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 667 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 668 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 669 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 670 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 671 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 672 u8 flags14; 673 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 674 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0 675 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 676 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1 677 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */ 678 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2 679 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */ 680 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3 681 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */ 682 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4 683 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */ 684 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5 685 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 686 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6 687 u8 byte2 /* byte2 */; 688 __le16 physical_q0 /* physical_q0 */; 689 __le16 consolid_prod /* physical_q1 */; 690 __le16 reserved16 /* physical_q2 */; 691 __le16 tx_bd_cons /* word3 */; 692 __le16 tx_bd_or_spq_prod /* word4 */; 693 __le16 word5 /* word5 */; 694 __le16 conn_dpi /* conn_dpi */; 695 u8 byte3 /* byte3 */; 696 u8 byte4 /* byte4 */; 697 u8 byte5 /* byte5 */; 698 u8 byte6 /* byte6 */; 699 __le32 reg0 /* reg0 */; 700 __le32 reg1 /* reg1 */; 701 __le32 reg2 /* reg2 */; 702 __le32 reg3 /* reg3 */; 703 __le32 reg4 /* reg4 */; 704 __le32 reg5 /* cf_array0 */; 705 __le32 reg6 /* cf_array1 */; 706 __le16 word7 /* word7 */; 707 __le16 word8 /* word8 */; 708 __le16 word9 /* word9 */; 709 __le16 word10 /* word10 */; 710 __le32 reg7 /* reg7 */; 711 __le32 reg8 /* reg8 */; 712 __le32 reg9 /* reg9 */; 713 u8 byte7 /* byte7 */; 714 u8 byte8 /* byte8 */; 715 u8 byte9 /* byte9 */; 716 u8 byte10 /* byte10 */; 717 u8 byte11 /* byte11 */; 718 u8 byte12 /* byte12 */; 719 u8 byte13 /* byte13 */; 720 u8 byte14 /* byte14 */; 721 u8 byte15 /* byte15 */; 722 u8 e5_reserved /* e5_reserved */; 723 __le16 word11 /* word11 */; 724 __le32 reg10 /* reg10 */; 725 __le32 reg11 /* reg11 */; 726 __le32 reg12 /* reg12 */; 727 __le32 reg13 /* reg13 */; 728 __le32 reg14 /* reg14 */; 729 __le32 reg15 /* reg15 */; 730 __le32 reg16 /* reg16 */; 731 __le32 reg17 /* reg17 */; 732 __le32 reg18 /* reg18 */; 733 __le32 reg19 /* reg19 */; 734 __le16 word12 /* word12 */; 735 __le16 word13 /* word13 */; 736 __le16 word14 /* word14 */; 737 __le16 word15 /* word15 */; 738 }; 739 740 struct e4_tstorm_core_conn_ag_ctx 741 { 742 u8 byte0 /* cdu_validation */; 743 u8 byte1 /* state */; 744 u8 flags0; 745 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 746 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 747 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 748 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 749 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 750 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2 751 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 752 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3 753 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 754 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4 755 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 756 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5 757 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 758 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6 759 u8 flags1; 760 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 761 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0 762 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 763 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2 764 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 765 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4 766 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 767 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6 768 u8 flags2; 769 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 770 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0 771 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 772 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2 773 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 774 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4 775 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 776 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6 777 u8 flags3; 778 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 779 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0 780 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 781 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2 782 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 783 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4 784 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 785 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5 786 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 787 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6 788 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 789 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7 790 u8 flags4; 791 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 792 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0 793 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 794 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1 795 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 796 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2 797 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 798 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3 799 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 800 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4 801 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 802 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5 803 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 804 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6 805 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 806 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 807 u8 flags5; 808 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 809 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 810 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 811 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 812 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 813 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 814 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 815 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 816 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 817 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 818 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 819 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 820 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 821 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 822 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 823 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 824 __le32 reg0 /* reg0 */; 825 __le32 reg1 /* reg1 */; 826 __le32 reg2 /* reg2 */; 827 __le32 reg3 /* reg3 */; 828 __le32 reg4 /* reg4 */; 829 __le32 reg5 /* reg5 */; 830 __le32 reg6 /* reg6 */; 831 __le32 reg7 /* reg7 */; 832 __le32 reg8 /* reg8 */; 833 u8 byte2 /* byte2 */; 834 u8 byte3 /* byte3 */; 835 __le16 word0 /* word0 */; 836 u8 byte4 /* byte4 */; 837 u8 byte5 /* byte5 */; 838 __le16 word1 /* word1 */; 839 __le16 word2 /* conn_dpi */; 840 __le16 word3 /* word3 */; 841 __le32 reg9 /* reg9 */; 842 __le32 reg10 /* reg10 */; 843 }; 844 845 struct e4_ustorm_core_conn_ag_ctx 846 { 847 u8 reserved /* cdu_validation */; 848 u8 byte1 /* state */; 849 u8 flags0; 850 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 851 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 852 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 853 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 854 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 855 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 856 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 857 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 858 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 859 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 860 u8 flags1; 861 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 862 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0 863 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 864 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2 865 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 866 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4 867 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 868 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6 869 u8 flags2; 870 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 871 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 872 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 873 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 874 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 875 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 876 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 877 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3 878 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 879 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4 880 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 881 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5 882 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 883 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6 884 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 885 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 886 u8 flags3; 887 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 888 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 889 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 890 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 891 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 892 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 893 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 894 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 895 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 896 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 897 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 898 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 899 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 900 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 901 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 902 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 903 u8 byte2 /* byte2 */; 904 u8 byte3 /* byte3 */; 905 __le16 word0 /* conn_dpi */; 906 __le16 word1 /* word1 */; 907 __le32 rx_producers /* reg0 */; 908 __le32 reg1 /* reg1 */; 909 __le32 reg2 /* reg2 */; 910 __le32 reg3 /* reg3 */; 911 __le16 word2 /* word2 */; 912 __le16 word3 /* word3 */; 913 }; 914 915 /* 916 * The core storm context for the Mstorm 917 */ 918 struct mstorm_core_conn_st_ctx 919 { 920 __le32 reserved[24]; 921 }; 922 923 /* 924 * The core storm context for the Ustorm 925 */ 926 struct ustorm_core_conn_st_ctx 927 { 928 __le32 reserved[4]; 929 }; 930 931 /* 932 * core connection context 933 */ 934 struct e4_core_conn_context 935 { 936 struct ystorm_core_conn_st_ctx ystorm_st_context /* ystorm storm context */; 937 struct regpair ystorm_st_padding[2] /* padding */; 938 struct pstorm_core_conn_st_ctx pstorm_st_context /* pstorm storm context */; 939 struct regpair pstorm_st_padding[2] /* padding */; 940 struct xstorm_core_conn_st_ctx xstorm_st_context /* xstorm storm context */; 941 struct e4_xstorm_core_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 942 struct e4_tstorm_core_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 943 struct e4_ustorm_core_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 944 struct mstorm_core_conn_st_ctx mstorm_st_context /* mstorm storm context */; 945 struct ustorm_core_conn_st_ctx ustorm_st_context /* ustorm storm context */; 946 struct regpair ustorm_st_padding[2] /* padding */; 947 }; 948 949 struct e5_xstorm_core_conn_ag_ctx 950 { 951 u8 reserved0 /* cdu_validation */; 952 u8 state_and_core_id /* state_and_core_id */; 953 u8 flags0; 954 #define E5_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 955 #define E5_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 956 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 957 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1 958 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 959 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2 960 #define E5_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 961 #define E5_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 962 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 963 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4 964 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 965 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5 966 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 967 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6 968 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 969 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7 970 u8 flags1; 971 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 972 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0 973 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 974 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1 975 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 976 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2 977 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 978 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3 979 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 980 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4 981 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 982 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5 983 #define E5_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 984 #define E5_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 985 #define E5_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 986 #define E5_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 987 u8 flags2; 988 #define E5_XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 989 #define E5_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0 990 #define E5_XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 991 #define E5_XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2 992 #define E5_XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 993 #define E5_XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4 994 #define E5_XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 995 #define E5_XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6 996 u8 flags3; 997 #define E5_XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 998 #define E5_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0 999 #define E5_XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1000 #define E5_XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2 1001 #define E5_XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1002 #define E5_XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4 1003 #define E5_XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1004 #define E5_XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6 1005 u8 flags4; 1006 #define E5_XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1007 #define E5_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0 1008 #define E5_XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1009 #define E5_XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2 1010 #define E5_XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1011 #define E5_XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4 1012 #define E5_XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 1013 #define E5_XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6 1014 u8 flags5; 1015 #define E5_XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 1016 #define E5_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0 1017 #define E5_XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 1018 #define E5_XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2 1019 #define E5_XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 1020 #define E5_XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4 1021 #define E5_XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 1022 #define E5_XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6 1023 u8 flags6; 1024 #define E5_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3 /* cf16 */ 1025 #define E5_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0 1026 #define E5_XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 1027 #define E5_XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2 1028 #define E5_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 1029 #define E5_XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4 1030 #define E5_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 1031 #define E5_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 1032 u8 flags7; 1033 #define E5_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 1034 #define E5_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 1035 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 1036 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2 1037 #define E5_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 1038 #define E5_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 1039 #define E5_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1040 #define E5_XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6 1041 #define E5_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1042 #define E5_XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7 1043 u8 flags8; 1044 #define E5_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1045 #define E5_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0 1046 #define E5_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1047 #define E5_XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1 1048 #define E5_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1049 #define E5_XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2 1050 #define E5_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1051 #define E5_XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3 1052 #define E5_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1053 #define E5_XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4 1054 #define E5_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1055 #define E5_XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5 1056 #define E5_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1057 #define E5_XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6 1058 #define E5_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1059 #define E5_XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7 1060 u8 flags9; 1061 #define E5_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1062 #define E5_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0 1063 #define E5_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 1064 #define E5_XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1 1065 #define E5_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 1066 #define E5_XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2 1067 #define E5_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 1068 #define E5_XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3 1069 #define E5_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 1070 #define E5_XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4 1071 #define E5_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 1072 #define E5_XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5 1073 #define E5_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1 /* cf16en */ 1074 #define E5_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6 1075 #define E5_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 1076 #define E5_XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7 1077 u8 flags10; 1078 #define E5_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 1079 #define E5_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 1080 #define E5_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 1081 #define E5_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 1082 #define E5_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 1083 #define E5_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 1084 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 1085 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3 1086 #define E5_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1087 #define E5_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 1088 #define E5_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 1089 #define E5_XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5 1090 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 1091 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6 1092 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 1093 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7 1094 u8 flags11; 1095 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 1096 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0 1097 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 1098 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1 1099 #define E5_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 1100 #define E5_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 1101 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1102 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3 1103 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1104 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4 1105 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1106 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5 1107 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 1108 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 1109 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 1110 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7 1111 u8 flags12; 1112 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 1113 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0 1114 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 1115 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1 1116 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 1117 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 1118 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 1119 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 1120 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 1121 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4 1122 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 1123 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5 1124 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 1125 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6 1126 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 1127 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7 1128 u8 flags13; 1129 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 1130 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0 1131 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 1132 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1 1133 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 1134 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 1135 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 1136 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 1137 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 1138 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 1139 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 1140 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 1141 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 1142 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 1143 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 1144 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 1145 u8 flags14; 1146 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 1147 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0 1148 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 1149 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1 1150 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */ 1151 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2 1152 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */ 1153 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3 1154 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */ 1155 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4 1156 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */ 1157 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5 1158 #define E5_XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 1159 #define E5_XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6 1160 u8 byte2 /* byte2 */; 1161 __le16 physical_q0 /* physical_q0 */; 1162 __le16 consolid_prod /* physical_q1 */; 1163 __le16 reserved16 /* physical_q2 */; 1164 __le16 tx_bd_cons /* word3 */; 1165 __le16 tx_bd_or_spq_prod /* word4 */; 1166 __le16 word5 /* word5 */; 1167 __le16 conn_dpi /* conn_dpi */; 1168 u8 byte3 /* byte3 */; 1169 u8 byte4 /* byte4 */; 1170 u8 byte5 /* byte5 */; 1171 u8 byte6 /* byte6 */; 1172 __le32 reg0 /* reg0 */; 1173 __le32 reg1 /* reg1 */; 1174 __le32 reg2 /* reg2 */; 1175 __le32 reg3 /* reg3 */; 1176 __le32 reg4 /* reg4 */; 1177 __le32 reg5 /* cf_array0 */; 1178 __le32 reg6 /* cf_array1 */; 1179 u8 flags15; 1180 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit22 */ 1181 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1182 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit23 */ 1183 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1184 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit24 */ 1185 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1186 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf24 */ 1187 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 1188 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf24en */ 1189 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 1190 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule26en */ 1191 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 1192 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule27en */ 1193 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 1194 u8 byte7 /* byte7 */; 1195 __le16 word7 /* word7 */; 1196 __le16 word8 /* word8 */; 1197 __le16 word9 /* word9 */; 1198 __le16 word10 /* word10 */; 1199 __le16 word11 /* word11 */; 1200 __le32 reg7 /* reg7 */; 1201 __le32 reg8 /* reg8 */; 1202 __le32 reg9 /* reg9 */; 1203 u8 byte8 /* byte8 */; 1204 u8 byte9 /* byte9 */; 1205 u8 byte10 /* byte10 */; 1206 u8 byte11 /* byte11 */; 1207 u8 byte12 /* byte12 */; 1208 u8 byte13 /* byte13 */; 1209 u8 byte14 /* byte14 */; 1210 u8 byte15 /* byte15 */; 1211 __le32 reg10 /* reg10 */; 1212 __le32 reg11 /* reg11 */; 1213 __le32 reg12 /* reg12 */; 1214 __le32 reg13 /* reg13 */; 1215 __le32 reg14 /* reg14 */; 1216 __le32 reg15 /* reg15 */; 1217 __le32 reg16 /* reg16 */; 1218 __le32 reg17 /* reg17 */; 1219 __le32 reg18 /* reg18 */; 1220 __le32 reg19 /* reg19 */; 1221 __le16 word12 /* word12 */; 1222 __le16 word13 /* word13 */; 1223 __le16 word14 /* word14 */; 1224 __le16 word15 /* word15 */; 1225 }; 1226 1227 struct e5_tstorm_core_conn_ag_ctx 1228 { 1229 u8 byte0 /* cdu_validation */; 1230 u8 byte1 /* state_and_core_id */; 1231 u8 flags0; 1232 #define E5_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1233 #define E5_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 1234 #define E5_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1235 #define E5_TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 1236 #define E5_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1237 #define E5_TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2 1238 #define E5_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1239 #define E5_TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3 1240 #define E5_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1241 #define E5_TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4 1242 #define E5_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 1243 #define E5_TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5 1244 #define E5_TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1245 #define E5_TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6 1246 u8 flags1; 1247 #define E5_TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1248 #define E5_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0 1249 #define E5_TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1250 #define E5_TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2 1251 #define E5_TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1252 #define E5_TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4 1253 #define E5_TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1254 #define E5_TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6 1255 u8 flags2; 1256 #define E5_TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1257 #define E5_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0 1258 #define E5_TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1259 #define E5_TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2 1260 #define E5_TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1261 #define E5_TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4 1262 #define E5_TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1263 #define E5_TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6 1264 u8 flags3; 1265 #define E5_TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1266 #define E5_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0 1267 #define E5_TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1268 #define E5_TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2 1269 #define E5_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1270 #define E5_TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4 1271 #define E5_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1272 #define E5_TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5 1273 #define E5_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1274 #define E5_TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6 1275 #define E5_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1276 #define E5_TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7 1277 u8 flags4; 1278 #define E5_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1279 #define E5_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0 1280 #define E5_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1281 #define E5_TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1 1282 #define E5_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1283 #define E5_TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2 1284 #define E5_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1285 #define E5_TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3 1286 #define E5_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1287 #define E5_TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4 1288 #define E5_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1289 #define E5_TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5 1290 #define E5_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1291 #define E5_TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6 1292 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1293 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 1294 u8 flags5; 1295 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1296 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 1297 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1298 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 1299 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1300 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 1301 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1302 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 1303 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1304 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 1305 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1306 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 1307 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1308 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 1309 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1310 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 1311 u8 flags6; 1312 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 1313 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1314 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 1315 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1316 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 1317 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1318 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 1319 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 1320 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 1321 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 1322 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 1323 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 1324 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 1325 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 1326 u8 byte2 /* byte2 */; 1327 __le16 word0 /* word0 */; 1328 __le32 reg0 /* reg0 */; 1329 __le32 reg1 /* reg1 */; 1330 __le32 reg2 /* reg2 */; 1331 __le32 reg3 /* reg3 */; 1332 __le32 reg4 /* reg4 */; 1333 __le32 reg5 /* reg5 */; 1334 __le32 reg6 /* reg6 */; 1335 __le32 reg7 /* reg7 */; 1336 __le32 reg8 /* reg8 */; 1337 u8 byte3 /* byte3 */; 1338 u8 byte4 /* byte4 */; 1339 u8 byte5 /* byte5 */; 1340 u8 e4_reserved8 /* byte6 */; 1341 __le16 word1 /* word1 */; 1342 __le16 word2 /* conn_dpi */; 1343 __le32 reg9 /* reg9 */; 1344 __le16 word3 /* word3 */; 1345 __le16 e4_reserved9 /* word4 */; 1346 }; 1347 1348 struct e5_ustorm_core_conn_ag_ctx 1349 { 1350 u8 reserved /* cdu_validation */; 1351 u8 byte1 /* state_and_core_id */; 1352 u8 flags0; 1353 #define E5_USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1354 #define E5_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 1355 #define E5_USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1356 #define E5_USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 1357 #define E5_USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1358 #define E5_USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 1359 #define E5_USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1360 #define E5_USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 1361 #define E5_USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1362 #define E5_USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 1363 u8 flags1; 1364 #define E5_USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1365 #define E5_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0 1366 #define E5_USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1367 #define E5_USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2 1368 #define E5_USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1369 #define E5_USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4 1370 #define E5_USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1371 #define E5_USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6 1372 u8 flags2; 1373 #define E5_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1374 #define E5_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 1375 #define E5_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1376 #define E5_USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 1377 #define E5_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1378 #define E5_USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 1379 #define E5_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1380 #define E5_USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3 1381 #define E5_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1382 #define E5_USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4 1383 #define E5_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1384 #define E5_USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5 1385 #define E5_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1386 #define E5_USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6 1387 #define E5_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1388 #define E5_USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 1389 u8 flags3; 1390 #define E5_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1391 #define E5_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 1392 #define E5_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1393 #define E5_USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 1394 #define E5_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1395 #define E5_USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 1396 #define E5_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1397 #define E5_USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 1398 #define E5_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1399 #define E5_USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 1400 #define E5_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1401 #define E5_USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 1402 #define E5_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1403 #define E5_USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 1404 #define E5_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1405 #define E5_USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 1406 u8 flags4; 1407 #define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 1408 #define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1409 #define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 1410 #define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1411 #define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 1412 #define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1413 #define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 1414 #define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 1415 #define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 1416 #define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 1417 #define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 1418 #define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 1419 u8 byte2 /* byte2 */; 1420 __le16 word0 /* conn_dpi */; 1421 __le16 word1 /* word1 */; 1422 __le32 rx_producers /* reg0 */; 1423 __le32 reg1 /* reg1 */; 1424 __le32 reg2 /* reg2 */; 1425 __le32 reg3 /* reg3 */; 1426 __le16 word2 /* word2 */; 1427 __le16 word3 /* word3 */; 1428 }; 1429 1430 /* 1431 * core connection context 1432 */ 1433 struct e5_core_conn_context 1434 { 1435 struct ystorm_core_conn_st_ctx ystorm_st_context /* ystorm storm context */; 1436 struct regpair ystorm_st_padding[2] /* padding */; 1437 struct pstorm_core_conn_st_ctx pstorm_st_context /* pstorm storm context */; 1438 struct regpair pstorm_st_padding[2] /* padding */; 1439 struct xstorm_core_conn_st_ctx xstorm_st_context /* xstorm storm context */; 1440 struct regpair xstorm_st_padding[2] /* padding */; 1441 struct e5_xstorm_core_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 1442 struct e5_tstorm_core_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 1443 struct e5_ustorm_core_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 1444 struct mstorm_core_conn_st_ctx mstorm_st_context /* mstorm storm context */; 1445 struct ustorm_core_conn_st_ctx ustorm_st_context /* ustorm storm context */; 1446 struct regpair ustorm_st_padding[2] /* padding */; 1447 }; 1448 1449 struct eth_mstorm_per_pf_stat 1450 { 1451 struct regpair gre_discard_pkts /* Dropped GRE RX packets */; 1452 struct regpair vxlan_discard_pkts /* Dropped VXLAN RX packets */; 1453 struct regpair geneve_discard_pkts /* Dropped GENEVE RX packets */; 1454 struct regpair lb_discard_pkts /* Dropped Tx switched packets */; 1455 }; 1456 1457 struct eth_mstorm_per_queue_stat 1458 { 1459 struct regpair ttl0_discard /* Number of packets discarded because TTL=0 (in IPv4) or hopLimit=0 (in IPv6) */; 1460 struct regpair packet_too_big_discard /* Number of packets discarded because they are bigger than MTU */; 1461 struct regpair no_buff_discard /* Number of packets discarded due to lack of host buffers (BDs/SGEs/CQEs) */; 1462 struct regpair not_active_discard /* Number of packets discarded because of no active Rx connection */; 1463 struct regpair tpa_coalesced_pkts /* number of coalesced packets in all TPA aggregations */; 1464 struct regpair tpa_coalesced_events /* total number of TPA aggregations */; 1465 struct regpair tpa_aborts_num /* number of aggregations, which abnormally ended */; 1466 struct regpair tpa_coalesced_bytes /* total TCP payload length in all TPA aggregations */; 1467 }; 1468 1469 /* 1470 * Ethernet TX Per PF 1471 */ 1472 struct eth_pstorm_per_pf_stat 1473 { 1474 struct regpair sent_lb_ucast_bytes /* number of total ucast bytes sent on loopback port without errors */; 1475 struct regpair sent_lb_mcast_bytes /* number of total mcast bytes sent on loopback port without errors */; 1476 struct regpair sent_lb_bcast_bytes /* number of total bcast bytes sent on loopback port without errors */; 1477 struct regpair sent_lb_ucast_pkts /* number of total ucast packets sent on loopback port without errors */; 1478 struct regpair sent_lb_mcast_pkts /* number of total mcast packets sent on loopback port without errors */; 1479 struct regpair sent_lb_bcast_pkts /* number of total bcast packets sent on loopback port without errors */; 1480 struct regpair sent_gre_bytes /* Sent GRE bytes */; 1481 struct regpair sent_vxlan_bytes /* Sent VXLAN bytes */; 1482 struct regpair sent_geneve_bytes /* Sent GENEVE bytes */; 1483 struct regpair sent_gre_pkts /* Sent GRE packets */; 1484 struct regpair sent_vxlan_pkts /* Sent VXLAN packets */; 1485 struct regpair sent_geneve_pkts /* Sent GENEVE packets */; 1486 struct regpair gre_drop_pkts /* Dropped GRE TX packets */; 1487 struct regpair vxlan_drop_pkts /* Dropped VXLAN TX packets */; 1488 struct regpair geneve_drop_pkts /* Dropped GENEVE TX packets */; 1489 }; 1490 1491 /* 1492 * Ethernet TX Per Queue Stats 1493 */ 1494 struct eth_pstorm_per_queue_stat 1495 { 1496 struct regpair sent_ucast_bytes /* number of total bytes sent without errors */; 1497 struct regpair sent_mcast_bytes /* number of total bytes sent without errors */; 1498 struct regpair sent_bcast_bytes /* number of total bytes sent without errors */; 1499 struct regpair sent_ucast_pkts /* number of total packets sent without errors */; 1500 struct regpair sent_mcast_pkts /* number of total packets sent without errors */; 1501 struct regpair sent_bcast_pkts /* number of total packets sent without errors */; 1502 struct regpair error_drop_pkts /* number of total packets dropped due to errors */; 1503 }; 1504 1505 /* 1506 * ETH Rx producers data 1507 */ 1508 struct eth_rx_rate_limit 1509 { 1510 __le16 mult /* Rate Limit Multiplier - (Storm Clock (MHz) * 8 / Desired Bandwidth (MB/s)) */; 1511 __le16 cnst /* Constant term to add (or subtract from number of cycles) */; 1512 u8 add_sub_cnst /* Add (1) or subtract (0) constant term */; 1513 u8 reserved0; 1514 __le16 reserved1; 1515 }; 1516 1517 struct eth_ustorm_per_pf_stat 1518 { 1519 struct regpair rcv_lb_ucast_bytes /* number of total ucast bytes received on loopback port without errors */; 1520 struct regpair rcv_lb_mcast_bytes /* number of total mcast bytes received on loopback port without errors */; 1521 struct regpair rcv_lb_bcast_bytes /* number of total bcast bytes received on loopback port without errors */; 1522 struct regpair rcv_lb_ucast_pkts /* number of total ucast packets received on loopback port without errors */; 1523 struct regpair rcv_lb_mcast_pkts /* number of total mcast packets received on loopback port without errors */; 1524 struct regpair rcv_lb_bcast_pkts /* number of total bcast packets received on loopback port without errors */; 1525 struct regpair rcv_gre_bytes /* Received GRE bytes */; 1526 struct regpair rcv_vxlan_bytes /* Received VXLAN bytes */; 1527 struct regpair rcv_geneve_bytes /* Received GENEVE bytes */; 1528 struct regpair rcv_gre_pkts /* Received GRE packets */; 1529 struct regpair rcv_vxlan_pkts /* Received VXLAN packets */; 1530 struct regpair rcv_geneve_pkts /* Received GENEVE packets */; 1531 }; 1532 1533 struct eth_ustorm_per_queue_stat 1534 { 1535 struct regpair rcv_ucast_bytes; 1536 struct regpair rcv_mcast_bytes; 1537 struct regpair rcv_bcast_bytes; 1538 struct regpair rcv_ucast_pkts; 1539 struct regpair rcv_mcast_pkts; 1540 struct regpair rcv_bcast_pkts; 1541 }; 1542 1543 /* 1544 * Event Ring VF-PF Channel data 1545 */ 1546 struct vf_pf_channel_eqe_data 1547 { 1548 struct regpair msg_addr /* VF-PF message address */; 1549 }; 1550 1551 /* 1552 * Event Ring malicious VF data 1553 */ 1554 struct malicious_vf_eqe_data 1555 { 1556 u8 vf_id /* Malicious VF ID */; 1557 u8 err_id /* Malicious VF error (use enum malicious_vf_error_id) */; 1558 __le16 reserved[3]; 1559 }; 1560 1561 /* 1562 * Event Ring initial cleanup data 1563 */ 1564 struct initial_cleanup_eqe_data 1565 { 1566 u8 vf_id /* VF ID */; 1567 u8 reserved[7]; 1568 }; 1569 1570 /* 1571 * Event Data Union 1572 */ 1573 union event_ring_data 1574 { 1575 u8 bytes[8] /* Byte Array */; 1576 struct vf_pf_channel_eqe_data vf_pf_channel /* VF-PF Channel data */; 1577 struct iscsi_eqe_data iscsi_info /* Dedicated fields to iscsi data */; 1578 struct iscsi_connect_done_results iscsi_conn_done_info /* Dedicated fields to iscsi connect done results */; 1579 union rdma_eqe_data rdma_data /* Dedicated field for RDMA data */; 1580 struct malicious_vf_eqe_data malicious_vf /* Malicious VF data */; 1581 struct initial_cleanup_eqe_data vf_init_cleanup /* VF Initial Cleanup data */; 1582 }; 1583 1584 /* 1585 * Event Ring Entry 1586 */ 1587 struct event_ring_entry 1588 { 1589 u8 protocol_id /* Event Protocol ID (use enum protocol_type) */; 1590 u8 opcode /* Event Opcode */; 1591 __le16 reserved0 /* Reserved */; 1592 __le16 echo /* Echo value from ramrod data on the host */; 1593 u8 fw_return_code /* FW return code for SP ramrods */; 1594 u8 flags; 1595 #define EVENT_RING_ENTRY_ASYNC_MASK 0x1 /* 0: synchronous EQE - a completion of SP message. 1: asynchronous EQE */ 1596 #define EVENT_RING_ENTRY_ASYNC_SHIFT 0 1597 #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F 1598 #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1 1599 union event_ring_data data; 1600 }; 1601 1602 /* 1603 * Event Ring Next Page Address 1604 */ 1605 struct event_ring_next_addr 1606 { 1607 struct regpair addr /* Next Page Address */; 1608 __le32 reserved[2] /* Reserved */; 1609 }; 1610 1611 /* 1612 * Event Ring Element 1613 */ 1614 union event_ring_element 1615 { 1616 struct event_ring_entry entry /* Event Ring Entry */; 1617 struct event_ring_next_addr next_addr /* Event Ring Next Page Address */; 1618 }; 1619 1620 /* 1621 * Ports mode 1622 */ 1623 enum fw_flow_ctrl_mode 1624 { 1625 flow_ctrl_pause, 1626 flow_ctrl_pfc, 1627 MAX_FW_FLOW_CTRL_MODE 1628 }; 1629 1630 /* 1631 * GFT profile type. 1632 */ 1633 enum gft_profile_type 1634 { 1635 GFT_PROFILE_TYPE_4_TUPLE /* tunnel type, inner 4 tuple, IP type and L4 type match. */, 1636 GFT_PROFILE_TYPE_L4_DST_PORT /* tunnel type, inner L4 destination port, IP type and L4 type match. */, 1637 GFT_PROFILE_TYPE_IP_DST_ADDR /* tunnel type, inner IP destination address and IP type match. */, 1638 GFT_PROFILE_TYPE_IP_SRC_ADDR /* tunnel type, inner IP source address and IP type match. */, 1639 GFT_PROFILE_TYPE_TUNNEL_TYPE /* tunnel type and outer IP type match. */, 1640 MAX_GFT_PROFILE_TYPE 1641 }; 1642 1643 /* 1644 * Major and Minor hsi Versions 1645 */ 1646 struct hsi_fp_ver_struct 1647 { 1648 u8 minor_ver_arr[2] /* Minor Version of hsi loading pf */; 1649 u8 major_ver_arr[2] /* Major Version of driver loading pf */; 1650 }; 1651 1652 /* 1653 * Integration Phase 1654 */ 1655 enum integ_phase 1656 { 1657 INTEG_PHASE_BB_A0_LATEST=3 /* BB A0 latest integration phase */, 1658 INTEG_PHASE_BB_B0_NO_MCP=10 /* BB B0 without MCP */, 1659 INTEG_PHASE_BB_B0_WITH_MCP=11 /* BB B0 with MCP */, 1660 MAX_INTEG_PHASE 1661 }; 1662 1663 /* 1664 * Ports mode 1665 */ 1666 enum iwarp_ll2_tx_queues 1667 { 1668 IWARP_LL2_IN_ORDER_TX_QUEUE=1 /* LL2 queue for OOO packets sent in-order by the driver */, 1669 IWARP_LL2_ALIGNED_TX_QUEUE /* LL2 queue for unaligned packets sent aligned by the driver */, 1670 IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE /* LL2 queue for unaligned packets sent aligned and was right-trimmed by the driver */, 1671 IWARP_LL2_ERROR /* Error indication */, 1672 MAX_IWARP_LL2_TX_QUEUES 1673 }; 1674 1675 /* 1676 * Malicious VF error ID 1677 */ 1678 enum malicious_vf_error_id 1679 { 1680 MALICIOUS_VF_NO_ERROR /* Zero placeholder value */, 1681 VF_PF_CHANNEL_NOT_READY /* Writing to VF/PF channel when it is not ready */, 1682 VF_ZONE_MSG_NOT_VALID /* VF channel message is not valid */, 1683 VF_ZONE_FUNC_NOT_ENABLED /* Parent PF of VF channel is not active */, 1684 ETH_PACKET_TOO_SMALL /* TX packet is shorter then reported on BDs or from minimal size */, 1685 ETH_ILLEGAL_VLAN_MODE /* Tx packet with marked as insert VLAN when its illegal */, 1686 ETH_MTU_VIOLATION /* TX packet is greater then MTU */, 1687 ETH_ILLEGAL_INBAND_TAGS /* TX packet has illegal inband tags marked */, 1688 ETH_VLAN_INSERT_AND_INBAND_VLAN /* Vlan cant be added to inband tag */, 1689 ETH_ILLEGAL_NBDS /* indicated number of BDs for the packet is illegal */, 1690 ETH_FIRST_BD_WO_SOP /* 1st BD must have start_bd flag set */, 1691 ETH_INSUFFICIENT_BDS /* There are not enough BDs for transmission of even one packet */, 1692 ETH_ILLEGAL_LSO_HDR_NBDS /* Header NBDs value is illegal */, 1693 ETH_ILLEGAL_LSO_MSS /* LSO MSS value is more than allowed */, 1694 ETH_ZERO_SIZE_BD /* empty BD (which not contains control flags) is illegal */, 1695 ETH_ILLEGAL_LSO_HDR_LEN /* LSO header size is above the limit */, 1696 ETH_INSUFFICIENT_PAYLOAD /* In LSO its expected that on the local BD ring there will be at least MSS bytes of data */, 1697 ETH_EDPM_OUT_OF_SYNC /* Valid BDs on local ring after EDPM L2 sync */, 1698 ETH_TUNN_IPV6_EXT_NBD_ERR /* Tunneled packet with IPv6+Ext without a proper number of BDs */, 1699 ETH_CONTROL_PACKET_VIOLATION /* VF sent control frame such as PFC */, 1700 ETH_ANTI_SPOOFING_ERR /* Anti-Spoofing verification failure */, 1701 ETH_PACKET_SIZE_TOO_LARGE /* packet scanned is too large (can be 9700 at most) */, 1702 MAX_MALICIOUS_VF_ERROR_ID 1703 }; 1704 1705 /* 1706 * Mstorm non-triggering VF zone 1707 */ 1708 struct mstorm_non_trigger_vf_zone 1709 { 1710 struct eth_mstorm_per_queue_stat eth_queue_stat /* VF statistic bucket */; 1711 struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD] /* VF RX queues producers */; 1712 }; 1713 1714 /* 1715 * Mstorm VF zone 1716 */ 1717 struct mstorm_vf_zone 1718 { 1719 struct mstorm_non_trigger_vf_zone non_trigger /* non-interrupt-triggering zone */; 1720 }; 1721 1722 /* 1723 * vlan header including TPID and TCI fields 1724 */ 1725 struct vlan_header 1726 { 1727 __le16 tpid /* Tag Protocol Identifier */; 1728 __le16 tci /* Tag Control Information */; 1729 }; 1730 1731 /* 1732 * outer tag configurations 1733 */ 1734 struct outer_tag_config_struct 1735 { 1736 u8 enable_stag_pri_change /* Enables updating S-tag priority from inner tag or DCB. Should be 1 for Bette Davis, UFP with Host Control mode, and UFP with DCB over base interface. else - 0. */; 1737 u8 pri_map_valid /* If inner_to_outer_pri_map is initialize then set pri_map_valid */; 1738 u8 reserved[2]; 1739 struct vlan_header outer_tag /* In case mf_mode is MF_OVLAN, this field specifies the outer tag protocol identifier and outer tag control information */; 1740 u8 inner_to_outer_pri_map[8] /* Map from inner to outer priority. Set pri_map_valid when init map */; 1741 }; 1742 1743 /* 1744 * personality per PF 1745 */ 1746 enum personality_type 1747 { 1748 BAD_PERSONALITY_TYP, 1749 PERSONALITY_ISCSI /* iSCSI and LL2 */, 1750 PERSONALITY_FCOE /* Fcoe and LL2 */, 1751 PERSONALITY_RDMA_AND_ETH /* Roce or Iwarp, Eth and LL2 */, 1752 PERSONALITY_RDMA /* Roce and LL2 */, 1753 PERSONALITY_CORE /* CORE(LL2) */, 1754 PERSONALITY_ETH /* Ethernet */, 1755 PERSONALITY_TOE /* Toe and LL2 */, 1756 MAX_PERSONALITY_TYPE 1757 }; 1758 1759 /* 1760 * tunnel configuration 1761 */ 1762 struct pf_start_tunnel_config 1763 { 1764 u8 set_vxlan_udp_port_flg /* Set VXLAN tunnel UDP destination port to vxlan_udp_port. If not set - FW will use a default port */; 1765 u8 set_geneve_udp_port_flg /* Set GENEVE tunnel UDP destination port to geneve_udp_port. If not set - FW will use a default port */; 1766 u8 tunnel_clss_vxlan /* Rx classification scheme for VXLAN tunnel. (use enum tunnel_clss) */; 1767 u8 tunnel_clss_l2geneve /* Rx classification scheme for l2 GENEVE tunnel. (use enum tunnel_clss) */; 1768 u8 tunnel_clss_ipgeneve /* Rx classification scheme for ip GENEVE tunnel. (use enum tunnel_clss) */; 1769 u8 tunnel_clss_l2gre /* Rx classification scheme for l2 GRE tunnel. (use enum tunnel_clss) */; 1770 u8 tunnel_clss_ipgre /* Rx classification scheme for ip GRE tunnel. (use enum tunnel_clss) */; 1771 u8 reserved; 1772 __le16 vxlan_udp_port /* VXLAN tunnel UDP destination port. Valid if set_vxlan_udp_port_flg=1 */; 1773 __le16 geneve_udp_port /* GENEVE tunnel UDP destination port. Valid if set_geneve_udp_port_flg=1 */; 1774 }; 1775 1776 /* 1777 * Ramrod data for PF start ramrod 1778 */ 1779 struct pf_start_ramrod_data 1780 { 1781 struct regpair event_ring_pbl_addr /* Address of event ring PBL */; 1782 struct regpair consolid_q_pbl_addr /* PBL address of consolidation queue */; 1783 struct pf_start_tunnel_config tunnel_config /* tunnel configuration. */; 1784 __le16 event_ring_sb_id /* Status block ID */; 1785 u8 base_vf_id /* All VfIds owned by Pf will be from baseVfId till baseVfId+numVfs */; 1786 u8 num_vfs /* Amount of vfs owned by PF */; 1787 u8 event_ring_num_pages /* Number of PBL pages in event ring */; 1788 u8 event_ring_sb_index /* Status block index */; 1789 u8 path_id /* HW path ID (engine ID) */; 1790 u8 warning_as_error /* In FW asserts, treat warning as error */; 1791 u8 dont_log_ramrods /* If not set - throw a warning for each ramrod (for debug) */; 1792 u8 personality /* define what type of personality is new PF (use enum personality_type) */; 1793 __le16 log_type_mask /* Log type mask. Each bit set enables a corresponding event type logging. Event types are defined as ASSERT_LOG_TYPE_xxx */; 1794 u8 mf_mode /* Multi function mode (use enum mf_mode) */; 1795 u8 integ_phase /* Integration phase (use enum integ_phase) */; 1796 u8 allow_npar_tx_switching /* If set, inter-pf tx switching is allowed in Switch Independent function mode */; 1797 u8 reserved0; 1798 struct hsi_fp_ver_struct hsi_fp_ver /* FP HSI version to be used by FW */; 1799 struct outer_tag_config_struct outer_tag_config /* Outer tag configurations */; 1800 }; 1801 1802 /* 1803 * Per protocol DCB data 1804 */ 1805 struct protocol_dcb_data 1806 { 1807 u8 dcb_enable_flag /* Enable DCB */; 1808 u8 dscp_enable_flag /* Enable updating DSCP value */; 1809 u8 dcb_priority /* DCB priority */; 1810 u8 dcb_tc /* DCB TC */; 1811 u8 dscp_val /* DSCP value to write if dscp_enable_flag is set */; 1812 u8 dcb_dont_add_vlan0 /* When DCB is enabled - if this flag is set, dont add VLAN 0 tag to untagged frames */; 1813 }; 1814 1815 /* 1816 * Update tunnel configuration 1817 */ 1818 struct pf_update_tunnel_config 1819 { 1820 u8 update_rx_pf_clss /* Update RX per PF tunnel classification scheme. */; 1821 u8 update_rx_def_ucast_clss /* Update per PORT default tunnel RX classification scheme for traffic with unknown unicast outer MAC in NPAR mode. */; 1822 u8 update_rx_def_non_ucast_clss /* Update per PORT default tunnel RX classification scheme for traffic with non unicast outer MAC in NPAR mode. */; 1823 u8 set_vxlan_udp_port_flg /* Update VXLAN tunnel UDP destination port. */; 1824 u8 set_geneve_udp_port_flg /* Update GENEVE tunnel UDP destination port. */; 1825 u8 tunnel_clss_vxlan /* Classification scheme for VXLAN tunnel. (use enum tunnel_clss) */; 1826 u8 tunnel_clss_l2geneve /* Classification scheme for l2 GENEVE tunnel. (use enum tunnel_clss) */; 1827 u8 tunnel_clss_ipgeneve /* Classification scheme for ip GENEVE tunnel. (use enum tunnel_clss) */; 1828 u8 tunnel_clss_l2gre /* Classification scheme for l2 GRE tunnel. (use enum tunnel_clss) */; 1829 u8 tunnel_clss_ipgre /* Classification scheme for ip GRE tunnel. (use enum tunnel_clss) */; 1830 __le16 vxlan_udp_port /* VXLAN tunnel UDP destination port. */; 1831 __le16 geneve_udp_port /* GENEVE tunnel UDP destination port. */; 1832 __le16 reserved; 1833 }; 1834 1835 /* 1836 * Data for port update ramrod 1837 */ 1838 struct pf_update_ramrod_data 1839 { 1840 u8 update_eth_dcb_data_mode /* Update Eth DCB data indication (use enum dcb_dscp_update_mode) */; 1841 u8 update_fcoe_dcb_data_mode /* Update FCOE DCB data indication (use enum dcb_dscp_update_mode) */; 1842 u8 update_iscsi_dcb_data_mode /* Update iSCSI DCB data indication (use enum dcb_dscp_update_mode) */; 1843 u8 update_roce_dcb_data_mode /* Update ROCE DCB data indication (use enum dcb_dscp_update_mode) */; 1844 u8 update_rroce_dcb_data_mode /* Update RROCE (RoceV2) DCB data indication (use enum dcb_dscp_update_mode) */; 1845 u8 update_iwarp_dcb_data_mode /* Update IWARP DCB data indication (use enum dcb_dscp_update_mode) */; 1846 u8 update_mf_vlan_flag /* Update MF outer vlan Id */; 1847 u8 update_enable_stag_pri_change /* Update Enable STAG Priority Change indication */; 1848 struct protocol_dcb_data eth_dcb_data /* core eth related fields */; 1849 struct protocol_dcb_data fcoe_dcb_data /* core fcoe related fields */; 1850 struct protocol_dcb_data iscsi_dcb_data /* core iscsi related fields */; 1851 struct protocol_dcb_data roce_dcb_data /* core roce related fields */; 1852 struct protocol_dcb_data rroce_dcb_data /* core roce related fields */; 1853 struct protocol_dcb_data iwarp_dcb_data /* core iwarp related fields */; 1854 __le16 mf_vlan /* new outer vlan id value */; 1855 u8 enable_stag_pri_change /* enables updating S-tag priority from inner tag or DCB. Should be 1 for Bette Davis, UFP with Host Control mode, and UFP with DCB over base interface. else - 0. */; 1856 u8 reserved; 1857 struct pf_update_tunnel_config tunnel_config /* tunnel configuration. */; 1858 }; 1859 1860 /* 1861 * Ports mode 1862 */ 1863 enum ports_mode 1864 { 1865 ENGX2_PORTX1 /* 2 engines x 1 port */, 1866 ENGX2_PORTX2 /* 2 engines x 2 ports */, 1867 ENGX1_PORTX1 /* 1 engine x 1 port */, 1868 ENGX1_PORTX2 /* 1 engine x 2 ports */, 1869 ENGX1_PORTX4 /* 1 engine x 4 ports */, 1870 MAX_PORTS_MODE 1871 }; 1872 1873 /* 1874 * use to index in hsi_fp_[major|minor]_ver_arr per protocol 1875 */ 1876 enum protocol_version_array_key 1877 { 1878 ETH_VER_KEY=0, 1879 ROCE_VER_KEY, 1880 MAX_PROTOCOL_VERSION_ARRAY_KEY 1881 }; 1882 1883 /* 1884 * RDMA TX Stats 1885 */ 1886 struct rdma_sent_stats 1887 { 1888 struct regpair sent_bytes /* number of total RDMA bytes sent */; 1889 struct regpair sent_pkts /* number of total RDMA packets sent */; 1890 }; 1891 1892 /* 1893 * Pstorm non-triggering VF zone 1894 */ 1895 struct pstorm_non_trigger_vf_zone 1896 { 1897 struct eth_pstorm_per_queue_stat eth_queue_stat /* VF statistic bucket */; 1898 struct rdma_sent_stats rdma_stats /* RoCE sent statistics */; 1899 }; 1900 1901 /* 1902 * Pstorm VF zone 1903 */ 1904 struct pstorm_vf_zone 1905 { 1906 struct pstorm_non_trigger_vf_zone non_trigger /* non-interrupt-triggering zone */; 1907 struct regpair reserved[7] /* vf_zone size mus be power of 2 */; 1908 }; 1909 1910 /* 1911 * Ramrod Header of SPQE 1912 */ 1913 struct ramrod_header 1914 { 1915 __le32 cid /* Slowpath Connection CID */; 1916 u8 cmd_id /* Ramrod Cmd (Per Protocol Type) */; 1917 u8 protocol_id /* Ramrod Protocol ID (use enum protocol_type) */; 1918 __le16 echo /* Ramrod echo */; 1919 }; 1920 1921 /* 1922 * RDMA RX Stats 1923 */ 1924 struct rdma_rcv_stats 1925 { 1926 struct regpair rcv_bytes /* number of total RDMA bytes received */; 1927 struct regpair rcv_pkts /* number of total RDMA packets received */; 1928 }; 1929 1930 /* 1931 * Data for update QCN/DCQCN RL ramrod 1932 */ 1933 struct rl_update_ramrod_data 1934 { 1935 u8 qcn_update_param_flg /* Update QCN global params: timeout. */; 1936 u8 dcqcn_update_param_flg /* Update DCQCN global params: timeout, g, k. */; 1937 u8 rl_init_flg /* Init RL parameters, when RL disabled. */; 1938 u8 rl_start_flg /* Start RL in IDLE state. Set rate to maximum. */; 1939 u8 rl_stop_flg /* Stop RL. */; 1940 u8 rl_id_first /* ID of first or single RL, that will be updated. */; 1941 u8 rl_id_last /* ID of last RL, that will be updated. If clear, single RL will updated. */; 1942 u8 rl_dc_qcn_flg /* If set, RL will used for DCQCN. */; 1943 __le32 rl_bc_rate /* Byte Counter Limit. */; 1944 __le16 rl_max_rate /* Maximum rate in 1.6 Mbps resolution. */; 1945 __le16 rl_r_ai /* Active increase rate. */; 1946 __le16 rl_r_hai /* Hyper active increase rate. */; 1947 __le16 dcqcn_g /* DCQCN Alpha update gain in 1/64K resolution . */; 1948 __le32 dcqcn_k_us /* DCQCN Alpha update interval. */; 1949 __le32 dcqcn_timeuot_us /* DCQCN timeout. */; 1950 __le32 qcn_timeuot_us /* QCN timeout. */; 1951 __le32 reserved[2]; 1952 }; 1953 1954 /* 1955 * Slowpath Element (SPQE) 1956 */ 1957 struct slow_path_element 1958 { 1959 struct ramrod_header hdr /* Ramrod Header */; 1960 struct regpair data_ptr /* Pointer to the Ramrod Data on the Host */; 1961 }; 1962 1963 /* 1964 * Tstorm non-triggering VF zone 1965 */ 1966 struct tstorm_non_trigger_vf_zone 1967 { 1968 struct rdma_rcv_stats rdma_stats /* RoCE received statistics */; 1969 }; 1970 1971 struct tstorm_per_port_stat 1972 { 1973 struct regpair trunc_error_discard /* packet is dropped because it was truncated in NIG */; 1974 struct regpair mac_error_discard /* packet is dropped because of Ethernet FCS error */; 1975 struct regpair mftag_filter_discard /* packet is dropped because classification was unsuccessful */; 1976 struct regpair eth_mac_filter_discard /* packet was passed to Ethernet and dropped because of no mac filter match */; 1977 struct regpair ll2_mac_filter_discard /* packet passed to Light L2 and dropped because Light L2 is not configured for this PF */; 1978 struct regpair ll2_conn_disabled_discard /* packet passed to Light L2 and dropped because Light L2 is not configured for this PF */; 1979 struct regpair iscsi_irregular_pkt /* packet is an ISCSI irregular packet */; 1980 struct regpair fcoe_irregular_pkt /* packet is an FCOE irregular packet */; 1981 struct regpair roce_irregular_pkt /* packet is an ROCE irregular packet */; 1982 struct regpair iwarp_irregular_pkt /* packet is an IWARP irregular packet */; 1983 struct regpair eth_irregular_pkt /* packet is an ETH irregular packet */; 1984 struct regpair toe_irregular_pkt /* packet is an TOE irregular packet */; 1985 struct regpair preroce_irregular_pkt /* packet is an PREROCE irregular packet */; 1986 struct regpair eth_gre_tunn_filter_discard /* GRE dropped packets */; 1987 struct regpair eth_vxlan_tunn_filter_discard /* VXLAN dropped packets */; 1988 struct regpair eth_geneve_tunn_filter_discard /* GENEVE dropped packets */; 1989 struct regpair eth_gft_drop_pkt /* GFT dropped packets */; 1990 }; 1991 1992 /* 1993 * Tstorm VF zone 1994 */ 1995 struct tstorm_vf_zone 1996 { 1997 struct tstorm_non_trigger_vf_zone non_trigger /* non-interrupt-triggering zone */; 1998 }; 1999 2000 /* 2001 * Tunnel classification scheme 2002 */ 2003 enum tunnel_clss 2004 { 2005 TUNNEL_CLSS_MAC_VLAN=0 /* Use MAC and VLAN from first L2 header for vport classification. */, 2006 TUNNEL_CLSS_MAC_VNI /* Use MAC from first L2 header and VNI from tunnel header for vport classification */, 2007 TUNNEL_CLSS_INNER_MAC_VLAN /* Use MAC and VLAN from last L2 header for vport classification */, 2008 TUNNEL_CLSS_INNER_MAC_VNI /* Use MAC from last L2 header and VNI from tunnel header for vport classification */, 2009 TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE /* Use MAC and VLAN from last L2 header for vport classification. If no exact match, use MAC and VLAN from first L2 header for classification. */, 2010 MAX_TUNNEL_CLSS 2011 }; 2012 2013 /* 2014 * Ustorm non-triggering VF zone 2015 */ 2016 struct ustorm_non_trigger_vf_zone 2017 { 2018 struct eth_ustorm_per_queue_stat eth_queue_stat /* VF statistic bucket */; 2019 struct regpair vf_pf_msg_addr /* VF-PF message address */; 2020 }; 2021 2022 /* 2023 * Ustorm triggering VF zone 2024 */ 2025 struct ustorm_trigger_vf_zone 2026 { 2027 u8 vf_pf_msg_valid /* VF-PF message valid flag */; 2028 u8 reserved[7]; 2029 }; 2030 2031 /* 2032 * Ustorm VF zone 2033 */ 2034 struct ustorm_vf_zone 2035 { 2036 struct ustorm_non_trigger_vf_zone non_trigger /* non-interrupt-triggering zone */; 2037 struct ustorm_trigger_vf_zone trigger /* interrupt triggering zone */; 2038 }; 2039 2040 /* 2041 * VF-PF channel data 2042 */ 2043 struct vf_pf_channel_data 2044 { 2045 __le32 ready /* 0: VF-PF Channel NOT ready. Waiting for ack from PF driver. 1: VF-PF Channel is ready for a new transaction. */; 2046 u8 valid /* 0: VF-PF Channel is invalid because of malicious VF. 1: VF-PF Channel is valid. */; 2047 u8 reserved0; 2048 __le16 reserved1; 2049 }; 2050 2051 /* 2052 * Ramrod data for VF start ramrod 2053 */ 2054 struct vf_start_ramrod_data 2055 { 2056 u8 vf_id /* VF ID */; 2057 u8 enable_flr_ack /* If set, initial cleanup ack will be sent to parent PF SP event queue */; 2058 __le16 opaque_fid /* VF opaque FID */; 2059 u8 personality /* define what type of personality is new VF (use enum personality_type) */; 2060 u8 reserved[7]; 2061 struct hsi_fp_ver_struct hsi_fp_ver /* FP HSI version to be used by FW */; 2062 }; 2063 2064 /* 2065 * Ramrod data for VF start ramrod 2066 */ 2067 struct vf_stop_ramrod_data 2068 { 2069 u8 vf_id /* VF ID */; 2070 u8 reserved0; 2071 __le16 reserved1; 2072 __le32 reserved2; 2073 }; 2074 2075 /* 2076 * VF zone size mode. 2077 */ 2078 enum vf_zone_size_mode 2079 { 2080 VF_ZONE_SIZE_MODE_DEFAULT /* Default VF zone size. Up to 192 VF supported. */, 2081 VF_ZONE_SIZE_MODE_DOUBLE /* Doubled VF zone size. Up to 96 VF supported. */, 2082 VF_ZONE_SIZE_MODE_QUAD /* Quad VF zone size. Up to 48 VF supported. */, 2083 MAX_VF_ZONE_SIZE_MODE 2084 }; 2085 2086 /* 2087 * Attentions status block 2088 */ 2089 struct atten_status_block 2090 { 2091 __le32 atten_bits; 2092 __le32 atten_ack; 2093 __le16 reserved0; 2094 __le16 sb_index /* status block running index */; 2095 __le32 reserved1; 2096 }; 2097 2098 /* 2099 * DMAE command 2100 */ 2101 struct dmae_cmd 2102 { 2103 __le32 opcode; 2104 #define DMAE_CMD_SRC_MASK 0x1 /* DMA Source. 0 - PCIe, 1 - GRC (use enum dmae_cmd_src_enum) */ 2105 #define DMAE_CMD_SRC_SHIFT 0 2106 #define DMAE_CMD_DST_MASK 0x3 /* DMA destination. 0 - None, 1 - PCIe, 2 - GRC, 3 - None (use enum dmae_cmd_dst_enum) */ 2107 #define DMAE_CMD_DST_SHIFT 1 2108 #define DMAE_CMD_C_DST_MASK 0x1 /* Completion destination. 0 - PCie, 1 - GRC (use enum dmae_cmd_c_dst_enum) */ 2109 #define DMAE_CMD_C_DST_SHIFT 3 2110 #define DMAE_CMD_CRC_RESET_MASK 0x1 /* Reset the CRC result (do not use the previous result as the seed) */ 2111 #define DMAE_CMD_CRC_RESET_SHIFT 4 2112 #define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1 /* Reset the source address in the next go to the same source address of the previous go */ 2113 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5 2114 #define DMAE_CMD_DST_ADDR_RESET_MASK 0x1 /* Reset the destination address in the next go to the same destination address of the previous go */ 2115 #define DMAE_CMD_DST_ADDR_RESET_SHIFT 6 2116 #define DMAE_CMD_COMP_FUNC_MASK 0x1 /* 0 completion function is the same as src function, 1 - 0 completion function is the same as dst function (use enum dmae_cmd_comp_func_enum) */ 2117 #define DMAE_CMD_COMP_FUNC_SHIFT 7 2118 #define DMAE_CMD_COMP_WORD_EN_MASK 0x1 /* 0 - Do not write a completion word, 1 - Write a completion word (use enum dmae_cmd_comp_word_en_enum) */ 2119 #define DMAE_CMD_COMP_WORD_EN_SHIFT 8 2120 #define DMAE_CMD_COMP_CRC_EN_MASK 0x1 /* 0 - Do not write a CRC word, 1 - Write a CRC word (use enum dmae_cmd_comp_crc_en_enum) */ 2121 #define DMAE_CMD_COMP_CRC_EN_SHIFT 9 2122 #define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7 /* The CRC word should be taken from the DMAE address space from address 9+X, where X is the value in these bits. */ 2123 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10 2124 #define DMAE_CMD_RESERVED1_MASK 0x1 2125 #define DMAE_CMD_RESERVED1_SHIFT 13 2126 #define DMAE_CMD_ENDIANITY_MODE_MASK 0x3 2127 #define DMAE_CMD_ENDIANITY_MODE_SHIFT 14 2128 #define DMAE_CMD_ERR_HANDLING_MASK 0x3 /* The field specifies how the completion word is affected by PCIe read error. 0 Send a regular completion, 1 - Send a completion with an error indication, 2 do not send a completion (use enum dmae_cmd_error_handling_enum) */ 2129 #define DMAE_CMD_ERR_HANDLING_SHIFT 16 2130 #define DMAE_CMD_PORT_ID_MASK 0x3 /* The port ID to be placed on the RF FID field of the GRC bus. this field is used both when GRC is the destination and when it is the source of the DMAE transaction. */ 2131 #define DMAE_CMD_PORT_ID_SHIFT 18 2132 #define DMAE_CMD_SRC_PF_ID_MASK 0xF /* Source PCI function number [3:0] */ 2133 #define DMAE_CMD_SRC_PF_ID_SHIFT 20 2134 #define DMAE_CMD_DST_PF_ID_MASK 0xF /* Destination PCI function number [3:0] */ 2135 #define DMAE_CMD_DST_PF_ID_SHIFT 24 2136 #define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1 /* Source VFID valid */ 2137 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28 2138 #define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1 /* Destination VFID valid */ 2139 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29 2140 #define DMAE_CMD_RESERVED2_MASK 0x3 2141 #define DMAE_CMD_RESERVED2_SHIFT 30 2142 __le32 src_addr_lo /* PCIe source address low in bytes or GRC source address in DW */; 2143 __le32 src_addr_hi /* PCIe source address high in bytes or reserved (if source is GRC) */; 2144 __le32 dst_addr_lo /* PCIe destination address low in bytes or GRC destination address in DW */; 2145 __le32 dst_addr_hi /* PCIe destination address high in bytes or reserved (if destination is GRC) */; 2146 __le16 length_dw /* Length in DW */; 2147 __le16 opcode_b; 2148 #define DMAE_CMD_SRC_VF_ID_MASK 0xFF /* Source VF id */ 2149 #define DMAE_CMD_SRC_VF_ID_SHIFT 0 2150 #define DMAE_CMD_DST_VF_ID_MASK 0xFF /* Destination VF id */ 2151 #define DMAE_CMD_DST_VF_ID_SHIFT 8 2152 __le32 comp_addr_lo /* PCIe completion address low in bytes or GRC completion address in DW */; 2153 __le32 comp_addr_hi /* PCIe completion address high in bytes or reserved (if completion address is GRC) */; 2154 __le32 comp_val /* Value to write to completion address */; 2155 __le32 crc32 /* crc16 result */; 2156 __le32 crc_32_c /* crc32_c result */; 2157 __le16 crc16 /* crc16 result */; 2158 __le16 crc16_c /* crc16_c result */; 2159 __le16 crc10 /* crc_t10 result */; 2160 __le16 reserved; 2161 __le16 xsum16 /* checksum16 result */; 2162 __le16 xsum8 /* checksum8 result */; 2163 }; 2164 2165 enum dmae_cmd_comp_crc_en_enum 2166 { 2167 dmae_cmd_comp_crc_disabled /* Do not write a CRC word */, 2168 dmae_cmd_comp_crc_enabled /* Write a CRC word */, 2169 MAX_DMAE_CMD_COMP_CRC_EN_ENUM 2170 }; 2171 2172 enum dmae_cmd_comp_func_enum 2173 { 2174 dmae_cmd_comp_func_to_src /* completion word and/or CRC will be sent to SRC-PCI function/SRC VFID */, 2175 dmae_cmd_comp_func_to_dst /* completion word and/or CRC will be sent to DST-PCI function/DST VFID */, 2176 MAX_DMAE_CMD_COMP_FUNC_ENUM 2177 }; 2178 2179 enum dmae_cmd_comp_word_en_enum 2180 { 2181 dmae_cmd_comp_word_disabled /* Do not write a completion word */, 2182 dmae_cmd_comp_word_enabled /* Write the completion word */, 2183 MAX_DMAE_CMD_COMP_WORD_EN_ENUM 2184 }; 2185 2186 enum dmae_cmd_c_dst_enum 2187 { 2188 dmae_cmd_c_dst_pcie, 2189 dmae_cmd_c_dst_grc, 2190 MAX_DMAE_CMD_C_DST_ENUM 2191 }; 2192 2193 enum dmae_cmd_dst_enum 2194 { 2195 dmae_cmd_dst_none_0, 2196 dmae_cmd_dst_pcie, 2197 dmae_cmd_dst_grc, 2198 dmae_cmd_dst_none_3, 2199 MAX_DMAE_CMD_DST_ENUM 2200 }; 2201 2202 enum dmae_cmd_error_handling_enum 2203 { 2204 dmae_cmd_error_handling_send_regular_comp /* Send a regular completion (with no error indication) */, 2205 dmae_cmd_error_handling_send_comp_with_err /* Send a completion with an error indication (i.e. set bit 31 of the completion word) */, 2206 dmae_cmd_error_handling_dont_send_comp /* Do not send a completion */, 2207 MAX_DMAE_CMD_ERROR_HANDLING_ENUM 2208 }; 2209 2210 enum dmae_cmd_src_enum 2211 { 2212 dmae_cmd_src_pcie /* The source is the PCIe */, 2213 dmae_cmd_src_grc /* The source is the GRC */, 2214 MAX_DMAE_CMD_SRC_ENUM 2215 }; 2216 2217 struct e4_mstorm_core_conn_ag_ctx 2218 { 2219 u8 byte0 /* cdu_validation */; 2220 u8 byte1 /* state */; 2221 u8 flags0; 2222 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2223 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 2224 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2225 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 2226 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2227 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 2228 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2229 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 2230 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2231 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 2232 u8 flags1; 2233 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2234 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 2235 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2236 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 2237 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2238 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 2239 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2240 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3 2241 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2242 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4 2243 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2244 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5 2245 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2246 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6 2247 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2248 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7 2249 __le16 word0 /* word0 */; 2250 __le16 word1 /* word1 */; 2251 __le32 reg0 /* reg0 */; 2252 __le32 reg1 /* reg1 */; 2253 }; 2254 2255 struct e4_ystorm_core_conn_ag_ctx 2256 { 2257 u8 byte0 /* cdu_validation */; 2258 u8 byte1 /* state */; 2259 u8 flags0; 2260 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2261 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 2262 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2263 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 2264 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2265 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 2266 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2267 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 2268 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2269 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 2270 u8 flags1; 2271 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2272 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 2273 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2274 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 2275 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2276 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 2277 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2278 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3 2279 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2280 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4 2281 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2282 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5 2283 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2284 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6 2285 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2286 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7 2287 u8 byte2 /* byte2 */; 2288 u8 byte3 /* byte3 */; 2289 __le16 word0 /* word0 */; 2290 __le32 reg0 /* reg0 */; 2291 __le32 reg1 /* reg1 */; 2292 __le16 word1 /* word1 */; 2293 __le16 word2 /* word2 */; 2294 __le16 word3 /* word3 */; 2295 __le16 word4 /* word4 */; 2296 __le32 reg2 /* reg2 */; 2297 __le32 reg3 /* reg3 */; 2298 }; 2299 2300 struct e5_mstorm_core_conn_ag_ctx 2301 { 2302 u8 byte0 /* cdu_validation */; 2303 u8 byte1 /* state_and_core_id */; 2304 u8 flags0; 2305 #define E5_MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2306 #define E5_MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 2307 #define E5_MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2308 #define E5_MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 2309 #define E5_MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2310 #define E5_MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 2311 #define E5_MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2312 #define E5_MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 2313 #define E5_MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2314 #define E5_MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 2315 u8 flags1; 2316 #define E5_MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2317 #define E5_MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 2318 #define E5_MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2319 #define E5_MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 2320 #define E5_MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2321 #define E5_MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 2322 #define E5_MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2323 #define E5_MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3 2324 #define E5_MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2325 #define E5_MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4 2326 #define E5_MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2327 #define E5_MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5 2328 #define E5_MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2329 #define E5_MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6 2330 #define E5_MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2331 #define E5_MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7 2332 __le16 word0 /* word0 */; 2333 __le16 word1 /* word1 */; 2334 __le32 reg0 /* reg0 */; 2335 __le32 reg1 /* reg1 */; 2336 }; 2337 2338 struct e5_ystorm_core_conn_ag_ctx 2339 { 2340 u8 byte0 /* cdu_validation */; 2341 u8 byte1 /* state_and_core_id */; 2342 u8 flags0; 2343 #define E5_YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2344 #define E5_YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 2345 #define E5_YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2346 #define E5_YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 2347 #define E5_YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2348 #define E5_YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 2349 #define E5_YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2350 #define E5_YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 2351 #define E5_YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2352 #define E5_YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 2353 u8 flags1; 2354 #define E5_YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2355 #define E5_YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 2356 #define E5_YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2357 #define E5_YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 2358 #define E5_YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2359 #define E5_YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 2360 #define E5_YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2361 #define E5_YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3 2362 #define E5_YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2363 #define E5_YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4 2364 #define E5_YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2365 #define E5_YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5 2366 #define E5_YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2367 #define E5_YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6 2368 #define E5_YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2369 #define E5_YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7 2370 u8 byte2 /* byte2 */; 2371 u8 byte3 /* byte3 */; 2372 __le16 word0 /* word0 */; 2373 __le32 reg0 /* reg0 */; 2374 __le32 reg1 /* reg1 */; 2375 __le16 word1 /* word1 */; 2376 __le16 word2 /* word2 */; 2377 __le16 word3 /* word3 */; 2378 __le16 word4 /* word4 */; 2379 __le32 reg2 /* reg2 */; 2380 __le32 reg3 /* reg3 */; 2381 }; 2382 2383 struct fw_asserts_ram_section 2384 { 2385 __le16 section_ram_line_offset /* The offset of the section in the RAM in RAM lines (64-bit units) */; 2386 __le16 section_ram_line_size /* The size of the section in RAM lines (64-bit units) */; 2387 u8 list_dword_offset /* The offset of the asserts list within the section in dwords */; 2388 u8 list_element_dword_size /* The size of an assert list element in dwords */; 2389 u8 list_num_elements /* The number of elements in the asserts list */; 2390 u8 list_next_index_dword_offset /* The offset of the next list index field within the section in dwords */; 2391 }; 2392 2393 struct fw_ver_num 2394 { 2395 u8 major /* Firmware major version number */; 2396 u8 minor /* Firmware minor version number */; 2397 u8 rev /* Firmware revision version number */; 2398 u8 eng /* Firmware engineering version number (for bootleg versions) */; 2399 }; 2400 2401 struct fw_ver_info 2402 { 2403 __le16 tools_ver /* Tools version number */; 2404 u8 image_id /* FW image ID (e.g. main, l2b, kuku) */; 2405 u8 reserved1; 2406 struct fw_ver_num num /* FW version number */; 2407 __le32 timestamp /* FW Timestamp in unix time (sec. since 1970) */; 2408 __le32 reserved2; 2409 }; 2410 2411 struct fw_info 2412 { 2413 struct fw_ver_info ver /* FW version information */; 2414 struct fw_asserts_ram_section fw_asserts_section /* Info regarding the FW asserts section in the Storm RAM */; 2415 }; 2416 2417 struct fw_info_location 2418 { 2419 __le32 grc_addr /* GRC address where the fw_info struct is located. */; 2420 __le32 size /* Size of the fw_info structure (thats located at the grc_addr). */; 2421 }; 2422 2423 /* 2424 * IGU cleanup command 2425 */ 2426 struct igu_cleanup 2427 { 2428 __le32 sb_id_and_flags; 2429 #define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF 2430 #define IGU_CLEANUP_RESERVED0_SHIFT 0 2431 #define IGU_CLEANUP_CLEANUP_SET_MASK 0x1 /* cleanup clear - 0, set - 1 */ 2432 #define IGU_CLEANUP_CLEANUP_SET_SHIFT 27 2433 #define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7 2434 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28 2435 #define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1 /* must always be set (use enum command_type_bit) */ 2436 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31 2437 __le32 reserved1; 2438 }; 2439 2440 /* 2441 * IGU firmware driver command 2442 */ 2443 union igu_command 2444 { 2445 struct igu_prod_cons_update prod_cons_update; 2446 struct igu_cleanup cleanup; 2447 }; 2448 2449 /* 2450 * IGU firmware driver command 2451 */ 2452 struct igu_command_reg_ctrl 2453 { 2454 __le16 opaque_fid; 2455 __le16 igu_command_reg_ctrl_fields; 2456 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF 2457 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0 2458 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7 2459 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12 2460 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1 /* command typ: 0 - read, 1 - write */ 2461 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15 2462 }; 2463 2464 /* 2465 * IGU mapping line structure 2466 */ 2467 struct igu_mapping_line 2468 { 2469 __le32 igu_mapping_line_fields; 2470 #define IGU_MAPPING_LINE_VALID_MASK 0x1 2471 #define IGU_MAPPING_LINE_VALID_SHIFT 0 2472 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF 2473 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1 2474 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF /* In BB: VF-0-120, PF-0-7; In K2: VF-0-191, PF-0-15 */ 2475 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9 2476 #define IGU_MAPPING_LINE_PF_VALID_MASK 0x1 /* PF-1, VF-0 */ 2477 #define IGU_MAPPING_LINE_PF_VALID_SHIFT 17 2478 #define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F 2479 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18 2480 #define IGU_MAPPING_LINE_RESERVED_MASK 0xFF 2481 #define IGU_MAPPING_LINE_RESERVED_SHIFT 24 2482 }; 2483 2484 /* 2485 * IGU MSIX line structure 2486 */ 2487 struct igu_msix_vector 2488 { 2489 struct regpair address; 2490 __le32 data; 2491 __le32 msix_vector_fields; 2492 #define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1 2493 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0 2494 #define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF 2495 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1 2496 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF 2497 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16 2498 #define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF 2499 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24 2500 }; 2501 2502 /* 2503 * per encapsulation type enabling flags 2504 */ 2505 struct prs_reg_encapsulation_type_en 2506 { 2507 u8 flags; 2508 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1 /* Enable bit for Ethernet-over-GRE (L2 GRE) encapsulation. */ 2509 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0 2510 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1 /* Enable bit for IP-over-GRE (IP GRE) encapsulation. */ 2511 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1 2512 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1 /* Enable bit for VXLAN encapsulation. */ 2513 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2 2514 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1 /* Enable bit for T-Tag encapsulation. */ 2515 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3 2516 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1 /* Enable bit for Ethernet-over-GENEVE (L2 GENEVE) encapsulation. */ 2517 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4 2518 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1 /* Enable bit for IP-over-GENEVE (IP GENEVE) encapsulation. */ 2519 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5 2520 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3 2521 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6 2522 }; 2523 2524 enum pxp_tph_st_hint 2525 { 2526 TPH_ST_HINT_BIDIR /* Read/Write access by Host and Device */, 2527 TPH_ST_HINT_REQUESTER /* Read/Write access by Device */, 2528 TPH_ST_HINT_TARGET /* Device Write and Host Read, or Host Write and Device Read */, 2529 TPH_ST_HINT_TARGET_PRIO /* Device Write and Host Read, or Host Write and Device Read - with temporal reuse */, 2530 MAX_PXP_TPH_ST_HINT 2531 }; 2532 2533 /* 2534 * QM hardware structure of enable bypass credit mask 2535 */ 2536 struct qm_rf_bypass_mask 2537 { 2538 u8 flags; 2539 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1 2540 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0 2541 #define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1 2542 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1 2543 #define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1 2544 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2 2545 #define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1 2546 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3 2547 #define QM_RF_BYPASS_MASK_PFRL_MASK 0x1 2548 #define QM_RF_BYPASS_MASK_PFRL_SHIFT 4 2549 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1 2550 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5 2551 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1 2552 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6 2553 #define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1 2554 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7 2555 }; 2556 2557 /* 2558 * QM hardware structure of opportunistic credit mask 2559 */ 2560 struct qm_rf_opportunistic_mask 2561 { 2562 __le16 flags; 2563 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1 2564 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0 2565 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1 2566 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1 2567 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1 2568 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2 2569 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1 2570 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3 2571 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1 2572 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4 2573 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1 2574 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5 2575 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1 2576 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6 2577 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1 2578 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7 2579 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1 2580 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8 2581 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F 2582 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9 2583 }; 2584 2585 /* 2586 * E4 QM hardware structure of QM map memory 2587 */ 2588 struct qm_rf_pq_map_e4 2589 { 2590 __le32 reg; 2591 #define QM_RF_PQ_MAP_E4_PQ_VALID_MASK 0x1 /* PQ active */ 2592 #define QM_RF_PQ_MAP_E4_PQ_VALID_SHIFT 0 2593 #define QM_RF_PQ_MAP_E4_RL_ID_MASK 0xFF /* RL ID */ 2594 #define QM_RF_PQ_MAP_E4_RL_ID_SHIFT 1 2595 #define QM_RF_PQ_MAP_E4_VP_PQ_ID_MASK 0x1FF /* the first PQ associated with the VPORT and VOQ of this PQ */ 2596 #define QM_RF_PQ_MAP_E4_VP_PQ_ID_SHIFT 9 2597 #define QM_RF_PQ_MAP_E4_VOQ_MASK 0x1F /* VOQ */ 2598 #define QM_RF_PQ_MAP_E4_VOQ_SHIFT 18 2599 #define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_MASK 0x3 /* WRR weight */ 2600 #define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_SHIFT 23 2601 #define QM_RF_PQ_MAP_E4_RL_VALID_MASK 0x1 /* RL active */ 2602 #define QM_RF_PQ_MAP_E4_RL_VALID_SHIFT 25 2603 #define QM_RF_PQ_MAP_E4_RESERVED_MASK 0x3F 2604 #define QM_RF_PQ_MAP_E4_RESERVED_SHIFT 26 2605 }; 2606 2607 /* 2608 * E5 QM hardware structure of QM map memory 2609 */ 2610 struct qm_rf_pq_map_e5 2611 { 2612 __le32 reg; 2613 #define QM_RF_PQ_MAP_E5_PQ_VALID_MASK 0x1 /* PQ active */ 2614 #define QM_RF_PQ_MAP_E5_PQ_VALID_SHIFT 0 2615 #define QM_RF_PQ_MAP_E5_RL_ID_MASK 0xFF /* RL ID */ 2616 #define QM_RF_PQ_MAP_E5_RL_ID_SHIFT 1 2617 #define QM_RF_PQ_MAP_E5_VP_PQ_ID_MASK 0x1FF /* the first PQ associated with the VPORT and VOQ of this PQ */ 2618 #define QM_RF_PQ_MAP_E5_VP_PQ_ID_SHIFT 9 2619 #define QM_RF_PQ_MAP_E5_VOQ_MASK 0x3F /* VOQ */ 2620 #define QM_RF_PQ_MAP_E5_VOQ_SHIFT 18 2621 #define QM_RF_PQ_MAP_E5_WRR_WEIGHT_GROUP_MASK 0x3 /* WRR weight */ 2622 #define QM_RF_PQ_MAP_E5_WRR_WEIGHT_GROUP_SHIFT 24 2623 #define QM_RF_PQ_MAP_E5_RL_VALID_MASK 0x1 /* RL active */ 2624 #define QM_RF_PQ_MAP_E5_RL_VALID_SHIFT 26 2625 #define QM_RF_PQ_MAP_E5_RESERVED_MASK 0x1F 2626 #define QM_RF_PQ_MAP_E5_RESERVED_SHIFT 27 2627 }; 2628 2629 /* 2630 * Completion params for aggregated interrupt completion 2631 */ 2632 struct sdm_agg_int_comp_params 2633 { 2634 __le16 params; 2635 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F /* the number of aggregated interrupt, 0-31 */ 2636 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0 2637 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1 /* 1 - set a bit in aggregated vector, 0 - dont set */ 2638 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6 2639 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF /* Number of bit in the aggregated vector, 0-279 (TBD) */ 2640 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7 2641 }; 2642 2643 /* 2644 * SDM operation gen command (generate aggregative interrupt) 2645 */ 2646 struct sdm_op_gen 2647 { 2648 __le32 command; 2649 #define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF /* completion parameters 0-15 */ 2650 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0 2651 #define SDM_OP_GEN_COMP_TYPE_MASK 0xF /* completion type 16-19 */ 2652 #define SDM_OP_GEN_COMP_TYPE_SHIFT 16 2653 #define SDM_OP_GEN_RESERVED_MASK 0xFFF /* reserved 20-31 */ 2654 #define SDM_OP_GEN_RESERVED_SHIFT 20 2655 }; 2656 2657 #endif /* __ECORE_HSI_COMMON__ */ 2658