1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __ECORE_HSI_DEBUG_TOOLS__ 32 #define __ECORE_HSI_DEBUG_TOOLS__ 33 /****************************************/ 34 /* Debug Tools HSI constants and macros */ 35 /****************************************/ 36 37 enum block_addr 38 { 39 GRCBASE_GRC = 0x50000, 40 GRCBASE_MISCS = 0x9000, 41 GRCBASE_MISC = 0x8000, 42 GRCBASE_DBU = 0xa000, 43 GRCBASE_PGLUE_B = 0x2a8000, 44 GRCBASE_CNIG = 0x218000, 45 GRCBASE_CPMU = 0x30000, 46 GRCBASE_NCSI = 0x40000, 47 GRCBASE_OPTE = 0x53000, 48 GRCBASE_BMB = 0x540000, 49 GRCBASE_PCIE = 0x54000, 50 GRCBASE_MCP = 0xe00000, 51 GRCBASE_MCP2 = 0x52000, 52 GRCBASE_PSWHST = 0x2a0000, 53 GRCBASE_PSWHST2 = 0x29e000, 54 GRCBASE_PSWRD = 0x29c000, 55 GRCBASE_PSWRD2 = 0x29d000, 56 GRCBASE_PSWWR = 0x29a000, 57 GRCBASE_PSWWR2 = 0x29b000, 58 GRCBASE_PSWRQ = 0x280000, 59 GRCBASE_PSWRQ2 = 0x240000, 60 GRCBASE_PGLCS = 0x0, 61 GRCBASE_DMAE = 0xc000, 62 GRCBASE_PTU = 0x560000, 63 GRCBASE_TCM = 0x1180000, 64 GRCBASE_MCM = 0x1200000, 65 GRCBASE_UCM = 0x1280000, 66 GRCBASE_XCM = 0x1000000, 67 GRCBASE_YCM = 0x1080000, 68 GRCBASE_PCM = 0x1100000, 69 GRCBASE_QM = 0x2f0000, 70 GRCBASE_TM = 0x2c0000, 71 GRCBASE_DORQ = 0x100000, 72 GRCBASE_BRB = 0x340000, 73 GRCBASE_SRC = 0x238000, 74 GRCBASE_PRS = 0x1f0000, 75 GRCBASE_TSDM = 0xfb0000, 76 GRCBASE_MSDM = 0xfc0000, 77 GRCBASE_USDM = 0xfd0000, 78 GRCBASE_XSDM = 0xf80000, 79 GRCBASE_YSDM = 0xf90000, 80 GRCBASE_PSDM = 0xfa0000, 81 GRCBASE_TSEM = 0x1700000, 82 GRCBASE_MSEM = 0x1800000, 83 GRCBASE_USEM = 0x1900000, 84 GRCBASE_XSEM = 0x1400000, 85 GRCBASE_YSEM = 0x1500000, 86 GRCBASE_PSEM = 0x1600000, 87 GRCBASE_RSS = 0x238800, 88 GRCBASE_TMLD = 0x4d0000, 89 GRCBASE_MULD = 0x4e0000, 90 GRCBASE_YULD = 0x4c8000, 91 GRCBASE_XYLD = 0x4c0000, 92 GRCBASE_PTLD = 0x5a0000, 93 GRCBASE_YPLD = 0x5c0000, 94 GRCBASE_PRM = 0x230000, 95 GRCBASE_PBF_PB1 = 0xda0000, 96 GRCBASE_PBF_PB2 = 0xda4000, 97 GRCBASE_RPB = 0x23c000, 98 GRCBASE_BTB = 0xdb0000, 99 GRCBASE_PBF = 0xd80000, 100 GRCBASE_RDIF = 0x300000, 101 GRCBASE_TDIF = 0x310000, 102 GRCBASE_CDU = 0x580000, 103 GRCBASE_CCFC = 0x2e0000, 104 GRCBASE_TCFC = 0x2d0000, 105 GRCBASE_IGU = 0x180000, 106 GRCBASE_CAU = 0x1c0000, 107 GRCBASE_RGFS = 0xf00000, 108 GRCBASE_RGSRC = 0x320000, 109 GRCBASE_TGFS = 0xd00000, 110 GRCBASE_TGSRC = 0x322000, 111 GRCBASE_UMAC = 0x51000, 112 GRCBASE_XMAC = 0x210000, 113 GRCBASE_DBG = 0x10000, 114 GRCBASE_NIG = 0x500000, 115 GRCBASE_WOL = 0x600000, 116 GRCBASE_BMBN = 0x610000, 117 GRCBASE_IPC = 0x20000, 118 GRCBASE_NWM = 0x800000, 119 GRCBASE_NWS = 0x700000, 120 GRCBASE_MS = 0x6a0000, 121 GRCBASE_PHY_PCIE = 0x620000, 122 GRCBASE_LED = 0x6b8000, 123 GRCBASE_AVS_WRAP = 0x6b0000, 124 GRCBASE_PXPREQBUS = 0x56000, 125 GRCBASE_MISC_AEU = 0x8000, 126 GRCBASE_BAR0_MAP = 0x1c00000, 127 MAX_BLOCK_ADDR 128 }; 129 130 enum block_id 131 { 132 BLOCK_GRC, 133 BLOCK_MISCS, 134 BLOCK_MISC, 135 BLOCK_DBU, 136 BLOCK_PGLUE_B, 137 BLOCK_CNIG, 138 BLOCK_CPMU, 139 BLOCK_NCSI, 140 BLOCK_OPTE, 141 BLOCK_BMB, 142 BLOCK_PCIE, 143 BLOCK_MCP, 144 BLOCK_MCP2, 145 BLOCK_PSWHST, 146 BLOCK_PSWHST2, 147 BLOCK_PSWRD, 148 BLOCK_PSWRD2, 149 BLOCK_PSWWR, 150 BLOCK_PSWWR2, 151 BLOCK_PSWRQ, 152 BLOCK_PSWRQ2, 153 BLOCK_PGLCS, 154 BLOCK_DMAE, 155 BLOCK_PTU, 156 BLOCK_TCM, 157 BLOCK_MCM, 158 BLOCK_UCM, 159 BLOCK_XCM, 160 BLOCK_YCM, 161 BLOCK_PCM, 162 BLOCK_QM, 163 BLOCK_TM, 164 BLOCK_DORQ, 165 BLOCK_BRB, 166 BLOCK_SRC, 167 BLOCK_PRS, 168 BLOCK_TSDM, 169 BLOCK_MSDM, 170 BLOCK_USDM, 171 BLOCK_XSDM, 172 BLOCK_YSDM, 173 BLOCK_PSDM, 174 BLOCK_TSEM, 175 BLOCK_MSEM, 176 BLOCK_USEM, 177 BLOCK_XSEM, 178 BLOCK_YSEM, 179 BLOCK_PSEM, 180 BLOCK_RSS, 181 BLOCK_TMLD, 182 BLOCK_MULD, 183 BLOCK_YULD, 184 BLOCK_XYLD, 185 BLOCK_PTLD, 186 BLOCK_YPLD, 187 BLOCK_PRM, 188 BLOCK_PBF_PB1, 189 BLOCK_PBF_PB2, 190 BLOCK_RPB, 191 BLOCK_BTB, 192 BLOCK_PBF, 193 BLOCK_RDIF, 194 BLOCK_TDIF, 195 BLOCK_CDU, 196 BLOCK_CCFC, 197 BLOCK_TCFC, 198 BLOCK_IGU, 199 BLOCK_CAU, 200 BLOCK_RGFS, 201 BLOCK_RGSRC, 202 BLOCK_TGFS, 203 BLOCK_TGSRC, 204 BLOCK_UMAC, 205 BLOCK_XMAC, 206 BLOCK_DBG, 207 BLOCK_NIG, 208 BLOCK_WOL, 209 BLOCK_BMBN, 210 BLOCK_IPC, 211 BLOCK_NWM, 212 BLOCK_NWS, 213 BLOCK_MS, 214 BLOCK_PHY_PCIE, 215 BLOCK_LED, 216 BLOCK_AVS_WRAP, 217 BLOCK_PXPREQBUS, 218 BLOCK_MISC_AEU, 219 BLOCK_BAR0_MAP, 220 MAX_BLOCK_ID 221 }; 222 223 /* 224 * binary debug buffer types 225 */ 226 enum bin_dbg_buffer_type 227 { 228 BIN_BUF_DBG_MODE_TREE /* init modes tree */, 229 BIN_BUF_DBG_DUMP_REG /* GRC Dump registers */, 230 BIN_BUF_DBG_DUMP_MEM /* GRC Dump memories */, 231 BIN_BUF_DBG_IDLE_CHK_REGS /* Idle Check registers */, 232 BIN_BUF_DBG_IDLE_CHK_IMMS /* Idle Check immediates */, 233 BIN_BUF_DBG_IDLE_CHK_RULES /* Idle Check rules */, 234 BIN_BUF_DBG_IDLE_CHK_PARSING_DATA /* Idle Check parsing data */, 235 BIN_BUF_DBG_ATTN_BLOCKS /* Attention blocks */, 236 BIN_BUF_DBG_ATTN_REGS /* Attention registers */, 237 BIN_BUF_DBG_ATTN_INDEXES /* Attention indexes */, 238 BIN_BUF_DBG_ATTN_NAME_OFFSETS /* Attention name offsets */, 239 BIN_BUF_DBG_BUS_BLOCKS /* Debug Bus blocks */, 240 BIN_BUF_DBG_BUS_LINES /* Debug Bus lines */, 241 BIN_BUF_DBG_BUS_BLOCKS_USER_DATA /* Debug Bus blocks user data */, 242 BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS /* Debug Bus line name offsets */, 243 BIN_BUF_DBG_PARSING_STRINGS /* Debug Tools parsing strings */, 244 MAX_BIN_DBG_BUFFER_TYPE 245 }; 246 247 /* 248 * Attention bit mapping 249 */ 250 struct dbg_attn_bit_mapping 251 { 252 u16 data; 253 #define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF /* The index of an attention in the blocks attentions list (if is_unused_bit_cnt=0), or a number of consecutive unused attention bits (if is_unused_bit_cnt=1) */ 254 #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0 255 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1 /* if set, the val field indicates the number of consecutive unused attention bits */ 256 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT 15 257 }; 258 259 /* 260 * Attention block per-type data 261 */ 262 struct dbg_attn_block_type_data 263 { 264 u16 names_offset /* Offset of this block attention names in the debug attention name offsets array */; 265 u16 reserved1; 266 u8 num_regs /* Number of attention registers in this block */; 267 u8 reserved2; 268 u16 regs_offset /* Offset of this blocks attention registers in the attention registers array (in dbg_attn_reg units) */; 269 }; 270 271 /* 272 * Block attentions 273 */ 274 struct dbg_attn_block 275 { 276 struct dbg_attn_block_type_data per_type_data[2] /* attention block per-type data. Count must match the number of elements in dbg_attn_type. */; 277 }; 278 279 /* 280 * Attention register result 281 */ 282 struct dbg_attn_reg_result 283 { 284 u32 data; 285 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF /* STS attention register GRC address (in dwords) */ 286 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0 287 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK 0xFF /* Number of attention indexes in this register */ 288 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT 24 289 u16 block_attn_offset /* The offset of this registers attentions within the blocks attentions list (a value in the range 0..number of block attentions-1) */; 290 u16 reserved; 291 u32 sts_val /* Value read from the STS attention register */; 292 u32 mask_val /* Value read from the MASK attention register */; 293 }; 294 295 /* 296 * Attention block result 297 */ 298 struct dbg_attn_block_result 299 { 300 u8 block_id /* Registers block ID */; 301 u8 data; 302 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK 0x3 /* Value from dbg_attn_type enum */ 303 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0 304 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F /* Number of registers in the block in which at least one attention bit is set */ 305 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT 2 306 u16 names_offset /* Offset of this registers block attention names in the attention name offsets array */; 307 struct dbg_attn_reg_result reg_results[15] /* result data for each register in the block in which at least one attention bit is set */; 308 }; 309 310 /* 311 * mode header 312 */ 313 struct dbg_mode_hdr 314 { 315 u16 data; 316 #define DBG_MODE_HDR_EVAL_MODE_MASK 0x1 /* indicates if a mode expression should be evaluated (0/1) */ 317 #define DBG_MODE_HDR_EVAL_MODE_SHIFT 0 318 #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF /* offset (in bytes) in modes expression buffer. valid only if eval_mode is set. */ 319 #define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1 320 }; 321 322 /* 323 * Attention register 324 */ 325 struct dbg_attn_reg 326 { 327 struct dbg_mode_hdr mode /* Mode header */; 328 u16 block_attn_offset /* The offset of this registers attentions within the blocks attentions list (a value in the range 0..number of block attentions-1) */; 329 u32 data; 330 #define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF /* STS attention register GRC address (in dwords) */ 331 #define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0 332 #define DBG_ATTN_REG_NUM_REG_ATTN_MASK 0xFF /* Number of attention in this register */ 333 #define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24 334 u32 sts_clr_address /* STS_CLR attention register GRC address (in dwords) */; 335 u32 mask_address /* MASK attention register GRC address (in dwords) */; 336 }; 337 338 /* 339 * attention types 340 */ 341 enum dbg_attn_type 342 { 343 ATTN_TYPE_INTERRUPT, 344 ATTN_TYPE_PARITY, 345 MAX_DBG_ATTN_TYPE 346 }; 347 348 /* 349 * Debug Bus block data 350 */ 351 struct dbg_bus_block 352 { 353 u8 num_of_lines /* Number of debug lines in this block (excluding signature and latency events). */; 354 u8 has_latency_events /* Indicates if this block has a latency events debug line (0/1). */; 355 u16 lines_offset /* Offset of this blocks lines in the Debug Bus lines array. */; 356 }; 357 358 /* 359 * Debug Bus block user data 360 */ 361 struct dbg_bus_block_user_data 362 { 363 u8 num_of_lines /* Number of debug lines in this block (excluding signature and latency events). */; 364 u8 has_latency_events /* Indicates if this block has a latency events debug line (0/1). */; 365 u16 names_offset /* Offset of this blocks lines in the debug bus line name offsets array. */; 366 }; 367 368 /* 369 * Block Debug line data 370 */ 371 struct dbg_bus_line 372 { 373 u8 data; 374 #define DBG_BUS_LINE_NUM_OF_GROUPS_MASK 0xF /* Number of groups in the line (0-3) */ 375 #define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT 0 376 #define DBG_BUS_LINE_IS_256B_MASK 0x1 /* Indicates if this is a 128b line (0) or a 256b line (1). */ 377 #define DBG_BUS_LINE_IS_256B_SHIFT 4 378 #define DBG_BUS_LINE_RESERVED_MASK 0x7 379 #define DBG_BUS_LINE_RESERVED_SHIFT 5 380 u8 group_sizes /* Four 2-bit values, indicating the size of each group minus 1 (i.e. value=0 means size=1, value=1 means size=2, etc), starting from lsb. The sizes are in dwords (if is_256b=0) or in qwords (if is_256b=1). */; 381 }; 382 383 /* 384 * condition header for registers dump 385 */ 386 struct dbg_dump_cond_hdr 387 { 388 struct dbg_mode_hdr mode /* Mode header */; 389 u8 block_id /* block ID */; 390 u8 data_size /* size in dwords of the data following this header */; 391 }; 392 393 /* 394 * memory data for registers dump 395 */ 396 struct dbg_dump_mem 397 { 398 u32 dword0; 399 #define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF /* register address (in dwords) */ 400 #define DBG_DUMP_MEM_ADDRESS_SHIFT 0 401 #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF /* memory group ID */ 402 #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24 403 u32 dword1; 404 #define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF /* register size (in dwords) */ 405 #define DBG_DUMP_MEM_LENGTH_SHIFT 0 406 #define DBG_DUMP_MEM_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 407 #define DBG_DUMP_MEM_WIDE_BUS_SHIFT 24 408 #define DBG_DUMP_MEM_RESERVED_MASK 0x7F 409 #define DBG_DUMP_MEM_RESERVED_SHIFT 25 410 }; 411 412 /* 413 * register data for registers dump 414 */ 415 struct dbg_dump_reg 416 { 417 u32 data; 418 #define DBG_DUMP_REG_ADDRESS_MASK 0x7FFFFF /* register address (in dwords) */ 419 #define DBG_DUMP_REG_ADDRESS_SHIFT 0 420 #define DBG_DUMP_REG_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 421 #define DBG_DUMP_REG_WIDE_BUS_SHIFT 23 422 #define DBG_DUMP_REG_LENGTH_MASK 0xFF /* register size (in dwords) */ 423 #define DBG_DUMP_REG_LENGTH_SHIFT 24 424 }; 425 426 /* 427 * split header for registers dump 428 */ 429 struct dbg_dump_split_hdr 430 { 431 u32 hdr; 432 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF /* size in dwords of the data following this header */ 433 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0 434 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF /* split type ID */ 435 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24 436 }; 437 438 /* 439 * condition header for idle check 440 */ 441 struct dbg_idle_chk_cond_hdr 442 { 443 struct dbg_mode_hdr mode /* Mode header */; 444 u16 data_size /* size in dwords of the data following this header */; 445 }; 446 447 /* 448 * Idle Check condition register 449 */ 450 struct dbg_idle_chk_cond_reg 451 { 452 u32 data; 453 #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0x7FFFFF /* Register GRC address (in dwords) */ 454 #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0 455 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 456 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT 23 457 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF /* value from block_id enum */ 458 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24 459 u16 num_entries /* number of registers entries to check */; 460 u8 entry_size /* size of registers entry (in dwords) */; 461 u8 start_entry /* index of the first entry to check */; 462 }; 463 464 /* 465 * Idle Check info register 466 */ 467 struct dbg_idle_chk_info_reg 468 { 469 u32 data; 470 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0x7FFFFF /* Register GRC address (in dwords) */ 471 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0 472 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 473 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT 23 474 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF /* value from block_id enum */ 475 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24 476 u16 size /* register size in dwords */; 477 struct dbg_mode_hdr mode /* Mode header */; 478 }; 479 480 /* 481 * Idle Check register 482 */ 483 union dbg_idle_chk_reg 484 { 485 struct dbg_idle_chk_cond_reg cond_reg /* condition register */; 486 struct dbg_idle_chk_info_reg info_reg /* info register */; 487 }; 488 489 /* 490 * Idle Check result header 491 */ 492 struct dbg_idle_chk_result_hdr 493 { 494 u16 rule_id /* Failing rule index */; 495 u16 mem_entry_id /* Failing memory entry index */; 496 u8 num_dumped_cond_regs /* number of dumped condition registers */; 497 u8 num_dumped_info_regs /* number of dumped condition registers */; 498 u8 severity /* from dbg_idle_chk_severity_types enum */; 499 u8 reserved; 500 }; 501 502 /* 503 * Idle Check result register header 504 */ 505 struct dbg_idle_chk_result_reg_hdr 506 { 507 u8 data; 508 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK 0x1 /* indicates if this register is a memory */ 509 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0 510 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F /* register index within the failing rule */ 511 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1 512 u8 start_entry /* index of the first checked entry */; 513 u16 size /* register size in dwords */; 514 }; 515 516 /* 517 * Idle Check rule 518 */ 519 struct dbg_idle_chk_rule 520 { 521 u16 rule_id /* Idle Check rule ID */; 522 u8 severity /* value from dbg_idle_chk_severity_types enum */; 523 u8 cond_id /* Condition ID */; 524 u8 num_cond_regs /* number of condition registers */; 525 u8 num_info_regs /* number of info registers */; 526 u8 num_imms /* number of immediates in the condition */; 527 u8 reserved1; 528 u16 reg_offset /* offset of this rules registers in the idle check register array (in dbg_idle_chk_reg units) */; 529 u16 imm_offset /* offset of this rules immediate values in the immediate values array (in dwords) */; 530 }; 531 532 /* 533 * Idle Check rule parsing data 534 */ 535 struct dbg_idle_chk_rule_parsing_data 536 { 537 u32 data; 538 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1 /* indicates if this register has a FW message */ 539 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0 540 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF /* Offset of this rules strings in the debug strings array (in bytes) */ 541 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1 542 }; 543 544 /* 545 * idle check severity types 546 */ 547 enum dbg_idle_chk_severity_types 548 { 549 IDLE_CHK_SEVERITY_ERROR /* idle check failure should cause an error */, 550 IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC /* idle check failure should cause an error only if theres no traffic */, 551 IDLE_CHK_SEVERITY_WARNING /* idle check failure should cause a warning */, 552 MAX_DBG_IDLE_CHK_SEVERITY_TYPES 553 }; 554 555 /* 556 * Debug Bus block data 557 */ 558 struct dbg_bus_block_data 559 { 560 u16 data; 561 #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_MASK 0xF /* 4-bit value: bit i set -> dword/qword i is enabled. */ 562 #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_SHIFT 0 563 #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_MASK 0xF /* Number of dwords/qwords to shift right the debug data (0-3) */ 564 #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_SHIFT 4 565 #define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_MASK 0xF /* 4-bit value: bit i set -> dword/qword i is forced valid. */ 566 #define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_SHIFT 8 567 #define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_MASK 0xF /* 4-bit value: bit i set -> dword/qword i frame bit is forced. */ 568 #define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_SHIFT 12 569 u8 line_num /* Debug line number to select */; 570 u8 hw_id /* HW ID associated with the block */; 571 }; 572 573 /* 574 * Debug Bus Clients 575 */ 576 enum dbg_bus_clients 577 { 578 DBG_BUS_CLIENT_RBCN, 579 DBG_BUS_CLIENT_RBCP, 580 DBG_BUS_CLIENT_RBCR, 581 DBG_BUS_CLIENT_RBCT, 582 DBG_BUS_CLIENT_RBCU, 583 DBG_BUS_CLIENT_RBCF, 584 DBG_BUS_CLIENT_RBCX, 585 DBG_BUS_CLIENT_RBCS, 586 DBG_BUS_CLIENT_RBCH, 587 DBG_BUS_CLIENT_RBCZ, 588 DBG_BUS_CLIENT_OTHER_ENGINE, 589 DBG_BUS_CLIENT_TIMESTAMP, 590 DBG_BUS_CLIENT_CPU, 591 DBG_BUS_CLIENT_RBCY, 592 DBG_BUS_CLIENT_RBCQ, 593 DBG_BUS_CLIENT_RBCM, 594 DBG_BUS_CLIENT_RBCB, 595 DBG_BUS_CLIENT_RBCW, 596 DBG_BUS_CLIENT_RBCV, 597 MAX_DBG_BUS_CLIENTS 598 }; 599 600 /* 601 * Debug Bus constraint operation types 602 */ 603 enum dbg_bus_constraint_ops 604 { 605 DBG_BUS_CONSTRAINT_OP_EQ /* equal */, 606 DBG_BUS_CONSTRAINT_OP_NE /* not equal */, 607 DBG_BUS_CONSTRAINT_OP_LT /* less than */, 608 DBG_BUS_CONSTRAINT_OP_LTC /* less than (cyclic) */, 609 DBG_BUS_CONSTRAINT_OP_LE /* less than or equal */, 610 DBG_BUS_CONSTRAINT_OP_LEC /* less than or equal (cyclic) */, 611 DBG_BUS_CONSTRAINT_OP_GT /* greater than */, 612 DBG_BUS_CONSTRAINT_OP_GTC /* greater than (cyclic) */, 613 DBG_BUS_CONSTRAINT_OP_GE /* greater than or equal */, 614 DBG_BUS_CONSTRAINT_OP_GEC /* greater than or equal (cyclic) */, 615 MAX_DBG_BUS_CONSTRAINT_OPS 616 }; 617 618 /* 619 * Debug Bus trigger state data 620 */ 621 struct dbg_bus_trigger_state_data 622 { 623 u8 data; 624 #define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_MASK 0xF /* 4-bit value: bit i set -> dword i of the trigger state block (after right shift) is enabled. */ 625 #define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_SHIFT 0 626 #define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_MASK 0xF /* 4-bit value: bit i set -> dword i is compared by a constraint */ 627 #define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_SHIFT 4 628 }; 629 630 /* 631 * Debug Bus memory address 632 */ 633 struct dbg_bus_mem_addr 634 { 635 u32 lo; 636 u32 hi; 637 }; 638 639 /* 640 * Debug Bus PCI buffer data 641 */ 642 struct dbg_bus_pci_buf_data 643 { 644 struct dbg_bus_mem_addr phys_addr /* PCI buffer physical address */; 645 struct dbg_bus_mem_addr virt_addr /* PCI buffer virtual address */; 646 u32 size /* PCI buffer size in bytes */; 647 }; 648 649 /* 650 * Debug Bus Storm EID range filter params 651 */ 652 struct dbg_bus_storm_eid_range_params 653 { 654 u8 min /* Minimal event ID to filter on */; 655 u8 max /* Maximal event ID to filter on */; 656 }; 657 658 /* 659 * Debug Bus Storm EID mask filter params 660 */ 661 struct dbg_bus_storm_eid_mask_params 662 { 663 u8 val /* Event ID value */; 664 u8 mask /* Event ID mask. 1s in the mask = dont care bits. */; 665 }; 666 667 /* 668 * Debug Bus Storm EID filter params 669 */ 670 union dbg_bus_storm_eid_params 671 { 672 struct dbg_bus_storm_eid_range_params range /* EID range filter params */; 673 struct dbg_bus_storm_eid_mask_params mask /* EID mask filter params */; 674 }; 675 676 /* 677 * Debug Bus Storm data 678 */ 679 struct dbg_bus_storm_data 680 { 681 u8 enabled /* indicates if the Storm is enabled for recording */; 682 u8 mode /* Storm debug mode, valid only if the Storm is enabled (use enum dbg_bus_storm_modes) */; 683 u8 hw_id /* HW ID associated with the Storm */; 684 u8 eid_filter_en /* Indicates if EID filtering is performed (0/1) */; 685 u8 eid_range_not_mask /* 1 = EID range filter, 0 = EID mask filter. Valid only if eid_filter_en is set, */; 686 u8 cid_filter_en /* Indicates if CID filtering is performed (0/1) */; 687 union dbg_bus_storm_eid_params eid_filter_params /* EID filter params to filter on. Valid only if eid_filter_en is set. */; 688 u32 cid /* CID to filter on. Valid only if cid_filter_en is set. */; 689 }; 690 691 /* 692 * Debug Bus data 693 */ 694 struct dbg_bus_data 695 { 696 u32 app_version /* The tools version number of the application */; 697 u8 state /* The current debug bus state (use enum dbg_bus_states) */; 698 u8 hw_dwords /* HW dwords per cycle */; 699 u16 hw_id_mask /* The HW IDs of the recorded HW blocks, where bits i*3..i*3+2 contain the HW ID of dword/qword i */; 700 u8 num_enabled_blocks /* Number of blocks enabled for recording */; 701 u8 num_enabled_storms /* Number of Storms enabled for recording */; 702 u8 target /* Output target (use enum dbg_bus_targets) */; 703 u8 one_shot_en /* Indicates if one-shot mode is enabled (0/1) */; 704 u8 grc_input_en /* Indicates if GRC recording is enabled (0/1) */; 705 u8 timestamp_input_en /* Indicates if timestamp recording is enabled (0/1) */; 706 u8 filter_en /* Indicates if the recording filter is enabled (0/1) */; 707 u8 adding_filter /* If true, the next added constraint belong to the filter. Otherwise, it belongs to the last added trigger state. Valid only if either filter or triggers are enabled. */; 708 u8 filter_pre_trigger /* Indicates if the recording filter should be applied before the trigger. Valid only if both filter and trigger are enabled (0/1) */; 709 u8 filter_post_trigger /* Indicates if the recording filter should be applied after the trigger. Valid only if both filter and trigger are enabled (0/1) */; 710 u16 reserved; 711 u8 trigger_en /* Indicates if the recording trigger is enabled (0/1) */; 712 struct dbg_bus_trigger_state_data trigger_states[3] /* trigger states data */; 713 u8 next_trigger_state /* ID of next trigger state to be added */; 714 u8 next_constraint_id /* ID of next filter/trigger constraint to be added */; 715 u8 unify_inputs /* If true, all inputs are associated with HW ID 0. Otherwise, each input is assigned a different HW ID (0/1) */; 716 u8 rcv_from_other_engine /* Indicates if the other engine sends it NW recording to this engine (0/1) */; 717 struct dbg_bus_pci_buf_data pci_buf /* Debug Bus PCI buffer data. Valid only when the target is DBG_BUS_TARGET_ID_PCI. */; 718 struct dbg_bus_block_data blocks[88] /* Debug Bus data for each block */; 719 struct dbg_bus_storm_data storms[6] /* Debug Bus data for each block */; 720 }; 721 722 /* 723 * Debug bus filter types 724 */ 725 enum dbg_bus_filter_types 726 { 727 DBG_BUS_FILTER_TYPE_OFF /* filter always off */, 728 DBG_BUS_FILTER_TYPE_PRE /* filter before trigger only */, 729 DBG_BUS_FILTER_TYPE_POST /* filter after trigger only */, 730 DBG_BUS_FILTER_TYPE_ON /* filter always on */, 731 MAX_DBG_BUS_FILTER_TYPES 732 }; 733 734 /* 735 * Debug bus frame modes 736 */ 737 enum dbg_bus_frame_modes 738 { 739 DBG_BUS_FRAME_MODE_0HW_4ST=0 /* 0 HW dwords, 4 Storm dwords */, 740 DBG_BUS_FRAME_MODE_4HW_0ST=3 /* 4 HW dwords, 0 Storm dwords */, 741 DBG_BUS_FRAME_MODE_8HW_0ST=4 /* 8 HW dwords, 0 Storm dwords */, 742 MAX_DBG_BUS_FRAME_MODES 743 }; 744 745 /* 746 * Debug bus other engine mode 747 */ 748 enum dbg_bus_other_engine_modes 749 { 750 DBG_BUS_OTHER_ENGINE_MODE_NONE, 751 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX, 752 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX, 753 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX, 754 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX, 755 MAX_DBG_BUS_OTHER_ENGINE_MODES 756 }; 757 758 /* 759 * Debug bus post-trigger recording types 760 */ 761 enum dbg_bus_post_trigger_types 762 { 763 DBG_BUS_POST_TRIGGER_RECORD /* start recording after trigger */, 764 DBG_BUS_POST_TRIGGER_DROP /* drop data after trigger */, 765 MAX_DBG_BUS_POST_TRIGGER_TYPES 766 }; 767 768 /* 769 * Debug bus pre-trigger recording types 770 */ 771 enum dbg_bus_pre_trigger_types 772 { 773 DBG_BUS_PRE_TRIGGER_START_FROM_ZERO /* start recording from time 0 */, 774 DBG_BUS_PRE_TRIGGER_NUM_CHUNKS /* start recording some chunks before trigger */, 775 DBG_BUS_PRE_TRIGGER_DROP /* drop data before trigger */, 776 MAX_DBG_BUS_PRE_TRIGGER_TYPES 777 }; 778 779 /* 780 * Debug bus SEMI frame modes 781 */ 782 enum dbg_bus_semi_frame_modes 783 { 784 DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST=0 /* 0 slow dwords, 4 fast dwords */, 785 DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST=3 /* 4 slow dwords, 0 fast dwords */, 786 MAX_DBG_BUS_SEMI_FRAME_MODES 787 }; 788 789 /* 790 * Debug bus states 791 */ 792 enum dbg_bus_states 793 { 794 DBG_BUS_STATE_IDLE /* debug bus idle state (not recording) */, 795 DBG_BUS_STATE_READY /* debug bus is ready for configuration and recording */, 796 DBG_BUS_STATE_RECORDING /* debug bus is currently recording */, 797 DBG_BUS_STATE_STOPPED /* debug bus recording has stopped */, 798 MAX_DBG_BUS_STATES 799 }; 800 801 /* 802 * Debug Bus Storm modes 803 */ 804 enum dbg_bus_storm_modes 805 { 806 DBG_BUS_STORM_MODE_PRINTF /* store data (fast debug) */, 807 DBG_BUS_STORM_MODE_PRAM_ADDR /* pram address (fast debug) */, 808 DBG_BUS_STORM_MODE_DRA_RW /* DRA read/write data (fast debug) */, 809 DBG_BUS_STORM_MODE_DRA_W /* DRA write data (fast debug) */, 810 DBG_BUS_STORM_MODE_LD_ST_ADDR /* load/store address (fast debug) */, 811 DBG_BUS_STORM_MODE_DRA_FSM /* DRA state machines (fast debug) */, 812 DBG_BUS_STORM_MODE_RH /* recording handlers (fast debug) */, 813 DBG_BUS_STORM_MODE_FOC /* FOC: FIN + DRA Rd (slow debug) */, 814 DBG_BUS_STORM_MODE_EXT_STORE /* FOC: External Store (slow) */, 815 MAX_DBG_BUS_STORM_MODES 816 }; 817 818 /* 819 * Debug bus target IDs 820 */ 821 enum dbg_bus_targets 822 { 823 DBG_BUS_TARGET_ID_INT_BUF /* records debug bus to DBG block internal buffer */, 824 DBG_BUS_TARGET_ID_NIG /* records debug bus to the NW */, 825 DBG_BUS_TARGET_ID_PCI /* records debug bus to a PCI buffer */, 826 MAX_DBG_BUS_TARGETS 827 }; 828 829 /* 830 * GRC Dump data 831 */ 832 struct dbg_grc_data 833 { 834 u8 params_initialized /* Indicates if the GRC parameters were initialized */; 835 u8 reserved1; 836 u16 reserved2; 837 u32 param_val[48] /* Value of each GRC parameter. Array size must match the enum dbg_grc_params. */; 838 }; 839 840 /* 841 * Debug GRC params 842 */ 843 enum dbg_grc_params 844 { 845 DBG_GRC_PARAM_DUMP_TSTORM /* dump Tstorm memories (0/1) */, 846 DBG_GRC_PARAM_DUMP_MSTORM /* dump Mstorm memories (0/1) */, 847 DBG_GRC_PARAM_DUMP_USTORM /* dump Ustorm memories (0/1) */, 848 DBG_GRC_PARAM_DUMP_XSTORM /* dump Xstorm memories (0/1) */, 849 DBG_GRC_PARAM_DUMP_YSTORM /* dump Ystorm memories (0/1) */, 850 DBG_GRC_PARAM_DUMP_PSTORM /* dump Pstorm memories (0/1) */, 851 DBG_GRC_PARAM_DUMP_REGS /* dump non-memory registers (0/1) */, 852 DBG_GRC_PARAM_DUMP_RAM /* dump Storm internal RAMs (0/1) */, 853 DBG_GRC_PARAM_DUMP_PBUF /* dump Storm passive buffer (0/1) */, 854 DBG_GRC_PARAM_DUMP_IOR /* dump Storm IORs (0/1) */, 855 DBG_GRC_PARAM_DUMP_VFC /* dump VFC memories (0/1) */, 856 DBG_GRC_PARAM_DUMP_CM_CTX /* dump CM contexts (0/1) */, 857 DBG_GRC_PARAM_DUMP_PXP /* dump PXP memories (0/1) */, 858 DBG_GRC_PARAM_DUMP_RSS /* dump RSS memories (0/1) */, 859 DBG_GRC_PARAM_DUMP_CAU /* dump CAU memories (0/1) */, 860 DBG_GRC_PARAM_DUMP_QM /* dump QM memories (0/1) */, 861 DBG_GRC_PARAM_DUMP_MCP /* dump MCP memories (0/1) */, 862 DBG_GRC_PARAM_RESERVED /* reserved */, 863 DBG_GRC_PARAM_DUMP_CFC /* dump CFC memories (0/1) */, 864 DBG_GRC_PARAM_DUMP_IGU /* dump IGU memories (0/1) */, 865 DBG_GRC_PARAM_DUMP_BRB /* dump BRB memories (0/1) */, 866 DBG_GRC_PARAM_DUMP_BTB /* dump BTB memories (0/1) */, 867 DBG_GRC_PARAM_DUMP_BMB /* dump BMB memories (0/1) */, 868 DBG_GRC_PARAM_DUMP_NIG /* dump NIG memories (0/1) */, 869 DBG_GRC_PARAM_DUMP_MULD /* dump MULD memories (0/1) */, 870 DBG_GRC_PARAM_DUMP_PRS /* dump PRS memories (0/1) */, 871 DBG_GRC_PARAM_DUMP_DMAE /* dump PRS memories (0/1) */, 872 DBG_GRC_PARAM_DUMP_TM /* dump TM (timers) memories (0/1) */, 873 DBG_GRC_PARAM_DUMP_SDM /* dump SDM memories (0/1) */, 874 DBG_GRC_PARAM_DUMP_DIF /* dump DIF memories (0/1) */, 875 DBG_GRC_PARAM_DUMP_STATIC /* dump static debug data (0/1) */, 876 DBG_GRC_PARAM_UNSTALL /* un-stall Storms after dump (0/1) */, 877 DBG_GRC_PARAM_NUM_LCIDS /* number of LCIDs (0..320) */, 878 DBG_GRC_PARAM_NUM_LTIDS /* number of LTIDs (0..320) */, 879 DBG_GRC_PARAM_EXCLUDE_ALL /* preset: exclude all memories from dump (1 only) */, 880 DBG_GRC_PARAM_CRASH /* preset: include memories for crash dump (1 only) */, 881 DBG_GRC_PARAM_PARITY_SAFE /* perform dump only if MFW is responding (0/1) */, 882 DBG_GRC_PARAM_DUMP_CM /* dump CM memories (0/1) */, 883 DBG_GRC_PARAM_DUMP_PHY /* dump PHY memories (0/1) */, 884 DBG_GRC_PARAM_NO_MCP /* dont perform MCP commands (0/1) */, 885 DBG_GRC_PARAM_NO_FW_VER /* dont read FW/MFW version (0/1) */, 886 MAX_DBG_GRC_PARAMS 887 }; 888 889 /* 890 * Debug reset registers 891 */ 892 enum dbg_reset_regs 893 { 894 DBG_RESET_REG_MISCS_PL_UA, 895 DBG_RESET_REG_MISCS_PL_HV, 896 DBG_RESET_REG_MISCS_PL_HV_2, 897 DBG_RESET_REG_MISC_PL_UA, 898 DBG_RESET_REG_MISC_PL_HV, 899 DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 900 DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 901 DBG_RESET_REG_MISC_PL_PDA_VAUX, 902 MAX_DBG_RESET_REGS 903 }; 904 905 /* 906 * Debug status codes 907 */ 908 enum dbg_status 909 { 910 DBG_STATUS_OK, 911 DBG_STATUS_APP_VERSION_NOT_SET, 912 DBG_STATUS_UNSUPPORTED_APP_VERSION, 913 DBG_STATUS_DBG_BLOCK_NOT_RESET, 914 DBG_STATUS_INVALID_ARGS, 915 DBG_STATUS_OUTPUT_ALREADY_SET, 916 DBG_STATUS_INVALID_PCI_BUF_SIZE, 917 DBG_STATUS_PCI_BUF_ALLOC_FAILED, 918 DBG_STATUS_PCI_BUF_NOT_ALLOCATED, 919 DBG_STATUS_TOO_MANY_INPUTS, 920 DBG_STATUS_INPUT_OVERLAP, 921 DBG_STATUS_HW_ONLY_RECORDING, 922 DBG_STATUS_STORM_ALREADY_ENABLED, 923 DBG_STATUS_STORM_NOT_ENABLED, 924 DBG_STATUS_BLOCK_ALREADY_ENABLED, 925 DBG_STATUS_BLOCK_NOT_ENABLED, 926 DBG_STATUS_NO_INPUT_ENABLED, 927 DBG_STATUS_NO_FILTER_TRIGGER_64B, 928 DBG_STATUS_FILTER_ALREADY_ENABLED, 929 DBG_STATUS_TRIGGER_ALREADY_ENABLED, 930 DBG_STATUS_TRIGGER_NOT_ENABLED, 931 DBG_STATUS_CANT_ADD_CONSTRAINT, 932 DBG_STATUS_TOO_MANY_TRIGGER_STATES, 933 DBG_STATUS_TOO_MANY_CONSTRAINTS, 934 DBG_STATUS_RECORDING_NOT_STARTED, 935 DBG_STATUS_DATA_DIDNT_TRIGGER, 936 DBG_STATUS_NO_DATA_RECORDED, 937 DBG_STATUS_DUMP_BUF_TOO_SMALL, 938 DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED, 939 DBG_STATUS_UNKNOWN_CHIP, 940 DBG_STATUS_VIRT_MEM_ALLOC_FAILED, 941 DBG_STATUS_BLOCK_IN_RESET, 942 DBG_STATUS_INVALID_TRACE_SIGNATURE, 943 DBG_STATUS_INVALID_NVRAM_BUNDLE, 944 DBG_STATUS_NVRAM_GET_IMAGE_FAILED, 945 DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE, 946 DBG_STATUS_NVRAM_READ_FAILED, 947 DBG_STATUS_IDLE_CHK_PARSE_FAILED, 948 DBG_STATUS_MCP_TRACE_BAD_DATA, 949 DBG_STATUS_MCP_TRACE_NO_META, 950 DBG_STATUS_MCP_COULD_NOT_HALT, 951 DBG_STATUS_MCP_COULD_NOT_RESUME, 952 DBG_STATUS_RESERVED2, 953 DBG_STATUS_SEMI_FIFO_NOT_EMPTY, 954 DBG_STATUS_IGU_FIFO_BAD_DATA, 955 DBG_STATUS_MCP_COULD_NOT_MASK_PRTY, 956 DBG_STATUS_FW_ASSERTS_PARSE_FAILED, 957 DBG_STATUS_REG_FIFO_BAD_DATA, 958 DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA, 959 DBG_STATUS_DBG_ARRAY_NOT_SET, 960 DBG_STATUS_FILTER_BUG, 961 DBG_STATUS_NON_MATCHING_LINES, 962 DBG_STATUS_INVALID_TRIGGER_DWORD_OFFSET, 963 DBG_STATUS_DBG_BUS_IN_USE, 964 MAX_DBG_STATUS 965 }; 966 967 /* 968 * Debug Storms IDs 969 */ 970 enum dbg_storms 971 { 972 DBG_TSTORM_ID, 973 DBG_MSTORM_ID, 974 DBG_USTORM_ID, 975 DBG_XSTORM_ID, 976 DBG_YSTORM_ID, 977 DBG_PSTORM_ID, 978 MAX_DBG_STORMS 979 }; 980 981 /* 982 * Idle Check data 983 */ 984 struct idle_chk_data 985 { 986 u32 buf_size /* Idle check buffer size in dwords */; 987 u8 buf_size_set /* Indicates if the idle check buffer size was set (0/1) */; 988 u8 reserved1; 989 u16 reserved2; 990 }; 991 992 /* 993 * Debug Tools data (per HW function) 994 */ 995 struct dbg_tools_data 996 { 997 struct dbg_grc_data grc /* GRC Dump data */; 998 struct dbg_bus_data bus /* Debug Bus data */; 999 struct idle_chk_data idle_chk /* Idle Check data */; 1000 u8 mode_enable[40] /* Indicates if a mode is enabled (0/1) */; 1001 u8 block_in_reset[88] /* Indicates if a block is in reset state (0/1) */; 1002 u8 chip_id /* Chip ID (from enum chip_ids) */; 1003 u8 platform_id /* Platform ID */; 1004 u8 initialized /* Indicates if the data was initialized */; 1005 u8 use_dmae /* Indicates if DMAE should be used */; 1006 u32 num_regs_read /* Numbers of registers that were read since last log */; 1007 }; 1008 1009 #endif /* __ECORE_HSI_DEBUG_TOOLS__ */ 1010