1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __ECORE_HSI_DEBUG_TOOLS__ 32 #define __ECORE_HSI_DEBUG_TOOLS__ 33 /****************************************/ 34 /* Debug Tools HSI constants and macros */ 35 /****************************************/ 36 37 38 enum block_addr 39 { 40 GRCBASE_GRC = 0x50000, 41 GRCBASE_MISCS = 0x9000, 42 GRCBASE_MISC = 0x8000, 43 GRCBASE_DBU = 0xa000, 44 GRCBASE_PGLUE_B = 0x2a8000, 45 GRCBASE_CNIG = 0x218000, 46 GRCBASE_CPMU = 0x30000, 47 GRCBASE_NCSI = 0x40000, 48 GRCBASE_OPTE = 0x53000, 49 GRCBASE_BMB = 0x540000, 50 GRCBASE_PCIE = 0x54000, 51 GRCBASE_MCP = 0xe00000, 52 GRCBASE_MCP2 = 0x52000, 53 GRCBASE_PSWHST = 0x2a0000, 54 GRCBASE_PSWHST2 = 0x29e000, 55 GRCBASE_PSWRD = 0x29c000, 56 GRCBASE_PSWRD2 = 0x29d000, 57 GRCBASE_PSWWR = 0x29a000, 58 GRCBASE_PSWWR2 = 0x29b000, 59 GRCBASE_PSWRQ = 0x280000, 60 GRCBASE_PSWRQ2 = 0x240000, 61 GRCBASE_PGLCS = 0x0, 62 GRCBASE_DMAE = 0xc000, 63 GRCBASE_PTU = 0x560000, 64 GRCBASE_TCM = 0x1180000, 65 GRCBASE_MCM = 0x1200000, 66 GRCBASE_UCM = 0x1280000, 67 GRCBASE_XCM = 0x1000000, 68 GRCBASE_YCM = 0x1080000, 69 GRCBASE_PCM = 0x1100000, 70 GRCBASE_QM = 0x2f0000, 71 GRCBASE_TM = 0x2c0000, 72 GRCBASE_DORQ = 0x100000, 73 GRCBASE_BRB = 0x340000, 74 GRCBASE_SRC = 0x238000, 75 GRCBASE_PRS = 0x1f0000, 76 GRCBASE_TSDM = 0xfb0000, 77 GRCBASE_MSDM = 0xfc0000, 78 GRCBASE_USDM = 0xfd0000, 79 GRCBASE_XSDM = 0xf80000, 80 GRCBASE_YSDM = 0xf90000, 81 GRCBASE_PSDM = 0xfa0000, 82 GRCBASE_TSEM = 0x1700000, 83 GRCBASE_MSEM = 0x1800000, 84 GRCBASE_USEM = 0x1900000, 85 GRCBASE_XSEM = 0x1400000, 86 GRCBASE_YSEM = 0x1500000, 87 GRCBASE_PSEM = 0x1600000, 88 GRCBASE_RSS = 0x238800, 89 GRCBASE_TMLD = 0x4d0000, 90 GRCBASE_MULD = 0x4e0000, 91 GRCBASE_YULD = 0x4c8000, 92 GRCBASE_XYLD = 0x4c0000, 93 GRCBASE_PTLD = 0x5a0000, 94 GRCBASE_YPLD = 0x5c0000, 95 GRCBASE_PRM = 0x230000, 96 GRCBASE_PBF_PB1 = 0xda0000, 97 GRCBASE_PBF_PB2 = 0xda4000, 98 GRCBASE_RPB = 0x23c000, 99 GRCBASE_BTB = 0xdb0000, 100 GRCBASE_PBF = 0xd80000, 101 GRCBASE_RDIF = 0x300000, 102 GRCBASE_TDIF = 0x310000, 103 GRCBASE_CDU = 0x580000, 104 GRCBASE_CCFC = 0x2e0000, 105 GRCBASE_TCFC = 0x2d0000, 106 GRCBASE_IGU = 0x180000, 107 GRCBASE_CAU = 0x1c0000, 108 GRCBASE_RGFS = 0xf00000, 109 GRCBASE_RGSRC = 0x320000, 110 GRCBASE_TGFS = 0xd00000, 111 GRCBASE_TGSRC = 0x322000, 112 GRCBASE_UMAC = 0x51000, 113 GRCBASE_XMAC = 0x210000, 114 GRCBASE_DBG = 0x10000, 115 GRCBASE_NIG = 0x500000, 116 GRCBASE_WOL = 0x600000, 117 GRCBASE_BMBN = 0x610000, 118 GRCBASE_IPC = 0x20000, 119 GRCBASE_NWM = 0x800000, 120 GRCBASE_NWS = 0x700000, 121 GRCBASE_MS = 0x6a0000, 122 GRCBASE_PHY_PCIE = 0x620000, 123 GRCBASE_LED = 0x6b8000, 124 GRCBASE_AVS_WRAP = 0x6b0000, 125 GRCBASE_PXPREQBUS = 0x56000, 126 GRCBASE_MISC_AEU = 0x8000, 127 GRCBASE_BAR0_MAP = 0x1c00000, 128 MAX_BLOCK_ADDR 129 }; 130 131 132 enum block_id 133 { 134 BLOCK_GRC, 135 BLOCK_MISCS, 136 BLOCK_MISC, 137 BLOCK_DBU, 138 BLOCK_PGLUE_B, 139 BLOCK_CNIG, 140 BLOCK_CPMU, 141 BLOCK_NCSI, 142 BLOCK_OPTE, 143 BLOCK_BMB, 144 BLOCK_PCIE, 145 BLOCK_MCP, 146 BLOCK_MCP2, 147 BLOCK_PSWHST, 148 BLOCK_PSWHST2, 149 BLOCK_PSWRD, 150 BLOCK_PSWRD2, 151 BLOCK_PSWWR, 152 BLOCK_PSWWR2, 153 BLOCK_PSWRQ, 154 BLOCK_PSWRQ2, 155 BLOCK_PGLCS, 156 BLOCK_DMAE, 157 BLOCK_PTU, 158 BLOCK_TCM, 159 BLOCK_MCM, 160 BLOCK_UCM, 161 BLOCK_XCM, 162 BLOCK_YCM, 163 BLOCK_PCM, 164 BLOCK_QM, 165 BLOCK_TM, 166 BLOCK_DORQ, 167 BLOCK_BRB, 168 BLOCK_SRC, 169 BLOCK_PRS, 170 BLOCK_TSDM, 171 BLOCK_MSDM, 172 BLOCK_USDM, 173 BLOCK_XSDM, 174 BLOCK_YSDM, 175 BLOCK_PSDM, 176 BLOCK_TSEM, 177 BLOCK_MSEM, 178 BLOCK_USEM, 179 BLOCK_XSEM, 180 BLOCK_YSEM, 181 BLOCK_PSEM, 182 BLOCK_RSS, 183 BLOCK_TMLD, 184 BLOCK_MULD, 185 BLOCK_YULD, 186 BLOCK_XYLD, 187 BLOCK_PTLD, 188 BLOCK_YPLD, 189 BLOCK_PRM, 190 BLOCK_PBF_PB1, 191 BLOCK_PBF_PB2, 192 BLOCK_RPB, 193 BLOCK_BTB, 194 BLOCK_PBF, 195 BLOCK_RDIF, 196 BLOCK_TDIF, 197 BLOCK_CDU, 198 BLOCK_CCFC, 199 BLOCK_TCFC, 200 BLOCK_IGU, 201 BLOCK_CAU, 202 BLOCK_RGFS, 203 BLOCK_RGSRC, 204 BLOCK_TGFS, 205 BLOCK_TGSRC, 206 BLOCK_UMAC, 207 BLOCK_XMAC, 208 BLOCK_DBG, 209 BLOCK_NIG, 210 BLOCK_WOL, 211 BLOCK_BMBN, 212 BLOCK_IPC, 213 BLOCK_NWM, 214 BLOCK_NWS, 215 BLOCK_MS, 216 BLOCK_PHY_PCIE, 217 BLOCK_LED, 218 BLOCK_AVS_WRAP, 219 BLOCK_PXPREQBUS, 220 BLOCK_MISC_AEU, 221 BLOCK_BAR0_MAP, 222 MAX_BLOCK_ID 223 }; 224 225 226 /* 227 * binary debug buffer types 228 */ 229 enum bin_dbg_buffer_type 230 { 231 BIN_BUF_DBG_MODE_TREE /* init modes tree */, 232 BIN_BUF_DBG_DUMP_REG /* GRC Dump registers */, 233 BIN_BUF_DBG_DUMP_MEM /* GRC Dump memories */, 234 BIN_BUF_DBG_IDLE_CHK_REGS /* Idle Check registers */, 235 BIN_BUF_DBG_IDLE_CHK_IMMS /* Idle Check immediates */, 236 BIN_BUF_DBG_IDLE_CHK_RULES /* Idle Check rules */, 237 BIN_BUF_DBG_IDLE_CHK_PARSING_DATA /* Idle Check parsing data */, 238 BIN_BUF_DBG_ATTN_BLOCKS /* Attention blocks */, 239 BIN_BUF_DBG_ATTN_REGS /* Attention registers */, 240 BIN_BUF_DBG_ATTN_INDEXES /* Attention indexes */, 241 BIN_BUF_DBG_ATTN_NAME_OFFSETS /* Attention name offsets */, 242 BIN_BUF_DBG_BUS_BLOCKS /* Debug Bus blocks */, 243 BIN_BUF_DBG_BUS_LINES /* Debug Bus lines */, 244 BIN_BUF_DBG_BUS_BLOCKS_USER_DATA /* Debug Bus blocks user data */, 245 BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS /* Debug Bus line name offsets */, 246 BIN_BUF_DBG_PARSING_STRINGS /* Debug Tools parsing strings */, 247 MAX_BIN_DBG_BUFFER_TYPE 248 }; 249 250 251 /* 252 * Attention bit mapping 253 */ 254 struct dbg_attn_bit_mapping 255 { 256 u16 data; 257 #define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF /* The index of an attention in the blocks attentions list (if is_unused_bit_cnt=0), or a number of consecutive unused attention bits (if is_unused_bit_cnt=1) */ 258 #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0 259 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1 /* if set, the val field indicates the number of consecutive unused attention bits */ 260 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT 15 261 }; 262 263 264 /* 265 * Attention block per-type data 266 */ 267 struct dbg_attn_block_type_data 268 { 269 u16 names_offset /* Offset of this block attention names in the debug attention name offsets array */; 270 u16 reserved1; 271 u8 num_regs /* Number of attention registers in this block */; 272 u8 reserved2; 273 u16 regs_offset /* Offset of this blocks attention registers in the attention registers array (in dbg_attn_reg units) */; 274 }; 275 276 /* 277 * Block attentions 278 */ 279 struct dbg_attn_block 280 { 281 struct dbg_attn_block_type_data per_type_data[2] /* attention block per-type data. Count must match the number of elements in dbg_attn_type. */; 282 }; 283 284 285 /* 286 * Attention register result 287 */ 288 struct dbg_attn_reg_result 289 { 290 u32 data; 291 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF /* STS attention register GRC address (in dwords) */ 292 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0 293 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK 0xFF /* Number of attention indexes in this register */ 294 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT 24 295 u16 block_attn_offset /* The offset of this registers attentions within the blocks attentions list (a value in the range 0..number of block attentions-1) */; 296 u16 reserved; 297 u32 sts_val /* Value read from the STS attention register */; 298 u32 mask_val /* Value read from the MASK attention register */; 299 }; 300 301 /* 302 * Attention block result 303 */ 304 struct dbg_attn_block_result 305 { 306 u8 block_id /* Registers block ID */; 307 u8 data; 308 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK 0x3 /* Value from dbg_attn_type enum */ 309 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0 310 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F /* Number of registers in the block in which at least one attention bit is set */ 311 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT 2 312 u16 names_offset /* Offset of this registers block attention names in the attention name offsets array */; 313 struct dbg_attn_reg_result reg_results[15] /* result data for each register in the block in which at least one attention bit is set */; 314 }; 315 316 317 318 /* 319 * mode header 320 */ 321 struct dbg_mode_hdr 322 { 323 u16 data; 324 #define DBG_MODE_HDR_EVAL_MODE_MASK 0x1 /* indicates if a mode expression should be evaluated (0/1) */ 325 #define DBG_MODE_HDR_EVAL_MODE_SHIFT 0 326 #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF /* offset (in bytes) in modes expression buffer. valid only if eval_mode is set. */ 327 #define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1 328 }; 329 330 /* 331 * Attention register 332 */ 333 struct dbg_attn_reg 334 { 335 struct dbg_mode_hdr mode /* Mode header */; 336 u16 block_attn_offset /* The offset of this registers attentions within the blocks attentions list (a value in the range 0..number of block attentions-1) */; 337 u32 data; 338 #define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF /* STS attention register GRC address (in dwords) */ 339 #define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0 340 #define DBG_ATTN_REG_NUM_REG_ATTN_MASK 0xFF /* Number of attention in this register */ 341 #define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24 342 u32 sts_clr_address /* STS_CLR attention register GRC address (in dwords) */; 343 u32 mask_address /* MASK attention register GRC address (in dwords) */; 344 }; 345 346 347 348 /* 349 * attention types 350 */ 351 enum dbg_attn_type 352 { 353 ATTN_TYPE_INTERRUPT, 354 ATTN_TYPE_PARITY, 355 MAX_DBG_ATTN_TYPE 356 }; 357 358 359 /* 360 * Debug Bus block data 361 */ 362 struct dbg_bus_block 363 { 364 u8 num_of_lines /* Number of debug lines in this block (excluding signature and latency events). */; 365 u8 has_latency_events /* Indicates if this block has a latency events debug line (0/1). */; 366 u16 lines_offset /* Offset of this blocks lines in the Debug Bus lines array. */; 367 }; 368 369 370 /* 371 * Debug Bus block user data 372 */ 373 struct dbg_bus_block_user_data 374 { 375 u8 num_of_lines /* Number of debug lines in this block (excluding signature and latency events). */; 376 u8 has_latency_events /* Indicates if this block has a latency events debug line (0/1). */; 377 u16 names_offset /* Offset of this blocks lines in the debug bus line name offsets array. */; 378 }; 379 380 381 /* 382 * Block Debug line data 383 */ 384 struct dbg_bus_line 385 { 386 u8 data; 387 #define DBG_BUS_LINE_NUM_OF_GROUPS_MASK 0xF /* Number of groups in the line (0-3) */ 388 #define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT 0 389 #define DBG_BUS_LINE_IS_256B_MASK 0x1 /* Indicates if this is a 128b line (0) or a 256b line (1). */ 390 #define DBG_BUS_LINE_IS_256B_SHIFT 4 391 #define DBG_BUS_LINE_RESERVED_MASK 0x7 392 #define DBG_BUS_LINE_RESERVED_SHIFT 5 393 u8 group_sizes /* Four 2-bit values, indicating the size of each group minus 1 (i.e. value=0 means size=1, value=1 means size=2, etc), starting from lsb. The sizes are in dwords (if is_256b=0) or in qwords (if is_256b=1). */; 394 }; 395 396 397 /* 398 * condition header for registers dump 399 */ 400 struct dbg_dump_cond_hdr 401 { 402 struct dbg_mode_hdr mode /* Mode header */; 403 u8 block_id /* block ID */; 404 u8 data_size /* size in dwords of the data following this header */; 405 }; 406 407 408 /* 409 * memory data for registers dump 410 */ 411 struct dbg_dump_mem 412 { 413 u32 dword0; 414 #define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF /* register address (in dwords) */ 415 #define DBG_DUMP_MEM_ADDRESS_SHIFT 0 416 #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF /* memory group ID */ 417 #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24 418 u32 dword1; 419 #define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF /* register size (in dwords) */ 420 #define DBG_DUMP_MEM_LENGTH_SHIFT 0 421 #define DBG_DUMP_MEM_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 422 #define DBG_DUMP_MEM_WIDE_BUS_SHIFT 24 423 #define DBG_DUMP_MEM_RESERVED_MASK 0x7F 424 #define DBG_DUMP_MEM_RESERVED_SHIFT 25 425 }; 426 427 428 /* 429 * register data for registers dump 430 */ 431 struct dbg_dump_reg 432 { 433 u32 data; 434 #define DBG_DUMP_REG_ADDRESS_MASK 0x7FFFFF /* register address (in dwords) */ 435 #define DBG_DUMP_REG_ADDRESS_SHIFT 0 436 #define DBG_DUMP_REG_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 437 #define DBG_DUMP_REG_WIDE_BUS_SHIFT 23 438 #define DBG_DUMP_REG_LENGTH_MASK 0xFF /* register size (in dwords) */ 439 #define DBG_DUMP_REG_LENGTH_SHIFT 24 440 }; 441 442 443 /* 444 * split header for registers dump 445 */ 446 struct dbg_dump_split_hdr 447 { 448 u32 hdr; 449 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF /* size in dwords of the data following this header */ 450 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0 451 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF /* split type ID */ 452 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24 453 }; 454 455 456 /* 457 * condition header for idle check 458 */ 459 struct dbg_idle_chk_cond_hdr 460 { 461 struct dbg_mode_hdr mode /* Mode header */; 462 u16 data_size /* size in dwords of the data following this header */; 463 }; 464 465 466 /* 467 * Idle Check condition register 468 */ 469 struct dbg_idle_chk_cond_reg 470 { 471 u32 data; 472 #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0x7FFFFF /* Register GRC address (in dwords) */ 473 #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0 474 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 475 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT 23 476 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF /* value from block_id enum */ 477 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24 478 u16 num_entries /* number of registers entries to check */; 479 u8 entry_size /* size of registers entry (in dwords) */; 480 u8 start_entry /* index of the first entry to check */; 481 }; 482 483 484 /* 485 * Idle Check info register 486 */ 487 struct dbg_idle_chk_info_reg 488 { 489 u32 data; 490 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0x7FFFFF /* Register GRC address (in dwords) */ 491 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0 492 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 493 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT 23 494 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF /* value from block_id enum */ 495 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24 496 u16 size /* register size in dwords */; 497 struct dbg_mode_hdr mode /* Mode header */; 498 }; 499 500 501 /* 502 * Idle Check register 503 */ 504 union dbg_idle_chk_reg 505 { 506 struct dbg_idle_chk_cond_reg cond_reg /* condition register */; 507 struct dbg_idle_chk_info_reg info_reg /* info register */; 508 }; 509 510 511 /* 512 * Idle Check result header 513 */ 514 struct dbg_idle_chk_result_hdr 515 { 516 u16 rule_id /* Failing rule index */; 517 u16 mem_entry_id /* Failing memory entry index */; 518 u8 num_dumped_cond_regs /* number of dumped condition registers */; 519 u8 num_dumped_info_regs /* number of dumped condition registers */; 520 u8 severity /* from dbg_idle_chk_severity_types enum */; 521 u8 reserved; 522 }; 523 524 525 /* 526 * Idle Check result register header 527 */ 528 struct dbg_idle_chk_result_reg_hdr 529 { 530 u8 data; 531 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK 0x1 /* indicates if this register is a memory */ 532 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0 533 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F /* register index within the failing rule */ 534 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1 535 u8 start_entry /* index of the first checked entry */; 536 u16 size /* register size in dwords */; 537 }; 538 539 540 /* 541 * Idle Check rule 542 */ 543 struct dbg_idle_chk_rule 544 { 545 u16 rule_id /* Idle Check rule ID */; 546 u8 severity /* value from dbg_idle_chk_severity_types enum */; 547 u8 cond_id /* Condition ID */; 548 u8 num_cond_regs /* number of condition registers */; 549 u8 num_info_regs /* number of info registers */; 550 u8 num_imms /* number of immediates in the condition */; 551 u8 reserved1; 552 u16 reg_offset /* offset of this rules registers in the idle check register array (in dbg_idle_chk_reg units) */; 553 u16 imm_offset /* offset of this rules immediate values in the immediate values array (in dwords) */; 554 }; 555 556 557 /* 558 * Idle Check rule parsing data 559 */ 560 struct dbg_idle_chk_rule_parsing_data 561 { 562 u32 data; 563 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1 /* indicates if this register has a FW message */ 564 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0 565 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF /* Offset of this rules strings in the debug strings array (in bytes) */ 566 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1 567 }; 568 569 570 /* 571 * idle check severity types 572 */ 573 enum dbg_idle_chk_severity_types 574 { 575 IDLE_CHK_SEVERITY_ERROR /* idle check failure should cause an error */, 576 IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC /* idle check failure should cause an error only if theres no traffic */, 577 IDLE_CHK_SEVERITY_WARNING /* idle check failure should cause a warning */, 578 MAX_DBG_IDLE_CHK_SEVERITY_TYPES 579 }; 580 581 582 583 /* 584 * Debug Bus block data 585 */ 586 struct dbg_bus_block_data 587 { 588 u16 data; 589 #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_MASK 0xF /* 4-bit value: bit i set -> dword/qword i is enabled. */ 590 #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_SHIFT 0 591 #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_MASK 0xF /* Number of dwords/qwords to shift right the debug data (0-3) */ 592 #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_SHIFT 4 593 #define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_MASK 0xF /* 4-bit value: bit i set -> dword/qword i is forced valid. */ 594 #define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_SHIFT 8 595 #define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_MASK 0xF /* 4-bit value: bit i set -> dword/qword i frame bit is forced. */ 596 #define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_SHIFT 12 597 u8 line_num /* Debug line number to select */; 598 u8 hw_id /* HW ID associated with the block */; 599 }; 600 601 602 /* 603 * Debug Bus Clients 604 */ 605 enum dbg_bus_clients 606 { 607 DBG_BUS_CLIENT_RBCN, 608 DBG_BUS_CLIENT_RBCP, 609 DBG_BUS_CLIENT_RBCR, 610 DBG_BUS_CLIENT_RBCT, 611 DBG_BUS_CLIENT_RBCU, 612 DBG_BUS_CLIENT_RBCF, 613 DBG_BUS_CLIENT_RBCX, 614 DBG_BUS_CLIENT_RBCS, 615 DBG_BUS_CLIENT_RBCH, 616 DBG_BUS_CLIENT_RBCZ, 617 DBG_BUS_CLIENT_OTHER_ENGINE, 618 DBG_BUS_CLIENT_TIMESTAMP, 619 DBG_BUS_CLIENT_CPU, 620 DBG_BUS_CLIENT_RBCY, 621 DBG_BUS_CLIENT_RBCQ, 622 DBG_BUS_CLIENT_RBCM, 623 DBG_BUS_CLIENT_RBCB, 624 DBG_BUS_CLIENT_RBCW, 625 DBG_BUS_CLIENT_RBCV, 626 MAX_DBG_BUS_CLIENTS 627 }; 628 629 630 /* 631 * Debug Bus constraint operation types 632 */ 633 enum dbg_bus_constraint_ops 634 { 635 DBG_BUS_CONSTRAINT_OP_EQ /* equal */, 636 DBG_BUS_CONSTRAINT_OP_NE /* not equal */, 637 DBG_BUS_CONSTRAINT_OP_LT /* less than */, 638 DBG_BUS_CONSTRAINT_OP_LTC /* less than (cyclic) */, 639 DBG_BUS_CONSTRAINT_OP_LE /* less than or equal */, 640 DBG_BUS_CONSTRAINT_OP_LEC /* less than or equal (cyclic) */, 641 DBG_BUS_CONSTRAINT_OP_GT /* greater than */, 642 DBG_BUS_CONSTRAINT_OP_GTC /* greater than (cyclic) */, 643 DBG_BUS_CONSTRAINT_OP_GE /* greater than or equal */, 644 DBG_BUS_CONSTRAINT_OP_GEC /* greater than or equal (cyclic) */, 645 MAX_DBG_BUS_CONSTRAINT_OPS 646 }; 647 648 649 /* 650 * Debug Bus trigger state data 651 */ 652 struct dbg_bus_trigger_state_data 653 { 654 u8 data; 655 #define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_MASK 0xF /* 4-bit value: bit i set -> dword i of the trigger state block (after right shift) is enabled. */ 656 #define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_SHIFT 0 657 #define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_MASK 0xF /* 4-bit value: bit i set -> dword i is compared by a constraint */ 658 #define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_SHIFT 4 659 }; 660 661 /* 662 * Debug Bus memory address 663 */ 664 struct dbg_bus_mem_addr 665 { 666 u32 lo; 667 u32 hi; 668 }; 669 670 /* 671 * Debug Bus PCI buffer data 672 */ 673 struct dbg_bus_pci_buf_data 674 { 675 struct dbg_bus_mem_addr phys_addr /* PCI buffer physical address */; 676 struct dbg_bus_mem_addr virt_addr /* PCI buffer virtual address */; 677 u32 size /* PCI buffer size in bytes */; 678 }; 679 680 /* 681 * Debug Bus Storm EID range filter params 682 */ 683 struct dbg_bus_storm_eid_range_params 684 { 685 u8 min /* Minimal event ID to filter on */; 686 u8 max /* Maximal event ID to filter on */; 687 }; 688 689 /* 690 * Debug Bus Storm EID mask filter params 691 */ 692 struct dbg_bus_storm_eid_mask_params 693 { 694 u8 val /* Event ID value */; 695 u8 mask /* Event ID mask. 1s in the mask = dont care bits. */; 696 }; 697 698 /* 699 * Debug Bus Storm EID filter params 700 */ 701 union dbg_bus_storm_eid_params 702 { 703 struct dbg_bus_storm_eid_range_params range /* EID range filter params */; 704 struct dbg_bus_storm_eid_mask_params mask /* EID mask filter params */; 705 }; 706 707 /* 708 * Debug Bus Storm data 709 */ 710 struct dbg_bus_storm_data 711 { 712 u8 enabled /* indicates if the Storm is enabled for recording */; 713 u8 mode /* Storm debug mode, valid only if the Storm is enabled (use enum dbg_bus_storm_modes) */; 714 u8 hw_id /* HW ID associated with the Storm */; 715 u8 eid_filter_en /* Indicates if EID filtering is performed (0/1) */; 716 u8 eid_range_not_mask /* 1 = EID range filter, 0 = EID mask filter. Valid only if eid_filter_en is set, */; 717 u8 cid_filter_en /* Indicates if CID filtering is performed (0/1) */; 718 union dbg_bus_storm_eid_params eid_filter_params /* EID filter params to filter on. Valid only if eid_filter_en is set. */; 719 u32 cid /* CID to filter on. Valid only if cid_filter_en is set. */; 720 }; 721 722 /* 723 * Debug Bus data 724 */ 725 struct dbg_bus_data 726 { 727 u32 app_version /* The tools version number of the application */; 728 u8 state /* The current debug bus state (use enum dbg_bus_states) */; 729 u8 hw_dwords /* HW dwords per cycle */; 730 u16 hw_id_mask /* The HW IDs of the recorded HW blocks, where bits i*3..i*3+2 contain the HW ID of dword/qword i */; 731 u8 num_enabled_blocks /* Number of blocks enabled for recording */; 732 u8 num_enabled_storms /* Number of Storms enabled for recording */; 733 u8 target /* Output target (use enum dbg_bus_targets) */; 734 u8 one_shot_en /* Indicates if one-shot mode is enabled (0/1) */; 735 u8 grc_input_en /* Indicates if GRC recording is enabled (0/1) */; 736 u8 timestamp_input_en /* Indicates if timestamp recording is enabled (0/1) */; 737 u8 filter_en /* Indicates if the recording filter is enabled (0/1) */; 738 u8 adding_filter /* If true, the next added constraint belong to the filter. Otherwise, it belongs to the last added trigger state. Valid only if either filter or triggers are enabled. */; 739 u8 filter_pre_trigger /* Indicates if the recording filter should be applied before the trigger. Valid only if both filter and trigger are enabled (0/1) */; 740 u8 filter_post_trigger /* Indicates if the recording filter should be applied after the trigger. Valid only if both filter and trigger are enabled (0/1) */; 741 u16 reserved; 742 u8 trigger_en /* Indicates if the recording trigger is enabled (0/1) */; 743 struct dbg_bus_trigger_state_data trigger_states[3] /* trigger states data */; 744 u8 next_trigger_state /* ID of next trigger state to be added */; 745 u8 next_constraint_id /* ID of next filter/trigger constraint to be added */; 746 u8 unify_inputs /* If true, all inputs are associated with HW ID 0. Otherwise, each input is assigned a different HW ID (0/1) */; 747 u8 rcv_from_other_engine /* Indicates if the other engine sends it NW recording to this engine (0/1) */; 748 struct dbg_bus_pci_buf_data pci_buf /* Debug Bus PCI buffer data. Valid only when the target is DBG_BUS_TARGET_ID_PCI. */; 749 struct dbg_bus_block_data blocks[88] /* Debug Bus data for each block */; 750 struct dbg_bus_storm_data storms[6] /* Debug Bus data for each block */; 751 }; 752 753 754 /* 755 * Debug bus filter types 756 */ 757 enum dbg_bus_filter_types 758 { 759 DBG_BUS_FILTER_TYPE_OFF /* filter always off */, 760 DBG_BUS_FILTER_TYPE_PRE /* filter before trigger only */, 761 DBG_BUS_FILTER_TYPE_POST /* filter after trigger only */, 762 DBG_BUS_FILTER_TYPE_ON /* filter always on */, 763 MAX_DBG_BUS_FILTER_TYPES 764 }; 765 766 767 /* 768 * Debug bus frame modes 769 */ 770 enum dbg_bus_frame_modes 771 { 772 DBG_BUS_FRAME_MODE_0HW_4ST=0 /* 0 HW dwords, 4 Storm dwords */, 773 DBG_BUS_FRAME_MODE_4HW_0ST=3 /* 4 HW dwords, 0 Storm dwords */, 774 DBG_BUS_FRAME_MODE_8HW_0ST=4 /* 8 HW dwords, 0 Storm dwords */, 775 MAX_DBG_BUS_FRAME_MODES 776 }; 777 778 779 780 /* 781 * Debug bus other engine mode 782 */ 783 enum dbg_bus_other_engine_modes 784 { 785 DBG_BUS_OTHER_ENGINE_MODE_NONE, 786 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX, 787 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX, 788 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX, 789 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX, 790 MAX_DBG_BUS_OTHER_ENGINE_MODES 791 }; 792 793 794 795 /* 796 * Debug bus post-trigger recording types 797 */ 798 enum dbg_bus_post_trigger_types 799 { 800 DBG_BUS_POST_TRIGGER_RECORD /* start recording after trigger */, 801 DBG_BUS_POST_TRIGGER_DROP /* drop data after trigger */, 802 MAX_DBG_BUS_POST_TRIGGER_TYPES 803 }; 804 805 806 /* 807 * Debug bus pre-trigger recording types 808 */ 809 enum dbg_bus_pre_trigger_types 810 { 811 DBG_BUS_PRE_TRIGGER_START_FROM_ZERO /* start recording from time 0 */, 812 DBG_BUS_PRE_TRIGGER_NUM_CHUNKS /* start recording some chunks before trigger */, 813 DBG_BUS_PRE_TRIGGER_DROP /* drop data before trigger */, 814 MAX_DBG_BUS_PRE_TRIGGER_TYPES 815 }; 816 817 818 /* 819 * Debug bus SEMI frame modes 820 */ 821 enum dbg_bus_semi_frame_modes 822 { 823 DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST=0 /* 0 slow dwords, 4 fast dwords */, 824 DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST=3 /* 4 slow dwords, 0 fast dwords */, 825 MAX_DBG_BUS_SEMI_FRAME_MODES 826 }; 827 828 829 /* 830 * Debug bus states 831 */ 832 enum dbg_bus_states 833 { 834 DBG_BUS_STATE_IDLE /* debug bus idle state (not recording) */, 835 DBG_BUS_STATE_READY /* debug bus is ready for configuration and recording */, 836 DBG_BUS_STATE_RECORDING /* debug bus is currently recording */, 837 DBG_BUS_STATE_STOPPED /* debug bus recording has stopped */, 838 MAX_DBG_BUS_STATES 839 }; 840 841 842 843 844 845 846 /* 847 * Debug Bus Storm modes 848 */ 849 enum dbg_bus_storm_modes 850 { 851 DBG_BUS_STORM_MODE_PRINTF /* store data (fast debug) */, 852 DBG_BUS_STORM_MODE_PRAM_ADDR /* pram address (fast debug) */, 853 DBG_BUS_STORM_MODE_DRA_RW /* DRA read/write data (fast debug) */, 854 DBG_BUS_STORM_MODE_DRA_W /* DRA write data (fast debug) */, 855 DBG_BUS_STORM_MODE_LD_ST_ADDR /* load/store address (fast debug) */, 856 DBG_BUS_STORM_MODE_DRA_FSM /* DRA state machines (fast debug) */, 857 DBG_BUS_STORM_MODE_RH /* recording handlers (fast debug) */, 858 DBG_BUS_STORM_MODE_FOC /* FOC: FIN + DRA Rd (slow debug) */, 859 DBG_BUS_STORM_MODE_EXT_STORE /* FOC: External Store (slow) */, 860 MAX_DBG_BUS_STORM_MODES 861 }; 862 863 864 /* 865 * Debug bus target IDs 866 */ 867 enum dbg_bus_targets 868 { 869 DBG_BUS_TARGET_ID_INT_BUF /* records debug bus to DBG block internal buffer */, 870 DBG_BUS_TARGET_ID_NIG /* records debug bus to the NW */, 871 DBG_BUS_TARGET_ID_PCI /* records debug bus to a PCI buffer */, 872 MAX_DBG_BUS_TARGETS 873 }; 874 875 876 877 /* 878 * GRC Dump data 879 */ 880 struct dbg_grc_data 881 { 882 u8 params_initialized /* Indicates if the GRC parameters were initialized */; 883 u8 reserved1; 884 u16 reserved2; 885 u32 param_val[48] /* Value of each GRC parameter. Array size must match the enum dbg_grc_params. */; 886 }; 887 888 889 /* 890 * Debug GRC params 891 */ 892 enum dbg_grc_params 893 { 894 DBG_GRC_PARAM_DUMP_TSTORM /* dump Tstorm memories (0/1) */, 895 DBG_GRC_PARAM_DUMP_MSTORM /* dump Mstorm memories (0/1) */, 896 DBG_GRC_PARAM_DUMP_USTORM /* dump Ustorm memories (0/1) */, 897 DBG_GRC_PARAM_DUMP_XSTORM /* dump Xstorm memories (0/1) */, 898 DBG_GRC_PARAM_DUMP_YSTORM /* dump Ystorm memories (0/1) */, 899 DBG_GRC_PARAM_DUMP_PSTORM /* dump Pstorm memories (0/1) */, 900 DBG_GRC_PARAM_DUMP_REGS /* dump non-memory registers (0/1) */, 901 DBG_GRC_PARAM_DUMP_RAM /* dump Storm internal RAMs (0/1) */, 902 DBG_GRC_PARAM_DUMP_PBUF /* dump Storm passive buffer (0/1) */, 903 DBG_GRC_PARAM_DUMP_IOR /* dump Storm IORs (0/1) */, 904 DBG_GRC_PARAM_DUMP_VFC /* dump VFC memories (0/1) */, 905 DBG_GRC_PARAM_DUMP_CM_CTX /* dump CM contexts (0/1) */, 906 DBG_GRC_PARAM_DUMP_PXP /* dump PXP memories (0/1) */, 907 DBG_GRC_PARAM_DUMP_RSS /* dump RSS memories (0/1) */, 908 DBG_GRC_PARAM_DUMP_CAU /* dump CAU memories (0/1) */, 909 DBG_GRC_PARAM_DUMP_QM /* dump QM memories (0/1) */, 910 DBG_GRC_PARAM_DUMP_MCP /* dump MCP memories (0/1) */, 911 DBG_GRC_PARAM_RESERVED /* reserved */, 912 DBG_GRC_PARAM_DUMP_CFC /* dump CFC memories (0/1) */, 913 DBG_GRC_PARAM_DUMP_IGU /* dump IGU memories (0/1) */, 914 DBG_GRC_PARAM_DUMP_BRB /* dump BRB memories (0/1) */, 915 DBG_GRC_PARAM_DUMP_BTB /* dump BTB memories (0/1) */, 916 DBG_GRC_PARAM_DUMP_BMB /* dump BMB memories (0/1) */, 917 DBG_GRC_PARAM_DUMP_NIG /* dump NIG memories (0/1) */, 918 DBG_GRC_PARAM_DUMP_MULD /* dump MULD memories (0/1) */, 919 DBG_GRC_PARAM_DUMP_PRS /* dump PRS memories (0/1) */, 920 DBG_GRC_PARAM_DUMP_DMAE /* dump PRS memories (0/1) */, 921 DBG_GRC_PARAM_DUMP_TM /* dump TM (timers) memories (0/1) */, 922 DBG_GRC_PARAM_DUMP_SDM /* dump SDM memories (0/1) */, 923 DBG_GRC_PARAM_DUMP_DIF /* dump DIF memories (0/1) */, 924 DBG_GRC_PARAM_DUMP_STATIC /* dump static debug data (0/1) */, 925 DBG_GRC_PARAM_UNSTALL /* un-stall Storms after dump (0/1) */, 926 DBG_GRC_PARAM_NUM_LCIDS /* number of LCIDs (0..320) */, 927 DBG_GRC_PARAM_NUM_LTIDS /* number of LTIDs (0..320) */, 928 DBG_GRC_PARAM_EXCLUDE_ALL /* preset: exclude all memories from dump (1 only) */, 929 DBG_GRC_PARAM_CRASH /* preset: include memories for crash dump (1 only) */, 930 DBG_GRC_PARAM_PARITY_SAFE /* perform dump only if MFW is responding (0/1) */, 931 DBG_GRC_PARAM_DUMP_CM /* dump CM memories (0/1) */, 932 DBG_GRC_PARAM_DUMP_PHY /* dump PHY memories (0/1) */, 933 DBG_GRC_PARAM_NO_MCP /* dont perform MCP commands (0/1) */, 934 DBG_GRC_PARAM_NO_FW_VER /* dont read FW/MFW version (0/1) */, 935 MAX_DBG_GRC_PARAMS 936 }; 937 938 939 /* 940 * Debug reset registers 941 */ 942 enum dbg_reset_regs 943 { 944 DBG_RESET_REG_MISCS_PL_UA, 945 DBG_RESET_REG_MISCS_PL_HV, 946 DBG_RESET_REG_MISCS_PL_HV_2, 947 DBG_RESET_REG_MISC_PL_UA, 948 DBG_RESET_REG_MISC_PL_HV, 949 DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 950 DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 951 DBG_RESET_REG_MISC_PL_PDA_VAUX, 952 MAX_DBG_RESET_REGS 953 }; 954 955 956 /* 957 * Debug status codes 958 */ 959 enum dbg_status 960 { 961 DBG_STATUS_OK, 962 DBG_STATUS_APP_VERSION_NOT_SET, 963 DBG_STATUS_UNSUPPORTED_APP_VERSION, 964 DBG_STATUS_DBG_BLOCK_NOT_RESET, 965 DBG_STATUS_INVALID_ARGS, 966 DBG_STATUS_OUTPUT_ALREADY_SET, 967 DBG_STATUS_INVALID_PCI_BUF_SIZE, 968 DBG_STATUS_PCI_BUF_ALLOC_FAILED, 969 DBG_STATUS_PCI_BUF_NOT_ALLOCATED, 970 DBG_STATUS_TOO_MANY_INPUTS, 971 DBG_STATUS_INPUT_OVERLAP, 972 DBG_STATUS_HW_ONLY_RECORDING, 973 DBG_STATUS_STORM_ALREADY_ENABLED, 974 DBG_STATUS_STORM_NOT_ENABLED, 975 DBG_STATUS_BLOCK_ALREADY_ENABLED, 976 DBG_STATUS_BLOCK_NOT_ENABLED, 977 DBG_STATUS_NO_INPUT_ENABLED, 978 DBG_STATUS_NO_FILTER_TRIGGER_64B, 979 DBG_STATUS_FILTER_ALREADY_ENABLED, 980 DBG_STATUS_TRIGGER_ALREADY_ENABLED, 981 DBG_STATUS_TRIGGER_NOT_ENABLED, 982 DBG_STATUS_CANT_ADD_CONSTRAINT, 983 DBG_STATUS_TOO_MANY_TRIGGER_STATES, 984 DBG_STATUS_TOO_MANY_CONSTRAINTS, 985 DBG_STATUS_RECORDING_NOT_STARTED, 986 DBG_STATUS_DATA_DIDNT_TRIGGER, 987 DBG_STATUS_NO_DATA_RECORDED, 988 DBG_STATUS_DUMP_BUF_TOO_SMALL, 989 DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED, 990 DBG_STATUS_UNKNOWN_CHIP, 991 DBG_STATUS_VIRT_MEM_ALLOC_FAILED, 992 DBG_STATUS_BLOCK_IN_RESET, 993 DBG_STATUS_INVALID_TRACE_SIGNATURE, 994 DBG_STATUS_INVALID_NVRAM_BUNDLE, 995 DBG_STATUS_NVRAM_GET_IMAGE_FAILED, 996 DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE, 997 DBG_STATUS_NVRAM_READ_FAILED, 998 DBG_STATUS_IDLE_CHK_PARSE_FAILED, 999 DBG_STATUS_MCP_TRACE_BAD_DATA, 1000 DBG_STATUS_MCP_TRACE_NO_META, 1001 DBG_STATUS_MCP_COULD_NOT_HALT, 1002 DBG_STATUS_MCP_COULD_NOT_RESUME, 1003 DBG_STATUS_RESERVED2, 1004 DBG_STATUS_SEMI_FIFO_NOT_EMPTY, 1005 DBG_STATUS_IGU_FIFO_BAD_DATA, 1006 DBG_STATUS_MCP_COULD_NOT_MASK_PRTY, 1007 DBG_STATUS_FW_ASSERTS_PARSE_FAILED, 1008 DBG_STATUS_REG_FIFO_BAD_DATA, 1009 DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA, 1010 DBG_STATUS_DBG_ARRAY_NOT_SET, 1011 DBG_STATUS_FILTER_BUG, 1012 DBG_STATUS_NON_MATCHING_LINES, 1013 DBG_STATUS_INVALID_TRIGGER_DWORD_OFFSET, 1014 DBG_STATUS_DBG_BUS_IN_USE, 1015 MAX_DBG_STATUS 1016 }; 1017 1018 1019 /* 1020 * Debug Storms IDs 1021 */ 1022 enum dbg_storms 1023 { 1024 DBG_TSTORM_ID, 1025 DBG_MSTORM_ID, 1026 DBG_USTORM_ID, 1027 DBG_XSTORM_ID, 1028 DBG_YSTORM_ID, 1029 DBG_PSTORM_ID, 1030 MAX_DBG_STORMS 1031 }; 1032 1033 1034 /* 1035 * Idle Check data 1036 */ 1037 struct idle_chk_data 1038 { 1039 u32 buf_size /* Idle check buffer size in dwords */; 1040 u8 buf_size_set /* Indicates if the idle check buffer size was set (0/1) */; 1041 u8 reserved1; 1042 u16 reserved2; 1043 }; 1044 1045 /* 1046 * Debug Tools data (per HW function) 1047 */ 1048 struct dbg_tools_data 1049 { 1050 struct dbg_grc_data grc /* GRC Dump data */; 1051 struct dbg_bus_data bus /* Debug Bus data */; 1052 struct idle_chk_data idle_chk /* Idle Check data */; 1053 u8 mode_enable[40] /* Indicates if a mode is enabled (0/1) */; 1054 u8 block_in_reset[88] /* Indicates if a block is in reset state (0/1) */; 1055 u8 chip_id /* Chip ID (from enum chip_ids) */; 1056 u8 platform_id /* Platform ID */; 1057 u8 initialized /* Indicates if the data was initialized */; 1058 u8 use_dmae /* Indicates if DMAE should be used */; 1059 u32 num_regs_read /* Numbers of registers that were read since last log */; 1060 }; 1061 1062 1063 #endif /* __ECORE_HSI_DEBUG_TOOLS__ */ 1064