1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __ECORE_HSI_ETH__ 32 #define __ECORE_HSI_ETH__ 33 /************************************************************************/ 34 /* Add include to common eth target for both eCore and protocol driver */ 35 /************************************************************************/ 36 #include "eth_common.h" 37 38 /* 39 * The eth storm context for the Tstorm 40 */ 41 struct tstorm_eth_conn_st_ctx 42 { 43 __le32 reserved[4]; 44 }; 45 46 /* 47 * The eth storm context for the Pstorm 48 */ 49 struct pstorm_eth_conn_st_ctx 50 { 51 __le32 reserved[8]; 52 }; 53 54 /* 55 * The eth storm context for the Xstorm 56 */ 57 struct xstorm_eth_conn_st_ctx 58 { 59 __le32 reserved[60]; 60 }; 61 62 struct e4_xstorm_eth_conn_ag_ctx 63 { 64 u8 reserved0 /* cdu_validation */; 65 u8 state /* state */; 66 u8 flags0; 67 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 68 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 69 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 70 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1 71 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 72 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2 73 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 74 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 75 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 76 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4 77 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 78 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5 79 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 80 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6 81 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 82 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7 83 u8 flags1; 84 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 85 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0 86 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 87 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1 88 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 89 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2 90 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 91 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3 92 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 /* bit12 */ 93 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 94 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 /* bit13 */ 95 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 96 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 97 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 98 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 99 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 100 u8 flags2; 101 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 102 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0 103 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 104 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2 105 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 106 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4 107 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 108 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6 109 u8 flags3; 110 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 111 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0 112 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 113 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2 114 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 115 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4 116 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 117 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6 118 u8 flags4; 119 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 120 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0 121 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 122 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2 123 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 124 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4 125 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 126 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6 127 u8 flags5; 128 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 129 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0 130 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 131 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2 132 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 133 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4 134 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 135 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6 136 u8 flags6; 137 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 138 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 139 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 /* cf_array_cf */ 140 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 141 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 142 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4 143 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 144 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 145 u8 flags7; 146 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 147 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 148 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 149 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2 150 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 151 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4 152 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 153 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6 154 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 155 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7 156 u8 flags8; 157 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 158 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0 159 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 160 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1 161 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 162 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2 163 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 164 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3 165 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 166 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4 167 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 168 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5 169 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 170 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6 171 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 172 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7 173 u8 flags9; 174 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 175 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0 176 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 177 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1 178 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 179 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2 180 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 181 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3 182 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 183 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4 184 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 185 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5 186 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 187 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 188 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 /* cf_array_cf_en */ 189 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 190 u8 flags10; 191 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 192 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 193 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 194 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 195 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 196 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 197 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 198 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3 199 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 200 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 201 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 202 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 203 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 204 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6 205 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 206 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7 207 u8 flags11; 208 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 209 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0 210 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 211 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1 212 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 213 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 214 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 215 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3 216 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 217 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4 218 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 219 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5 220 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 221 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 222 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 223 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7 224 u8 flags12; 225 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 226 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0 227 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 228 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1 229 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 230 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 231 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 232 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 233 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 234 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4 235 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 236 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5 237 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 238 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6 239 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 240 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7 241 u8 flags13; 242 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 243 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0 244 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 245 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1 246 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 247 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 248 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 249 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 250 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 251 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 252 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 253 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 254 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 255 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 256 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 257 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 258 u8 flags14; 259 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 260 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 261 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 262 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 263 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 264 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 265 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 266 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 267 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 268 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 269 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 270 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 271 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */ 272 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 273 u8 edpm_event_id /* byte2 */; 274 __le16 physical_q0 /* physical_q0 */; 275 __le16 e5_reserved1 /* physical_q1 */; 276 __le16 edpm_num_bds /* physical_q2 */; 277 __le16 tx_bd_cons /* word3 */; 278 __le16 tx_bd_prod /* word4 */; 279 __le16 tx_class /* word5 */; 280 __le16 conn_dpi /* conn_dpi */; 281 u8 byte3 /* byte3 */; 282 u8 byte4 /* byte4 */; 283 u8 byte5 /* byte5 */; 284 u8 byte6 /* byte6 */; 285 __le32 reg0 /* reg0 */; 286 __le32 reg1 /* reg1 */; 287 __le32 reg2 /* reg2 */; 288 __le32 reg3 /* reg3 */; 289 __le32 reg4 /* reg4 */; 290 __le32 reg5 /* cf_array0 */; 291 __le32 reg6 /* cf_array1 */; 292 __le16 word7 /* word7 */; 293 __le16 word8 /* word8 */; 294 __le16 word9 /* word9 */; 295 __le16 word10 /* word10 */; 296 __le32 reg7 /* reg7 */; 297 __le32 reg8 /* reg8 */; 298 __le32 reg9 /* reg9 */; 299 u8 byte7 /* byte7 */; 300 u8 byte8 /* byte8 */; 301 u8 byte9 /* byte9 */; 302 u8 byte10 /* byte10 */; 303 u8 byte11 /* byte11 */; 304 u8 byte12 /* byte12 */; 305 u8 byte13 /* byte13 */; 306 u8 byte14 /* byte14 */; 307 u8 byte15 /* byte15 */; 308 u8 e5_reserved /* e5_reserved */; 309 __le16 word11 /* word11 */; 310 __le32 reg10 /* reg10 */; 311 __le32 reg11 /* reg11 */; 312 __le32 reg12 /* reg12 */; 313 __le32 reg13 /* reg13 */; 314 __le32 reg14 /* reg14 */; 315 __le32 reg15 /* reg15 */; 316 __le32 reg16 /* reg16 */; 317 __le32 reg17 /* reg17 */; 318 __le32 reg18 /* reg18 */; 319 __le32 reg19 /* reg19 */; 320 __le16 word12 /* word12 */; 321 __le16 word13 /* word13 */; 322 __le16 word14 /* word14 */; 323 __le16 word15 /* word15 */; 324 }; 325 326 /* 327 * The eth storm context for the Ystorm 328 */ 329 struct ystorm_eth_conn_st_ctx 330 { 331 __le32 reserved[8]; 332 }; 333 334 struct e4_ystorm_eth_conn_ag_ctx 335 { 336 u8 byte0 /* cdu_validation */; 337 u8 state /* state */; 338 u8 flags0; 339 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 340 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 341 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 342 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 343 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf0 */ 344 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2 345 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 /* cf1 */ 346 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4 347 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 348 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 349 u8 flags1; 350 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf0en */ 351 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0 352 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */ 353 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1 354 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 355 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 356 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 357 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 358 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 359 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 360 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 361 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 362 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 363 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 364 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 365 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 366 u8 tx_q0_int_coallecing_timeset /* byte2 */; 367 u8 byte3 /* byte3 */; 368 __le16 word0 /* word0 */; 369 __le32 terminate_spqe /* reg0 */; 370 __le32 reg1 /* reg1 */; 371 __le16 tx_bd_cons_upd /* word1 */; 372 __le16 word2 /* word2 */; 373 __le16 word3 /* word3 */; 374 __le16 word4 /* word4 */; 375 __le32 reg2 /* reg2 */; 376 __le32 reg3 /* reg3 */; 377 }; 378 379 struct e4_tstorm_eth_conn_ag_ctx 380 { 381 u8 byte0 /* cdu_validation */; 382 u8 byte1 /* state */; 383 u8 flags0; 384 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 385 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 386 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 387 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 388 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 389 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2 390 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 391 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3 392 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 393 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4 394 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 395 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5 396 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 397 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6 398 u8 flags1; 399 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 400 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0 401 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 402 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2 403 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 404 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4 405 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 406 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6 407 u8 flags2; 408 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 409 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0 410 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 411 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2 412 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 413 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4 414 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 415 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6 416 u8 flags3; 417 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 418 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0 419 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 420 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2 421 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 422 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4 423 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 424 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5 425 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 426 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6 427 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 428 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7 429 u8 flags4; 430 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 431 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0 432 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 433 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1 434 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 435 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2 436 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 437 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3 438 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 439 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4 440 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 441 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5 442 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 443 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6 444 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 445 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 446 u8 flags5; 447 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 448 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 449 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 450 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 451 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 452 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 453 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 454 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 455 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 456 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 457 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 /* rule6en */ 458 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5 459 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 460 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 461 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 462 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 463 __le32 reg0 /* reg0 */; 464 __le32 reg1 /* reg1 */; 465 __le32 reg2 /* reg2 */; 466 __le32 reg3 /* reg3 */; 467 __le32 reg4 /* reg4 */; 468 __le32 reg5 /* reg5 */; 469 __le32 reg6 /* reg6 */; 470 __le32 reg7 /* reg7 */; 471 __le32 reg8 /* reg8 */; 472 u8 byte2 /* byte2 */; 473 u8 byte3 /* byte3 */; 474 __le16 rx_bd_cons /* word0 */; 475 u8 byte4 /* byte4 */; 476 u8 byte5 /* byte5 */; 477 __le16 rx_bd_prod /* word1 */; 478 __le16 word2 /* conn_dpi */; 479 __le16 word3 /* word3 */; 480 __le32 reg9 /* reg9 */; 481 __le32 reg10 /* reg10 */; 482 }; 483 484 struct e4_ustorm_eth_conn_ag_ctx 485 { 486 u8 byte0 /* cdu_validation */; 487 u8 byte1 /* state */; 488 u8 flags0; 489 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 490 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 491 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 492 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 493 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3 /* timer0cf */ 494 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2 495 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3 /* timer1cf */ 496 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4 497 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 498 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 499 u8 flags1; 500 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 501 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0 502 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3 /* cf4 */ 503 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2 504 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3 /* cf5 */ 505 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4 506 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf6 */ 507 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6 508 u8 flags2; 509 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf0en */ 510 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0 511 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */ 512 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1 513 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 514 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 515 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 516 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3 517 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1 /* cf4en */ 518 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4 519 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1 /* cf5en */ 520 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5 521 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf6en */ 522 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6 523 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 524 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 525 u8 flags3; 526 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 527 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 528 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 529 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 530 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 531 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 532 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 533 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 534 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 535 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 536 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 537 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5 538 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 539 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 540 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 541 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 542 u8 byte2 /* byte2 */; 543 u8 byte3 /* byte3 */; 544 __le16 word0 /* conn_dpi */; 545 __le16 tx_bd_cons /* word1 */; 546 __le32 reg0 /* reg0 */; 547 __le32 reg1 /* reg1 */; 548 __le32 reg2 /* reg2 */; 549 __le32 tx_int_coallecing_timeset /* reg3 */; 550 __le16 tx_drv_bd_cons /* word2 */; 551 __le16 rx_drv_cqe_cons /* word3 */; 552 }; 553 554 /* 555 * The eth storm context for the Ustorm 556 */ 557 struct ustorm_eth_conn_st_ctx 558 { 559 __le32 reserved[40]; 560 }; 561 562 /* 563 * The eth storm context for the Mstorm 564 */ 565 struct mstorm_eth_conn_st_ctx 566 { 567 __le32 reserved[8]; 568 }; 569 570 /* 571 * eth connection context 572 */ 573 struct e4_eth_conn_context 574 { 575 struct tstorm_eth_conn_st_ctx tstorm_st_context /* tstorm storm context */; 576 struct regpair tstorm_st_padding[2] /* padding */; 577 struct pstorm_eth_conn_st_ctx pstorm_st_context /* pstorm storm context */; 578 struct xstorm_eth_conn_st_ctx xstorm_st_context /* xstorm storm context */; 579 struct e4_xstorm_eth_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 580 struct ystorm_eth_conn_st_ctx ystorm_st_context /* ystorm storm context */; 581 struct e4_ystorm_eth_conn_ag_ctx ystorm_ag_context /* ystorm aggregative context */; 582 struct e4_tstorm_eth_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 583 struct e4_ustorm_eth_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 584 struct ustorm_eth_conn_st_ctx ustorm_st_context /* ustorm storm context */; 585 struct mstorm_eth_conn_st_ctx mstorm_st_context /* mstorm storm context */; 586 }; 587 588 struct e5_xstorm_eth_conn_ag_ctx 589 { 590 u8 reserved0 /* cdu_validation */; 591 u8 state_and_core_id /* state_and_core_id */; 592 u8 flags0; 593 #define E5_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 594 #define E5_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 595 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 596 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1 597 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 598 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2 599 #define E5_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 600 #define E5_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 601 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 602 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4 603 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 604 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5 605 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 606 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6 607 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 608 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7 609 u8 flags1; 610 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 611 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0 612 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 613 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1 614 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 615 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2 616 #define E5_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 617 #define E5_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3 618 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_COPY_CONDITION_LO_MASK 0x1 /* bit12 */ 619 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_COPY_CONDITION_LO_SHIFT 4 620 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_COPY_CONDITION_HI_MASK 0x1 /* bit13 */ 621 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_COPY_CONDITION_HI_SHIFT 5 622 #define E5_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 623 #define E5_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 624 #define E5_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 625 #define E5_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 626 u8 flags2; 627 #define E5_XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 628 #define E5_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0 629 #define E5_XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 630 #define E5_XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2 631 #define E5_XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 632 #define E5_XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4 633 #define E5_XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 634 #define E5_XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6 635 u8 flags3; 636 #define E5_XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 637 #define E5_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0 638 #define E5_XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 639 #define E5_XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2 640 #define E5_XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 641 #define E5_XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4 642 #define E5_XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 643 #define E5_XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6 644 u8 flags4; 645 #define E5_XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 646 #define E5_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0 647 #define E5_XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 648 #define E5_XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2 649 #define E5_XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 650 #define E5_XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4 651 #define E5_XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 652 #define E5_XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6 653 u8 flags5; 654 #define E5_XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 655 #define E5_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0 656 #define E5_XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 657 #define E5_XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2 658 #define E5_XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 659 #define E5_XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4 660 #define E5_XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 661 #define E5_XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6 662 u8 flags6; 663 #define E5_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 664 #define E5_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 665 #define E5_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 /* cf_array_cf */ 666 #define E5_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 667 #define E5_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 668 #define E5_XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4 669 #define E5_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 670 #define E5_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 671 u8 flags7; 672 #define E5_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 673 #define E5_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 674 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 675 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2 676 #define E5_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 677 #define E5_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4 678 #define E5_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 679 #define E5_XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6 680 #define E5_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 681 #define E5_XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7 682 u8 flags8; 683 #define E5_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 684 #define E5_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0 685 #define E5_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 686 #define E5_XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1 687 #define E5_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 688 #define E5_XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2 689 #define E5_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 690 #define E5_XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3 691 #define E5_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 692 #define E5_XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4 693 #define E5_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 694 #define E5_XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5 695 #define E5_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 696 #define E5_XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6 697 #define E5_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 698 #define E5_XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7 699 u8 flags9; 700 #define E5_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 701 #define E5_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0 702 #define E5_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 703 #define E5_XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1 704 #define E5_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 705 #define E5_XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2 706 #define E5_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 707 #define E5_XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3 708 #define E5_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 709 #define E5_XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4 710 #define E5_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 711 #define E5_XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5 712 #define E5_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 713 #define E5_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 714 #define E5_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 /* cf_array_cf_en */ 715 #define E5_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 716 u8 flags10; 717 #define E5_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 718 #define E5_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 719 #define E5_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 720 #define E5_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 721 #define E5_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 722 #define E5_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 723 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 724 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3 725 #define E5_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 726 #define E5_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 727 #define E5_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 728 #define E5_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 729 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 730 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6 731 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 732 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7 733 u8 flags11; 734 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 735 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0 736 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 737 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1 738 #define E5_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 739 #define E5_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 740 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 741 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3 742 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 743 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4 744 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 745 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5 746 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 747 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 748 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 749 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7 750 u8 flags12; 751 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 752 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0 753 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 754 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1 755 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 756 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 757 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 758 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 759 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 760 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4 761 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 762 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5 763 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 764 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6 765 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 766 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7 767 u8 flags13; 768 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 769 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0 770 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 771 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1 772 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 773 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 774 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 775 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 776 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 777 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 778 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 779 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 780 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 781 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 782 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 783 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 784 u8 flags14; 785 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 786 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 787 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 788 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 789 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 790 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 791 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 792 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 793 #define E5_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 794 #define E5_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 795 #define E5_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 796 #define E5_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 797 #define E5_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */ 798 #define E5_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 799 u8 edpm_vport /* byte2 */; 800 __le16 physical_q0 /* physical_q0 */; 801 __le16 tx_l2_edpm_usg_cnt /* physical_q1 */; 802 __le16 edpm_num_bds /* physical_q2 */; 803 __le16 tx_bd_cons /* word3 */; 804 __le16 tx_bd_prod /* word4 */; 805 __le16 tx_class /* word5 */; 806 __le16 conn_dpi /* conn_dpi */; 807 u8 byte3 /* byte3 */; 808 u8 byte4 /* byte4 */; 809 u8 byte5 /* byte5 */; 810 u8 byte6 /* byte6 */; 811 __le32 reg0 /* reg0 */; 812 __le32 reg1 /* reg1 */; 813 __le32 reg2 /* reg2 */; 814 __le32 reg3 /* reg3 */; 815 __le32 reg4 /* reg4 */; 816 __le32 reg5 /* cf_array0 */; 817 __le32 reg6 /* cf_array1 */; 818 u8 flags15; 819 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_REDIRECTION_CONDITION_LO_MASK 0x1 /* bit22 */ 820 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_REDIRECTION_CONDITION_LO_SHIFT 0 821 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_REDIRECTION_CONDITION_HI_MASK 0x1 /* bit23 */ 822 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_REDIRECTION_CONDITION_HI_SHIFT 1 823 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit24 */ 824 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 825 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf24 */ 826 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 827 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf24en */ 828 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 829 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule26en */ 830 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 831 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule27en */ 832 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 833 u8 byte7 /* byte7 */; 834 __le16 word7 /* word7 */; 835 __le16 word8 /* word8 */; 836 __le16 word9 /* word9 */; 837 __le16 word10 /* word10 */; 838 __le16 word11 /* word11 */; 839 __le32 reg7 /* reg7 */; 840 __le32 reg8 /* reg8 */; 841 __le32 reg9 /* reg9 */; 842 u8 byte8 /* byte8 */; 843 u8 byte9 /* byte9 */; 844 u8 byte10 /* byte10 */; 845 u8 byte11 /* byte11 */; 846 u8 byte12 /* byte12 */; 847 u8 byte13 /* byte13 */; 848 u8 byte14 /* byte14 */; 849 u8 byte15 /* byte15 */; 850 __le32 reg10 /* reg10 */; 851 __le32 reg11 /* reg11 */; 852 __le32 reg12 /* reg12 */; 853 __le32 reg13 /* reg13 */; 854 __le32 reg14 /* reg14 */; 855 __le32 reg15 /* reg15 */; 856 __le32 reg16 /* reg16 */; 857 __le32 reg17 /* reg17 */; 858 __le32 reg18 /* reg18 */; 859 __le32 reg19 /* reg19 */; 860 __le16 word12 /* word12 */; 861 __le16 word13 /* word13 */; 862 __le16 word14 /* word14 */; 863 __le16 word15 /* word15 */; 864 }; 865 866 struct e5_tstorm_eth_conn_ag_ctx 867 { 868 u8 byte0 /* cdu_validation */; 869 u8 byte1 /* state_and_core_id */; 870 u8 flags0; 871 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 872 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 873 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 874 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 875 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 876 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2 877 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 878 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3 879 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 880 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4 881 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 882 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5 883 #define E5_TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 884 #define E5_TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6 885 u8 flags1; 886 #define E5_TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 887 #define E5_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0 888 #define E5_TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 889 #define E5_TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2 890 #define E5_TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 891 #define E5_TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4 892 #define E5_TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 893 #define E5_TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6 894 u8 flags2; 895 #define E5_TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 896 #define E5_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0 897 #define E5_TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 898 #define E5_TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2 899 #define E5_TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 900 #define E5_TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4 901 #define E5_TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 902 #define E5_TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6 903 u8 flags3; 904 #define E5_TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 905 #define E5_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0 906 #define E5_TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 907 #define E5_TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2 908 #define E5_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 909 #define E5_TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4 910 #define E5_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 911 #define E5_TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5 912 #define E5_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 913 #define E5_TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6 914 #define E5_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 915 #define E5_TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7 916 u8 flags4; 917 #define E5_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 918 #define E5_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0 919 #define E5_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 920 #define E5_TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1 921 #define E5_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 922 #define E5_TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2 923 #define E5_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 924 #define E5_TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3 925 #define E5_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 926 #define E5_TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4 927 #define E5_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 928 #define E5_TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5 929 #define E5_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 930 #define E5_TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6 931 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 932 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 933 u8 flags5; 934 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 935 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 936 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 937 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 938 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 939 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 940 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 941 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 942 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 943 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 944 #define E5_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 /* rule6en */ 945 #define E5_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5 946 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 947 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 948 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 949 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 950 u8 flags6; 951 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 952 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 953 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 954 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 955 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 956 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 957 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 958 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 959 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 960 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 961 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 962 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 963 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 964 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 965 u8 byte2 /* byte2 */; 966 __le16 rx_bd_cons /* word0 */; 967 __le32 reg0 /* reg0 */; 968 __le32 reg1 /* reg1 */; 969 __le32 reg2 /* reg2 */; 970 __le32 reg3 /* reg3 */; 971 __le32 reg4 /* reg4 */; 972 __le32 reg5 /* reg5 */; 973 __le32 reg6 /* reg6 */; 974 __le32 reg7 /* reg7 */; 975 __le32 reg8 /* reg8 */; 976 u8 byte3 /* byte3 */; 977 u8 byte4 /* byte4 */; 978 u8 byte5 /* byte5 */; 979 u8 e4_reserved8 /* byte6 */; 980 __le16 rx_bd_prod /* word1 */; 981 __le16 word2 /* conn_dpi */; 982 __le32 reg9 /* reg9 */; 983 __le16 word3 /* word3 */; 984 __le16 e4_reserved9 /* word4 */; 985 }; 986 987 struct e5_ystorm_eth_conn_ag_ctx 988 { 989 u8 byte0 /* cdu_validation */; 990 u8 state_and_core_id /* state_and_core_id */; 991 u8 flags0; 992 #define E5_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 993 #define E5_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 994 #define E5_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 995 #define E5_YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 996 #define E5_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf0 */ 997 #define E5_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2 998 #define E5_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 /* cf1 */ 999 #define E5_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4 1000 #define E5_YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1001 #define E5_YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 1002 u8 flags1; 1003 #define E5_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf0en */ 1004 #define E5_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0 1005 #define E5_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */ 1006 #define E5_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1 1007 #define E5_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1008 #define E5_YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 1009 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1010 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 1011 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1012 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 1013 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1014 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 1015 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1016 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 1017 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1018 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 1019 u8 tx_q0_int_coallecing_timeset /* byte2 */; 1020 u8 byte3 /* byte3 */; 1021 __le16 word0 /* word0 */; 1022 __le32 terminate_spqe /* reg0 */; 1023 __le32 reg1 /* reg1 */; 1024 __le16 tx_bd_cons_upd /* word1 */; 1025 __le16 word2 /* word2 */; 1026 __le16 word3 /* word3 */; 1027 __le16 word4 /* word4 */; 1028 __le32 reg2 /* reg2 */; 1029 __le32 reg3 /* reg3 */; 1030 }; 1031 1032 struct e5_ustorm_eth_conn_ag_ctx 1033 { 1034 u8 byte0 /* cdu_validation */; 1035 u8 byte1 /* state_and_core_id */; 1036 u8 flags0; 1037 #define E5_USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1038 #define E5_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 1039 #define E5_USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1040 #define E5_USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 1041 #define E5_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3 /* timer0cf */ 1042 #define E5_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2 1043 #define E5_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3 /* timer1cf */ 1044 #define E5_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4 1045 #define E5_USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1046 #define E5_USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 1047 u8 flags1; 1048 #define E5_USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1049 #define E5_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0 1050 #define E5_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3 /* cf4 */ 1051 #define E5_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2 1052 #define E5_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3 /* cf5 */ 1053 #define E5_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4 1054 #define E5_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf6 */ 1055 #define E5_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6 1056 u8 flags2; 1057 #define E5_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf0en */ 1058 #define E5_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0 1059 #define E5_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */ 1060 #define E5_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1 1061 #define E5_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1062 #define E5_USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 1063 #define E5_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1064 #define E5_USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3 1065 #define E5_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1 /* cf4en */ 1066 #define E5_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4 1067 #define E5_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1 /* cf5en */ 1068 #define E5_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5 1069 #define E5_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf6en */ 1070 #define E5_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6 1071 #define E5_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1072 #define E5_USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 1073 u8 flags3; 1074 #define E5_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1075 #define E5_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 1076 #define E5_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1077 #define E5_USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 1078 #define E5_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1079 #define E5_USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 1080 #define E5_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1081 #define E5_USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 1082 #define E5_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1083 #define E5_USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 1084 #define E5_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1085 #define E5_USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5 1086 #define E5_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1087 #define E5_USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 1088 #define E5_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1089 #define E5_USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 1090 u8 flags4; 1091 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 1092 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1093 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 1094 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1095 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 1096 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1097 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 1098 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 1099 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 1100 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 1101 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 1102 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 1103 u8 byte2 /* byte2 */; 1104 __le16 word0 /* conn_dpi */; 1105 __le16 tx_bd_cons /* word1 */; 1106 __le32 reg0 /* reg0 */; 1107 __le32 reg1 /* reg1 */; 1108 __le32 reg2 /* reg2 */; 1109 __le32 tx_int_coallecing_timeset /* reg3 */; 1110 __le16 tx_drv_bd_cons /* word2 */; 1111 __le16 rx_drv_cqe_cons /* word3 */; 1112 }; 1113 1114 /* 1115 * eth connection context 1116 */ 1117 struct e5_eth_conn_context 1118 { 1119 struct tstorm_eth_conn_st_ctx tstorm_st_context /* tstorm storm context */; 1120 struct regpair tstorm_st_padding[2] /* padding */; 1121 struct pstorm_eth_conn_st_ctx pstorm_st_context /* pstorm storm context */; 1122 struct xstorm_eth_conn_st_ctx xstorm_st_context /* xstorm storm context */; 1123 struct regpair xstorm_st_padding[2] /* padding */; 1124 struct e5_xstorm_eth_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 1125 struct e5_tstorm_eth_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 1126 struct ystorm_eth_conn_st_ctx ystorm_st_context /* ystorm storm context */; 1127 struct e5_ystorm_eth_conn_ag_ctx ystorm_ag_context /* ystorm aggregative context */; 1128 struct e5_ustorm_eth_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 1129 struct ustorm_eth_conn_st_ctx ustorm_st_context /* ustorm storm context */; 1130 struct mstorm_eth_conn_st_ctx mstorm_st_context /* mstorm storm context */; 1131 }; 1132 1133 /* 1134 * Ethernet filter types: mac/vlan/pair 1135 */ 1136 enum eth_error_code 1137 { 1138 ETH_OK=0x00 /* command succeeded */, 1139 ETH_FILTERS_MAC_ADD_FAIL_FULL /* mac add filters command failed due to cam full state */, 1140 ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2 /* mac add filters command failed due to mtt2 full state */, 1141 ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2 /* mac add filters command failed due to duplicate mac address */, 1142 ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2 /* mac add filters command failed due to duplicate mac address */, 1143 ETH_FILTERS_MAC_DEL_FAIL_NOF /* mac delete filters command failed due to not found state */, 1144 ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2 /* mac delete filters command failed due to not found state */, 1145 ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2 /* mac delete filters command failed due to not found state */, 1146 ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC /* mac add filters command failed due to MAC Address of 00:00:00:00:00:00 */, 1147 ETH_FILTERS_VLAN_ADD_FAIL_FULL /* vlan add filters command failed due to cam full state */, 1148 ETH_FILTERS_VLAN_ADD_FAIL_DUP /* vlan add filters command failed due to duplicate VLAN filter */, 1149 ETH_FILTERS_VLAN_DEL_FAIL_NOF /* vlan delete filters command failed due to not found state */, 1150 ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1 /* vlan delete filters command failed due to not found state */, 1151 ETH_FILTERS_PAIR_ADD_FAIL_DUP /* pair add filters command failed due to duplicate request */, 1152 ETH_FILTERS_PAIR_ADD_FAIL_FULL /* pair add filters command failed due to full state */, 1153 ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC /* pair add filters command failed due to full state */, 1154 ETH_FILTERS_PAIR_DEL_FAIL_NOF /* pair add filters command failed due not found state */, 1155 ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1 /* pair add filters command failed due not found state */, 1156 ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC /* pair add filters command failed due to MAC Address of 00:00:00:00:00:00 */, 1157 ETH_FILTERS_VNI_ADD_FAIL_FULL /* vni add filters command failed due to cam full state */, 1158 ETH_FILTERS_VNI_ADD_FAIL_DUP /* vni add filters command failed due to duplicate VNI filter */, 1159 ETH_FILTERS_GFT_UPDATE_FAIL /* Fail update GFT filter. */, 1160 MAX_ETH_ERROR_CODE 1161 }; 1162 1163 /* 1164 * opcodes for the event ring 1165 */ 1166 enum eth_event_opcode 1167 { 1168 ETH_EVENT_UNUSED, 1169 ETH_EVENT_VPORT_START, 1170 ETH_EVENT_VPORT_UPDATE, 1171 ETH_EVENT_VPORT_STOP, 1172 ETH_EVENT_TX_QUEUE_START, 1173 ETH_EVENT_TX_QUEUE_STOP, 1174 ETH_EVENT_RX_QUEUE_START, 1175 ETH_EVENT_RX_QUEUE_UPDATE, 1176 ETH_EVENT_RX_QUEUE_STOP, 1177 ETH_EVENT_FILTERS_UPDATE, 1178 ETH_EVENT_RX_ADD_OPENFLOW_FILTER, 1179 ETH_EVENT_RX_DELETE_OPENFLOW_FILTER, 1180 ETH_EVENT_RX_CREATE_OPENFLOW_ACTION, 1181 ETH_EVENT_RX_ADD_UDP_FILTER, 1182 ETH_EVENT_RX_DELETE_UDP_FILTER, 1183 ETH_EVENT_RX_CREATE_GFT_ACTION, 1184 ETH_EVENT_RX_GFT_UPDATE_FILTER, 1185 ETH_EVENT_TX_QUEUE_UPDATE, 1186 MAX_ETH_EVENT_OPCODE 1187 }; 1188 1189 /* 1190 * Classify rule types in E2/E3 1191 */ 1192 enum eth_filter_action 1193 { 1194 ETH_FILTER_ACTION_UNUSED, 1195 ETH_FILTER_ACTION_REMOVE, 1196 ETH_FILTER_ACTION_ADD, 1197 ETH_FILTER_ACTION_REMOVE_ALL /* Remove all filters of given type and vport ID. */, 1198 MAX_ETH_FILTER_ACTION 1199 }; 1200 1201 /* 1202 * Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ 1203 */ 1204 struct eth_filter_cmd 1205 { 1206 u8 type /* Filter Type (MAC/VLAN/Pair/VNI) (use enum eth_filter_type) */; 1207 u8 vport_id /* the vport id */; 1208 u8 action /* filter command action: add/remove/replace (use enum eth_filter_action) */; 1209 u8 reserved0; 1210 __le32 vni; 1211 __le16 mac_lsb; 1212 __le16 mac_mid; 1213 __le16 mac_msb; 1214 __le16 vlan_id; 1215 }; 1216 1217 /* 1218 * $$KEEP_ENDIANNESS$$ 1219 */ 1220 struct eth_filter_cmd_header 1221 { 1222 u8 rx /* If set, apply these commands to the RX path */; 1223 u8 tx /* If set, apply these commands to the TX path */; 1224 u8 cmd_cnt /* Number of filter commands */; 1225 u8 assert_on_error /* 0 - dont assert in case of filter configuration error. Just return an error code. 1 - assert in case of filter configuration error. */; 1226 u8 reserved1[4]; 1227 }; 1228 1229 /* 1230 * Ethernet filter types: mac/vlan/pair 1231 */ 1232 enum eth_filter_type 1233 { 1234 ETH_FILTER_TYPE_UNUSED, 1235 ETH_FILTER_TYPE_MAC /* Add/remove a MAC address */, 1236 ETH_FILTER_TYPE_VLAN /* Add/remove a VLAN */, 1237 ETH_FILTER_TYPE_PAIR /* Add/remove a MAC-VLAN pair */, 1238 ETH_FILTER_TYPE_INNER_MAC /* Add/remove a inner MAC address */, 1239 ETH_FILTER_TYPE_INNER_VLAN /* Add/remove a inner VLAN */, 1240 ETH_FILTER_TYPE_INNER_PAIR /* Add/remove a inner MAC-VLAN pair */, 1241 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR /* Add/remove a inner MAC-VNI pair */, 1242 ETH_FILTER_TYPE_MAC_VNI_PAIR /* Add/remove a MAC-VNI pair */, 1243 ETH_FILTER_TYPE_VNI /* Add/remove a VNI */, 1244 MAX_ETH_FILTER_TYPE 1245 }; 1246 1247 /* 1248 * eth IPv4 Fragment Type 1249 */ 1250 enum eth_ipv4_frag_type 1251 { 1252 ETH_IPV4_NOT_FRAG /* IPV4 Packet Not Fragmented */, 1253 ETH_IPV4_FIRST_FRAG /* First Fragment of IPv4 Packet (contains headers) */, 1254 ETH_IPV4_NON_FIRST_FRAG /* Non-First Fragment of IPv4 Packet (does not contain headers) */, 1255 MAX_ETH_IPV4_FRAG_TYPE 1256 }; 1257 1258 /* 1259 * eth IPv4 Fragment Type 1260 */ 1261 enum eth_ip_type 1262 { 1263 ETH_IPV4 /* IPv4 */, 1264 ETH_IPV6 /* IPv6 */, 1265 MAX_ETH_IP_TYPE 1266 }; 1267 1268 /* 1269 * Ethernet Ramrod Command IDs 1270 */ 1271 enum eth_ramrod_cmd_id 1272 { 1273 ETH_RAMROD_UNUSED, 1274 ETH_RAMROD_VPORT_START /* VPort Start Ramrod */, 1275 ETH_RAMROD_VPORT_UPDATE /* VPort Update Ramrod */, 1276 ETH_RAMROD_VPORT_STOP /* VPort Stop Ramrod */, 1277 ETH_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */, 1278 ETH_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */, 1279 ETH_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */, 1280 ETH_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */, 1281 ETH_RAMROD_FILTERS_UPDATE /* Add or Remove Mac/Vlan/Pair filters */, 1282 ETH_RAMROD_RX_QUEUE_UPDATE /* RX Queue Update Ramrod */, 1283 ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION /* RX - Create an Openflow Action */, 1284 ETH_RAMROD_RX_ADD_OPENFLOW_FILTER /* RX - Add an Openflow Filter to the Searcher */, 1285 ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER /* RX - Delete an Openflow Filter to the Searcher */, 1286 ETH_RAMROD_RX_ADD_UDP_FILTER /* RX - Add a UDP Filter to the Searcher */, 1287 ETH_RAMROD_RX_DELETE_UDP_FILTER /* RX - Delete a UDP Filter to the Searcher */, 1288 ETH_RAMROD_RX_CREATE_GFT_ACTION /* RX - Create a Gft Action */, 1289 ETH_RAMROD_GFT_UPDATE_FILTER /* RX - Add/Delete a GFT Filter to the Searcher */, 1290 ETH_RAMROD_TX_QUEUE_UPDATE /* TX Queue Update Ramrod */, 1291 MAX_ETH_RAMROD_CMD_ID 1292 }; 1293 1294 /* 1295 * return code from eth sp ramrods 1296 */ 1297 struct eth_return_code 1298 { 1299 u8 value; 1300 #define ETH_RETURN_CODE_ERR_CODE_MASK 0x1F /* error code (use enum eth_error_code) */ 1301 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0 1302 #define ETH_RETURN_CODE_RESERVED_MASK 0x3 1303 #define ETH_RETURN_CODE_RESERVED_SHIFT 5 1304 #define ETH_RETURN_CODE_RX_TX_MASK 0x1 /* rx path - 0, tx path - 1 */ 1305 #define ETH_RETURN_CODE_RX_TX_SHIFT 7 1306 }; 1307 1308 /* 1309 * What to do in case an error occurs 1310 */ 1311 enum eth_tx_err 1312 { 1313 ETH_TX_ERR_DROP /* Drop erroneous packet. */, 1314 ETH_TX_ERR_ASSERT_MALICIOUS /* Assert an interrupt for PF, declare as malicious for VF */, 1315 MAX_ETH_TX_ERR 1316 }; 1317 1318 /* 1319 * Array of the different error type behaviors 1320 */ 1321 struct eth_tx_err_vals 1322 { 1323 __le16 values; 1324 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1 /* Wrong VLAN insertion mode (use enum eth_tx_err) */ 1325 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0 1326 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1 /* Packet is below minimal size (use enum eth_tx_err) */ 1327 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1 1328 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1 /* Vport has sent spoofed packet (use enum eth_tx_err) */ 1329 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2 1330 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1 /* Packet with illegal type of inband tag (use enum eth_tx_err) */ 1331 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3 1332 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1 /* Packet marked for VLAN insertion when inband tag is present (use enum eth_tx_err) */ 1333 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4 1334 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1 /* Non LSO packet larger than MTU (use enum eth_tx_err) */ 1335 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5 1336 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1 /* VF/PF has sent LLDP/PFC or any other type of control packet which is not allowed to (use enum eth_tx_err) */ 1337 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6 1338 #define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF 1339 #define ETH_TX_ERR_VALS_RESERVED_SHIFT 7 1340 }; 1341 1342 /* 1343 * vport rss configuration data 1344 */ 1345 struct eth_vport_rss_config 1346 { 1347 __le16 capabilities; 1348 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1 /* configuration of the IpV4 2-tuple capability */ 1349 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0 1350 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1 /* configuration of the IpV6 2-tuple capability */ 1351 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1 1352 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1 /* configuration of the IpV4 4-tuple capability for TCP */ 1353 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2 1354 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1 /* configuration of the IpV6 4-tuple capability for TCP */ 1355 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3 1356 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1 /* configuration of the IpV4 4-tuple capability for UDP */ 1357 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4 1358 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1 /* configuration of the IpV6 4-tuple capability for UDP */ 1359 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5 1360 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1 /* configuration of the 5-tuple capability */ 1361 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6 1362 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF /* if set update the rss keys */ 1363 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7 1364 u8 rss_id /* The RSS engine ID. Must be allocated to each vport with RSS enabled. Total number of RSS engines is ETH_RSS_ENGINE_NUM_ , according to chip type. */; 1365 u8 rss_mode /* The RSS mode for this function (use enum eth_vport_rss_mode) */; 1366 u8 update_rss_key /* if set update the rss key */; 1367 u8 update_rss_ind_table /* if set update the indirection table values */; 1368 u8 update_rss_capabilities /* if set update the capabilities and indirection table size. */; 1369 u8 tbl_size /* rss mask (Tbl size) */; 1370 __le32 reserved2[2]; 1371 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM] /* RSS indirection table */; 1372 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS] /* RSS key supplied to us by OS */; 1373 __le32 reserved3[2]; 1374 }; 1375 1376 /* 1377 * eth vport RSS mode 1378 */ 1379 enum eth_vport_rss_mode 1380 { 1381 ETH_VPORT_RSS_MODE_DISABLED /* RSS Disabled */, 1382 ETH_VPORT_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */, 1383 MAX_ETH_VPORT_RSS_MODE 1384 }; 1385 1386 /* 1387 * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ 1388 */ 1389 struct eth_vport_rx_mode 1390 { 1391 __le16 state; 1392 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1 /* drop all unicast packets */ 1393 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0 1394 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1 /* accept all unicast packets (subject to vlan) */ 1395 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1 1396 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1 /* accept all unmatched unicast packets */ 1397 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2 1398 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1 /* drop all multicast packets */ 1399 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3 1400 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1 /* accept all multicast packets (subject to vlan) */ 1401 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4 1402 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 /* accept all broadcast packets (subject to vlan) */ 1403 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5 1404 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF 1405 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6 1406 }; 1407 1408 /* 1409 * Command for setting tpa parameters 1410 */ 1411 struct eth_vport_tpa_param 1412 { 1413 u8 tpa_ipv4_en_flg /* Enable TPA for IPv4 packets */; 1414 u8 tpa_ipv6_en_flg /* Enable TPA for IPv6 packets */; 1415 u8 tpa_ipv4_tunn_en_flg /* Enable TPA for IPv4 over tunnel */; 1416 u8 tpa_ipv6_tunn_en_flg /* Enable TPA for IPv6 over tunnel */; 1417 u8 tpa_pkt_split_flg /* If set, start each TPA segment on new BD (GRO mode). One BD per segment allowed. */; 1418 u8 tpa_hdr_data_split_flg /* If set, put header of first TPA segment on first BD and data on second BD. */; 1419 u8 tpa_gro_consistent_flg /* If set, GRO data consistent will checked for TPA continue */; 1420 u8 tpa_max_aggs_num /* maximum number of opened aggregations per v-port */; 1421 __le16 tpa_max_size /* maximal size for the aggregated TPA packets */; 1422 __le16 tpa_min_size_to_start /* minimum TCP payload size for a packet to start aggregation */; 1423 __le16 tpa_min_size_to_cont /* minimum TCP payload size for a packet to continue aggregation */; 1424 u8 max_buff_num /* maximal number of buffers that can be used for one aggregation */; 1425 u8 reserved; 1426 }; 1427 1428 /* 1429 * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ 1430 */ 1431 struct eth_vport_tx_mode 1432 { 1433 __le16 state; 1434 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1 /* drop all unicast packets */ 1435 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0 1436 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1 /* accept all unicast packets (subject to vlan) */ 1437 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1 1438 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1 /* drop all multicast packets */ 1439 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2 1440 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1 /* accept all multicast packets (subject to vlan) */ 1441 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3 1442 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 /* accept all broadcast packets (subject to vlan) */ 1443 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4 1444 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF 1445 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5 1446 }; 1447 1448 /* 1449 * GFT filter update action type. 1450 */ 1451 enum gft_filter_update_action 1452 { 1453 GFT_ADD_FILTER, 1454 GFT_DELETE_FILTER, 1455 MAX_GFT_FILTER_UPDATE_ACTION 1456 }; 1457 1458 /* 1459 * Ramrod data for rx add openflow filter 1460 */ 1461 struct rx_add_openflow_filter_data 1462 { 1463 __le16 action_icid /* CID of Action to run for this filter */; 1464 u8 priority /* Searcher String - Packet priority */; 1465 u8 reserved0; 1466 __le32 tenant_id /* Searcher String - Tenant ID */; 1467 __le16 dst_mac_hi /* Searcher String - Destination Mac Bytes 0 to 1 */; 1468 __le16 dst_mac_mid /* Searcher String - Destination Mac Bytes 2 to 3 */; 1469 __le16 dst_mac_lo /* Searcher String - Destination Mac Bytes 4 to 5 */; 1470 __le16 src_mac_hi /* Searcher String - Source Mac 0 to 1 */; 1471 __le16 src_mac_mid /* Searcher String - Source Mac 2 to 3 */; 1472 __le16 src_mac_lo /* Searcher String - Source Mac 4 to 5 */; 1473 __le16 vlan_id /* Searcher String - Vlan ID */; 1474 __le16 l2_eth_type /* Searcher String - Last L2 Ethertype */; 1475 u8 ipv4_dscp /* Searcher String - IPv4 6 MSBs of the TOS Field */; 1476 u8 ipv4_frag_type /* Searcher String - IPv4 Fragmentation Type (use enum eth_ipv4_frag_type) */; 1477 u8 ipv4_over_ip /* Searcher String - IPv4 Over IP Type */; 1478 u8 tenant_id_exists /* Searcher String - Tenant ID Exists */; 1479 __le32 ipv4_dst_addr /* Searcher String - IPv4 Destination Address */; 1480 __le32 ipv4_src_addr /* Searcher String - IPv4 Source Address */; 1481 __le16 l4_dst_port /* Searcher String - TCP/UDP Destination Port */; 1482 __le16 l4_src_port /* Searcher String - TCP/UDP Source Port */; 1483 }; 1484 1485 /* 1486 * Ramrod data for rx create gft action 1487 */ 1488 struct rx_create_gft_action_data 1489 { 1490 u8 vport_id /* Vport Id of GFT Action */; 1491 u8 reserved[7]; 1492 }; 1493 1494 /* 1495 * Ramrod data for rx create openflow action 1496 */ 1497 struct rx_create_openflow_action_data 1498 { 1499 u8 vport_id /* ID of RX queue */; 1500 u8 reserved[7]; 1501 }; 1502 1503 /* 1504 * Ramrod data for rx queue start ramrod 1505 */ 1506 struct rx_queue_start_ramrod_data 1507 { 1508 __le16 rx_queue_id /* ID of RX queue */; 1509 __le16 num_of_pbl_pages /* Number of pages in CQE PBL */; 1510 __le16 bd_max_bytes /* maximal bytes that can be places on the bd */; 1511 __le16 sb_id /* Status block ID */; 1512 u8 sb_index /* index of the protocol index */; 1513 u8 vport_id /* ID of virtual port */; 1514 u8 default_rss_queue_flg /* set queue as default rss queue if set */; 1515 u8 complete_cqe_flg /* post completion to the CQE ring if set */; 1516 u8 complete_event_flg /* post completion to the event ring if set */; 1517 u8 stats_counter_id /* Statistics counter ID */; 1518 u8 pin_context /* Pin context in CCFC to improve performance */; 1519 u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD/SGE fetch */; 1520 u8 pxp_tph_valid_pkt /* PXP command TPH Valid - for packet placement */; 1521 u8 pxp_st_hint /* PXP command Steering tag hint. Use enum pxp_tph_st_hint */; 1522 __le16 pxp_st_index /* PXP command Steering tag index */; 1523 u8 pmd_mode /* Indicates that current queue belongs to poll-mode driver */; 1524 u8 notify_en /* Indicates that the current queue is using the TX notification queue mechanism - should be set only for PMD queue */; 1525 u8 toggle_val /* Initial value for the toggle valid bit - used in PMD mode */; 1526 u8 vf_rx_prod_index /* Index of RX producers in VF zone. Used for VF only. */; 1527 u8 vf_rx_prod_use_zone_a /* Backward compatibility mode. If set, unprotected mStorm queue zone will used for VF RX producers instead of VF zone. */; 1528 u8 reserved[5]; 1529 __le16 reserved1 /* FW reserved. */; 1530 struct regpair cqe_pbl_addr /* Base address on host of CQE PBL */; 1531 struct regpair bd_base /* bd address of the first bd page */; 1532 struct regpair reserved2 /* FW reserved. */; 1533 }; 1534 1535 /* 1536 * Ramrod data for rx queue stop ramrod 1537 */ 1538 struct rx_queue_stop_ramrod_data 1539 { 1540 __le16 rx_queue_id /* ID of RX queue */; 1541 u8 complete_cqe_flg /* post completion to the CQE ring if set */; 1542 u8 complete_event_flg /* post completion to the event ring if set */; 1543 u8 vport_id /* ID of virtual port */; 1544 u8 reserved[3]; 1545 }; 1546 1547 /* 1548 * Ramrod data for rx queue update ramrod 1549 */ 1550 struct rx_queue_update_ramrod_data 1551 { 1552 __le16 rx_queue_id /* ID of RX queue */; 1553 u8 complete_cqe_flg /* post completion to the CQE ring if set */; 1554 u8 complete_event_flg /* post completion to the event ring if set */; 1555 u8 vport_id /* ID of virtual port */; 1556 u8 set_default_rss_queue /* If set, update default rss queue to this RX queue. */; 1557 u8 reserved[3]; 1558 u8 reserved1 /* FW reserved. */; 1559 u8 reserved2 /* FW reserved. */; 1560 u8 reserved3 /* FW reserved. */; 1561 __le16 reserved4 /* FW reserved. */; 1562 __le16 reserved5 /* FW reserved. */; 1563 struct regpair reserved6 /* FW reserved. */; 1564 }; 1565 1566 /* 1567 * Ramrod data for rx Add UDP Filter 1568 */ 1569 struct rx_udp_filter_data 1570 { 1571 __le16 action_icid /* CID of Action to run for this filter */; 1572 __le16 vlan_id /* Searcher String - Vlan ID */; 1573 u8 ip_type /* Searcher String - IP Type (use enum eth_ip_type) */; 1574 u8 tenant_id_exists /* Searcher String - Tenant ID Exists */; 1575 __le16 reserved1; 1576 __le32 ip_dst_addr[4] /* Searcher String - IP Destination Address, for IPv4 use ip_dst_addr[0] only */; 1577 __le32 ip_src_addr[4] /* Searcher String - IP Source Address, for IPv4 use ip_dst_addr[0] only */; 1578 __le16 udp_dst_port /* Searcher String - UDP Destination Port */; 1579 __le16 udp_src_port /* Searcher String - UDP Source Port */; 1580 __le32 tenant_id /* Searcher String - Tenant ID */; 1581 }; 1582 1583 /* 1584 * add or delete GFT filter - filter is packet header of type of packet wished to pass certain FW flow 1585 */ 1586 struct rx_update_gft_filter_data 1587 { 1588 struct regpair pkt_hdr_addr /* Pointer to Packet Header That Defines GFT Filter */; 1589 __le16 pkt_hdr_length /* Packet Header Length */; 1590 __le16 action_icid /* Action icid. Valid if action_icid_valid flag set. */; 1591 __le16 rx_qid /* RX queue ID. Valid if rx_qid_valid set. */; 1592 __le16 flow_id /* RX flow ID. Valid if flow_id_valid set. */; 1593 __le16 vport_id /* RX vport Id. For drop flow, set to ETH_GFT_TRASHCAN_VPORT. */; 1594 u8 action_icid_valid /* If set, action_icid will used for GFT filter update. */; 1595 u8 rx_qid_valid /* If set, rx_qid will used for traffic steering, in additional to vport_id. flow_id_valid must be cleared. If cleared, queue ID will selected by RSS. */; 1596 u8 flow_id_valid /* If set, flow_id will reported by CQE, rx_qid_valid must be cleared. If cleared, flow_id 0 will reported by CQE. */; 1597 u8 filter_action /* Use to set type of action on filter (use enum gft_filter_update_action) */; 1598 u8 assert_on_error /* 0 - dont assert in case of error. Just return an error code. 1 - assert in case of error. */; 1599 u8 reserved; 1600 }; 1601 1602 /* 1603 * Ramrod data for tx queue start ramrod 1604 */ 1605 struct tx_queue_start_ramrod_data 1606 { 1607 __le16 sb_id /* Status block ID */; 1608 u8 sb_index /* Status block protocol index */; 1609 u8 vport_id /* VPort ID */; 1610 u8 reserved0 /* FW reserved. (qcn_rl_en) */; 1611 u8 stats_counter_id /* Statistics counter ID to use */; 1612 __le16 qm_pq_id /* QM PQ ID */; 1613 u8 flags; 1614 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1 /* 0: Enable QM opportunistic flow. 1: Disable QM opportunistic flow */ 1615 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0 1616 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1 /* If set, Test Mode - packets will be duplicated by Xstorm handler */ 1617 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1 1618 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1 /* If set, Test Mode - packets destination will be determined by dest_port_mode field from Tx BD */ 1619 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2 1620 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1 /* Indicates that current queue belongs to poll-mode driver */ 1621 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3 1622 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1 /* Indicates that the current queue is using the TX notification queue mechanism - should be set only for PMD queue */ 1623 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4 1624 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1 /* Pin context in CCFC to improve performance */ 1625 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5 1626 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3 1627 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6 1628 u8 pxp_st_hint /* PXP command Steering tag hint (use enum pxp_tph_st_hint) */; 1629 u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD fetch */; 1630 u8 pxp_tph_valid_pkt /* PXP command TPH Valid - for packet fetch */; 1631 __le16 pxp_st_index /* PXP command Steering tag index */; 1632 __le16 comp_agg_size /* TX completion min agg size - for PMD queues */; 1633 __le16 queue_zone_id /* queue zone ID to use */; 1634 __le16 reserved2 /* FW reserved. (test_dup_count) */; 1635 __le16 pbl_size /* Number of BD pages pointed by PBL */; 1636 __le16 tx_queue_id /* unique Queue ID - currently used only by PMD flow */; 1637 __le16 same_as_last_id /* Unique Same-As-Last Resource ID - improves performance for same-as-last packets per connection (range 0..ETH_TX_NUM_SAME_AS_LAST_ENTRIES-1 IDs available) */; 1638 __le16 reserved[3]; 1639 struct regpair pbl_base_addr /* address of the pbl page */; 1640 struct regpair bd_cons_address /* BD consumer address in host - for PMD queues */; 1641 }; 1642 1643 /* 1644 * Ramrod data for tx queue stop ramrod 1645 */ 1646 struct tx_queue_stop_ramrod_data 1647 { 1648 __le16 reserved[4]; 1649 }; 1650 1651 /* 1652 * Ramrod data for tx queue update ramrod 1653 */ 1654 struct tx_queue_update_ramrod_data 1655 { 1656 __le16 update_qm_pq_id_flg /* Flag to Update QM PQ ID */; 1657 __le16 qm_pq_id /* Updated QM PQ ID */; 1658 __le32 reserved0; 1659 struct regpair reserved1[5]; 1660 }; 1661 1662 /* 1663 * Ramrod data for vport update ramrod 1664 */ 1665 struct vport_filter_update_ramrod_data 1666 { 1667 struct eth_filter_cmd_header filter_cmd_hdr /* Header for Filter Commands (RX/TX, Add/Remove/Replace, etc) */; 1668 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT] /* Filter Commands */; 1669 }; 1670 1671 /* 1672 * Ramrod data for vport start ramrod 1673 */ 1674 struct vport_start_ramrod_data 1675 { 1676 u8 vport_id; 1677 u8 sw_fid; 1678 __le16 mtu; 1679 u8 drop_ttl0_en /* if set, drop packet with ttl=0 */; 1680 u8 inner_vlan_removal_en; 1681 struct eth_vport_rx_mode rx_mode /* Rx filter data */; 1682 struct eth_vport_tx_mode tx_mode /* Tx filter data */; 1683 struct eth_vport_tpa_param tpa_param /* TPA configuration parameters */; 1684 __le16 default_vlan /* Default Vlan value to be forced by FW */; 1685 u8 tx_switching_en /* Tx switching is enabled for current Vport */; 1686 u8 anti_spoofing_en /* Anti-spoofing verification is set for current Vport */; 1687 u8 default_vlan_en /* If set, the default Vlan value is forced by the FW */; 1688 u8 handle_ptp_pkts /* If set, the vport handles PTP Timesync Packets */; 1689 u8 silent_vlan_removal_en /* If enable then innerVlan will be striped and not written to cqe */; 1690 u8 untagged /* If set untagged filter (vlan0) is added to current Vport, otherwise port is marked as any-vlan */; 1691 struct eth_tx_err_vals tx_err_behav /* Desired behavior per TX error type */; 1692 u8 zero_placement_offset /* If set, ETH header padding will not inserted. placement_offset will be zero. */; 1693 u8 ctl_frame_mac_check_en /* If set, control frames will be filtered according to MAC check. */; 1694 u8 ctl_frame_ethtype_check_en /* If set, control frames will be filtered according to ethtype check. */; 1695 u8 reserved[1]; 1696 }; 1697 1698 /* 1699 * Ramrod data for vport stop ramrod 1700 */ 1701 struct vport_stop_ramrod_data 1702 { 1703 u8 vport_id; 1704 u8 reserved[7]; 1705 }; 1706 1707 /* 1708 * Ramrod data for vport update ramrod 1709 */ 1710 struct vport_update_ramrod_data_cmn 1711 { 1712 u8 vport_id; 1713 u8 update_rx_active_flg /* set if rx active flag should be handled */; 1714 u8 rx_active_flg /* rx active flag value */; 1715 u8 update_tx_active_flg /* set if tx active flag should be handled */; 1716 u8 tx_active_flg /* tx active flag value */; 1717 u8 update_rx_mode_flg /* set if rx state data should be handled */; 1718 u8 update_tx_mode_flg /* set if tx state data should be handled */; 1719 u8 update_approx_mcast_flg /* set if approx. mcast data should be handled */; 1720 u8 update_rss_flg /* set if rss data should be handled */; 1721 u8 update_inner_vlan_removal_en_flg /* set if inner_vlan_removal_en should be handled */; 1722 u8 inner_vlan_removal_en; 1723 u8 update_tpa_param_flg /* set if tpa parameters should be handled, TPA must be disable before */; 1724 u8 update_tpa_en_flg /* set if tpa enable changes */; 1725 u8 update_tx_switching_en_flg /* set if tx switching en flag should be handled */; 1726 u8 tx_switching_en /* tx switching en value */; 1727 u8 update_anti_spoofing_en_flg /* set if anti spoofing flag should be handled */; 1728 u8 anti_spoofing_en /* Anti-spoofing verification en value */; 1729 u8 update_handle_ptp_pkts /* set if handle_ptp_pkts should be handled. */; 1730 u8 handle_ptp_pkts /* If set, the vport handles PTP Timesync Packets */; 1731 u8 update_default_vlan_en_flg /* If set, the default Vlan enable flag is updated */; 1732 u8 default_vlan_en /* If set, the default Vlan value is forced by the FW */; 1733 u8 update_default_vlan_flg /* If set, the default Vlan value is updated */; 1734 __le16 default_vlan /* Default Vlan value to be forced by FW */; 1735 u8 update_accept_any_vlan_flg /* set if accept_any_vlan should be handled */; 1736 u8 accept_any_vlan /* accept_any_vlan updated value */; 1737 u8 silent_vlan_removal_en /* Set to remove vlan silently, update_inner_vlan_removal_en_flg must be enabled as well. If Rx is in noSgl mode send rx_queue_update_ramrod_data */; 1738 u8 update_mtu_flg /* If set, MTU will be updated. Vport must be not active. */; 1739 __le16 mtu /* New MTU value. Used if update_mtu_flg are set */; 1740 u8 update_ctl_frame_checks_en_flg /* If set, ctl_frame_mac_check_en and ctl_frame_ethtype_check_en will be updated */; 1741 u8 ctl_frame_mac_check_en /* If set, control frames will be filtered according to MAC check. */; 1742 u8 ctl_frame_ethtype_check_en /* If set, control frames will be filtered according to ethtype check. */; 1743 u8 reserved[15]; 1744 }; 1745 1746 struct vport_update_ramrod_mcast 1747 { 1748 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS] /* multicast bins */; 1749 }; 1750 1751 /* 1752 * Ramrod data for vport update ramrod 1753 */ 1754 struct vport_update_ramrod_data 1755 { 1756 struct vport_update_ramrod_data_cmn common /* Common data for all vport update ramrods */; 1757 struct eth_vport_rx_mode rx_mode /* vport rx mode bitmap */; 1758 struct eth_vport_tx_mode tx_mode /* vport tx mode bitmap */; 1759 __le32 reserved[3]; 1760 struct eth_vport_tpa_param tpa_param /* TPA configuration parameters */; 1761 struct vport_update_ramrod_mcast approx_mcast; 1762 struct eth_vport_rss_config rss_config /* rss config data */; 1763 }; 1764 1765 struct E4XstormEthConnAgCtxDqExtLdPart 1766 { 1767 u8 reserved0 /* cdu_validation */; 1768 u8 state /* state */; 1769 u8 flags0; 1770 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1771 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 1772 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 1773 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1 1774 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 1775 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2 1776 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 1777 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 1778 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1 /* bit4 */ 1779 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4 1780 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1 /* cf_array_active */ 1781 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5 1782 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1 /* bit6 */ 1783 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6 1784 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1 /* bit7 */ 1785 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7 1786 u8 flags1; 1787 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1 /* bit8 */ 1788 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0 1789 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1 /* bit9 */ 1790 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1 1791 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1 /* bit10 */ 1792 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2 1793 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 /* bit11 */ 1794 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 1795 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_MASK 0x1 /* bit12 */ 1796 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_SHIFT 4 1797 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_MASK 0x1 /* bit13 */ 1798 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_SHIFT 5 1799 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 1800 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6 1801 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 1802 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7 1803 u8 flags2; 1804 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3 /* timer0cf */ 1805 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0 1806 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3 /* timer1cf */ 1807 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2 1808 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3 /* timer2cf */ 1809 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4 1810 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3 /* timer_stop_all */ 1811 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6 1812 u8 flags3; 1813 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3 /* cf4 */ 1814 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0 1815 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3 /* cf5 */ 1816 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2 1817 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3 /* cf6 */ 1818 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4 1819 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3 /* cf7 */ 1820 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6 1821 u8 flags4; 1822 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3 /* cf8 */ 1823 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0 1824 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3 /* cf9 */ 1825 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2 1826 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3 /* cf10 */ 1827 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4 1828 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3 /* cf11 */ 1829 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6 1830 u8 flags5; 1831 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3 /* cf12 */ 1832 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0 1833 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3 /* cf13 */ 1834 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2 1835 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3 /* cf14 */ 1836 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4 1837 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3 /* cf15 */ 1838 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6 1839 u8 flags6; 1840 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 1841 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0 1842 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3 /* cf_array_cf */ 1843 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2 1844 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3 /* cf18 */ 1845 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4 1846 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3 /* cf19 */ 1847 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6 1848 u8 flags7; 1849 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3 /* cf20 */ 1850 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0 1851 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3 /* cf21 */ 1852 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2 1853 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 /* cf22 */ 1854 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 1855 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 /* cf0en */ 1856 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 1857 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 /* cf1en */ 1858 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 1859 u8 flags8; 1860 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 /* cf2en */ 1861 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 1862 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 /* cf3en */ 1863 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 1864 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 /* cf4en */ 1865 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 1866 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 /* cf5en */ 1867 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 1868 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 /* cf6en */ 1869 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 1870 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1 /* cf7en */ 1871 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5 1872 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 /* cf8en */ 1873 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 1874 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 /* cf9en */ 1875 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 1876 u8 flags9; 1877 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 /* cf10en */ 1878 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 1879 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 /* cf11en */ 1880 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 1881 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 /* cf12en */ 1882 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 1883 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 /* cf13en */ 1884 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 1885 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 /* cf14en */ 1886 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 1887 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 /* cf15en */ 1888 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 1889 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 1890 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6 1891 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1 /* cf_array_cf_en */ 1892 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7 1893 u8 flags10; 1894 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1 /* cf18en */ 1895 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0 1896 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 1897 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1 1898 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 1899 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2 1900 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1 /* cf21en */ 1901 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3 1902 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1903 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 1904 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 1905 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5 1906 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1 /* rule0en */ 1907 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6 1908 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1 /* rule1en */ 1909 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7 1910 u8 flags11; 1911 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1 /* rule2en */ 1912 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0 1913 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1 /* rule3en */ 1914 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1 1915 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 1916 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2 1917 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 /* rule5en */ 1918 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 1919 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 /* rule6en */ 1920 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 1921 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 /* rule7en */ 1922 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 1923 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 /* rule8en */ 1924 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 1925 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 /* rule9en */ 1926 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 1927 u8 flags12; 1928 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 /* rule10en */ 1929 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 1930 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 /* rule11en */ 1931 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 1932 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 /* rule12en */ 1933 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 1934 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 /* rule13en */ 1935 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 1936 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 /* rule14en */ 1937 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 1938 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 /* rule15en */ 1939 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 1940 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 /* rule16en */ 1941 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 1942 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 /* rule17en */ 1943 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 1944 u8 flags13; 1945 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 /* rule18en */ 1946 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 1947 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 /* rule19en */ 1948 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 1949 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 /* rule20en */ 1950 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 1951 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 /* rule21en */ 1952 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 1953 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 /* rule22en */ 1954 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 1955 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 /* rule23en */ 1956 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 1957 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 /* rule24en */ 1958 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 1959 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 /* rule25en */ 1960 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 1961 u8 flags14; 1962 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 1963 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0 1964 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 1965 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1 1966 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 1967 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2 1968 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 1969 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3 1970 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 1971 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4 1972 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 1973 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 1974 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3 /* cf23 */ 1975 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6 1976 u8 edpm_event_id /* byte2 */; 1977 __le16 physical_q0 /* physical_q0 */; 1978 __le16 e5_reserved1 /* physical_q1 */; 1979 __le16 edpm_num_bds /* physical_q2 */; 1980 __le16 tx_bd_cons /* word3 */; 1981 __le16 tx_bd_prod /* word4 */; 1982 __le16 tx_class /* word5 */; 1983 __le16 conn_dpi /* conn_dpi */; 1984 u8 byte3 /* byte3 */; 1985 u8 byte4 /* byte4 */; 1986 u8 byte5 /* byte5 */; 1987 u8 byte6 /* byte6 */; 1988 __le32 reg0 /* reg0 */; 1989 __le32 reg1 /* reg1 */; 1990 __le32 reg2 /* reg2 */; 1991 __le32 reg3 /* reg3 */; 1992 __le32 reg4 /* reg4 */; 1993 }; 1994 1995 struct e4_mstorm_eth_conn_ag_ctx 1996 { 1997 u8 byte0 /* cdu_validation */; 1998 u8 byte1 /* state */; 1999 u8 flags0; 2000 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2001 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 2002 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2003 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 2004 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2005 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2 2006 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2007 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4 2008 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2009 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 2010 u8 flags1; 2011 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2012 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0 2013 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2014 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1 2015 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2016 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 2017 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2018 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 2019 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2020 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 2021 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2022 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 2023 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2024 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 2025 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2026 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 2027 __le16 word0 /* word0 */; 2028 __le16 word1 /* word1 */; 2029 __le32 reg0 /* reg0 */; 2030 __le32 reg1 /* reg1 */; 2031 }; 2032 2033 struct e4_xstorm_eth_hw_conn_ag_ctx 2034 { 2035 u8 reserved0 /* cdu_validation */; 2036 u8 state /* state */; 2037 u8 flags0; 2038 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2039 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 2040 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 2041 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1 2042 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 2043 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2 2044 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 2045 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 2046 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 2047 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4 2048 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 2049 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5 2050 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 2051 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6 2052 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 2053 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7 2054 u8 flags1; 2055 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 2056 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0 2057 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 2058 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1 2059 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 2060 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2 2061 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 2062 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3 2063 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 /* bit12 */ 2064 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 2065 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 /* bit13 */ 2066 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 2067 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 2068 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 2069 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 2070 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 2071 u8 flags2; 2072 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2073 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0 2074 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2075 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2 2076 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2077 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4 2078 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2079 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6 2080 u8 flags3; 2081 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 2082 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0 2083 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 2084 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2 2085 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 2086 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4 2087 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 2088 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6 2089 u8 flags4; 2090 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 2091 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0 2092 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 2093 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2 2094 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 2095 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4 2096 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 2097 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6 2098 u8 flags5; 2099 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 2100 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0 2101 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 2102 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2 2103 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 2104 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4 2105 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 2106 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6 2107 u8 flags6; 2108 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 2109 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 2110 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 /* cf_array_cf */ 2111 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 2112 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 2113 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4 2114 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 2115 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 2116 u8 flags7; 2117 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 2118 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 2119 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 2120 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2 2121 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 2122 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4 2123 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2124 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6 2125 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2126 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7 2127 u8 flags8; 2128 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2129 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0 2130 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2131 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1 2132 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 2133 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2 2134 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 2135 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3 2136 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 2137 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4 2138 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 2139 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5 2140 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 2141 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6 2142 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 2143 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7 2144 u8 flags9; 2145 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 2146 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0 2147 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 2148 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1 2149 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 2150 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2 2151 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 2152 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3 2153 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 2154 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4 2155 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 2156 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5 2157 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 2158 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 2159 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 /* cf_array_cf_en */ 2160 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 2161 u8 flags10; 2162 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 2163 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 2164 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 2165 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 2166 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 2167 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 2168 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 2169 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3 2170 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 2171 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 2172 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 2173 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 2174 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 2175 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6 2176 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 2177 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7 2178 u8 flags11; 2179 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 2180 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0 2181 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 2182 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1 2183 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 2184 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 2185 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2186 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3 2187 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2188 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4 2189 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2190 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5 2191 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 2192 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 2193 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 2194 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7 2195 u8 flags12; 2196 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 2197 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0 2198 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 2199 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1 2200 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 2201 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 2202 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 2203 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 2204 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 2205 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4 2206 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 2207 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5 2208 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 2209 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6 2210 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 2211 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7 2212 u8 flags13; 2213 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 2214 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0 2215 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 2216 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1 2217 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 2218 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 2219 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 2220 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 2221 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 2222 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 2223 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 2224 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 2225 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 2226 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 2227 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 2228 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 2229 u8 flags14; 2230 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 2231 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 2232 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 2233 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 2234 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 2235 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 2236 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 2237 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 2238 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 2239 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 2240 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 2241 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 2242 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */ 2243 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 2244 u8 edpm_event_id /* byte2 */; 2245 __le16 physical_q0 /* physical_q0 */; 2246 __le16 e5_reserved1 /* physical_q1 */; 2247 __le16 edpm_num_bds /* physical_q2 */; 2248 __le16 tx_bd_cons /* word3 */; 2249 __le16 tx_bd_prod /* word4 */; 2250 __le16 tx_class /* word5 */; 2251 __le16 conn_dpi /* conn_dpi */; 2252 }; 2253 2254 struct E5XstormEthConnAgCtxDqExtLdPart 2255 { 2256 u8 reserved0 /* cdu_validation */; 2257 u8 state_and_core_id /* state_and_core_id */; 2258 u8 flags0; 2259 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2260 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 2261 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 2262 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1 2263 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 2264 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2 2265 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 2266 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 2267 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1 /* bit4 */ 2268 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4 2269 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1 /* cf_array_active */ 2270 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5 2271 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1 /* bit6 */ 2272 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6 2273 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1 /* bit7 */ 2274 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7 2275 u8 flags1; 2276 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1 /* bit8 */ 2277 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0 2278 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1 /* bit9 */ 2279 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1 2280 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1 /* bit10 */ 2281 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2 2282 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 /* bit11 */ 2283 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 2284 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_COPY_CONDITION_LO_MASK 0x1 /* bit12 */ 2285 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_COPY_CONDITION_LO_SHIFT 4 2286 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_COPY_CONDITION_HI_MASK 0x1 /* bit13 */ 2287 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_COPY_CONDITION_HI_SHIFT 5 2288 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 2289 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6 2290 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 2291 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7 2292 u8 flags2; 2293 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3 /* timer0cf */ 2294 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0 2295 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3 /* timer1cf */ 2296 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2 2297 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3 /* timer2cf */ 2298 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4 2299 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3 /* timer_stop_all */ 2300 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6 2301 u8 flags3; 2302 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3 /* cf4 */ 2303 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0 2304 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3 /* cf5 */ 2305 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2 2306 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3 /* cf6 */ 2307 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4 2308 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3 /* cf7 */ 2309 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6 2310 u8 flags4; 2311 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3 /* cf8 */ 2312 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0 2313 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3 /* cf9 */ 2314 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2 2315 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3 /* cf10 */ 2316 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4 2317 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3 /* cf11 */ 2318 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6 2319 u8 flags5; 2320 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3 /* cf12 */ 2321 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0 2322 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3 /* cf13 */ 2323 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2 2324 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3 /* cf14 */ 2325 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4 2326 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3 /* cf15 */ 2327 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6 2328 u8 flags6; 2329 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 2330 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0 2331 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3 /* cf_array_cf */ 2332 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2 2333 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3 /* cf18 */ 2334 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4 2335 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3 /* cf19 */ 2336 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6 2337 u8 flags7; 2338 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3 /* cf20 */ 2339 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0 2340 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3 /* cf21 */ 2341 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2 2342 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 /* cf22 */ 2343 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 2344 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 /* cf0en */ 2345 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 2346 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 /* cf1en */ 2347 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 2348 u8 flags8; 2349 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 /* cf2en */ 2350 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 2351 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 /* cf3en */ 2352 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 2353 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 /* cf4en */ 2354 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 2355 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 /* cf5en */ 2356 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 2357 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 /* cf6en */ 2358 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 2359 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1 /* cf7en */ 2360 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5 2361 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 /* cf8en */ 2362 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 2363 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 /* cf9en */ 2364 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 2365 u8 flags9; 2366 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 /* cf10en */ 2367 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 2368 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 /* cf11en */ 2369 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 2370 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 /* cf12en */ 2371 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 2372 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 /* cf13en */ 2373 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 2374 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 /* cf14en */ 2375 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 2376 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 /* cf15en */ 2377 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 2378 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 2379 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6 2380 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1 /* cf_array_cf_en */ 2381 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7 2382 u8 flags10; 2383 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1 /* cf18en */ 2384 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0 2385 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 2386 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1 2387 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 2388 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2 2389 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1 /* cf21en */ 2390 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3 2391 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 2392 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 2393 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 2394 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5 2395 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1 /* rule0en */ 2396 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6 2397 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1 /* rule1en */ 2398 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7 2399 u8 flags11; 2400 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1 /* rule2en */ 2401 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0 2402 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1 /* rule3en */ 2403 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1 2404 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 2405 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2 2406 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 /* rule5en */ 2407 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 2408 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 /* rule6en */ 2409 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 2410 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 /* rule7en */ 2411 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 2412 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 /* rule8en */ 2413 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 2414 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 /* rule9en */ 2415 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 2416 u8 flags12; 2417 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 /* rule10en */ 2418 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 2419 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 /* rule11en */ 2420 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 2421 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 /* rule12en */ 2422 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 2423 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 /* rule13en */ 2424 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 2425 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 /* rule14en */ 2426 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 2427 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 /* rule15en */ 2428 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 2429 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 /* rule16en */ 2430 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 2431 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 /* rule17en */ 2432 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 2433 u8 flags13; 2434 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 /* rule18en */ 2435 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 2436 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 /* rule19en */ 2437 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 2438 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 /* rule20en */ 2439 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 2440 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 /* rule21en */ 2441 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 2442 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 /* rule22en */ 2443 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 2444 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 /* rule23en */ 2445 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 2446 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 /* rule24en */ 2447 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 2448 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 /* rule25en */ 2449 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 2450 u8 flags14; 2451 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 2452 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0 2453 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 2454 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1 2455 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 2456 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2 2457 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 2458 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3 2459 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 2460 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4 2461 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 2462 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 2463 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3 /* cf23 */ 2464 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6 2465 u8 edpm_vport /* byte2 */; 2466 __le16 physical_q0 /* physical_q0 */; 2467 __le16 tx_l2_edpm_usg_cnt /* physical_q1 */; 2468 __le16 edpm_num_bds /* physical_q2 */; 2469 __le16 tx_bd_cons /* word3 */; 2470 __le16 tx_bd_prod /* word4 */; 2471 __le16 tx_class /* word5 */; 2472 __le16 conn_dpi /* conn_dpi */; 2473 u8 byte3 /* byte3 */; 2474 u8 byte4 /* byte4 */; 2475 u8 byte5 /* byte5 */; 2476 u8 byte6 /* byte6 */; 2477 __le32 reg0 /* reg0 */; 2478 __le32 reg1 /* reg1 */; 2479 __le32 reg2 /* reg2 */; 2480 __le32 reg3 /* reg3 */; 2481 __le32 reg4 /* reg4 */; 2482 }; 2483 2484 struct e5_mstorm_eth_conn_ag_ctx 2485 { 2486 u8 byte0 /* cdu_validation */; 2487 u8 byte1 /* state_and_core_id */; 2488 u8 flags0; 2489 #define E5_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2490 #define E5_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 2491 #define E5_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2492 #define E5_MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 2493 #define E5_MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2494 #define E5_MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2 2495 #define E5_MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2496 #define E5_MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4 2497 #define E5_MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2498 #define E5_MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 2499 u8 flags1; 2500 #define E5_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2501 #define E5_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0 2502 #define E5_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2503 #define E5_MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1 2504 #define E5_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2505 #define E5_MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 2506 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2507 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 2508 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2509 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 2510 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2511 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 2512 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2513 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 2514 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2515 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 2516 __le16 word0 /* word0 */; 2517 __le16 word1 /* word1 */; 2518 __le32 reg0 /* reg0 */; 2519 __le32 reg1 /* reg1 */; 2520 }; 2521 2522 struct e5_xstorm_eth_hw_conn_ag_ctx 2523 { 2524 u8 reserved0 /* cdu_validation */; 2525 u8 state_and_core_id /* state_and_core_id */; 2526 u8 flags0; 2527 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2528 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 2529 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 2530 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1 2531 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 2532 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2 2533 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 2534 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 2535 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 2536 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4 2537 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 2538 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5 2539 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 2540 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6 2541 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 2542 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7 2543 u8 flags1; 2544 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 2545 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0 2546 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 2547 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1 2548 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 2549 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2 2550 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 2551 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3 2552 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_COPY_CONDITION_LO_MASK 0x1 /* bit12 */ 2553 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_COPY_CONDITION_LO_SHIFT 4 2554 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_COPY_CONDITION_HI_MASK 0x1 /* bit13 */ 2555 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_COPY_CONDITION_HI_SHIFT 5 2556 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 2557 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 2558 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 2559 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 2560 u8 flags2; 2561 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2562 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0 2563 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2564 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2 2565 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2566 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4 2567 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2568 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6 2569 u8 flags3; 2570 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 2571 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0 2572 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 2573 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2 2574 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 2575 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4 2576 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 2577 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6 2578 u8 flags4; 2579 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 2580 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0 2581 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 2582 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2 2583 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 2584 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4 2585 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 2586 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6 2587 u8 flags5; 2588 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 2589 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0 2590 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 2591 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2 2592 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 2593 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4 2594 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 2595 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6 2596 u8 flags6; 2597 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 2598 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 2599 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 /* cf_array_cf */ 2600 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 2601 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 2602 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4 2603 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 2604 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 2605 u8 flags7; 2606 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 2607 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 2608 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 2609 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2 2610 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 2611 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4 2612 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2613 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6 2614 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2615 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7 2616 u8 flags8; 2617 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2618 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0 2619 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2620 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1 2621 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 2622 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2 2623 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 2624 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3 2625 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 2626 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4 2627 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 2628 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5 2629 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 2630 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6 2631 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 2632 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7 2633 u8 flags9; 2634 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 2635 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0 2636 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 2637 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1 2638 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 2639 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2 2640 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 2641 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3 2642 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 2643 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4 2644 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 2645 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5 2646 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 2647 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 2648 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 /* cf_array_cf_en */ 2649 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 2650 u8 flags10; 2651 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 2652 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 2653 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 2654 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 2655 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 2656 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 2657 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 2658 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3 2659 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 2660 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 2661 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 2662 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 2663 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 2664 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6 2665 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 2666 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7 2667 u8 flags11; 2668 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 2669 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0 2670 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 2671 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1 2672 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 2673 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 2674 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2675 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3 2676 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2677 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4 2678 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2679 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5 2680 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 2681 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 2682 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 2683 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7 2684 u8 flags12; 2685 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 2686 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0 2687 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 2688 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1 2689 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 2690 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 2691 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 2692 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 2693 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 2694 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4 2695 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 2696 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5 2697 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 2698 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6 2699 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 2700 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7 2701 u8 flags13; 2702 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 2703 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0 2704 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 2705 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1 2706 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 2707 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 2708 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 2709 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 2710 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 2711 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 2712 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 2713 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 2714 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 2715 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 2716 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 2717 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 2718 u8 flags14; 2719 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 2720 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 2721 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 2722 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 2723 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 2724 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 2725 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 2726 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 2727 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 2728 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 2729 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 2730 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 2731 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */ 2732 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 2733 u8 edpm_vport /* byte2 */; 2734 __le16 physical_q0 /* physical_q0 */; 2735 __le16 tx_l2_edpm_usg_cnt /* physical_q1 */; 2736 __le16 edpm_num_bds /* physical_q2 */; 2737 __le16 tx_bd_cons /* word3 */; 2738 __le16 tx_bd_prod /* word4 */; 2739 __le16 tx_class /* word5 */; 2740 __le16 conn_dpi /* conn_dpi */; 2741 }; 2742 2743 /* 2744 * GFT CAM line struct 2745 */ 2746 struct gft_cam_line 2747 { 2748 __le32 camline; 2749 #define GFT_CAM_LINE_VALID_MASK 0x1 /* Indication if the line is valid. */ 2750 #define GFT_CAM_LINE_VALID_SHIFT 0 2751 #define GFT_CAM_LINE_DATA_MASK 0x3FFF /* Data bits, the word that compared with the profile key */ 2752 #define GFT_CAM_LINE_DATA_SHIFT 1 2753 #define GFT_CAM_LINE_MASK_BITS_MASK 0x3FFF /* Mask bits, indicate the bits in the data that are Dont-Care */ 2754 #define GFT_CAM_LINE_MASK_BITS_SHIFT 15 2755 #define GFT_CAM_LINE_RESERVED1_MASK 0x7 2756 #define GFT_CAM_LINE_RESERVED1_SHIFT 29 2757 }; 2758 2759 /* 2760 * GFT CAM line struct with fields breakout 2761 */ 2762 struct gft_cam_line_mapped 2763 { 2764 __le32 camline; 2765 #define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1 /* Indication if the line is valid. */ 2766 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0 2767 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1 /* (use enum gft_profile_ip_version) */ 2768 #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT 1 2769 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1 /* (use enum gft_profile_ip_version) */ 2770 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT 2 2771 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF /* (use enum gft_profile_upper_protocol_type) */ 2772 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT 3 2773 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF /* (use enum gft_profile_tunnel_type) */ 2774 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT 7 2775 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF 2776 #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT 11 2777 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1 2778 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT 15 2779 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1 2780 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT 16 2781 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF 2782 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17 2783 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF 2784 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT 21 2785 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF 2786 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT 25 2787 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7 2788 #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29 2789 }; 2790 2791 union gft_cam_line_union 2792 { 2793 struct gft_cam_line cam_line; 2794 struct gft_cam_line_mapped cam_line_mapped; 2795 }; 2796 2797 /* 2798 * Used in gft_profile_key: Indication for ip version 2799 */ 2800 enum gft_profile_ip_version 2801 { 2802 GFT_PROFILE_IPV4=0, 2803 GFT_PROFILE_IPV6=1, 2804 MAX_GFT_PROFILE_IP_VERSION 2805 }; 2806 2807 /* 2808 * Profile key stucr fot GFT logic in Prs 2809 */ 2810 struct gft_profile_key 2811 { 2812 __le16 profile_key; 2813 #define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */ 2814 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0 2815 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */ 2816 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1 2817 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF /* use enum gft_profile_upper_protocol_type (use enum gft_profile_upper_protocol_type) */ 2818 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2 2819 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */ 2820 #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6 2821 #define GFT_PROFILE_KEY_PF_ID_MASK 0xF 2822 #define GFT_PROFILE_KEY_PF_ID_SHIFT 10 2823 #define GFT_PROFILE_KEY_RESERVED0_MASK 0x3 2824 #define GFT_PROFILE_KEY_RESERVED0_SHIFT 14 2825 }; 2826 2827 /* 2828 * Used in gft_profile_key: Indication for tunnel type 2829 */ 2830 enum gft_profile_tunnel_type 2831 { 2832 GFT_PROFILE_NO_TUNNEL=0, 2833 GFT_PROFILE_VXLAN_TUNNEL=1, 2834 GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL=2, 2835 GFT_PROFILE_GRE_IP_TUNNEL=3, 2836 GFT_PROFILE_GENEVE_MAC_TUNNEL=4, 2837 GFT_PROFILE_GENEVE_IP_TUNNEL=5, 2838 MAX_GFT_PROFILE_TUNNEL_TYPE 2839 }; 2840 2841 /* 2842 * Used in gft_profile_key: Indication for protocol type 2843 */ 2844 enum gft_profile_upper_protocol_type 2845 { 2846 GFT_PROFILE_ROCE_PROTOCOL=0, 2847 GFT_PROFILE_RROCE_PROTOCOL=1, 2848 GFT_PROFILE_FCOE_PROTOCOL=2, 2849 GFT_PROFILE_ICMP_PROTOCOL=3, 2850 GFT_PROFILE_ARP_PROTOCOL=4, 2851 GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER=5, 2852 GFT_PROFILE_USER_TCP_DST_PORT_1_INNER=6, 2853 GFT_PROFILE_TCP_PROTOCOL=7, 2854 GFT_PROFILE_USER_UDP_DST_PORT_1_INNER=8, 2855 GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER=9, 2856 GFT_PROFILE_UDP_PROTOCOL=10, 2857 GFT_PROFILE_USER_IP_1_INNER=11, 2858 GFT_PROFILE_USER_IP_2_OUTER=12, 2859 GFT_PROFILE_USER_ETH_1_INNER=13, 2860 GFT_PROFILE_USER_ETH_2_OUTER=14, 2861 GFT_PROFILE_RAW=15, 2862 MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE 2863 }; 2864 2865 /* 2866 * GFT RAM line struct 2867 */ 2868 struct gft_ram_line 2869 { 2870 __le32 lo; 2871 #define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3 /* (use enum gft_vlan_select) */ 2872 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0 2873 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1 2874 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT 2 2875 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1 2876 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT 3 2877 #define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1 2878 #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT 4 2879 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1 2880 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT 5 2881 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1 2882 #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT 6 2883 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1 2884 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT 7 2885 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1 2886 #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT 8 2887 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1 2888 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT 9 2889 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1 2890 #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT 10 2891 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1 2892 #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT 11 2893 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1 2894 #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT 12 2895 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1 2896 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT 13 2897 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1 2898 #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT 14 2899 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1 2900 #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT 15 2901 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1 2902 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT 16 2903 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1 2904 #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT 17 2905 #define GFT_RAM_LINE_TTL_MASK 0x1 2906 #define GFT_RAM_LINE_TTL_SHIFT 18 2907 #define GFT_RAM_LINE_ETHERTYPE_MASK 0x1 2908 #define GFT_RAM_LINE_ETHERTYPE_SHIFT 19 2909 #define GFT_RAM_LINE_RESERVED0_MASK 0x1 2910 #define GFT_RAM_LINE_RESERVED0_SHIFT 20 2911 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1 2912 #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT 21 2913 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1 2914 #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT 22 2915 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1 2916 #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT 23 2917 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1 2918 #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT 24 2919 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1 2920 #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT 25 2921 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1 2922 #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT 26 2923 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1 2924 #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT 27 2925 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1 2926 #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT 28 2927 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1 2928 #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT 29 2929 #define GFT_RAM_LINE_DST_PORT_MASK 0x1 2930 #define GFT_RAM_LINE_DST_PORT_SHIFT 30 2931 #define GFT_RAM_LINE_SRC_PORT_MASK 0x1 2932 #define GFT_RAM_LINE_SRC_PORT_SHIFT 31 2933 __le32 hi; 2934 #define GFT_RAM_LINE_DSCP_MASK 0x1 2935 #define GFT_RAM_LINE_DSCP_SHIFT 0 2936 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1 2937 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT 1 2938 #define GFT_RAM_LINE_DST_IP_MASK 0x1 2939 #define GFT_RAM_LINE_DST_IP_SHIFT 2 2940 #define GFT_RAM_LINE_SRC_IP_MASK 0x1 2941 #define GFT_RAM_LINE_SRC_IP_SHIFT 3 2942 #define GFT_RAM_LINE_PRIORITY_MASK 0x1 2943 #define GFT_RAM_LINE_PRIORITY_SHIFT 4 2944 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1 2945 #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT 5 2946 #define GFT_RAM_LINE_VLAN_MASK 0x1 2947 #define GFT_RAM_LINE_VLAN_SHIFT 6 2948 #define GFT_RAM_LINE_DST_MAC_MASK 0x1 2949 #define GFT_RAM_LINE_DST_MAC_SHIFT 7 2950 #define GFT_RAM_LINE_SRC_MAC_MASK 0x1 2951 #define GFT_RAM_LINE_SRC_MAC_SHIFT 8 2952 #define GFT_RAM_LINE_TENANT_ID_MASK 0x1 2953 #define GFT_RAM_LINE_TENANT_ID_SHIFT 9 2954 #define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF 2955 #define GFT_RAM_LINE_RESERVED1_SHIFT 10 2956 }; 2957 2958 /* 2959 * Used in the first 2 bits for gft_ram_line: Indication for vlan mask 2960 */ 2961 enum gft_vlan_select 2962 { 2963 INNER_PROVIDER_VLAN=0, 2964 INNER_VLAN=1, 2965 OUTER_PROVIDER_VLAN=2, 2966 OUTER_VLAN=3, 2967 MAX_GFT_VLAN_SELECT 2968 }; 2969 2970 #endif /* __ECORE_HSI_ETH__ */ 2971