1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __ECORE_HSI_INIT_TOOL__ 32 #define __ECORE_HSI_INIT_TOOL__ 33 /**************************************/ 34 /* Init Tool HSI constants and macros */ 35 /**************************************/ 36 37 /* Width of GRC address in bits (addresses are specified in dwords) */ 38 #define GRC_ADDR_BITS 23 39 #define MAX_GRC_ADDR ((1 << GRC_ADDR_BITS) - 1) 40 41 /* indicates an init that should be applied to any phase ID */ 42 #define ANY_PHASE_ID 0xffff 43 44 /* Max size in dwords of a zipped array */ 45 #define MAX_ZIPPED_SIZE 8192 46 47 enum chip_ids 48 { 49 CHIP_BB, 50 CHIP_K2, 51 CHIP_E5, 52 MAX_CHIP_IDS 53 }; 54 55 enum init_modes 56 { 57 MODE_BB_A0_DEPRECATED, 58 MODE_BB, 59 MODE_K2, 60 MODE_ASIC, 61 MODE_EMUL_REDUCED, 62 MODE_EMUL_FULL, 63 MODE_FPGA, 64 MODE_CHIPSIM, 65 MODE_SF, 66 MODE_MF_SD, 67 MODE_MF_SI, 68 MODE_PORTS_PER_ENG_1, 69 MODE_PORTS_PER_ENG_2, 70 MODE_PORTS_PER_ENG_4, 71 MODE_100G, 72 MODE_E5, 73 MAX_INIT_MODES 74 }; 75 76 enum init_phases 77 { 78 PHASE_ENGINE, 79 PHASE_PORT, 80 PHASE_PF, 81 PHASE_VF, 82 PHASE_QM_PF, 83 MAX_INIT_PHASES 84 }; 85 86 enum init_split_types 87 { 88 SPLIT_TYPE_NONE, 89 SPLIT_TYPE_PORT, 90 SPLIT_TYPE_PF, 91 SPLIT_TYPE_PORT_PF, 92 SPLIT_TYPE_VF, 93 MAX_INIT_SPLIT_TYPES 94 }; 95 96 /* 97 * Binary buffer header 98 */ 99 struct bin_buffer_hdr 100 { 101 u32 offset /* buffer offset in bytes from the beginning of the binary file */; 102 u32 length /* buffer length in bytes */; 103 }; 104 105 /* 106 * binary init buffer types 107 */ 108 enum bin_init_buffer_type 109 { 110 BIN_BUF_INIT_FW_VER_INFO /* fw_ver_info struct */, 111 BIN_BUF_INIT_CMD /* init commands */, 112 BIN_BUF_INIT_VAL /* init data */, 113 BIN_BUF_INIT_MODE_TREE /* init modes tree */, 114 BIN_BUF_INIT_IRO /* internal RAM offsets */, 115 MAX_BIN_INIT_BUFFER_TYPE 116 }; 117 118 /* 119 * init array header: raw 120 */ 121 struct init_array_raw_hdr 122 { 123 u32 data; 124 #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 125 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0 126 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF /* init array params */ 127 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4 128 }; 129 130 /* 131 * init array header: standard 132 */ 133 struct init_array_standard_hdr 134 { 135 u32 data; 136 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 137 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0 138 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF /* Init array size (in dwords) */ 139 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4 140 }; 141 142 /* 143 * init array header: zipped 144 */ 145 struct init_array_zipped_hdr 146 { 147 u32 data; 148 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 149 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0 150 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF /* Init array zipped size (in bytes) */ 151 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4 152 }; 153 154 /* 155 * init array header: pattern 156 */ 157 struct init_array_pattern_hdr 158 { 159 u32 data; 160 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 161 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0 162 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF /* pattern size in dword */ 163 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4 164 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF /* pattern repetitions */ 165 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8 166 }; 167 168 /* 169 * init array header union 170 */ 171 union init_array_hdr 172 { 173 struct init_array_raw_hdr raw /* raw init array header */; 174 struct init_array_standard_hdr standard /* standard init array header */; 175 struct init_array_zipped_hdr zipped /* zipped init array header */; 176 struct init_array_pattern_hdr pattern /* pattern init array header */; 177 }; 178 179 /* 180 * init array types 181 */ 182 enum init_array_types 183 { 184 INIT_ARR_STANDARD /* standard init array */, 185 INIT_ARR_ZIPPED /* zipped init array */, 186 INIT_ARR_PATTERN /* a repeated pattern */, 187 MAX_INIT_ARRAY_TYPES 188 }; 189 190 /* 191 * init operation: callback 192 */ 193 struct init_callback_op 194 { 195 u32 op_data; 196 #define INIT_CALLBACK_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 197 #define INIT_CALLBACK_OP_OP_SHIFT 0 198 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF 199 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4 200 u16 callback_id /* Callback ID */; 201 u16 block_id /* Blocks ID */; 202 }; 203 204 /* 205 * init operation: delay 206 */ 207 struct init_delay_op 208 { 209 u32 op_data; 210 #define INIT_DELAY_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 211 #define INIT_DELAY_OP_OP_SHIFT 0 212 #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF 213 #define INIT_DELAY_OP_RESERVED_SHIFT 4 214 u32 delay /* delay in us */; 215 }; 216 217 /* 218 * init operation: if_mode 219 */ 220 struct init_if_mode_op 221 { 222 u32 op_data; 223 #define INIT_IF_MODE_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 224 #define INIT_IF_MODE_OP_OP_SHIFT 0 225 #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF 226 #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4 227 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF /* Commands to skip if the modes dont match */ 228 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16 229 u16 reserved2; 230 u16 modes_buf_offset /* offset (in bytes) in modes expression buffer */; 231 }; 232 233 /* 234 * init operation: if_phase 235 */ 236 struct init_if_phase_op 237 { 238 u32 op_data; 239 #define INIT_IF_PHASE_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 240 #define INIT_IF_PHASE_OP_OP_SHIFT 0 241 #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1 /* Indicates if DMAE is enabled in this phase */ 242 #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4 243 #define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF 244 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5 245 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF /* Commands to skip if the phases dont match */ 246 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16 247 u32 phase_data; 248 #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF /* Init phase */ 249 #define INIT_IF_PHASE_OP_PHASE_SHIFT 0 250 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF 251 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8 252 #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF /* Init phase ID */ 253 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16 254 }; 255 256 /* 257 * init mode operators 258 */ 259 enum init_mode_ops 260 { 261 INIT_MODE_OP_NOT /* init mode not operator */, 262 INIT_MODE_OP_OR /* init mode or operator */, 263 INIT_MODE_OP_AND /* init mode and operator */, 264 MAX_INIT_MODE_OPS 265 }; 266 267 /* 268 * init operation: raw 269 */ 270 struct init_raw_op 271 { 272 u32 op_data; 273 #define INIT_RAW_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 274 #define INIT_RAW_OP_OP_SHIFT 0 275 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF /* init param 1 */ 276 #define INIT_RAW_OP_PARAM1_SHIFT 4 277 u32 param2 /* Init param 2 */; 278 }; 279 280 /* 281 * init array params 282 */ 283 struct init_op_array_params 284 { 285 u16 size /* array size in dwords */; 286 u16 offset /* array start offset in dwords */; 287 }; 288 289 /* 290 * Write init operation arguments 291 */ 292 union init_write_args 293 { 294 u32 inline_val /* value to write, used when init source is INIT_SRC_INLINE */; 295 u32 zeros_count /* number of zeros to write, used when init source is INIT_SRC_ZEROS */; 296 u32 array_offset /* array offset to write, used when init source is INIT_SRC_ARRAY */; 297 struct init_op_array_params runtime /* runtime array params to write, used when init source is INIT_SRC_RUNTIME */; 298 }; 299 300 /* 301 * init operation: write 302 */ 303 struct init_write_op 304 { 305 u32 data; 306 #define INIT_WRITE_OP_OP_MASK 0xF /* init operation, from init_op_types enum */ 307 #define INIT_WRITE_OP_OP_SHIFT 0 308 #define INIT_WRITE_OP_SOURCE_MASK 0x7 /* init source type, taken from init_source_types enum */ 309 #define INIT_WRITE_OP_SOURCE_SHIFT 4 310 #define INIT_WRITE_OP_RESERVED_MASK 0x1 311 #define INIT_WRITE_OP_RESERVED_SHIFT 7 312 #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 313 #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8 314 #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF /* internal (absolute) GRC address, in dwords */ 315 #define INIT_WRITE_OP_ADDRESS_SHIFT 9 316 union init_write_args args /* Write init operation arguments */; 317 }; 318 319 /* 320 * init operation: read 321 */ 322 struct init_read_op 323 { 324 u32 op_data; 325 #define INIT_READ_OP_OP_MASK 0xF /* init operation, from init_op_types enum */ 326 #define INIT_READ_OP_OP_SHIFT 0 327 #define INIT_READ_OP_POLL_TYPE_MASK 0xF /* polling type, from init_poll_types enum */ 328 #define INIT_READ_OP_POLL_TYPE_SHIFT 4 329 #define INIT_READ_OP_RESERVED_MASK 0x1 330 #define INIT_READ_OP_RESERVED_SHIFT 8 331 #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF /* internal (absolute) GRC address, in dwords */ 332 #define INIT_READ_OP_ADDRESS_SHIFT 9 333 u32 expected_val /* expected polling value, used only when polling is done */; 334 }; 335 336 /* 337 * Init operations union 338 */ 339 union init_op 340 { 341 struct init_raw_op raw /* raw init operation */; 342 struct init_write_op write /* write init operation */; 343 struct init_read_op read /* read init operation */; 344 struct init_if_mode_op if_mode /* if_mode init operation */; 345 struct init_if_phase_op if_phase /* if_phase init operation */; 346 struct init_callback_op callback /* callback init operation */; 347 struct init_delay_op delay /* delay init operation */; 348 }; 349 350 /* 351 * Init command operation types 352 */ 353 enum init_op_types 354 { 355 INIT_OP_READ /* GRC read init command */, 356 INIT_OP_WRITE /* GRC write init command */, 357 INIT_OP_IF_MODE /* Skip init commands if the init modes expression doesnt match */, 358 INIT_OP_IF_PHASE /* Skip init commands if the init phase doesnt match */, 359 INIT_OP_DELAY /* delay init command */, 360 INIT_OP_CALLBACK /* callback init command */, 361 MAX_INIT_OP_TYPES 362 }; 363 364 /* 365 * init polling types 366 */ 367 enum init_poll_types 368 { 369 INIT_POLL_NONE /* No polling */, 370 INIT_POLL_EQ /* init value is included in the init command */, 371 INIT_POLL_OR /* init value is all zeros */, 372 INIT_POLL_AND /* init value is an array of values */, 373 MAX_INIT_POLL_TYPES 374 }; 375 376 /* 377 * init source types 378 */ 379 enum init_source_types 380 { 381 INIT_SRC_INLINE /* init value is included in the init command */, 382 INIT_SRC_ZEROS /* init value is all zeros */, 383 INIT_SRC_ARRAY /* init value is an array of values */, 384 INIT_SRC_RUNTIME /* init value is provided during runtime */, 385 MAX_INIT_SOURCE_TYPES 386 }; 387 388 /* 389 * Internal RAM Offsets macro data 390 */ 391 struct iro 392 { 393 u32 base /* RAM field offset */; 394 u16 m1 /* multiplier 1 */; 395 u16 m2 /* multiplier 2 */; 396 u16 m3 /* multiplier 3 */; 397 u16 size /* RAM field size */; 398 }; 399 400 #endif /* __ECORE_HSI_INIT_TOOL__ */ 401