1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __ECORE_HSI_IWARP__ 32 #define __ECORE_HSI_IWARP__ 33 /************************************************************************/ 34 /* Add include to ecore hsi rdma target for both roce and iwarp ecore driver */ 35 /************************************************************************/ 36 #include "ecore_hsi_rdma.h" 37 /************************************************************************/ 38 /* Add include to common TCP target */ 39 /************************************************************************/ 40 #include "tcp_common.h" 41 42 /************************************************************************/ 43 /* Add include to common iwarp target for both eCore and protocol iwarp driver */ 44 /************************************************************************/ 45 #include "iwarp_common.h" 46 47 /* 48 * The iwarp storm context of Ystorm 49 */ 50 struct ystorm_iwarp_conn_st_ctx 51 { 52 __le32 reserved[4]; 53 }; 54 55 /* 56 * The iwarp storm context of Pstorm 57 */ 58 struct pstorm_iwarp_conn_st_ctx 59 { 60 __le32 reserved[36]; 61 }; 62 63 /* 64 * The iwarp storm context of Xstorm 65 */ 66 struct xstorm_iwarp_conn_st_ctx 67 { 68 __le32 reserved[48]; 69 }; 70 71 struct e4_xstorm_iwarp_conn_ag_ctx 72 { 73 u8 reserved0 /* cdu_validation */; 74 u8 state /* state */; 75 u8 flags0; 76 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 77 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 78 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 /* exist_in_qm1 */ 79 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1 80 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK 0x1 /* exist_in_qm2 */ 81 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT 2 82 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 83 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 84 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 85 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 86 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1 /* cf_array_active */ 87 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT 5 88 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */ 89 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT 6 90 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */ 91 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT 7 92 u8 flags1; 93 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */ 94 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0 95 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1 /* bit9 */ 96 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT 1 97 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 98 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT 2 99 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 100 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3 101 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 102 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT 4 103 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 104 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT 5 105 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */ 106 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT 6 107 #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1 /* bit15 */ 108 #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7 109 u8 flags2; 110 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 111 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0 112 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 113 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 2 114 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 115 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 4 116 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 117 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6 118 u8 flags3; 119 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 120 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0 121 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 122 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 2 123 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 124 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 4 125 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 126 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 6 127 u8 flags4; 128 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 129 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0 130 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 131 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT 2 132 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 133 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 4 134 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 135 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT 6 136 u8 flags5; 137 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 138 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0 139 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 140 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT 2 141 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 /* cf14 */ 142 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 4 143 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 144 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT 6 145 u8 flags6; 146 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3 /* cf16 */ 147 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0 148 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 149 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT 2 150 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 151 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT 4 152 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 /* cf19 */ 153 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT 6 154 u8 flags7; 155 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 156 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 157 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3 /* cf21 */ 158 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT 2 159 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 160 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 161 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 162 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 6 163 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 164 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 7 165 u8 flags8; 166 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 167 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0 168 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */ 169 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1 170 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 171 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 2 172 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 173 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 3 174 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 175 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 4 176 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 177 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 5 178 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 179 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 6 180 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 181 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT 7 182 u8 flags9; 183 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 184 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0 185 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 186 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT 1 187 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 188 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT 2 189 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 190 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT 3 191 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 /* cf14en */ 192 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 4 193 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 194 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT 5 195 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1 /* cf16en */ 196 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6 197 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 198 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT 7 199 u8 flags10; 200 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 201 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0 202 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 /* cf19en */ 203 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1 204 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 205 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 206 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1 /* cf21en */ 207 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3 208 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 209 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 210 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 211 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF23EN_SHIFT 5 212 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 213 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6 214 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1 /* rule1en */ 215 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7 216 u8 flags11; 217 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1 /* rule2en */ 218 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0 219 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 220 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 1 221 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1 /* rule4en */ 222 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT 2 223 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 224 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 3 225 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 226 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 4 227 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 228 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 5 229 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 230 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 231 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 232 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT 7 233 u8 flags12; 234 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1 /* rule10en */ 235 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0 236 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 237 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT 1 238 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 239 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 240 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 241 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 242 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1 /* rule14en */ 243 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT 4 244 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 245 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT 5 246 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 247 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT 6 248 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 249 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT 7 250 u8 flags13; 251 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1 /* rule18en */ 252 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0 253 #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1 /* rule19en */ 254 #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT 1 255 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1 /* rule20en */ 256 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT 2 257 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1 /* rule21en */ 258 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT 3 259 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 260 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 261 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1 /* rule23en */ 262 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT 5 263 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 264 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 265 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 266 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 267 u8 flags14; 268 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 269 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0 270 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 271 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT 1 272 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */ 273 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT 2 274 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK 0x1 /* bit19 */ 275 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT 3 276 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 /* bit20 */ 277 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 278 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 /* bit21 */ 279 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 280 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 281 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF23_SHIFT 6 282 u8 byte2 /* byte2 */; 283 __le16 physical_q0 /* physical_q0 */; 284 __le16 physical_q1 /* physical_q1 */; 285 __le16 sq_comp_cons /* physical_q2 */; 286 __le16 sq_tx_cons /* word3 */; 287 __le16 sq_prod /* word4 */; 288 __le16 word5 /* word5 */; 289 __le16 conn_dpi /* conn_dpi */; 290 u8 byte3 /* byte3 */; 291 u8 byte4 /* byte4 */; 292 u8 byte5 /* byte5 */; 293 u8 byte6 /* byte6 */; 294 __le32 reg0 /* reg0 */; 295 __le32 reg1 /* reg1 */; 296 __le32 reg2 /* reg2 */; 297 __le32 more_to_send_seq /* reg3 */; 298 __le32 reg4 /* reg4 */; 299 __le32 rewinded_snd_max /* cf_array0 */; 300 __le32 rd_msn /* cf_array1 */; 301 __le16 irq_prod_via_msdm /* word7 */; 302 __le16 irq_cons /* word8 */; 303 __le16 hq_cons_th_or_mpa_data /* word9 */; 304 __le16 hq_cons /* word10 */; 305 __le32 atom_msn /* reg7 */; 306 __le32 orq_cons /* reg8 */; 307 __le32 orq_cons_th /* reg9 */; 308 u8 byte7 /* byte7 */; 309 u8 max_ord /* byte8 */; 310 u8 wqe_data_pad_bytes /* byte9 */; 311 u8 former_hq_prod /* byte10 */; 312 u8 irq_prod_via_msem /* byte11 */; 313 u8 byte12 /* byte12 */; 314 u8 max_pkt_pdu_size_lo /* byte13 */; 315 u8 max_pkt_pdu_size_hi /* byte14 */; 316 u8 byte15 /* byte15 */; 317 u8 e5_reserved /* e5_reserved */; 318 __le16 e5_reserved4 /* word11 */; 319 __le32 reg10 /* reg10 */; 320 __le32 reg11 /* reg11 */; 321 __le32 shared_queue_page_addr_lo /* reg12 */; 322 __le32 shared_queue_page_addr_hi /* reg13 */; 323 __le32 reg14 /* reg14 */; 324 __le32 reg15 /* reg15 */; 325 __le32 reg16 /* reg16 */; 326 __le32 reg17 /* reg17 */; 327 }; 328 329 struct e4_tstorm_iwarp_conn_ag_ctx 330 { 331 u8 reserved0 /* cdu_validation */; 332 u8 state /* state */; 333 u8 flags0; 334 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 335 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 336 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 337 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 338 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 339 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2 340 #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit3 */ 341 #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 3 342 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 343 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 344 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 /* bit5 */ 345 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 346 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 347 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 6 348 u8 flags1; 349 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3 /* timer1cf */ 350 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0 351 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK 0x3 /* timer2cf */ 352 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_SHIFT 2 353 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 354 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4 355 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 356 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 6 357 u8 flags2; 358 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 359 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0 360 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 361 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 2 362 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 363 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 4 364 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 365 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 6 366 u8 flags3; 367 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_MASK 0x3 /* cf9 */ 368 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_SHIFT 0 369 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3 /* cf10 */ 370 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT 2 371 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 372 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 4 373 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1 /* cf1en */ 374 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT 5 375 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK 0x1 /* cf2en */ 376 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_SHIFT 6 377 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */ 378 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7 379 u8 flags4; 380 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 381 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0 382 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 383 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 1 384 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 385 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 2 386 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 387 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 3 388 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 389 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 4 390 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_EN_MASK 0x1 /* cf9en */ 391 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_EN_SHIFT 5 392 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1 /* cf10en */ 393 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT 6 394 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 395 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 7 396 u8 flags5; 397 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 398 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0 399 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 400 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1 401 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 402 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2 403 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 404 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3 405 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 406 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4 407 #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1 /* rule6en */ 408 #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT 5 409 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 410 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6 411 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 412 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7 413 __le32 reg0 /* reg0 */; 414 __le32 reg1 /* reg1 */; 415 __le32 unaligned_nxt_seq /* reg2 */; 416 __le32 reg3 /* reg3 */; 417 __le32 reg4 /* reg4 */; 418 __le32 reg5 /* reg5 */; 419 __le32 reg6 /* reg6 */; 420 __le32 reg7 /* reg7 */; 421 __le32 reg8 /* reg8 */; 422 u8 orq_cache_idx /* byte2 */; 423 u8 hq_prod /* byte3 */; 424 __le16 sq_tx_cons_th /* word0 */; 425 u8 orq_prod /* byte4 */; 426 u8 irq_cons /* byte5 */; 427 __le16 sq_tx_cons /* word1 */; 428 __le16 conn_dpi /* conn_dpi */; 429 __le16 rq_prod /* word3 */; 430 __le32 snd_seq /* reg9 */; 431 __le32 last_hq_sequence /* reg10 */; 432 }; 433 434 /* 435 * The iwarp storm context of Tstorm 436 */ 437 struct tstorm_iwarp_conn_st_ctx 438 { 439 __le32 reserved[60]; 440 }; 441 442 /* 443 * The iwarp storm context of Mstorm 444 */ 445 struct mstorm_iwarp_conn_st_ctx 446 { 447 __le32 reserved[32]; 448 }; 449 450 /* 451 * The iwarp storm context of Ustorm 452 */ 453 struct ustorm_iwarp_conn_st_ctx 454 { 455 __le32 reserved[24]; 456 }; 457 458 /* 459 * iwarp connection context 460 */ 461 struct e4_iwarp_conn_context 462 { 463 struct ystorm_iwarp_conn_st_ctx ystorm_st_context /* ystorm storm context */; 464 struct regpair ystorm_st_padding[2] /* padding */; 465 struct pstorm_iwarp_conn_st_ctx pstorm_st_context /* pstorm storm context */; 466 struct regpair pstorm_st_padding[2] /* padding */; 467 struct xstorm_iwarp_conn_st_ctx xstorm_st_context /* xstorm storm context */; 468 struct regpair xstorm_st_padding[2] /* padding */; 469 struct e4_xstorm_iwarp_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 470 struct e4_tstorm_iwarp_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 471 struct timers_context timer_context /* timer context */; 472 struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 473 struct tstorm_iwarp_conn_st_ctx tstorm_st_context /* tstorm storm context */; 474 struct regpair tstorm_st_padding[2] /* padding */; 475 struct mstorm_iwarp_conn_st_ctx mstorm_st_context /* mstorm storm context */; 476 struct ustorm_iwarp_conn_st_ctx ustorm_st_context /* ustorm storm context */; 477 }; 478 479 480 struct e5_xstorm_iwarp_conn_ag_ctx 481 { 482 u8 reserved0 /* cdu_validation */; 483 u8 state_and_core_id /* state_and_core_id */; 484 u8 flags0; 485 #define E5_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 486 #define E5_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 487 #define E5_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 /* exist_in_qm1 */ 488 #define E5_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1 489 #define E5_XSTORM_IWARP_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm2 */ 490 #define E5_XSTORM_IWARP_CONN_AG_CTX_RESERVED1_SHIFT 2 491 #define E5_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 492 #define E5_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 493 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 494 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 495 #define E5_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1 /* cf_array_active */ 496 #define E5_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT 5 497 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */ 498 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT 6 499 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */ 500 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT 7 501 u8 flags1; 502 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */ 503 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0 504 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1 /* bit9 */ 505 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT 1 506 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 507 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT 2 508 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 509 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3 510 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 511 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT 4 512 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 513 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT 5 514 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */ 515 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT 6 516 #define E5_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1 /* bit15 */ 517 #define E5_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7 518 u8 flags2; 519 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 520 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0 521 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 522 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 2 523 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 524 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 4 525 #define E5_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 526 #define E5_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6 527 u8 flags3; 528 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 529 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0 530 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 531 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 2 532 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 533 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 4 534 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 535 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 6 536 u8 flags4; 537 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 538 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0 539 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 540 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT 2 541 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 542 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 4 543 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 544 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT 6 545 u8 flags5; 546 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 547 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0 548 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 549 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT 2 550 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 /* cf14 */ 551 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 4 552 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 553 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT 6 554 u8 flags6; 555 #define E5_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3 /* cf16 */ 556 #define E5_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0 557 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 558 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT 2 559 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 560 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT 4 561 #define E5_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 /* cf19 */ 562 #define E5_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT 6 563 u8 flags7; 564 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 565 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 566 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3 /* cf21 */ 567 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT 2 568 #define E5_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 569 #define E5_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 570 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 571 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 6 572 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 573 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 7 574 u8 flags8; 575 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 576 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0 577 #define E5_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */ 578 #define E5_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1 579 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 580 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 2 581 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 582 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 3 583 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 584 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 4 585 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 586 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 5 587 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 588 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 6 589 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 590 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT 7 591 u8 flags9; 592 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 593 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0 594 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 595 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT 1 596 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 597 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT 2 598 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 599 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT 3 600 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 /* cf14en */ 601 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 4 602 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 603 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT 5 604 #define E5_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1 /* cf16en */ 605 #define E5_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6 606 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 607 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT 7 608 u8 flags10; 609 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 610 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0 611 #define E5_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 /* cf19en */ 612 #define E5_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1 613 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 614 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 615 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1 /* cf21en */ 616 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3 617 #define E5_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 618 #define E5_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 619 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 620 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF23EN_SHIFT 5 621 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 622 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6 623 #define E5_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1 /* rule1en */ 624 #define E5_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7 625 u8 flags11; 626 #define E5_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1 /* rule2en */ 627 #define E5_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0 628 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 629 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 1 630 #define E5_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1 /* rule4en */ 631 #define E5_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT 2 632 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 633 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 3 634 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 635 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 4 636 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 637 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 5 638 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 639 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 640 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 641 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT 7 642 u8 flags12; 643 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1 /* rule10en */ 644 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0 645 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 646 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT 1 647 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 648 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 649 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 650 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 651 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1 /* rule14en */ 652 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT 4 653 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 654 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT 5 655 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 656 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT 6 657 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 658 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT 7 659 u8 flags13; 660 #define E5_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1 /* rule18en */ 661 #define E5_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0 662 #define E5_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1 /* rule19en */ 663 #define E5_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT 1 664 #define E5_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1 /* rule20en */ 665 #define E5_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT 2 666 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1 /* rule21en */ 667 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT 3 668 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 669 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 670 #define E5_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1 /* rule23en */ 671 #define E5_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT 5 672 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 673 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 674 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 675 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 676 u8 flags14; 677 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 678 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0 679 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 680 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT 1 681 #define E5_XSTORM_IWARP_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 682 #define E5_XSTORM_IWARP_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 683 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */ 684 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT20_SHIFT 4 685 #define E5_XSTORM_IWARP_CONN_AG_CTX_RDMA_EDPM_ENABLE_MASK 0x1 /* bit21 */ 686 #define E5_XSTORM_IWARP_CONN_AG_CTX_RDMA_EDPM_ENABLE_SHIFT 5 687 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 688 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF23_SHIFT 6 689 u8 byte2 /* byte2 */; 690 __le16 physical_q0 /* physical_q0 */; 691 __le16 physical_q1 /* physical_q1 */; 692 __le16 sq_comp_cons /* physical_q2 */; 693 __le16 sq_tx_cons /* word3 */; 694 __le16 sq_prod /* word4 */; 695 __le16 word5 /* word5 */; 696 __le16 conn_dpi /* conn_dpi */; 697 u8 byte3 /* byte3 */; 698 u8 byte4 /* byte4 */; 699 u8 byte5 /* byte5 */; 700 u8 byte6 /* byte6 */; 701 __le32 reg0 /* reg0 */; 702 __le32 reg1 /* reg1 */; 703 __le32 reg2 /* reg2 */; 704 __le32 more_to_send_seq /* reg3 */; 705 __le32 reg4 /* reg4 */; 706 __le32 rewinded_snd_max /* cf_array0 */; 707 __le32 rd_msn /* cf_array1 */; 708 u8 flags15; 709 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit22 */ 710 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 711 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit23 */ 712 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 713 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit24 */ 714 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 715 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf24 */ 716 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 717 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf24en */ 718 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 719 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule26en */ 720 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 721 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule27en */ 722 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 723 u8 byte7 /* byte7 */; 724 __le16 irq_prod_via_msdm /* word7 */; 725 __le16 irq_cons /* word8 */; 726 __le16 hq_cons_th_or_mpa_data /* word9 */; 727 __le16 hq_cons /* word10 */; 728 __le16 tx_rdma_edpm_usg_cnt /* word11 */; 729 __le32 atom_msn /* reg7 */; 730 __le32 orq_cons /* reg8 */; 731 __le32 orq_cons_th /* reg9 */; 732 u8 max_ord /* byte8 */; 733 u8 wqe_data_pad_bytes /* byte9 */; 734 u8 former_hq_prod /* byte10 */; 735 u8 irq_prod_via_msem /* byte11 */; 736 u8 byte12 /* byte12 */; 737 u8 max_pkt_pdu_size_lo /* byte13 */; 738 u8 max_pkt_pdu_size_hi /* byte14 */; 739 u8 byte15 /* byte15 */; 740 __le32 reg10 /* reg10 */; 741 __le32 reg11 /* reg11 */; 742 __le32 reg12 /* reg12 */; 743 __le32 shared_queue_page_addr_lo /* reg13 */; 744 __le32 shared_queue_page_addr_hi /* reg14 */; 745 __le32 reg15 /* reg15 */; 746 __le32 reg16 /* reg16 */; 747 __le32 reg17 /* reg17 */; 748 }; 749 750 struct e5_tstorm_iwarp_conn_ag_ctx 751 { 752 u8 reserved0 /* cdu_validation */; 753 u8 state_and_core_id /* state_and_core_id */; 754 u8 flags0; 755 #define E5_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 756 #define E5_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 757 #define E5_TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 758 #define E5_TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 759 #define E5_TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 760 #define E5_TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2 761 #define E5_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit3 */ 762 #define E5_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 3 763 #define E5_TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 764 #define E5_TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 765 #define E5_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 /* bit5 */ 766 #define E5_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 767 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 768 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 6 769 u8 flags1; 770 #define E5_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3 /* timer1cf */ 771 #define E5_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0 772 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3 /* timer2cf */ 773 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT 2 774 #define E5_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 775 #define E5_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4 776 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 777 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 6 778 u8 flags2; 779 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 780 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0 781 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 782 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 2 783 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 784 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 4 785 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 786 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 6 787 u8 flags3; 788 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf9 */ 789 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 790 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 791 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 2 792 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 793 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 4 794 #define E5_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1 /* cf1en */ 795 #define E5_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT 5 796 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1 /* cf2en */ 797 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT 6 798 #define E5_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */ 799 #define E5_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7 800 u8 flags4; 801 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 802 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0 803 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 804 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 1 805 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 806 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 2 807 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 808 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 3 809 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 810 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 4 811 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf9en */ 812 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5 813 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 814 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 6 815 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 816 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 7 817 u8 flags5; 818 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 819 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0 820 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 821 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1 822 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 823 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2 824 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 825 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3 826 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 827 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4 828 #define E5_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1 /* rule6en */ 829 #define E5_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT 5 830 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 831 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6 832 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 833 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7 834 u8 flags6; 835 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 836 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 837 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 838 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 839 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 840 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 841 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 842 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 843 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 844 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 845 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 846 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 847 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 848 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 849 u8 orq_cache_idx /* byte2 */; 850 __le16 sq_tx_cons_th /* word0 */; 851 __le32 reg0 /* reg0 */; 852 __le32 reg1 /* reg1 */; 853 __le32 unaligned_nxt_seq /* reg2 */; 854 __le32 reg3 /* reg3 */; 855 __le32 reg4 /* reg4 */; 856 __le32 reg5 /* reg5 */; 857 __le32 reg6 /* reg6 */; 858 __le32 reg7 /* reg7 */; 859 __le32 reg8 /* reg8 */; 860 u8 hq_prod /* byte3 */; 861 u8 orq_prod /* byte4 */; 862 u8 irq_cons /* byte5 */; 863 u8 e4_reserved8 /* byte6 */; 864 __le16 sq_tx_cons /* word1 */; 865 __le16 conn_dpi /* conn_dpi */; 866 __le32 snd_seq /* reg9 */; 867 __le16 rq_prod /* word3 */; 868 __le16 e4_reserved9 /* word4 */; 869 }; 870 871 /* 872 * iwarp connection context 873 */ 874 struct e5_iwarp_conn_context 875 { 876 struct ystorm_iwarp_conn_st_ctx ystorm_st_context /* ystorm storm context */; 877 struct regpair ystorm_st_padding[2] /* padding */; 878 struct pstorm_iwarp_conn_st_ctx pstorm_st_context /* pstorm storm context */; 879 struct regpair pstorm_st_padding[2] /* padding */; 880 struct xstorm_iwarp_conn_st_ctx xstorm_st_context /* xstorm storm context */; 881 struct regpair xstorm_st_padding[2] /* padding */; 882 struct e5_xstorm_iwarp_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 883 struct e5_tstorm_iwarp_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 884 struct timers_context timer_context /* timer context */; 885 struct e5_ustorm_rdma_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 886 struct tstorm_iwarp_conn_st_ctx tstorm_st_context /* tstorm storm context */; 887 struct regpair tstorm_st_padding[2] /* padding */; 888 struct mstorm_iwarp_conn_st_ctx mstorm_st_context /* mstorm storm context */; 889 struct ustorm_iwarp_conn_st_ctx ustorm_st_context /* ustorm storm context */; 890 }; 891 892 893 /* 894 * iWARP create QP params passed by driver to FW in CreateQP Request Ramrod 895 */ 896 struct iwarp_create_qp_ramrod_data 897 { 898 u8 flags; 899 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1 900 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 0 901 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK 0x1 902 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_SHIFT 1 903 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 904 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2 905 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 906 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3 907 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 908 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 4 909 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK 0x1 910 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT 5 911 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_MASK 0x1 912 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_SHIFT 6 913 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK 0x1 914 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT 7 915 u8 reserved1 /* Basic/Enhanced (use enum mpa_negotiation_mode) */; 916 __le16 pd; 917 __le16 sq_num_pages; 918 __le16 rq_num_pages; 919 __le32 reserved3[2]; 920 struct regpair qp_handle_for_cqe /* For use in CQEs */; 921 struct rdma_srq_id srq_id; 922 __le32 cq_cid_for_sq /* Cid of the CQ that will be posted from SQ */; 923 __le32 cq_cid_for_rq /* Cid of the CQ that will be posted from RQ */; 924 __le16 dpi; 925 __le16 physical_q0 /* Physical QM queue to be tied to logical Q0 */; 926 __le16 physical_q1 /* Physical QM queue to be tied to logical Q1 */; 927 u8 reserved2[6]; 928 }; 929 930 931 /* 932 * iWARP completion queue types 933 */ 934 enum iwarp_eqe_async_opcode 935 { 936 IWARP_EVENT_TYPE_ASYNC_CONNECT_COMPLETE /* Async completion oafter TCP 3-way handshake */, 937 IWARP_EVENT_TYPE_ASYNC_ENHANCED_MPA_REPLY_ARRIVED /* Enhanced MPA reply arrived. Driver should either send RTR or reject */, 938 IWARP_EVENT_TYPE_ASYNC_MPA_HANDSHAKE_COMPLETE /* MPA Negotiations completed */, 939 IWARP_EVENT_TYPE_ASYNC_CID_CLEANED /* Async completion that indicates to the driver that the CID can be re-used. */, 940 IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED /* Async EQE indicating detection of an error/exception on a QP at Firmware */, 941 IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE /* Async EQE indicating QP is in Error state. */, 942 IWARP_EVENT_TYPE_ASYNC_CQ_OVERFLOW /* Async EQE indicating CQ, whose handle is sent with this event, has overflowed */, 943 MAX_IWARP_EQE_ASYNC_OPCODE 944 }; 945 946 947 struct iwarp_eqe_data_mpa_async_completion 948 { 949 __le16 ulp_data_len /* On active side, length of ULP Data, from peers MPA Connect Response */; 950 u8 reserved[6]; 951 }; 952 953 954 struct iwarp_eqe_data_tcp_async_completion 955 { 956 __le16 ulp_data_len /* On passive side, length of ULP Data, from peers active MPA Connect Request */; 957 u8 mpa_handshake_mode /* Negotiation type Basic/Enhanced */; 958 u8 reserved[5]; 959 }; 960 961 962 /* 963 * iWARP completion queue types 964 */ 965 enum iwarp_eqe_sync_opcode 966 { 967 IWARP_EVENT_TYPE_TCP_OFFLOAD=11 /* iWARP event queue response after option 2 offload Ramrod */, 968 IWARP_EVENT_TYPE_MPA_OFFLOAD /* Synchronous completion for MPA offload Request */, 969 IWARP_EVENT_TYPE_MPA_OFFLOAD_SEND_RTR, 970 IWARP_EVENT_TYPE_CREATE_QP, 971 IWARP_EVENT_TYPE_QUERY_QP, 972 IWARP_EVENT_TYPE_MODIFY_QP, 973 IWARP_EVENT_TYPE_DESTROY_QP, 974 IWARP_EVENT_TYPE_ABORT_TCP_OFFLOAD, 975 MAX_IWARP_EQE_SYNC_OPCODE 976 }; 977 978 979 /* 980 * iWARP EQE completion status 981 */ 982 enum iwarp_fw_return_code 983 { 984 IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET=5 /* Got invalid packet SYN/SYN-ACK */, 985 IWARP_CONN_ERROR_TCP_CONNECTION_RST /* Got RST during offload TCP connection */, 986 IWARP_CONN_ERROR_TCP_CONNECT_TIMEOUT /* TCP connection setup timed out */, 987 IWARP_CONN_ERROR_MPA_ERROR_REJECT /* Got Reject in MPA reply. */, 988 IWARP_CONN_ERROR_MPA_NOT_SUPPORTED_VER /* Got MPA request with higher version that we support. */, 989 IWARP_CONN_ERROR_MPA_RST /* Got RST during MPA negotiation */, 990 IWARP_CONN_ERROR_MPA_FIN /* Got FIN during MPA negotiation */, 991 IWARP_CONN_ERROR_MPA_RTR_MISMATCH /* RTR mismatch detected when MPA reply arrived. */, 992 IWARP_CONN_ERROR_MPA_INSUF_IRD /* Insufficient IRD on the MPA reply that arrived. */, 993 IWARP_CONN_ERROR_MPA_INVALID_PACKET /* Incoming MPAp acket failed on FW verifications */, 994 IWARP_CONN_ERROR_MPA_LOCAL_ERROR /* Detected an internal error during MPA negotiation. */, 995 IWARP_CONN_ERROR_MPA_TIMEOUT /* MPA negotiation timed out. */, 996 IWARP_CONN_ERROR_MPA_TERMINATE /* Got Terminate during MPA negotiation. */, 997 IWARP_QP_IN_ERROR_GOOD_CLOSE /* LLP connection was closed gracefully - Used for async IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE */, 998 IWARP_QP_IN_ERROR_BAD_CLOSE /* LLP Connection was closed abortively - Used for async IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE */, 999 IWARP_EXCEPTION_DETECTED_LLP_CLOSED /* LLP has been disociated from the QP, although the TCP connection may not be closed yet - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */, 1000 IWARP_EXCEPTION_DETECTED_LLP_RESET /* LLP has Reset (either because of an RST, or a bad-close condition) - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */, 1001 IWARP_EXCEPTION_DETECTED_IRQ_FULL /* Peer sent more outstanding Read Requests than IRD - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */, 1002 IWARP_EXCEPTION_DETECTED_RQ_EMPTY /* SEND request received with RQ empty - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */, 1003 IWARP_EXCEPTION_DETECTED_SRQ_EMPTY /* SEND request received with SRQ empty - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */, 1004 IWARP_EXCEPTION_DETECTED_SRQ_LIMIT /* Number of SRQ wqes is below the limit */, 1005 IWARP_EXCEPTION_DETECTED_LLP_TIMEOUT /* TCP Retransmissions timed out - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */, 1006 IWARP_EXCEPTION_DETECTED_REMOTE_PROTECTION_ERROR /* Peers Remote Access caused error */, 1007 IWARP_EXCEPTION_DETECTED_CQ_OVERFLOW /* CQ overflow detected */, 1008 IWARP_EXCEPTION_DETECTED_LOCAL_CATASTROPHIC /* Local catastrophic error detected - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */, 1009 IWARP_EXCEPTION_DETECTED_LOCAL_ACCESS_ERROR /* Local Access error detected while responding - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */, 1010 IWARP_EXCEPTION_DETECTED_REMOTE_OPERATION_ERROR /* An operation/protocol error caused by Remote Consumer */, 1011 IWARP_EXCEPTION_DETECTED_TERMINATE_RECEIVED /* Peer sent a TERMINATE message */, 1012 MAX_IWARP_FW_RETURN_CODE 1013 }; 1014 1015 1016 /* 1017 * unaligned opaque data received from LL2 1018 */ 1019 struct iwarp_init_func_params 1020 { 1021 u8 ll2_ooo_q_index /* LL2 OOO queue id. The unaligned queue id will be + 1 */; 1022 u8 reserved1[7]; 1023 }; 1024 1025 1026 /* 1027 * iwarp func init ramrod data 1028 */ 1029 struct iwarp_init_func_ramrod_data 1030 { 1031 struct rdma_init_func_ramrod_data rdma; 1032 struct tcp_init_params tcp; 1033 struct iwarp_init_func_params iwarp; 1034 }; 1035 1036 1037 /* 1038 * iWARP QP - possible states to transition to 1039 */ 1040 enum iwarp_modify_qp_new_state_type 1041 { 1042 IWARP_MODIFY_QP_STATE_CLOSING=1 /* graceful close */, 1043 IWARP_MODIFY_QP_STATE_ERROR=2 /* abortive close, if LLP connection still exists */, 1044 MAX_IWARP_MODIFY_QP_NEW_STATE_TYPE 1045 }; 1046 1047 1048 /* 1049 * iwarp modify qp responder ramrod data 1050 */ 1051 struct iwarp_modify_qp_ramrod_data 1052 { 1053 __le16 transition_to_state /* (use enum iwarp_modify_qp_new_state_type) */; 1054 __le16 flags; 1055 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 1056 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 0 1057 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 1058 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 1 1059 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 1060 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 2 1061 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK 0x1 /* change QP state as per transition_to_state field */ 1062 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_SHIFT 3 1063 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1 /* If set, the rdma_rd/wr/atomic_en should be updated */ 1064 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 4 1065 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1 /* If set, the physicalQ1Val/physicalQ0Val/regularLatencyPhyQueue should be updated */ 1066 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 5 1067 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK 0x3FF 1068 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT 6 1069 __le16 physical_q0 /* Updated physicalQ0Val */; 1070 __le16 physical_q1 /* Updated physicalQ1Val */; 1071 __le32 reserved1[10]; 1072 }; 1073 1074 1075 /* 1076 * MPA params for Enhanced mode 1077 */ 1078 struct mpa_rq_params 1079 { 1080 __le32 ird; 1081 __le32 ord; 1082 }; 1083 1084 /* 1085 * MPA host Address-Len for private data 1086 */ 1087 struct mpa_ulp_buffer 1088 { 1089 struct regpair addr; 1090 __le16 len; 1091 __le16 reserved[3]; 1092 }; 1093 1094 /* 1095 * iWARP MPA offload params common to Basic and Enhanced modes 1096 */ 1097 struct mpa_outgoing_params 1098 { 1099 u8 crc_needed; 1100 u8 reject /* Valid only for passive side. */; 1101 u8 reserved[6]; 1102 struct mpa_rq_params out_rq; 1103 struct mpa_ulp_buffer outgoing_ulp_buffer /* ULP buffer populated by the host */; 1104 }; 1105 1106 /* 1107 * iWARP MPA offload params passed by driver to FW in MPA Offload Request Ramrod 1108 */ 1109 struct iwarp_mpa_offload_ramrod_data 1110 { 1111 struct mpa_outgoing_params common; 1112 __le32 tcp_cid; 1113 u8 mode /* Basic/Enhanced (use enum mpa_negotiation_mode) */; 1114 u8 tcp_connect_side /* Passive/Active. use enum tcp_connect_mode */; 1115 u8 rtr_pref; 1116 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK 0x7 /* (use enum mpa_rtr_type) */ 1117 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT 0 1118 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK 0x1F 1119 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_SHIFT 3 1120 u8 reserved2; 1121 struct mpa_ulp_buffer incoming_ulp_buffer /* host buffer for placing the incoming MPA reply */; 1122 struct regpair async_eqe_output_buf /* host buffer for async tcp/mpa completion information - must have space for at least 8 bytes */; 1123 struct regpair handle_for_async /* a host cookie that will be echoed back with in every qp-specific async EQE */; 1124 struct regpair shared_queue_addr /* Address of shared queue address that consist of SQ/RQ and FW internal queues (IRQ/ORQ/HQ) */; 1125 __le16 rcv_wnd /* TCP window after scaling */; 1126 u8 stats_counter_id /* Statistics counter ID to use */; 1127 u8 reserved3[13]; 1128 }; 1129 1130 1131 /* 1132 * iWARP TCP connection offload params passed by driver to FW 1133 */ 1134 struct iwarp_offload_params 1135 { 1136 struct mpa_ulp_buffer incoming_ulp_buffer /* host buffer for placing the incoming MPA request */; 1137 struct regpair async_eqe_output_buf /* host buffer for async tcp/mpa completion information - must have space for at least 8 bytes */; 1138 struct regpair handle_for_async /* host handle that will be echoed back with in every qp-specific async EQE */; 1139 __le16 physical_q0 /* Physical QM queue to be tied to logical Q0 */; 1140 __le16 physical_q1 /* Physical QM queue to be tied to logical Q1 */; 1141 u8 stats_counter_id /* Statistics counter ID to use */; 1142 u8 mpa_mode /* Basic/Enahnced. Used for a verification for incoming MPA request (use enum mpa_negotiation_mode) */; 1143 u8 reserved[10]; 1144 }; 1145 1146 1147 /* 1148 * iWARP query QP output params 1149 */ 1150 struct iwarp_query_qp_output_params 1151 { 1152 __le32 flags; 1153 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1 1154 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0 1155 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF 1156 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_SHIFT 1 1157 u8 reserved1[4] /* 64 bit alignment */; 1158 }; 1159 1160 1161 /* 1162 * iWARP query QP ramrod data 1163 */ 1164 struct iwarp_query_qp_ramrod_data 1165 { 1166 struct regpair output_params_addr; 1167 }; 1168 1169 1170 /* 1171 * iWARP Ramrod Command IDs 1172 */ 1173 enum iwarp_ramrod_cmd_id 1174 { 1175 IWARP_RAMROD_CMD_ID_TCP_OFFLOAD=11 /* iWARP TCP connection offload ramrod */, 1176 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD /* iWARP MPA offload ramrod */, 1177 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD_SEND_RTR, 1178 IWARP_RAMROD_CMD_ID_CREATE_QP, 1179 IWARP_RAMROD_CMD_ID_QUERY_QP, 1180 IWARP_RAMROD_CMD_ID_MODIFY_QP, 1181 IWARP_RAMROD_CMD_ID_DESTROY_QP, 1182 IWARP_RAMROD_CMD_ID_ABORT_TCP_OFFLOAD, 1183 MAX_IWARP_RAMROD_CMD_ID 1184 }; 1185 1186 1187 /* 1188 * Per PF iWARP retransmit path statistics 1189 */ 1190 struct iwarp_rxmit_stats_drv 1191 { 1192 struct regpair tx_go_to_slow_start_event_cnt /* Number of times slow start event occurred */; 1193 struct regpair tx_fast_retransmit_event_cnt /* Number of times fast retransmit event occurred */; 1194 }; 1195 1196 1197 /* 1198 * iWARP and TCP connection offload params passed by driver to FW in iWARP offload ramrod 1199 */ 1200 struct iwarp_tcp_offload_ramrod_data 1201 { 1202 struct iwarp_offload_params iwarp /* iWARP connection offload params */; 1203 struct tcp_offload_params_opt2 tcp /* tcp offload params */; 1204 }; 1205 1206 1207 /* 1208 * iWARP MPA negotiation types 1209 */ 1210 enum mpa_negotiation_mode 1211 { 1212 MPA_NEGOTIATION_TYPE_BASIC=1, 1213 MPA_NEGOTIATION_TYPE_ENHANCED=2, 1214 MAX_MPA_NEGOTIATION_MODE 1215 }; 1216 1217 1218 1219 1220 /* 1221 * iWARP MPA Enhanced mode RTR types 1222 */ 1223 enum mpa_rtr_type 1224 { 1225 MPA_RTR_TYPE_NONE=0 /* No RTR type */, 1226 MPA_RTR_TYPE_ZERO_SEND=1, 1227 MPA_RTR_TYPE_ZERO_WRITE=2, 1228 MPA_RTR_TYPE_ZERO_SEND_AND_WRITE=3, 1229 MPA_RTR_TYPE_ZERO_READ=4, 1230 MPA_RTR_TYPE_ZERO_SEND_AND_READ=5, 1231 MPA_RTR_TYPE_ZERO_WRITE_AND_READ=6, 1232 MPA_RTR_TYPE_ZERO_SEND_AND_WRITE_AND_READ=7, 1233 MAX_MPA_RTR_TYPE 1234 }; 1235 1236 1237 1238 1239 1240 1241 /* 1242 * unaligned opaque data received from LL2 1243 */ 1244 struct unaligned_opaque_data 1245 { 1246 __le16 first_mpa_offset /* offset of first MPA byte that should be processed */; 1247 u8 tcp_payload_offset /* offset of first the byte that comes after the last byte of the TCP Hdr */; 1248 u8 flags; 1249 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK 0x1 /* packet reached window right edge */ 1250 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT 0 1251 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK 0x1 /* Indication that the connection is closed. Clean all connecitons database. */ 1252 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_SHIFT 1 1253 #define UNALIGNED_OPAQUE_DATA_RESERVED_MASK 0x3F 1254 #define UNALIGNED_OPAQUE_DATA_RESERVED_SHIFT 2 1255 __le32 cid; 1256 }; 1257 1258 1259 1260 1261 1262 struct e4_mstorm_iwarp_conn_ag_ctx 1263 { 1264 u8 reserved /* cdu_validation */; 1265 u8 state /* state */; 1266 u8 flags0; 1267 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1268 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1269 #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1270 #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 1271 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3 /* cf0 */ 1272 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2 1273 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1274 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 1275 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1276 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 1277 u8 flags1; 1278 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1 /* cf0en */ 1279 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0 1280 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1281 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 1282 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1283 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 1284 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1285 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3 1286 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1287 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4 1288 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1289 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5 1290 #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1 /* rule3en */ 1291 #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6 1292 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1293 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7 1294 __le16 rcq_cons /* word0 */; 1295 __le16 rcq_cons_th /* word1 */; 1296 __le32 reg0 /* reg0 */; 1297 __le32 reg1 /* reg1 */; 1298 }; 1299 1300 1301 1302 struct e4_ustorm_iwarp_conn_ag_ctx 1303 { 1304 u8 reserved /* cdu_validation */; 1305 u8 byte1 /* state */; 1306 u8 flags0; 1307 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1308 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1309 #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1310 #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 1311 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1312 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2 1313 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1314 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 1315 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1316 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 1317 u8 flags1; 1318 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1319 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0 1320 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 /* cf4 */ 1321 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 1322 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 /* cf5 */ 1323 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 1324 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1325 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 6 1326 u8 flags2; 1327 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1328 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0 1329 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1330 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 1331 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1332 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 1333 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1334 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT 3 1335 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 /* cf4en */ 1336 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 1337 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 /* cf5en */ 1338 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 1339 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1340 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 6 1341 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 /* rule0en */ 1342 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 1343 u8 flags3; 1344 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1 /* rule1en */ 1345 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0 1346 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1347 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1 1348 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1349 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2 1350 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1351 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3 1352 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1353 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4 1354 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1355 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 5 1356 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1357 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6 1358 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1359 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7 1360 u8 byte2 /* byte2 */; 1361 u8 byte3 /* byte3 */; 1362 __le16 word0 /* conn_dpi */; 1363 __le16 word1 /* word1 */; 1364 __le32 cq_cons /* reg0 */; 1365 __le32 cq_se_prod /* reg1 */; 1366 __le32 cq_prod /* reg2 */; 1367 __le32 reg3 /* reg3 */; 1368 __le16 word2 /* word2 */; 1369 __le16 word3 /* word3 */; 1370 }; 1371 1372 1373 1374 struct e4_ystorm_iwarp_conn_ag_ctx 1375 { 1376 u8 byte0 /* cdu_validation */; 1377 u8 byte1 /* state */; 1378 u8 flags0; 1379 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1380 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0 1381 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1382 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 1383 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1384 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2 1385 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1386 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 1387 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1388 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 1389 u8 flags1; 1390 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1391 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0 1392 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1393 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 1394 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1395 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 1396 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1397 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3 1398 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1399 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4 1400 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1401 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5 1402 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1403 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 6 1404 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1405 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7 1406 u8 byte2 /* byte2 */; 1407 u8 byte3 /* byte3 */; 1408 __le16 word0 /* word0 */; 1409 __le32 reg0 /* reg0 */; 1410 __le32 reg1 /* reg1 */; 1411 __le16 word1 /* word1 */; 1412 __le16 word2 /* word2 */; 1413 __le16 word3 /* word3 */; 1414 __le16 word4 /* word4 */; 1415 __le32 reg2 /* reg2 */; 1416 __le32 reg3 /* reg3 */; 1417 }; 1418 1419 1420 struct e5_mstorm_iwarp_conn_ag_ctx 1421 { 1422 u8 reserved /* cdu_validation */; 1423 u8 state_and_core_id /* state_and_core_id */; 1424 u8 flags0; 1425 #define E5_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1426 #define E5_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1427 #define E5_MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1428 #define E5_MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 1429 #define E5_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3 /* cf0 */ 1430 #define E5_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2 1431 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1432 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 1433 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1434 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 1435 u8 flags1; 1436 #define E5_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1 /* cf0en */ 1437 #define E5_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0 1438 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1439 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 1440 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1441 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 1442 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1443 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3 1444 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1445 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4 1446 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1447 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5 1448 #define E5_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1 /* rule3en */ 1449 #define E5_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6 1450 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1451 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7 1452 __le16 rcq_cons /* word0 */; 1453 __le16 rcq_cons_th /* word1 */; 1454 __le32 reg0 /* reg0 */; 1455 __le32 reg1 /* reg1 */; 1456 }; 1457 1458 1459 1460 struct e5_ustorm_iwarp_conn_ag_ctx 1461 { 1462 u8 reserved /* cdu_validation */; 1463 u8 byte1 /* state_and_core_id */; 1464 u8 flags0; 1465 #define E5_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1466 #define E5_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1467 #define E5_USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1468 #define E5_USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 1469 #define E5_USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1470 #define E5_USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2 1471 #define E5_USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1472 #define E5_USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 1473 #define E5_USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1474 #define E5_USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 1475 u8 flags1; 1476 #define E5_USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1477 #define E5_USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0 1478 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 /* cf4 */ 1479 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 1480 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 /* cf5 */ 1481 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 1482 #define E5_USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1483 #define E5_USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 6 1484 u8 flags2; 1485 #define E5_USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1486 #define E5_USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0 1487 #define E5_USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1488 #define E5_USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 1489 #define E5_USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1490 #define E5_USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 1491 #define E5_USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1492 #define E5_USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT 3 1493 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 /* cf4en */ 1494 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 1495 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 /* cf5en */ 1496 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 1497 #define E5_USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1498 #define E5_USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 6 1499 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 /* rule0en */ 1500 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 1501 u8 flags3; 1502 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1 /* rule1en */ 1503 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0 1504 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1505 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1 1506 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1507 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2 1508 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1509 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3 1510 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1511 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4 1512 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1513 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 5 1514 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1515 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6 1516 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1517 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7 1518 u8 flags4; 1519 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 1520 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1521 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 1522 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1523 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 1524 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1525 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 1526 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 1527 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 1528 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 1529 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 1530 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 1531 u8 byte2 /* byte2 */; 1532 __le16 word0 /* conn_dpi */; 1533 __le16 word1 /* word1 */; 1534 __le32 cq_cons /* reg0 */; 1535 __le32 cq_se_prod /* reg1 */; 1536 __le32 cq_prod /* reg2 */; 1537 __le32 reg3 /* reg3 */; 1538 __le16 word2 /* word2 */; 1539 __le16 word3 /* word3 */; 1540 }; 1541 1542 1543 1544 struct e5_ystorm_iwarp_conn_ag_ctx 1545 { 1546 u8 byte0 /* cdu_validation */; 1547 u8 byte1 /* state_and_core_id */; 1548 u8 flags0; 1549 #define E5_YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1550 #define E5_YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0 1551 #define E5_YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1552 #define E5_YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 1553 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1554 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2 1555 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1556 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 1557 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1558 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 1559 u8 flags1; 1560 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1561 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0 1562 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1563 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 1564 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1565 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 1566 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1567 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3 1568 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1569 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4 1570 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1571 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5 1572 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1573 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 6 1574 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1575 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7 1576 u8 byte2 /* byte2 */; 1577 u8 byte3 /* byte3 */; 1578 __le16 word0 /* word0 */; 1579 __le32 reg0 /* reg0 */; 1580 __le32 reg1 /* reg1 */; 1581 __le16 word1 /* word1 */; 1582 __le16 word2 /* word2 */; 1583 __le16 word3 /* word3 */; 1584 __le16 word4 /* word4 */; 1585 __le32 reg2 /* reg2 */; 1586 __le32 reg3 /* reg3 */; 1587 }; 1588 1589 #endif /* __ECORE_HSI_IWARP__ */ 1590