1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 32 #ifndef __ECORE_HSI_RDMA__ 33 #define __ECORE_HSI_RDMA__ 34 /************************************************************************/ 35 /* Add include to common rdma target for both eCore and protocol rdma driver */ 36 /************************************************************************/ 37 #include "rdma_common.h" 38 39 /* 40 * The roce task context of Mstorm 41 */ 42 struct mstorm_rdma_task_st_ctx 43 { 44 struct regpair temp[4]; 45 }; 46 47 48 /* 49 * rdma function init ramrod data 50 */ 51 struct rdma_close_func_ramrod_data 52 { 53 u8 cnq_start_offset; 54 u8 num_cnqs; 55 u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */; 56 u8 vf_valid; 57 u8 reserved[4]; 58 }; 59 60 61 /* 62 * rdma function init CNQ parameters 63 */ 64 struct rdma_cnq_params 65 { 66 __le16 sb_num /* Status block number used by the queue */; 67 u8 sb_index /* Status block index used by the queue */; 68 u8 num_pbl_pages /* Number of pages in the PBL allocated for this queue */; 69 __le32 reserved; 70 struct regpair pbl_base_addr /* Address to the first entry of the queue PBL */; 71 __le16 queue_zone_num /* Queue Zone ID used for CNQ consumer update */; 72 u8 reserved1[6]; 73 }; 74 75 76 /* 77 * rdma create cq ramrod data 78 */ 79 struct rdma_create_cq_ramrod_data 80 { 81 struct regpair cq_handle; 82 struct regpair pbl_addr; 83 __le32 max_cqes; 84 __le16 pbl_num_pages; 85 __le16 dpi; 86 u8 is_two_level_pbl; 87 u8 cnq_id; 88 u8 pbl_log_page_size; 89 u8 toggle_bit; 90 __le16 int_timeout /* Timeout used for interrupt moderation */; 91 __le16 reserved1; 92 }; 93 94 95 /* 96 * rdma deregister tid ramrod data 97 */ 98 struct rdma_deregister_tid_ramrod_data 99 { 100 __le32 itid; 101 __le32 reserved; 102 }; 103 104 105 /* 106 * rdma destroy cq output params 107 */ 108 struct rdma_destroy_cq_output_params 109 { 110 __le16 cnq_num /* Sequence number of completion notification sent for the cq on the associated CNQ */; 111 __le16 reserved0; 112 __le32 reserved1; 113 }; 114 115 116 /* 117 * rdma destroy cq ramrod data 118 */ 119 struct rdma_destroy_cq_ramrod_data 120 { 121 struct regpair output_params_addr; 122 }; 123 124 125 /* 126 * RDMA slow path EQ cmd IDs 127 */ 128 enum rdma_event_opcode 129 { 130 RDMA_EVENT_UNUSED, 131 RDMA_EVENT_FUNC_INIT, 132 RDMA_EVENT_FUNC_CLOSE, 133 RDMA_EVENT_REGISTER_MR, 134 RDMA_EVENT_DEREGISTER_MR, 135 RDMA_EVENT_CREATE_CQ, 136 RDMA_EVENT_RESIZE_CQ, 137 RDMA_EVENT_DESTROY_CQ, 138 RDMA_EVENT_CREATE_SRQ, 139 RDMA_EVENT_MODIFY_SRQ, 140 RDMA_EVENT_DESTROY_SRQ, 141 MAX_RDMA_EVENT_OPCODE 142 }; 143 144 145 /* 146 * RDMA FW return code for slow path ramrods 147 */ 148 enum rdma_fw_return_code 149 { 150 RDMA_RETURN_OK=0, 151 RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR, 152 RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR, 153 RDMA_RETURN_RESIZE_CQ_ERR, 154 RDMA_RETURN_NIG_DRAIN_REQ, 155 MAX_RDMA_FW_RETURN_CODE 156 }; 157 158 159 /* 160 * rdma function init header 161 */ 162 struct rdma_init_func_hdr 163 { 164 u8 cnq_start_offset /* First RDMA CNQ */; 165 u8 num_cnqs /* Number of CNQs */; 166 u8 cq_ring_mode /* 0 for 32 bit cq producer and consumer counters and 1 for 16 bit */; 167 u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */; 168 u8 vf_valid; 169 u8 reserved[3]; 170 }; 171 172 173 /* 174 * rdma function init ramrod data 175 */ 176 struct rdma_init_func_ramrod_data 177 { 178 struct rdma_init_func_hdr params_header; 179 struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES]; 180 }; 181 182 183 /* 184 * RDMA ramrod command IDs 185 */ 186 enum rdma_ramrod_cmd_id 187 { 188 RDMA_RAMROD_UNUSED, 189 RDMA_RAMROD_FUNC_INIT, 190 RDMA_RAMROD_FUNC_CLOSE, 191 RDMA_RAMROD_REGISTER_MR, 192 RDMA_RAMROD_DEREGISTER_MR, 193 RDMA_RAMROD_CREATE_CQ, 194 RDMA_RAMROD_RESIZE_CQ, 195 RDMA_RAMROD_DESTROY_CQ, 196 RDMA_RAMROD_CREATE_SRQ, 197 RDMA_RAMROD_MODIFY_SRQ, 198 RDMA_RAMROD_DESTROY_SRQ, 199 MAX_RDMA_RAMROD_CMD_ID 200 }; 201 202 203 /* 204 * rdma register tid ramrod data 205 */ 206 struct rdma_register_tid_ramrod_data 207 { 208 __le32 flags; 209 #define RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID_MASK 0x3FFFF 210 #define RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID_SHIFT 0 211 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F 212 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 18 213 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1 214 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT 23 215 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1 216 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT 24 217 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1 218 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT 25 219 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1 220 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT 26 221 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1 222 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT 27 223 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1 224 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT 28 225 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1 226 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT 29 227 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1 228 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT 30 229 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1 230 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT 31 231 u8 flags1; 232 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F 233 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0 234 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7 235 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT 5 236 u8 flags2; 237 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1 /* Bit indicating that this MR is DMA_MR meaning SGEs that use it have the physical address on them */ 238 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0 239 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1 /* Bit indicating that this MR has DIF protection enabled. */ 240 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT 1 241 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F 242 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT 2 243 u8 key; 244 u8 length_hi; 245 u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */; 246 u8 vf_valid; 247 __le16 pd; 248 __le32 length_lo /* lower 32 bits of the registered MR length. */; 249 __le32 itid; 250 __le32 reserved2; 251 struct regpair va; 252 struct regpair pbl_base; 253 struct regpair dif_error_addr /* DIF TX IO writes error information to this location when memory region is invalidated. */; 254 struct regpair dif_runt_addr /* DIF RX IO writes runt value to this location when last RDMA Read of the IO has completed. */; 255 __le32 reserved3[2]; 256 }; 257 258 259 /* 260 * rdma resize cq output params 261 */ 262 struct rdma_resize_cq_output_params 263 { 264 __le32 old_cq_cons /* cq consumer value on old PBL */; 265 __le32 old_cq_prod /* cq producer value on old PBL */; 266 }; 267 268 269 /* 270 * rdma resize cq ramrod data 271 */ 272 struct rdma_resize_cq_ramrod_data 273 { 274 u8 flags; 275 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1 276 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0 277 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1 278 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1 279 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x3F 280 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 2 281 u8 pbl_log_page_size; 282 __le16 pbl_num_pages; 283 __le32 max_cqes; 284 struct regpair pbl_addr; 285 struct regpair output_params_addr; 286 }; 287 288 289 /* 290 * The rdma storm context of Mstorm 291 */ 292 struct rdma_srq_context 293 { 294 struct regpair temp[8]; 295 }; 296 297 298 /* 299 * rdma create qp requester ramrod data 300 */ 301 struct rdma_srq_create_ramrod_data 302 { 303 struct regpair pbl_base_addr /* SRQ PBL base address */; 304 __le16 pages_in_srq_pbl /* Number of pages in PBL */; 305 __le16 pd_id; 306 struct rdma_srq_id srq_id /* SRQ Index */; 307 __le16 page_size /* Page size in SGEs(16 bytes) elements. Supports up to 2M bytes page size */; 308 __le16 reserved1; 309 __le32 reserved2; 310 struct regpair producers_addr /* SRQ PBL base address */; 311 }; 312 313 314 /* 315 * rdma create qp requester ramrod data 316 */ 317 struct rdma_srq_destroy_ramrod_data 318 { 319 struct rdma_srq_id srq_id /* SRQ Index */; 320 __le32 reserved; 321 }; 322 323 324 /* 325 * rdma create qp requester ramrod data 326 */ 327 struct rdma_srq_modify_ramrod_data 328 { 329 struct rdma_srq_id srq_id /* SRQ Index */; 330 __le32 wqe_limit; 331 }; 332 333 334 /* 335 * The rdma task context of Mstorm 336 */ 337 struct ystorm_rdma_task_st_ctx 338 { 339 struct regpair temp[4]; 340 }; 341 342 struct e4_ystorm_rdma_task_ag_ctx 343 { 344 u8 reserved /* cdu_validation */; 345 u8 byte1 /* state */; 346 __le16 msem_ctx_upd_seq /* icid */; 347 u8 flags0; 348 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 349 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 350 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 351 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 352 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 353 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 354 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1 /* bit2 */ 355 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6 356 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 357 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 358 u8 flags1; 359 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 360 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 361 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 362 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 363 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */ 364 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 365 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 366 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 367 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 368 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 369 u8 flags2; 370 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 371 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 372 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 373 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 374 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 375 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 376 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 377 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 378 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 379 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 380 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 381 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 382 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 383 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 384 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 385 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 386 u8 key /* byte2 */; 387 __le32 mw_cnt /* reg0 */; 388 u8 ref_cnt_seq /* byte3 */; 389 u8 ctx_upd_seq /* byte4 */; 390 __le16 dif_flags /* word1 */; 391 __le16 tx_ref_count /* word2 */; 392 __le16 last_used_ltid /* word3 */; 393 __le16 parent_mr_lo /* word4 */; 394 __le16 parent_mr_hi /* word5 */; 395 __le32 fbo_lo /* reg1 */; 396 __le32 fbo_hi /* reg2 */; 397 }; 398 399 struct e4_mstorm_rdma_task_ag_ctx 400 { 401 u8 reserved /* cdu_validation */; 402 u8 byte1 /* state */; 403 __le16 icid /* icid */; 404 u8 flags0; 405 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 406 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 407 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 408 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 409 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 410 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 411 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 412 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 413 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 414 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 415 u8 flags1; 416 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 417 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 418 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 419 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 420 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */ 421 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4 422 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 423 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 424 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 425 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 426 u8 flags2; 427 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 428 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0 429 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 430 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 431 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 432 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 433 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 434 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 435 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 436 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 437 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 438 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 439 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 440 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 441 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 442 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 443 u8 key /* byte2 */; 444 __le32 mw_cnt /* reg0 */; 445 u8 ref_cnt_seq /* byte3 */; 446 u8 ctx_upd_seq /* byte4 */; 447 __le16 dif_flags /* word1 */; 448 __le16 tx_ref_count /* word2 */; 449 __le16 last_used_ltid /* word3 */; 450 __le16 parent_mr_lo /* word4 */; 451 __le16 parent_mr_hi /* word5 */; 452 __le32 fbo_lo /* reg1 */; 453 __le32 fbo_hi /* reg2 */; 454 }; 455 456 /* 457 * The roce task context of Ustorm 458 */ 459 struct ustorm_rdma_task_st_ctx 460 { 461 struct regpair temp[2]; 462 }; 463 464 struct e4_ustorm_rdma_task_ag_ctx 465 { 466 u8 reserved /* cdu_validation */; 467 u8 byte1 /* state */; 468 __le16 icid /* icid */; 469 u8 flags0; 470 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 471 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 472 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 473 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 474 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1 /* exist_in_qm1 */ 475 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5 476 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3 /* timer0cf */ 477 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6 478 u8 flags1; 479 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3 /* timer1cf */ 480 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0 481 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3 /* timer2cf */ 482 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2 483 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 484 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4 485 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 /* cf4 */ 486 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 487 u8 flags2; 488 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1 /* cf0en */ 489 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0 490 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1 /* cf1en */ 491 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1 492 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1 /* cf2en */ 493 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2 494 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 495 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3 496 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 /* cf4en */ 497 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 498 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 499 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5 500 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 501 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6 502 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 503 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7 504 u8 flags3; 505 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 506 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0 507 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 508 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1 509 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 510 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2 511 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 512 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3 513 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF /* nibble1 */ 514 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 515 __le32 dif_err_intervals /* reg0 */; 516 __le32 dif_error_1st_interval /* reg1 */; 517 __le32 reg2 /* reg2 */; 518 __le32 dif_runt_value /* reg3 */; 519 __le32 reg4 /* reg4 */; 520 __le32 reg5 /* reg5 */; 521 }; 522 523 /* 524 * RDMA task context 525 */ 526 struct rdma_task_context 527 { 528 struct ystorm_rdma_task_st_ctx ystorm_st_context /* ystorm storm context */; 529 struct e4_ystorm_rdma_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */; 530 struct tdif_task_context tdif_context /* tdif context */; 531 struct e4_mstorm_rdma_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */; 532 struct mstorm_rdma_task_st_ctx mstorm_st_context /* mstorm storm context */; 533 struct rdif_task_context rdif_context /* rdif context */; 534 struct ustorm_rdma_task_st_ctx ustorm_st_context /* ustorm storm context */; 535 struct regpair ustorm_st_padding[2] /* padding */; 536 struct e4_ustorm_rdma_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 537 }; 538 539 540 /* 541 * RDMA Tid type enumeration (for register_tid ramrod) 542 */ 543 enum rdma_tid_type 544 { 545 RDMA_TID_REGISTERED_MR, 546 RDMA_TID_FMR, 547 RDMA_TID_MW_TYPE1, 548 RDMA_TID_MW_TYPE2A, 549 MAX_RDMA_TID_TYPE 550 }; 551 552 553 554 555 struct E4XstormRoceConnAgCtxDqExtLdPart 556 { 557 u8 reserved0 /* cdu_validation */; 558 u8 state /* state */; 559 u8 flags0; 560 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 561 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 562 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1 /* exist_in_qm1 */ 563 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1 564 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1 /* exist_in_qm2 */ 565 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2 566 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 567 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 568 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1 /* bit4 */ 569 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4 570 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1 /* cf_array_active */ 571 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5 572 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1 /* bit6 */ 573 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6 574 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1 /* bit7 */ 575 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7 576 u8 flags1; 577 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1 /* bit8 */ 578 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0 579 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1 /* bit9 */ 580 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1 581 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1 /* bit10 */ 582 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2 583 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 /* bit11 */ 584 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 585 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1 /* bit12 */ 586 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4 587 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_MASK 0x1 /* bit13 */ 588 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_SHIFT 5 589 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1 /* bit14 */ 590 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6 591 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 592 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7 593 u8 flags2; 594 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3 /* timer0cf */ 595 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0 596 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3 /* timer1cf */ 597 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2 598 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3 /* timer2cf */ 599 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4 600 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3 /* timer_stop_all */ 601 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6 602 u8 flags3; 603 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3 /* cf4 */ 604 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0 605 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3 /* cf5 */ 606 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2 607 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3 /* cf6 */ 608 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4 609 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 610 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6 611 u8 flags4; 612 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3 /* cf8 */ 613 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0 614 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3 /* cf9 */ 615 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2 616 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3 /* cf10 */ 617 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4 618 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3 /* cf11 */ 619 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6 620 u8 flags5; 621 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3 /* cf12 */ 622 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0 623 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3 /* cf13 */ 624 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2 625 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3 /* cf14 */ 626 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4 627 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3 /* cf15 */ 628 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6 629 u8 flags6; 630 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3 /* cf16 */ 631 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0 632 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3 /* cf_array_cf */ 633 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2 634 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3 /* cf18 */ 635 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4 636 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3 /* cf19 */ 637 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6 638 u8 flags7; 639 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3 /* cf20 */ 640 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0 641 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3 /* cf21 */ 642 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2 643 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 /* cf22 */ 644 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 645 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 /* cf0en */ 646 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 647 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 /* cf1en */ 648 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 649 u8 flags8; 650 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 /* cf2en */ 651 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 652 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 /* cf3en */ 653 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 654 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 /* cf4en */ 655 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 656 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 /* cf5en */ 657 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 658 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 /* cf6en */ 659 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 660 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 661 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5 662 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 /* cf8en */ 663 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 664 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 /* cf9en */ 665 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 666 u8 flags9; 667 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 /* cf10en */ 668 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 669 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 /* cf11en */ 670 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 671 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 /* cf12en */ 672 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 673 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 /* cf13en */ 674 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 675 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 /* cf14en */ 676 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 677 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 /* cf15en */ 678 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 679 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1 /* cf16en */ 680 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6 681 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1 /* cf_array_cf_en */ 682 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7 683 u8 flags10; 684 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1 /* cf18en */ 685 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0 686 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1 /* cf19en */ 687 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1 688 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1 /* cf20en */ 689 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2 690 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1 /* cf21en */ 691 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3 692 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 693 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 694 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1 /* cf23en */ 695 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5 696 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1 /* rule0en */ 697 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6 698 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1 /* rule1en */ 699 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7 700 u8 flags11; 701 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1 /* rule2en */ 702 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0 703 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1 /* rule3en */ 704 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1 705 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1 /* rule4en */ 706 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2 707 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 /* rule5en */ 708 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 709 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 /* rule6en */ 710 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 711 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 /* rule7en */ 712 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 713 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 /* rule8en */ 714 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 715 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 /* rule9en */ 716 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 717 u8 flags12; 718 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 /* rule10en */ 719 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 720 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 /* rule11en */ 721 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 722 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 /* rule12en */ 723 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 724 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 /* rule13en */ 725 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 726 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 /* rule14en */ 727 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 728 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 /* rule15en */ 729 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 730 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 /* rule16en */ 731 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 732 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 /* rule17en */ 733 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 734 u8 flags13; 735 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 /* rule18en */ 736 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 737 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 /* rule19en */ 738 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 739 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 /* rule20en */ 740 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 741 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 /* rule21en */ 742 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 743 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 /* rule22en */ 744 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 745 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 /* rule23en */ 746 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 747 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 /* rule24en */ 748 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 749 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 /* rule25en */ 750 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 751 u8 flags14; 752 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1 /* bit16 */ 753 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0 754 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1 /* bit17 */ 755 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1 756 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 757 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2 758 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1 /* bit20 */ 759 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4 760 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 761 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 762 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3 /* cf23 */ 763 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6 764 u8 byte2 /* byte2 */; 765 __le16 physical_q0 /* physical_q0 */; 766 __le16 word1 /* physical_q1 */; 767 __le16 word2 /* physical_q2 */; 768 __le16 word3 /* word3 */; 769 __le16 word4 /* word4 */; 770 __le16 word5 /* word5 */; 771 __le16 conn_dpi /* conn_dpi */; 772 u8 byte3 /* byte3 */; 773 u8 byte4 /* byte4 */; 774 u8 byte5 /* byte5 */; 775 u8 byte6 /* byte6 */; 776 __le32 reg0 /* reg0 */; 777 __le32 reg1 /* reg1 */; 778 __le32 reg2 /* reg2 */; 779 __le32 snd_nxt_psn /* reg3 */; 780 __le32 reg4 /* reg4 */; 781 }; 782 783 784 struct e4_mstorm_rdma_conn_ag_ctx 785 { 786 u8 byte0 /* cdu_validation */; 787 u8 byte1 /* state */; 788 u8 flags0; 789 #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 790 #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0 791 #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 792 #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 793 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 794 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2 795 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 796 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 797 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 798 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 799 u8 flags1; 800 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 801 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0 802 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 803 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 804 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 805 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 806 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 807 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3 808 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 809 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4 810 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 811 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5 812 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 813 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6 814 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 815 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7 816 __le16 word0 /* word0 */; 817 __le16 word1 /* word1 */; 818 __le32 reg0 /* reg0 */; 819 __le32 reg1 /* reg1 */; 820 }; 821 822 823 824 struct e4_tstorm_rdma_conn_ag_ctx 825 { 826 u8 reserved0 /* cdu_validation */; 827 u8 byte1 /* state */; 828 u8 flags0; 829 #define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 830 #define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 831 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 832 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 833 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 834 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2 835 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 836 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3 837 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 838 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4 839 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 840 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5 841 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 842 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6 843 u8 flags1; 844 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 845 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0 846 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 847 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2 848 #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */ 849 #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 850 #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */ 851 #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 852 u8 flags2; 853 #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */ 854 #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 855 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 856 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2 857 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 858 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4 859 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 860 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6 861 u8 flags3; 862 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 863 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0 864 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 865 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2 866 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 867 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4 868 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 869 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5 870 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 871 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6 872 #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */ 873 #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 874 u8 flags4; 875 #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */ 876 #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 877 #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */ 878 #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 879 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 880 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2 881 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 882 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3 883 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 884 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4 885 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 886 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5 887 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 888 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6 889 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 890 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7 891 u8 flags5; 892 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 893 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0 894 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 895 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 896 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 897 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 898 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 899 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 900 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 901 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 902 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 903 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 904 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 905 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 906 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 907 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 908 __le32 reg0 /* reg0 */; 909 __le32 reg1 /* reg1 */; 910 __le32 reg2 /* reg2 */; 911 __le32 reg3 /* reg3 */; 912 __le32 reg4 /* reg4 */; 913 __le32 reg5 /* reg5 */; 914 __le32 reg6 /* reg6 */; 915 __le32 reg7 /* reg7 */; 916 __le32 reg8 /* reg8 */; 917 u8 byte2 /* byte2 */; 918 u8 byte3 /* byte3 */; 919 __le16 word0 /* word0 */; 920 u8 byte4 /* byte4 */; 921 u8 byte5 /* byte5 */; 922 __le16 word1 /* word1 */; 923 __le16 word2 /* conn_dpi */; 924 __le16 word3 /* word3 */; 925 __le32 reg9 /* reg9 */; 926 __le32 reg10 /* reg10 */; 927 }; 928 929 930 struct e4_tstorm_rdma_task_ag_ctx 931 { 932 u8 byte0 /* cdu_validation */; 933 u8 byte1 /* state */; 934 __le16 word0 /* icid */; 935 u8 flags0; 936 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF /* connection_type */ 937 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0 938 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 939 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4 940 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 941 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 942 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 943 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 944 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 945 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 946 u8 flags1; 947 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 948 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 949 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 950 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1 951 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 952 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2 953 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 954 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4 955 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 956 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6 957 u8 flags2; 958 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 959 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0 960 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3 /* cf4 */ 961 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2 962 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3 /* cf5 */ 963 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4 964 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3 /* cf6 */ 965 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6 966 u8 flags3; 967 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3 /* cf7 */ 968 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0 969 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 970 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2 971 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 972 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3 973 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 974 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4 975 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 976 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5 977 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 978 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6 979 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 980 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7 981 u8 flags4; 982 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 983 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0 984 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 985 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1 986 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 987 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2 988 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 989 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3 990 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 991 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4 992 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 993 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5 994 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 995 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6 996 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 997 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7 998 u8 byte2 /* byte2 */; 999 __le16 word1 /* word1 */; 1000 __le32 reg0 /* reg0 */; 1001 u8 byte3 /* byte3 */; 1002 u8 byte4 /* byte4 */; 1003 __le16 word2 /* word2 */; 1004 __le16 word3 /* word3 */; 1005 __le16 word4 /* word4 */; 1006 __le32 reg1 /* reg1 */; 1007 __le32 reg2 /* reg2 */; 1008 }; 1009 1010 1011 struct e4_ustorm_rdma_conn_ag_ctx 1012 { 1013 u8 reserved /* cdu_validation */; 1014 u8 byte1 /* state */; 1015 u8 flags0; 1016 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1017 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1018 #define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1019 #define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1020 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* timer0cf */ 1021 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2 1022 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1023 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 1024 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1025 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 1026 u8 flags1; 1027 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1028 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0 1029 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 /* cf4 */ 1030 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 1031 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 /* cf5 */ 1032 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 1033 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1034 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6 1035 u8 flags2; 1036 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf0en */ 1037 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 1038 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1039 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 1040 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1041 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 1042 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1043 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3 1044 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 /* cf4en */ 1045 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 1046 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 /* cf5en */ 1047 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 1048 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1049 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6 1050 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 /* rule0en */ 1051 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 1052 u8 flags3; 1053 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1 /* rule1en */ 1054 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0 1055 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1056 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 1057 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1058 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 1059 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1060 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 1061 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1062 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 1063 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1064 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 1065 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1066 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 1067 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1068 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 1069 u8 byte2 /* byte2 */; 1070 u8 byte3 /* byte3 */; 1071 __le16 conn_dpi /* conn_dpi */; 1072 __le16 word1 /* word1 */; 1073 __le32 cq_cons /* reg0 */; 1074 __le32 cq_se_prod /* reg1 */; 1075 __le32 cq_prod /* reg2 */; 1076 __le32 reg3 /* reg3 */; 1077 __le16 int_timeout /* word2 */; 1078 __le16 word3 /* word3 */; 1079 }; 1080 1081 1082 1083 struct e4_xstorm_rdma_conn_ag_ctx 1084 { 1085 u8 reserved0 /* cdu_validation */; 1086 u8 state /* state */; 1087 u8 flags0; 1088 #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1089 #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1090 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1091 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1092 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 /* exist_in_qm2 */ 1093 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2 1094 #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 1095 #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 1096 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1097 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4 1098 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 /* cf_array_active */ 1099 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5 1100 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */ 1101 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6 1102 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */ 1103 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7 1104 u8 flags1; 1105 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */ 1106 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0 1107 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1 /* bit9 */ 1108 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1 1109 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 1110 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2 1111 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 1112 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3 1113 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 1114 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4 1115 #define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit13 */ 1116 #define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 5 1117 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */ 1118 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6 1119 #define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 1120 #define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 1121 u8 flags2; 1122 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1123 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0 1124 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1125 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2 1126 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1127 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4 1128 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1129 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6 1130 u8 flags3; 1131 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1132 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0 1133 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1134 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2 1135 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1136 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4 1137 #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 1138 #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1139 u8 flags4; 1140 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1141 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0 1142 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1143 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2 1144 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1145 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4 1146 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 1147 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6 1148 u8 flags5; 1149 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 1150 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0 1151 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 1152 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2 1153 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 1154 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4 1155 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 1156 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6 1157 u8 flags6; 1158 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 1159 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0 1160 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 1161 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2 1162 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 1163 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4 1164 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */ 1165 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6 1166 u8 flags7; 1167 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */ 1168 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0 1169 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */ 1170 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2 1171 #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 1172 #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4 1173 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1174 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6 1175 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1176 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7 1177 u8 flags8; 1178 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1179 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0 1180 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1181 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1 1182 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1183 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2 1184 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1185 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3 1186 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1187 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4 1188 #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 1189 #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 1190 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1191 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6 1192 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1193 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7 1194 u8 flags9; 1195 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1196 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0 1197 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 1198 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1 1199 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 1200 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2 1201 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 1202 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3 1203 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 1204 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4 1205 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 1206 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5 1207 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 1208 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6 1209 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 1210 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7 1211 u8 flags10; 1212 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 1213 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0 1214 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */ 1215 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1 1216 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */ 1217 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2 1218 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */ 1219 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3 1220 #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1221 #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 1222 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 1223 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5 1224 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1225 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6 1226 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1227 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7 1228 u8 flags11; 1229 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1230 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0 1231 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1232 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1 1233 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1234 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2 1235 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1236 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3 1237 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1238 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4 1239 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1240 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5 1241 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 1242 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 1243 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 1244 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7 1245 u8 flags12; 1246 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 1247 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0 1248 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 1249 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1 1250 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 1251 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 1252 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 1253 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 1254 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 1255 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4 1256 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 1257 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5 1258 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 1259 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6 1260 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 1261 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7 1262 u8 flags13; 1263 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 1264 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0 1265 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 1266 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1 1267 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 1268 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 1269 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 1270 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 1271 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 1272 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 1273 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 1274 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 1275 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 1276 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 1277 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 1278 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 1279 u8 flags14; 1280 #define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1 /* bit16 */ 1281 #define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0 1282 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 1283 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1 1284 #define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 1285 #define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 1286 #define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1 /* bit20 */ 1287 #define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4 1288 #define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 1289 #define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 1290 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 1291 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6 1292 u8 byte2 /* byte2 */; 1293 __le16 physical_q0 /* physical_q0 */; 1294 __le16 word1 /* physical_q1 */; 1295 __le16 word2 /* physical_q2 */; 1296 __le16 word3 /* word3 */; 1297 __le16 word4 /* word4 */; 1298 __le16 word5 /* word5 */; 1299 __le16 conn_dpi /* conn_dpi */; 1300 u8 byte3 /* byte3 */; 1301 u8 byte4 /* byte4 */; 1302 u8 byte5 /* byte5 */; 1303 u8 byte6 /* byte6 */; 1304 __le32 reg0 /* reg0 */; 1305 __le32 reg1 /* reg1 */; 1306 __le32 reg2 /* reg2 */; 1307 __le32 snd_nxt_psn /* reg3 */; 1308 __le32 reg4 /* reg4 */; 1309 __le32 reg5 /* cf_array0 */; 1310 __le32 reg6 /* cf_array1 */; 1311 }; 1312 1313 1314 struct e4_ystorm_rdma_conn_ag_ctx 1315 { 1316 u8 byte0 /* cdu_validation */; 1317 u8 byte1 /* state */; 1318 u8 flags0; 1319 #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1320 #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0 1321 #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1322 #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1323 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1324 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2 1325 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1326 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 1327 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1328 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 1329 u8 flags1; 1330 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1331 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0 1332 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1333 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 1334 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1335 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 1336 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1337 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3 1338 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1339 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4 1340 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1341 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5 1342 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1343 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6 1344 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1345 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7 1346 u8 byte2 /* byte2 */; 1347 u8 byte3 /* byte3 */; 1348 __le16 word0 /* word0 */; 1349 __le32 reg0 /* reg0 */; 1350 __le32 reg1 /* reg1 */; 1351 __le16 word1 /* word1 */; 1352 __le16 word2 /* word2 */; 1353 __le16 word3 /* word3 */; 1354 __le16 word4 /* word4 */; 1355 __le32 reg2 /* reg2 */; 1356 __le32 reg3 /* reg3 */; 1357 }; 1358 1359 1360 1361 struct e5_mstorm_rdma_conn_ag_ctx 1362 { 1363 u8 byte0 /* cdu_validation */; 1364 u8 byte1 /* state_and_core_id */; 1365 u8 flags0; 1366 #define E5_MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1367 #define E5_MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0 1368 #define E5_MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1369 #define E5_MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1370 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1371 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2 1372 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1373 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 1374 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1375 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 1376 u8 flags1; 1377 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1378 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0 1379 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1380 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 1381 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1382 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 1383 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1384 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3 1385 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1386 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4 1387 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1388 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5 1389 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1390 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6 1391 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1392 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7 1393 __le16 word0 /* word0 */; 1394 __le16 word1 /* word1 */; 1395 __le32 reg0 /* reg0 */; 1396 __le32 reg1 /* reg1 */; 1397 }; 1398 1399 1400 struct e5_mstorm_rdma_task_ag_ctx 1401 { 1402 u8 reserved /* cdu_validation */; 1403 u8 byte1 /* state_and_core_id */; 1404 __le16 icid /* icid */; 1405 u8 flags0; 1406 #define E5_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 1407 #define E5_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 1408 #define E5_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1409 #define E5_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 1410 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1411 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 1412 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1413 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 1414 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1415 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 1416 u8 flags1; 1417 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1418 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 1419 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1420 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 1421 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1422 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4 1423 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1424 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 1425 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1426 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 1427 u8 flags2; 1428 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1429 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0 1430 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1431 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 1432 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1433 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 1434 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1435 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 1436 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1437 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 1438 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1439 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 1440 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1441 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 1442 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1443 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 1444 u8 flags3; 1445 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit4 */ 1446 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_SHIFT 0 1447 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_MASK 0x3 /* cf3 */ 1448 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_SHIFT 1 1449 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf4 */ 1450 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_SHIFT 3 1451 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* cf3en */ 1452 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_SHIFT 5 1453 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf4en */ 1454 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_SHIFT 6 1455 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule7en */ 1456 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_SHIFT 7 1457 __le32 mw_cnt /* reg0 */; 1458 u8 key /* byte2 */; 1459 u8 ref_cnt_seq /* byte3 */; 1460 u8 ctx_upd_seq /* byte4 */; 1461 u8 e4_reserved7 /* byte5 */; 1462 __le16 dif_flags /* regpair0 */; 1463 __le16 tx_ref_count /* word2 */; 1464 __le16 last_used_ltid /* word3 */; 1465 __le16 parent_mr_lo /* word4 */; 1466 __le16 parent_mr_hi /* regpair1 */; 1467 __le16 e4_reserved8 /* word6 */; 1468 __le32 fbo_lo /* reg1 */; 1469 }; 1470 1471 1472 struct e5_tstorm_rdma_conn_ag_ctx 1473 { 1474 u8 reserved0 /* cdu_validation */; 1475 u8 byte1 /* state_and_core_id */; 1476 u8 flags0; 1477 #define E5_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1478 #define E5_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1479 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1480 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1481 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1482 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2 1483 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1484 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3 1485 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1486 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4 1487 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 1488 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5 1489 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1490 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6 1491 u8 flags1; 1492 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1493 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0 1494 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1495 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2 1496 #define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */ 1497 #define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 1498 #define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */ 1499 #define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1500 u8 flags2; 1501 #define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */ 1502 #define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 1503 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1504 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2 1505 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1506 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4 1507 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1508 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6 1509 u8 flags3; 1510 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1511 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0 1512 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1513 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2 1514 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1515 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4 1516 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1517 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5 1518 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1519 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6 1520 #define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */ 1521 #define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 1522 u8 flags4; 1523 #define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */ 1524 #define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 1525 #define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */ 1526 #define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 1527 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1528 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2 1529 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1530 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3 1531 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1532 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4 1533 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1534 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5 1535 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1536 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6 1537 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1538 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7 1539 u8 flags5; 1540 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1541 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0 1542 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1543 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 1544 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1545 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 1546 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1547 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 1548 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1549 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 1550 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1551 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 1552 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1553 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 1554 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1555 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 1556 u8 flags6; 1557 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 1558 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1559 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 1560 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1561 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 1562 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1563 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 1564 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 1565 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 1566 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 1567 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 1568 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 1569 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 1570 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 1571 u8 byte2 /* byte2 */; 1572 __le16 word0 /* word0 */; 1573 __le32 reg0 /* reg0 */; 1574 __le32 reg1 /* reg1 */; 1575 __le32 reg2 /* reg2 */; 1576 __le32 reg3 /* reg3 */; 1577 __le32 reg4 /* reg4 */; 1578 __le32 reg5 /* reg5 */; 1579 __le32 reg6 /* reg6 */; 1580 __le32 reg7 /* reg7 */; 1581 __le32 reg8 /* reg8 */; 1582 u8 byte3 /* byte3 */; 1583 u8 byte4 /* byte4 */; 1584 u8 byte5 /* byte5 */; 1585 u8 e4_reserved8 /* byte6 */; 1586 __le16 word1 /* word1 */; 1587 __le16 word2 /* conn_dpi */; 1588 __le32 reg9 /* reg9 */; 1589 __le16 word3 /* word3 */; 1590 __le16 e4_reserved9 /* word4 */; 1591 }; 1592 1593 1594 struct e5_tstorm_rdma_task_ag_ctx 1595 { 1596 u8 byte0 /* cdu_validation */; 1597 u8 byte1 /* state_and_core_id */; 1598 __le16 word0 /* icid */; 1599 u8 flags0; 1600 #define E5_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF /* connection_type */ 1601 #define E5_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0 1602 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1603 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4 1604 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1605 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 1606 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1607 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 1608 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1609 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 1610 u8 flags1; 1611 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1612 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 1613 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 1614 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1 1615 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1616 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2 1617 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1618 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4 1619 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1620 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6 1621 u8 flags2; 1622 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1623 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0 1624 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1625 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2 1626 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1627 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4 1628 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1629 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6 1630 u8 flags3; 1631 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1632 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0 1633 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1634 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2 1635 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1636 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3 1637 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1638 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4 1639 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1640 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5 1641 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1642 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6 1643 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1644 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7 1645 u8 flags4; 1646 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1647 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0 1648 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1649 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1 1650 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1651 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2 1652 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1653 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3 1654 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1655 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4 1656 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1657 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5 1658 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1659 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6 1660 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1661 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7 1662 u8 byte2 /* byte2 */; 1663 __le16 word1 /* word1 */; 1664 __le32 reg0 /* reg0 */; 1665 u8 byte3 /* regpair0 */; 1666 u8 byte4 /* byte4 */; 1667 __le16 word2 /* word2 */; 1668 __le16 word3 /* word3 */; 1669 __le16 word4 /* word4 */; 1670 __le32 reg1 /* regpair1 */; 1671 __le32 reg2 /* reg2 */; 1672 }; 1673 1674 1675 struct e5_ustorm_rdma_conn_ag_ctx 1676 { 1677 u8 reserved /* cdu_validation */; 1678 u8 byte1 /* state_and_core_id */; 1679 u8 flags0; 1680 #define E5_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1681 #define E5_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1682 #define E5_USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1683 #define E5_USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1684 #define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* timer0cf */ 1685 #define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2 1686 #define E5_USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1687 #define E5_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 1688 #define E5_USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1689 #define E5_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 1690 u8 flags1; 1691 #define E5_USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1692 #define E5_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0 1693 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 /* cf4 */ 1694 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 1695 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 /* cf5 */ 1696 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 1697 #define E5_USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1698 #define E5_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6 1699 u8 flags2; 1700 #define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf0en */ 1701 #define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 1702 #define E5_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1703 #define E5_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 1704 #define E5_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1705 #define E5_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 1706 #define E5_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1707 #define E5_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3 1708 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 /* cf4en */ 1709 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 1710 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 /* cf5en */ 1711 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 1712 #define E5_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1713 #define E5_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6 1714 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 /* rule0en */ 1715 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 1716 u8 flags3; 1717 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1 /* rule1en */ 1718 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0 1719 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1720 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 1721 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1722 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 1723 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1724 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 1725 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1726 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 1727 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1728 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 1729 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1730 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 1731 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1732 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 1733 u8 flags4; 1734 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 1735 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1736 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 1737 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1738 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 1739 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1740 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 1741 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 1742 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 1743 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 1744 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 1745 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 1746 u8 byte2 /* byte2 */; 1747 __le16 conn_dpi /* conn_dpi */; 1748 __le16 word1 /* word1 */; 1749 __le32 cq_cons /* reg0 */; 1750 __le32 cq_se_prod /* reg1 */; 1751 __le32 cq_prod /* reg2 */; 1752 __le32 reg3 /* reg3 */; 1753 __le16 int_timeout /* word2 */; 1754 __le16 word3 /* word3 */; 1755 }; 1756 1757 1758 struct e5_ustorm_rdma_task_ag_ctx 1759 { 1760 u8 reserved /* cdu_validation */; 1761 u8 byte1 /* state_and_core_id */; 1762 __le16 icid /* icid */; 1763 u8 flags0; 1764 #define E5_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 1765 #define E5_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 1766 #define E5_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1767 #define E5_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 1768 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1 /* exist_in_qm1 */ 1769 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5 1770 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3 /* timer0cf */ 1771 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6 1772 u8 flags1; 1773 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3 /* timer1cf */ 1774 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0 1775 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3 /* timer2cf */ 1776 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2 1777 #define E5_USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1778 #define E5_USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4 1779 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 /* dif_error_cf */ 1780 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 1781 u8 flags2; 1782 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1 /* cf0en */ 1783 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0 1784 #define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1 /* cf1en */ 1785 #define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1 1786 #define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1 /* cf2en */ 1787 #define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2 1788 #define E5_USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1789 #define E5_USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3 1790 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 /* cf4en */ 1791 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 1792 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1793 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5 1794 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1795 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6 1796 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1797 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7 1798 u8 flags3; 1799 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1800 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0 1801 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1802 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1 1803 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1804 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2 1805 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1806 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3 1807 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 1808 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_SHIFT 4 1809 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 1810 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_SHIFT 5 1811 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit4 */ 1812 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_SHIFT 6 1813 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* rule7en */ 1814 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_SHIFT 7 1815 u8 flags4; 1816 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_MASK 0x3 /* cf5 */ 1817 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_SHIFT 0 1818 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf5en */ 1819 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_SHIFT 2 1820 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule8en */ 1821 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED7_SHIFT 3 1822 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF /* dif_error_type */ 1823 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 1824 u8 byte2 /* byte2 */; 1825 u8 byte3 /* byte3 */; 1826 u8 e4_reserved8 /* byte4 */; 1827 __le32 dif_err_intervals /* dif_err_intervals */; 1828 __le32 dif_error_1st_interval /* dif_error_1st_interval */; 1829 __le32 reg2 /* reg2 */; 1830 __le32 dif_runt_value /* reg3 */; 1831 __le32 reg4 /* reg4 */; 1832 }; 1833 1834 1835 struct e5_xstorm_rdma_conn_ag_ctx 1836 { 1837 u8 reserved0 /* cdu_validation */; 1838 u8 state_and_core_id /* state_and_core_id */; 1839 u8 flags0; 1840 #define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1841 #define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1842 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1843 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1844 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 /* exist_in_qm2 */ 1845 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2 1846 #define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 1847 #define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 1848 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1849 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4 1850 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 /* cf_array_active */ 1851 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5 1852 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */ 1853 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6 1854 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */ 1855 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7 1856 u8 flags1; 1857 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */ 1858 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0 1859 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1 /* bit9 */ 1860 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1 1861 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 1862 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2 1863 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 1864 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3 1865 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 1866 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4 1867 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 1868 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT13_SHIFT 5 1869 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */ 1870 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6 1871 #define E5_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 1872 #define E5_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 1873 u8 flags2; 1874 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1875 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0 1876 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1877 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2 1878 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1879 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4 1880 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1881 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6 1882 u8 flags3; 1883 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1884 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0 1885 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1886 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2 1887 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1888 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4 1889 #define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 1890 #define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1891 u8 flags4; 1892 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1893 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0 1894 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1895 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2 1896 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1897 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4 1898 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 1899 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6 1900 u8 flags5; 1901 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 1902 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0 1903 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 1904 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2 1905 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 1906 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4 1907 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 1908 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6 1909 u8 flags6; 1910 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 1911 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0 1912 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 1913 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2 1914 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 1915 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4 1916 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */ 1917 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6 1918 u8 flags7; 1919 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */ 1920 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0 1921 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */ 1922 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2 1923 #define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 1924 #define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4 1925 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1926 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6 1927 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1928 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7 1929 u8 flags8; 1930 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1931 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0 1932 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1933 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1 1934 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1935 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2 1936 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1937 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3 1938 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1939 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4 1940 #define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 1941 #define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 1942 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1943 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6 1944 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1945 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7 1946 u8 flags9; 1947 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1948 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0 1949 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 1950 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1 1951 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 1952 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2 1953 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 1954 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3 1955 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 1956 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4 1957 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 1958 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5 1959 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 1960 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6 1961 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 1962 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7 1963 u8 flags10; 1964 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 1965 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0 1966 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */ 1967 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1 1968 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */ 1969 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2 1970 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */ 1971 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3 1972 #define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1973 #define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 1974 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 1975 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5 1976 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1977 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6 1978 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1979 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7 1980 u8 flags11; 1981 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1982 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0 1983 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1984 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1 1985 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1986 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2 1987 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1988 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3 1989 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1990 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4 1991 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1992 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5 1993 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 1994 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 1995 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 1996 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7 1997 u8 flags12; 1998 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 1999 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0 2000 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 2001 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1 2002 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 2003 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 2004 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 2005 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 2006 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 2007 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4 2008 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 2009 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5 2010 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 2011 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6 2012 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 2013 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7 2014 u8 flags13; 2015 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 2016 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0 2017 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 2018 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1 2019 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 2020 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 2021 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 2022 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 2023 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 2024 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 2025 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 2026 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 2027 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 2028 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 2029 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 2030 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 2031 u8 flags14; 2032 #define E5_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1 /* bit16 */ 2033 #define E5_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0 2034 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 2035 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1 2036 #define E5_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 2037 #define E5_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 2038 #define E5_XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1 /* bit20 */ 2039 #define E5_XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4 2040 #define E5_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 2041 #define E5_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 2042 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 2043 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6 2044 u8 byte2 /* byte2 */; 2045 __le16 physical_q0 /* physical_q0 */; 2046 __le16 word1 /* physical_q1 */; 2047 __le16 word2 /* physical_q2 */; 2048 __le16 word3 /* word3 */; 2049 __le16 word4 /* word4 */; 2050 __le16 word5 /* word5 */; 2051 __le16 conn_dpi /* conn_dpi */; 2052 u8 byte3 /* byte3 */; 2053 u8 byte4 /* byte4 */; 2054 u8 byte5 /* byte5 */; 2055 u8 byte6 /* byte6 */; 2056 __le32 reg0 /* reg0 */; 2057 __le32 reg1 /* reg1 */; 2058 __le32 reg2 /* reg2 */; 2059 __le32 snd_nxt_psn /* reg3 */; 2060 __le32 reg4 /* reg4 */; 2061 __le32 reg5 /* cf_array0 */; 2062 __le32 reg6 /* cf_array1 */; 2063 }; 2064 2065 2066 struct e5_ystorm_rdma_conn_ag_ctx 2067 { 2068 u8 byte0 /* cdu_validation */; 2069 u8 byte1 /* state_and_core_id */; 2070 u8 flags0; 2071 #define E5_YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2072 #define E5_YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0 2073 #define E5_YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2074 #define E5_YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 2075 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2076 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2 2077 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2078 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 2079 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2080 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 2081 u8 flags1; 2082 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2083 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0 2084 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2085 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 2086 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2087 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 2088 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2089 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3 2090 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2091 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4 2092 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2093 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5 2094 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2095 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6 2096 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2097 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7 2098 u8 byte2 /* byte2 */; 2099 u8 byte3 /* byte3 */; 2100 __le16 word0 /* word0 */; 2101 __le32 reg0 /* reg0 */; 2102 __le32 reg1 /* reg1 */; 2103 __le16 word1 /* word1 */; 2104 __le16 word2 /* word2 */; 2105 __le16 word3 /* word3 */; 2106 __le16 word4 /* word4 */; 2107 __le32 reg2 /* reg2 */; 2108 __le32 reg3 /* reg3 */; 2109 }; 2110 2111 2112 struct e5_ystorm_rdma_task_ag_ctx 2113 { 2114 u8 reserved /* cdu_validation */; 2115 u8 byte1 /* state_and_core_id */; 2116 __le16 msem_ctx_upd_seq /* icid */; 2117 u8 flags0; 2118 #define E5_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 2119 #define E5_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 2120 #define E5_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2121 #define E5_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 2122 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2123 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 2124 #define E5_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1 /* bit2 */ 2125 #define E5_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6 2126 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 2127 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 2128 u8 flags1; 2129 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2130 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 2131 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2132 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 2133 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */ 2134 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 2135 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2136 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 2137 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2138 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 2139 u8 flags2; 2140 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 2141 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 2142 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2143 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 2144 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2145 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 2146 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2147 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 2148 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2149 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 2150 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2151 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 2152 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2153 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 2154 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2155 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 2156 u8 flags3; 2157 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit5 */ 2158 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_SHIFT 0 2159 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_MASK 0x3 /* cf3 */ 2160 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_SHIFT 1 2161 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf4 */ 2162 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_SHIFT 3 2163 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* cf3en */ 2164 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_SHIFT 5 2165 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf4en */ 2166 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_SHIFT 6 2167 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule7en */ 2168 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_SHIFT 7 2169 __le32 mw_cnt /* reg0 */; 2170 u8 key /* byte2 */; 2171 u8 ref_cnt_seq /* byte3 */; 2172 u8 ctx_upd_seq /* byte4 */; 2173 u8 e4_reserved7 /* byte5 */; 2174 __le16 dif_flags /* word1 */; 2175 __le16 tx_ref_count /* word2 */; 2176 __le16 last_used_ltid /* word3 */; 2177 __le16 parent_mr_lo /* word4 */; 2178 __le16 parent_mr_hi /* word5 */; 2179 __le16 e4_reserved8 /* word6 */; 2180 __le32 fbo_lo /* reg1 */; 2181 }; 2182 2183 #endif /* __ECORE_HSI_RDMA__ */ 2184