1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __ECORE_HSI_RDMA__ 32 #define __ECORE_HSI_RDMA__ 33 /************************************************************************/ 34 /* Add include to common rdma target for both eCore and protocol rdma driver */ 35 /************************************************************************/ 36 #include "rdma_common.h" 37 38 /* 39 * The rdma task context of Mstorm 40 */ 41 struct ystorm_rdma_task_st_ctx 42 { 43 struct regpair temp[4]; 44 }; 45 46 struct e4_ystorm_rdma_task_ag_ctx 47 { 48 u8 reserved /* cdu_validation */; 49 u8 byte1 /* state */; 50 __le16 msem_ctx_upd_seq /* icid */; 51 u8 flags0; 52 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 53 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 54 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 55 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 56 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 57 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 58 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1 /* bit2 */ 59 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6 60 #define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1 /* bit3 */ 61 #define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT 7 62 u8 flags1; 63 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 64 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 65 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 66 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 67 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */ 68 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 69 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 70 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 71 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 72 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 73 u8 flags2; 74 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 75 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 76 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 77 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 78 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 79 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 80 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 81 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 82 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 83 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 84 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 85 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 86 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 87 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 88 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 89 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 90 u8 key /* byte2 */; 91 __le32 mw_cnt /* reg0 */; 92 u8 ref_cnt_seq /* byte3 */; 93 u8 ctx_upd_seq /* byte4 */; 94 __le16 dif_flags /* word1 */; 95 __le16 tx_ref_count /* word2 */; 96 __le16 last_used_ltid /* word3 */; 97 __le16 parent_mr_lo /* word4 */; 98 __le16 parent_mr_hi /* word5 */; 99 __le32 fbo_lo /* reg1 */; 100 __le32 fbo_hi /* reg2 */; 101 }; 102 103 struct e4_mstorm_rdma_task_ag_ctx 104 { 105 u8 reserved /* cdu_validation */; 106 u8 byte1 /* state */; 107 __le16 icid /* icid */; 108 u8 flags0; 109 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 110 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 111 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 112 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 113 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 114 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 115 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 116 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 117 #define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1 /* bit3 */ 118 #define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT 7 119 u8 flags1; 120 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 121 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 122 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 123 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 124 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */ 125 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4 126 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 127 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 128 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 129 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 130 u8 flags2; 131 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 132 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0 133 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 134 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 135 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 136 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 137 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 138 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 139 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 140 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 141 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 142 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 143 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 144 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 145 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 146 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 147 u8 key /* byte2 */; 148 __le32 mw_cnt /* reg0 */; 149 u8 ref_cnt_seq /* byte3 */; 150 u8 ctx_upd_seq /* byte4 */; 151 __le16 dif_flags /* word1 */; 152 __le16 tx_ref_count /* word2 */; 153 __le16 last_used_ltid /* word3 */; 154 __le16 parent_mr_lo /* word4 */; 155 __le16 parent_mr_hi /* word5 */; 156 __le32 fbo_lo /* reg1 */; 157 __le32 fbo_hi /* reg2 */; 158 }; 159 160 /* 161 * The roce task context of Mstorm 162 */ 163 struct mstorm_rdma_task_st_ctx 164 { 165 struct regpair temp[4]; 166 }; 167 168 /* 169 * The roce task context of Ustorm 170 */ 171 struct ustorm_rdma_task_st_ctx 172 { 173 struct regpair temp[2]; 174 }; 175 176 struct e4_ustorm_rdma_task_ag_ctx 177 { 178 u8 reserved /* cdu_validation */; 179 u8 byte1 /* state */; 180 __le16 icid /* icid */; 181 u8 flags0; 182 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 183 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 184 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 185 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 186 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1 /* exist_in_qm1 */ 187 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5 188 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3 /* timer0cf */ 189 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6 190 u8 flags1; 191 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3 /* timer1cf */ 192 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0 193 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3 /* timer2cf */ 194 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2 195 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 196 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4 197 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 /* cf4 */ 198 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 199 u8 flags2; 200 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1 /* cf0en */ 201 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0 202 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1 /* cf1en */ 203 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1 204 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1 /* cf2en */ 205 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2 206 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 207 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3 208 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 /* cf4en */ 209 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 210 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 211 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5 212 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 213 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6 214 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 215 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7 216 u8 flags3; 217 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 218 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0 219 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 220 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1 221 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 222 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2 223 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 224 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3 225 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF /* nibble1 */ 226 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 227 __le32 dif_err_intervals /* reg0 */; 228 __le32 dif_error_1st_interval /* reg1 */; 229 __le32 reg2 /* reg2 */; 230 __le32 dif_runt_value /* reg3 */; 231 __le32 reg4 /* reg4 */; 232 __le32 reg5 /* reg5 */; 233 }; 234 235 /* 236 * RDMA task context 237 */ 238 struct e4_rdma_task_context 239 { 240 struct ystorm_rdma_task_st_ctx ystorm_st_context /* ystorm storm context */; 241 struct e4_ystorm_rdma_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */; 242 struct tdif_task_context tdif_context /* tdif context */; 243 struct e4_mstorm_rdma_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */; 244 struct mstorm_rdma_task_st_ctx mstorm_st_context /* mstorm storm context */; 245 struct rdif_task_context rdif_context /* rdif context */; 246 struct ustorm_rdma_task_st_ctx ustorm_st_context /* ustorm storm context */; 247 struct regpair ustorm_st_padding[2] /* padding */; 248 struct e4_ustorm_rdma_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 249 }; 250 251 struct e5_ystorm_rdma_task_ag_ctx 252 { 253 u8 reserved /* cdu_validation */; 254 u8 byte1 /* state_and_core_id */; 255 __le16 msem_ctx_upd_seq /* icid */; 256 u8 flags0; 257 #define E5_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 258 #define E5_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 259 #define E5_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 260 #define E5_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 261 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 262 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 263 #define E5_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1 /* bit2 */ 264 #define E5_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6 265 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 266 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 267 u8 flags1; 268 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 269 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 270 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 271 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 272 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */ 273 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 274 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 275 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 276 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 277 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 278 u8 flags2; 279 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 280 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 281 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 282 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 283 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 284 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 285 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 286 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 287 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 288 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 289 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 290 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 291 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 292 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 293 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 294 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 295 u8 flags3; 296 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit5 */ 297 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_SHIFT 0 298 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_MASK 0x3 /* cf3 */ 299 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_SHIFT 1 300 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf4 */ 301 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_SHIFT 3 302 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* cf3en */ 303 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_SHIFT 5 304 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf4en */ 305 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_SHIFT 6 306 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule7en */ 307 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_SHIFT 7 308 __le32 mw_cnt /* reg0 */; 309 u8 key /* byte2 */; 310 u8 ref_cnt_seq /* byte3 */; 311 u8 ctx_upd_seq /* byte4 */; 312 u8 e4_reserved7 /* byte5 */; 313 __le16 dif_flags /* word1 */; 314 __le16 tx_ref_count /* word2 */; 315 __le16 last_used_ltid /* word3 */; 316 __le16 parent_mr_lo /* word4 */; 317 __le16 parent_mr_hi /* word5 */; 318 __le16 e4_reserved8 /* word6 */; 319 __le32 fbo_lo /* reg1 */; 320 }; 321 322 struct e5_mstorm_rdma_task_ag_ctx 323 { 324 u8 reserved /* cdu_validation */; 325 u8 byte1 /* state_and_core_id */; 326 __le16 icid /* icid */; 327 u8 flags0; 328 #define E5_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 329 #define E5_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 330 #define E5_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 331 #define E5_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 332 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 333 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 334 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 335 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 336 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 337 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 338 u8 flags1; 339 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 340 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 341 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 342 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 343 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */ 344 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4 345 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 346 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 347 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 348 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 349 u8 flags2; 350 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 351 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0 352 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 353 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 354 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 355 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 356 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 357 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 358 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 359 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 360 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 361 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 362 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 363 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 364 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 365 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 366 u8 flags3; 367 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit4 */ 368 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_SHIFT 0 369 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_MASK 0x3 /* cf3 */ 370 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_SHIFT 1 371 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf4 */ 372 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_SHIFT 3 373 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* cf3en */ 374 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_SHIFT 5 375 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf4en */ 376 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_SHIFT 6 377 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule7en */ 378 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_SHIFT 7 379 __le32 mw_cnt /* reg0 */; 380 u8 key /* byte2 */; 381 u8 ref_cnt_seq /* byte3 */; 382 u8 ctx_upd_seq /* byte4 */; 383 u8 e4_reserved7 /* byte5 */; 384 __le16 dif_flags /* regpair0 */; 385 __le16 tx_ref_count /* word2 */; 386 __le16 last_used_ltid /* word3 */; 387 __le16 parent_mr_lo /* word4 */; 388 __le16 parent_mr_hi /* regpair1 */; 389 __le16 e4_reserved8 /* word6 */; 390 __le32 fbo_lo /* reg1 */; 391 }; 392 393 struct e5_ustorm_rdma_task_ag_ctx 394 { 395 u8 reserved /* cdu_validation */; 396 u8 byte1 /* state_and_core_id */; 397 __le16 icid /* icid */; 398 u8 flags0; 399 #define E5_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 400 #define E5_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 401 #define E5_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 402 #define E5_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 403 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1 /* exist_in_qm1 */ 404 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5 405 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3 /* timer0cf */ 406 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6 407 u8 flags1; 408 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3 /* timer1cf */ 409 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0 410 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3 /* timer2cf */ 411 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2 412 #define E5_USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 413 #define E5_USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4 414 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 /* dif_error_cf */ 415 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 416 u8 flags2; 417 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1 /* cf0en */ 418 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0 419 #define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1 /* cf1en */ 420 #define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1 421 #define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1 /* cf2en */ 422 #define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2 423 #define E5_USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 424 #define E5_USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3 425 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 /* cf4en */ 426 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 427 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 428 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5 429 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 430 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6 431 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 432 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7 433 u8 flags3; 434 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 435 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0 436 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 437 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1 438 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 439 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2 440 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 441 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3 442 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 443 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_SHIFT 4 444 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 445 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_SHIFT 5 446 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit4 */ 447 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_SHIFT 6 448 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* rule7en */ 449 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_SHIFT 7 450 u8 flags4; 451 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_MASK 0x3 /* cf5 */ 452 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_SHIFT 0 453 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf5en */ 454 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_SHIFT 2 455 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule8en */ 456 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED7_SHIFT 3 457 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF /* dif_error_type */ 458 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 459 u8 byte2 /* byte2 */; 460 u8 byte3 /* byte3 */; 461 u8 e4_reserved8 /* byte4 */; 462 __le32 dif_err_intervals /* dif_err_intervals */; 463 __le32 dif_error_1st_interval /* dif_error_1st_interval */; 464 __le32 reg2 /* reg2 */; 465 __le32 dif_runt_value /* reg3 */; 466 __le32 reg4 /* reg4 */; 467 }; 468 469 /* 470 * RDMA task context 471 */ 472 struct e5_rdma_task_context 473 { 474 struct ystorm_rdma_task_st_ctx ystorm_st_context /* ystorm storm context */; 475 struct e5_ystorm_rdma_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */; 476 struct tdif_task_context tdif_context /* tdif context */; 477 struct e5_mstorm_rdma_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */; 478 struct mstorm_rdma_task_st_ctx mstorm_st_context /* mstorm storm context */; 479 struct rdif_task_context rdif_context /* rdif context */; 480 struct ustorm_rdma_task_st_ctx ustorm_st_context /* ustorm storm context */; 481 struct regpair ustorm_st_padding[2] /* padding */; 482 struct e5_ustorm_rdma_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 483 }; 484 485 /* 486 * rdma function init ramrod data 487 */ 488 struct rdma_close_func_ramrod_data 489 { 490 u8 cnq_start_offset; 491 u8 num_cnqs; 492 u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */; 493 u8 vf_valid; 494 u8 reserved[4]; 495 }; 496 497 /* 498 * rdma function init CNQ parameters 499 */ 500 struct rdma_cnq_params 501 { 502 __le16 sb_num /* Status block number used by the queue */; 503 u8 sb_index /* Status block index used by the queue */; 504 u8 num_pbl_pages /* Number of pages in the PBL allocated for this queue */; 505 __le32 reserved; 506 struct regpair pbl_base_addr /* Address to the first entry of the queue PBL */; 507 __le16 queue_zone_num /* Queue Zone ID used for CNQ consumer update */; 508 u8 reserved1[6]; 509 }; 510 511 /* 512 * rdma create cq ramrod data 513 */ 514 struct rdma_create_cq_ramrod_data 515 { 516 struct regpair cq_handle; 517 struct regpair pbl_addr; 518 __le32 max_cqes; 519 __le16 pbl_num_pages; 520 __le16 dpi; 521 u8 is_two_level_pbl; 522 u8 cnq_id; 523 u8 pbl_log_page_size; 524 u8 toggle_bit; 525 __le16 int_timeout /* Timeout used for interrupt moderation */; 526 __le16 reserved1; 527 }; 528 529 /* 530 * rdma deregister tid ramrod data 531 */ 532 struct rdma_deregister_tid_ramrod_data 533 { 534 __le32 itid; 535 __le32 reserved; 536 }; 537 538 /* 539 * rdma destroy cq output params 540 */ 541 struct rdma_destroy_cq_output_params 542 { 543 __le16 cnq_num /* Sequence number of completion notification sent for the cq on the associated CNQ */; 544 __le16 reserved0; 545 __le32 reserved1; 546 }; 547 548 /* 549 * rdma destroy cq ramrod data 550 */ 551 struct rdma_destroy_cq_ramrod_data 552 { 553 struct regpair output_params_addr; 554 }; 555 556 /* 557 * RDMA slow path EQ cmd IDs 558 */ 559 enum rdma_event_opcode 560 { 561 RDMA_EVENT_UNUSED, 562 RDMA_EVENT_FUNC_INIT, 563 RDMA_EVENT_FUNC_CLOSE, 564 RDMA_EVENT_REGISTER_MR, 565 RDMA_EVENT_DEREGISTER_MR, 566 RDMA_EVENT_CREATE_CQ, 567 RDMA_EVENT_RESIZE_CQ, 568 RDMA_EVENT_DESTROY_CQ, 569 RDMA_EVENT_CREATE_SRQ, 570 RDMA_EVENT_MODIFY_SRQ, 571 RDMA_EVENT_DESTROY_SRQ, 572 MAX_RDMA_EVENT_OPCODE 573 }; 574 575 /* 576 * RDMA FW return code for slow path ramrods 577 */ 578 enum rdma_fw_return_code 579 { 580 RDMA_RETURN_OK=0, 581 RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR, 582 RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR, 583 RDMA_RETURN_RESIZE_CQ_ERR, 584 RDMA_RETURN_NIG_DRAIN_REQ, 585 MAX_RDMA_FW_RETURN_CODE 586 }; 587 588 /* 589 * rdma function init header 590 */ 591 struct rdma_init_func_hdr 592 { 593 u8 cnq_start_offset /* First RDMA CNQ */; 594 u8 num_cnqs /* Number of CNQs */; 595 u8 cq_ring_mode /* 0 for 32 bit cq producer and consumer counters and 1 for 16 bit */; 596 u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */; 597 u8 vf_valid; 598 u8 relaxed_ordering /* 1 for using relaxed ordering PCI writes */; 599 __le16 first_reg_srq_id /* The SRQ ID of thr first regular (non XRC) SRQ */; 600 __le32 reg_srq_base_addr /* Logical base address of first regular (non XRC) SRQ */; 601 __le32 reserved; 602 }; 603 604 /* 605 * rdma function init ramrod data 606 */ 607 struct rdma_init_func_ramrod_data 608 { 609 struct rdma_init_func_hdr params_header; 610 struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES]; 611 }; 612 613 /* 614 * RDMA ramrod command IDs 615 */ 616 enum rdma_ramrod_cmd_id 617 { 618 RDMA_RAMROD_UNUSED, 619 RDMA_RAMROD_FUNC_INIT, 620 RDMA_RAMROD_FUNC_CLOSE, 621 RDMA_RAMROD_REGISTER_MR, 622 RDMA_RAMROD_DEREGISTER_MR, 623 RDMA_RAMROD_CREATE_CQ, 624 RDMA_RAMROD_RESIZE_CQ, 625 RDMA_RAMROD_DESTROY_CQ, 626 RDMA_RAMROD_CREATE_SRQ, 627 RDMA_RAMROD_MODIFY_SRQ, 628 RDMA_RAMROD_DESTROY_SRQ, 629 MAX_RDMA_RAMROD_CMD_ID 630 }; 631 632 /* 633 * rdma register tid ramrod data 634 */ 635 struct rdma_register_tid_ramrod_data 636 { 637 __le16 flags; 638 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F 639 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 0 640 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1 641 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT 5 642 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1 643 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT 6 644 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1 645 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT 7 646 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1 647 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT 8 648 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1 649 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT 9 650 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1 651 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT 10 652 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1 653 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT 11 654 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1 655 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT 12 656 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1 657 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT 13 658 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK 0x3 659 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_SHIFT 14 660 u8 flags1; 661 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F 662 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0 663 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7 664 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT 5 665 u8 flags2; 666 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1 /* Bit indicating that this MR is DMA_MR meaning SGEs that use it have the physical address on them */ 667 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0 668 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1 /* Bit indicating that this MR has DIF protection enabled. */ 669 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT 1 670 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F 671 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT 2 672 u8 key; 673 u8 length_hi; 674 u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */; 675 u8 vf_valid; 676 __le16 pd; 677 __le16 reserved2; 678 __le32 length_lo /* lower 32 bits of the registered MR length. */; 679 __le32 itid; 680 __le32 reserved3; 681 struct regpair va; 682 struct regpair pbl_base; 683 struct regpair dif_error_addr /* DIF TX IO writes error information to this location when memory region is invalidated. */; 684 struct regpair dif_runt_addr /* DIF RX IO writes runt value to this location when last RDMA Read of the IO has completed. */; 685 __le32 reserved4[2]; 686 }; 687 688 /* 689 * rdma resize cq output params 690 */ 691 struct rdma_resize_cq_output_params 692 { 693 __le32 old_cq_cons /* cq consumer value on old PBL */; 694 __le32 old_cq_prod /* cq producer value on old PBL */; 695 }; 696 697 /* 698 * rdma resize cq ramrod data 699 */ 700 struct rdma_resize_cq_ramrod_data 701 { 702 u8 flags; 703 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1 704 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0 705 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1 706 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1 707 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x3F 708 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 2 709 u8 pbl_log_page_size; 710 __le16 pbl_num_pages; 711 __le32 max_cqes; 712 struct regpair pbl_addr; 713 struct regpair output_params_addr; 714 }; 715 716 /* 717 * The rdma SRQ context 718 */ 719 struct rdma_srq_context 720 { 721 struct regpair temp[8]; 722 }; 723 724 /* 725 * rdma create qp requester ramrod data 726 */ 727 struct rdma_srq_create_ramrod_data 728 { 729 u8 flags; 730 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_MASK 0x1 731 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_SHIFT 0 732 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1 /* Only applicable when xrc_flag is set */ 733 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 1 734 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_MASK 0x3F 735 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_SHIFT 2 736 u8 reserved2; 737 __le16 xrc_domain /* Only applicable when xrc_flag is set */; 738 __le32 xrc_srq_cq_cid /* Only applicable when xrc_flag is set */; 739 struct regpair pbl_base_addr /* SRQ PBL base address */; 740 __le16 pages_in_srq_pbl /* Number of pages in PBL */; 741 __le16 pd_id; 742 struct rdma_srq_id srq_id /* SRQ Index */; 743 __le16 page_size /* Page size in SGEs(16 bytes) elements. Supports up to 2M bytes page size */; 744 __le16 reserved3; 745 __le32 reserved4; 746 struct regpair producers_addr /* SRQ PBL base address */; 747 }; 748 749 /* 750 * rdma create qp requester ramrod data 751 */ 752 struct rdma_srq_destroy_ramrod_data 753 { 754 struct rdma_srq_id srq_id /* SRQ Index */; 755 __le32 reserved; 756 }; 757 758 /* 759 * rdma create qp requester ramrod data 760 */ 761 struct rdma_srq_modify_ramrod_data 762 { 763 struct rdma_srq_id srq_id /* SRQ Index */; 764 __le32 wqe_limit; 765 }; 766 767 /* 768 * RDMA Tid type enumeration (for register_tid ramrod) 769 */ 770 enum rdma_tid_type 771 { 772 RDMA_TID_REGISTERED_MR, 773 RDMA_TID_FMR, 774 RDMA_TID_MW_TYPE1, 775 RDMA_TID_MW_TYPE2A, 776 MAX_RDMA_TID_TYPE 777 }; 778 779 /* 780 * The rdma XRC SRQ context 781 */ 782 struct rdma_xrc_srq_context 783 { 784 struct regpair temp[9]; 785 }; 786 787 struct E4XstormRoceConnAgCtxDqExtLdPart 788 { 789 u8 reserved0 /* cdu_validation */; 790 u8 state /* state */; 791 u8 flags0; 792 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 793 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 794 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1 /* exist_in_qm1 */ 795 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1 796 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1 /* exist_in_qm2 */ 797 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2 798 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 799 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 800 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1 /* bit4 */ 801 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4 802 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1 /* cf_array_active */ 803 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5 804 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1 /* bit6 */ 805 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6 806 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1 /* bit7 */ 807 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7 808 u8 flags1; 809 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1 /* bit8 */ 810 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0 811 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1 /* bit9 */ 812 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1 813 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1 /* bit10 */ 814 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2 815 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 /* bit11 */ 816 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 817 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1 /* bit12 */ 818 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4 819 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_MASK 0x1 /* bit13 */ 820 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_SHIFT 5 821 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1 /* bit14 */ 822 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6 823 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 824 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7 825 u8 flags2; 826 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3 /* timer0cf */ 827 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0 828 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3 /* timer1cf */ 829 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2 830 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3 /* timer2cf */ 831 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4 832 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3 /* timer_stop_all */ 833 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6 834 u8 flags3; 835 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3 /* cf4 */ 836 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0 837 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3 /* cf5 */ 838 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2 839 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3 /* cf6 */ 840 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4 841 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 842 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6 843 u8 flags4; 844 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3 /* cf8 */ 845 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0 846 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3 /* cf9 */ 847 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2 848 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3 /* cf10 */ 849 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4 850 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3 /* cf11 */ 851 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6 852 u8 flags5; 853 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3 /* cf12 */ 854 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0 855 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3 /* cf13 */ 856 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2 857 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3 /* cf14 */ 858 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4 859 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3 /* cf15 */ 860 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6 861 u8 flags6; 862 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3 /* cf16 */ 863 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0 864 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3 /* cf_array_cf */ 865 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2 866 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3 /* cf18 */ 867 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4 868 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3 /* cf19 */ 869 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6 870 u8 flags7; 871 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3 /* cf20 */ 872 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0 873 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3 /* cf21 */ 874 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2 875 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 /* cf22 */ 876 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 877 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 /* cf0en */ 878 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 879 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 /* cf1en */ 880 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 881 u8 flags8; 882 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 /* cf2en */ 883 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 884 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 /* cf3en */ 885 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 886 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 /* cf4en */ 887 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 888 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 /* cf5en */ 889 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 890 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 /* cf6en */ 891 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 892 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 893 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5 894 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 /* cf8en */ 895 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 896 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 /* cf9en */ 897 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 898 u8 flags9; 899 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 /* cf10en */ 900 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 901 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 /* cf11en */ 902 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 903 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 /* cf12en */ 904 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 905 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 /* cf13en */ 906 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 907 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 /* cf14en */ 908 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 909 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 /* cf15en */ 910 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 911 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1 /* cf16en */ 912 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6 913 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1 /* cf_array_cf_en */ 914 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7 915 u8 flags10; 916 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1 /* cf18en */ 917 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0 918 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1 /* cf19en */ 919 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1 920 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1 /* cf20en */ 921 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2 922 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1 /* cf21en */ 923 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3 924 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 925 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 926 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1 /* cf23en */ 927 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5 928 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1 /* rule0en */ 929 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6 930 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1 /* rule1en */ 931 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7 932 u8 flags11; 933 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1 /* rule2en */ 934 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0 935 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1 /* rule3en */ 936 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1 937 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1 /* rule4en */ 938 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2 939 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 /* rule5en */ 940 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 941 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 /* rule6en */ 942 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 943 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 /* rule7en */ 944 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 945 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 /* rule8en */ 946 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 947 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 /* rule9en */ 948 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 949 u8 flags12; 950 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 /* rule10en */ 951 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 952 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 /* rule11en */ 953 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 954 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 /* rule12en */ 955 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 956 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 /* rule13en */ 957 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 958 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 /* rule14en */ 959 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 960 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 /* rule15en */ 961 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 962 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 /* rule16en */ 963 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 964 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 /* rule17en */ 965 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 966 u8 flags13; 967 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 /* rule18en */ 968 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 969 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 /* rule19en */ 970 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 971 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 /* rule20en */ 972 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 973 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 /* rule21en */ 974 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 975 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 /* rule22en */ 976 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 977 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 /* rule23en */ 978 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 979 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 /* rule24en */ 980 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 981 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 /* rule25en */ 982 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 983 u8 flags14; 984 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1 /* bit16 */ 985 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0 986 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1 /* bit17 */ 987 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1 988 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 989 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2 990 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1 /* bit20 */ 991 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4 992 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 993 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 994 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3 /* cf23 */ 995 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6 996 u8 byte2 /* byte2 */; 997 __le16 physical_q0 /* physical_q0 */; 998 __le16 word1 /* physical_q1 */; 999 __le16 word2 /* physical_q2 */; 1000 __le16 word3 /* word3 */; 1001 __le16 word4 /* word4 */; 1002 __le16 word5 /* word5 */; 1003 __le16 conn_dpi /* conn_dpi */; 1004 u8 byte3 /* byte3 */; 1005 u8 byte4 /* byte4 */; 1006 u8 byte5 /* byte5 */; 1007 u8 byte6 /* byte6 */; 1008 __le32 reg0 /* reg0 */; 1009 __le32 reg1 /* reg1 */; 1010 __le32 reg2 /* reg2 */; 1011 __le32 snd_nxt_psn /* reg3 */; 1012 __le32 reg4 /* reg4 */; 1013 }; 1014 1015 struct e4_mstorm_rdma_conn_ag_ctx 1016 { 1017 u8 byte0 /* cdu_validation */; 1018 u8 byte1 /* state */; 1019 u8 flags0; 1020 #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1021 #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0 1022 #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1023 #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1024 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1025 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2 1026 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1027 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 1028 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1029 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 1030 u8 flags1; 1031 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1032 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0 1033 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1034 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 1035 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1036 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 1037 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1038 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3 1039 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1040 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4 1041 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1042 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5 1043 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1044 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6 1045 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1046 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7 1047 __le16 word0 /* word0 */; 1048 __le16 word1 /* word1 */; 1049 __le32 reg0 /* reg0 */; 1050 __le32 reg1 /* reg1 */; 1051 }; 1052 1053 struct e4_tstorm_rdma_conn_ag_ctx 1054 { 1055 u8 reserved0 /* cdu_validation */; 1056 u8 byte1 /* state */; 1057 u8 flags0; 1058 #define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1059 #define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1060 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1061 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1062 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1063 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2 1064 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1065 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3 1066 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1067 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4 1068 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 1069 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5 1070 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1071 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6 1072 u8 flags1; 1073 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1074 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0 1075 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1076 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2 1077 #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */ 1078 #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 1079 #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */ 1080 #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1081 u8 flags2; 1082 #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */ 1083 #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 1084 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1085 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2 1086 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1087 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4 1088 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1089 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6 1090 u8 flags3; 1091 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1092 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0 1093 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1094 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2 1095 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1096 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4 1097 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1098 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5 1099 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1100 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6 1101 #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */ 1102 #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 1103 u8 flags4; 1104 #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */ 1105 #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 1106 #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */ 1107 #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 1108 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1109 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2 1110 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1111 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3 1112 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1113 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4 1114 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1115 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5 1116 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1117 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6 1118 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1119 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7 1120 u8 flags5; 1121 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1122 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0 1123 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1124 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 1125 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1126 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 1127 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1128 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 1129 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1130 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 1131 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1132 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 1133 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1134 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 1135 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1136 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 1137 __le32 reg0 /* reg0 */; 1138 __le32 reg1 /* reg1 */; 1139 __le32 reg2 /* reg2 */; 1140 __le32 reg3 /* reg3 */; 1141 __le32 reg4 /* reg4 */; 1142 __le32 reg5 /* reg5 */; 1143 __le32 reg6 /* reg6 */; 1144 __le32 reg7 /* reg7 */; 1145 __le32 reg8 /* reg8 */; 1146 u8 byte2 /* byte2 */; 1147 u8 byte3 /* byte3 */; 1148 __le16 word0 /* word0 */; 1149 u8 byte4 /* byte4 */; 1150 u8 byte5 /* byte5 */; 1151 __le16 word1 /* word1 */; 1152 __le16 word2 /* conn_dpi */; 1153 __le16 word3 /* word3 */; 1154 __le32 reg9 /* reg9 */; 1155 __le32 reg10 /* reg10 */; 1156 }; 1157 1158 struct e4_tstorm_rdma_task_ag_ctx 1159 { 1160 u8 byte0 /* cdu_validation */; 1161 u8 byte1 /* state */; 1162 __le16 word0 /* icid */; 1163 u8 flags0; 1164 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF /* connection_type */ 1165 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0 1166 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1167 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4 1168 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1169 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 1170 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1171 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 1172 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1173 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 1174 u8 flags1; 1175 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1176 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 1177 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 1178 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1 1179 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1180 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2 1181 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1182 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4 1183 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1184 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6 1185 u8 flags2; 1186 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1187 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0 1188 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1189 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2 1190 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1191 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4 1192 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1193 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6 1194 u8 flags3; 1195 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1196 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0 1197 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1198 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2 1199 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1200 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3 1201 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1202 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4 1203 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1204 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5 1205 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1206 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6 1207 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1208 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7 1209 u8 flags4; 1210 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1211 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0 1212 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1213 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1 1214 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1215 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2 1216 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1217 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3 1218 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1219 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4 1220 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1221 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5 1222 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1223 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6 1224 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1225 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7 1226 u8 byte2 /* byte2 */; 1227 __le16 word1 /* word1 */; 1228 __le32 reg0 /* reg0 */; 1229 u8 byte3 /* byte3 */; 1230 u8 byte4 /* byte4 */; 1231 __le16 word2 /* word2 */; 1232 __le16 word3 /* word3 */; 1233 __le16 word4 /* word4 */; 1234 __le32 reg1 /* reg1 */; 1235 __le32 reg2 /* reg2 */; 1236 }; 1237 1238 struct e4_ustorm_rdma_conn_ag_ctx 1239 { 1240 u8 reserved /* cdu_validation */; 1241 u8 byte1 /* state */; 1242 u8 flags0; 1243 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1244 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1245 #define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1246 #define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1247 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* timer0cf */ 1248 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2 1249 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1250 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 1251 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1252 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 1253 u8 flags1; 1254 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1255 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0 1256 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 /* cf4 */ 1257 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 1258 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 /* cf5 */ 1259 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 1260 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1261 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6 1262 u8 flags2; 1263 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf0en */ 1264 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 1265 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1266 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 1267 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1268 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 1269 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1270 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3 1271 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 /* cf4en */ 1272 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 1273 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 /* cf5en */ 1274 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 1275 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1276 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6 1277 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 /* rule0en */ 1278 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 1279 u8 flags3; 1280 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1 /* rule1en */ 1281 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0 1282 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1283 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 1284 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1285 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 1286 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1287 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 1288 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1289 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 1290 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1291 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 1292 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1293 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 1294 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1295 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 1296 u8 byte2 /* byte2 */; 1297 u8 byte3 /* byte3 */; 1298 __le16 conn_dpi /* conn_dpi */; 1299 __le16 word1 /* word1 */; 1300 __le32 cq_cons /* reg0 */; 1301 __le32 cq_se_prod /* reg1 */; 1302 __le32 cq_prod /* reg2 */; 1303 __le32 reg3 /* reg3 */; 1304 __le16 int_timeout /* word2 */; 1305 __le16 word3 /* word3 */; 1306 }; 1307 1308 struct e4_xstorm_rdma_conn_ag_ctx 1309 { 1310 u8 reserved0 /* cdu_validation */; 1311 u8 state /* state */; 1312 u8 flags0; 1313 #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1314 #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1315 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1316 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1317 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 /* exist_in_qm2 */ 1318 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2 1319 #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 1320 #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 1321 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1322 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4 1323 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 /* cf_array_active */ 1324 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5 1325 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */ 1326 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6 1327 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */ 1328 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7 1329 u8 flags1; 1330 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */ 1331 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0 1332 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1 /* bit9 */ 1333 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1 1334 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 1335 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2 1336 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 1337 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3 1338 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 1339 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4 1340 #define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit13 */ 1341 #define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 5 1342 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */ 1343 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6 1344 #define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 1345 #define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 1346 u8 flags2; 1347 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1348 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0 1349 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1350 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2 1351 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1352 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4 1353 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1354 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6 1355 u8 flags3; 1356 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1357 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0 1358 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1359 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2 1360 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1361 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4 1362 #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 1363 #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1364 u8 flags4; 1365 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1366 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0 1367 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1368 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2 1369 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1370 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4 1371 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 1372 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6 1373 u8 flags5; 1374 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 1375 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0 1376 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 1377 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2 1378 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 1379 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4 1380 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 1381 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6 1382 u8 flags6; 1383 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 1384 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0 1385 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 1386 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2 1387 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 1388 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4 1389 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */ 1390 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6 1391 u8 flags7; 1392 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */ 1393 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0 1394 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */ 1395 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2 1396 #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 1397 #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4 1398 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1399 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6 1400 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1401 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7 1402 u8 flags8; 1403 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1404 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0 1405 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1406 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1 1407 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1408 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2 1409 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1410 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3 1411 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1412 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4 1413 #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 1414 #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 1415 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1416 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6 1417 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1418 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7 1419 u8 flags9; 1420 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1421 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0 1422 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 1423 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1 1424 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 1425 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2 1426 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 1427 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3 1428 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 1429 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4 1430 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 1431 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5 1432 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 1433 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6 1434 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 1435 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7 1436 u8 flags10; 1437 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 1438 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0 1439 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */ 1440 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1 1441 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */ 1442 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2 1443 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */ 1444 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3 1445 #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1446 #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 1447 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 1448 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5 1449 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1450 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6 1451 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1452 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7 1453 u8 flags11; 1454 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1455 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0 1456 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1457 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1 1458 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1459 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2 1460 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1461 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3 1462 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1463 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4 1464 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1465 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5 1466 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 1467 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 1468 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 1469 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7 1470 u8 flags12; 1471 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 1472 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0 1473 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 1474 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1 1475 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 1476 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 1477 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 1478 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 1479 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 1480 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4 1481 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 1482 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5 1483 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 1484 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6 1485 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 1486 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7 1487 u8 flags13; 1488 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 1489 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0 1490 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 1491 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1 1492 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 1493 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 1494 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 1495 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 1496 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 1497 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 1498 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 1499 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 1500 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 1501 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 1502 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 1503 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 1504 u8 flags14; 1505 #define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1 /* bit16 */ 1506 #define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0 1507 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 1508 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1 1509 #define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 1510 #define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 1511 #define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1 /* bit20 */ 1512 #define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4 1513 #define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 1514 #define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 1515 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 1516 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6 1517 u8 byte2 /* byte2 */; 1518 __le16 physical_q0 /* physical_q0 */; 1519 __le16 word1 /* physical_q1 */; 1520 __le16 word2 /* physical_q2 */; 1521 __le16 word3 /* word3 */; 1522 __le16 word4 /* word4 */; 1523 __le16 word5 /* word5 */; 1524 __le16 conn_dpi /* conn_dpi */; 1525 u8 byte3 /* byte3 */; 1526 u8 byte4 /* byte4 */; 1527 u8 byte5 /* byte5 */; 1528 u8 byte6 /* byte6 */; 1529 __le32 reg0 /* reg0 */; 1530 __le32 reg1 /* reg1 */; 1531 __le32 reg2 /* reg2 */; 1532 __le32 snd_nxt_psn /* reg3 */; 1533 __le32 reg4 /* reg4 */; 1534 __le32 reg5 /* cf_array0 */; 1535 __le32 reg6 /* cf_array1 */; 1536 }; 1537 1538 struct e4_ystorm_rdma_conn_ag_ctx 1539 { 1540 u8 byte0 /* cdu_validation */; 1541 u8 byte1 /* state */; 1542 u8 flags0; 1543 #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1544 #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0 1545 #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1546 #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1547 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1548 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2 1549 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1550 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 1551 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1552 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 1553 u8 flags1; 1554 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1555 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0 1556 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1557 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 1558 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1559 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 1560 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1561 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3 1562 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1563 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4 1564 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1565 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5 1566 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1567 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6 1568 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1569 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7 1570 u8 byte2 /* byte2 */; 1571 u8 byte3 /* byte3 */; 1572 __le16 word0 /* word0 */; 1573 __le32 reg0 /* reg0 */; 1574 __le32 reg1 /* reg1 */; 1575 __le16 word1 /* word1 */; 1576 __le16 word2 /* word2 */; 1577 __le16 word3 /* word3 */; 1578 __le16 word4 /* word4 */; 1579 __le32 reg2 /* reg2 */; 1580 __le32 reg3 /* reg3 */; 1581 }; 1582 1583 struct e5_mstorm_rdma_conn_ag_ctx 1584 { 1585 u8 byte0 /* cdu_validation */; 1586 u8 byte1 /* state_and_core_id */; 1587 u8 flags0; 1588 #define E5_MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1589 #define E5_MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0 1590 #define E5_MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1591 #define E5_MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1592 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1593 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2 1594 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1595 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 1596 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1597 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 1598 u8 flags1; 1599 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1600 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0 1601 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1602 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 1603 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1604 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 1605 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1606 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3 1607 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1608 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4 1609 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1610 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5 1611 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1612 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6 1613 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1614 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7 1615 __le16 word0 /* word0 */; 1616 __le16 word1 /* word1 */; 1617 __le32 reg0 /* reg0 */; 1618 __le32 reg1 /* reg1 */; 1619 }; 1620 1621 struct e5_tstorm_rdma_conn_ag_ctx 1622 { 1623 u8 reserved0 /* cdu_validation */; 1624 u8 byte1 /* state_and_core_id */; 1625 u8 flags0; 1626 #define E5_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1627 #define E5_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1628 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1629 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1630 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1631 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2 1632 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1633 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3 1634 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1635 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4 1636 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 1637 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5 1638 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1639 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6 1640 u8 flags1; 1641 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1642 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0 1643 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1644 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2 1645 #define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */ 1646 #define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 1647 #define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */ 1648 #define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1649 u8 flags2; 1650 #define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */ 1651 #define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 1652 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1653 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2 1654 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1655 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4 1656 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1657 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6 1658 u8 flags3; 1659 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1660 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0 1661 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1662 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2 1663 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1664 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4 1665 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1666 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5 1667 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1668 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6 1669 #define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */ 1670 #define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 1671 u8 flags4; 1672 #define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */ 1673 #define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 1674 #define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */ 1675 #define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 1676 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1677 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2 1678 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1679 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3 1680 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1681 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4 1682 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1683 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5 1684 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1685 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6 1686 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1687 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7 1688 u8 flags5; 1689 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1690 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0 1691 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1692 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 1693 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1694 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 1695 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1696 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 1697 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1698 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 1699 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1700 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 1701 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1702 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 1703 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1704 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 1705 u8 flags6; 1706 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 1707 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1708 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 1709 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1710 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 1711 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1712 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 1713 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 1714 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 1715 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 1716 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 1717 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 1718 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 1719 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 1720 u8 byte2 /* byte2 */; 1721 __le16 word0 /* word0 */; 1722 __le32 reg0 /* reg0 */; 1723 __le32 reg1 /* reg1 */; 1724 __le32 reg2 /* reg2 */; 1725 __le32 reg3 /* reg3 */; 1726 __le32 reg4 /* reg4 */; 1727 __le32 reg5 /* reg5 */; 1728 __le32 reg6 /* reg6 */; 1729 __le32 reg7 /* reg7 */; 1730 __le32 reg8 /* reg8 */; 1731 u8 byte3 /* byte3 */; 1732 u8 byte4 /* byte4 */; 1733 u8 byte5 /* byte5 */; 1734 u8 e4_reserved8 /* byte6 */; 1735 __le16 word1 /* word1 */; 1736 __le16 word2 /* conn_dpi */; 1737 __le32 reg9 /* reg9 */; 1738 __le16 word3 /* word3 */; 1739 __le16 e4_reserved9 /* word4 */; 1740 }; 1741 1742 struct e5_tstorm_rdma_task_ag_ctx 1743 { 1744 u8 byte0 /* cdu_validation */; 1745 u8 byte1 /* state_and_core_id */; 1746 __le16 word0 /* icid */; 1747 u8 flags0; 1748 #define E5_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF /* connection_type */ 1749 #define E5_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0 1750 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1751 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4 1752 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1753 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 1754 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1755 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 1756 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1757 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 1758 u8 flags1; 1759 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1760 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 1761 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 1762 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1 1763 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1764 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2 1765 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1766 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4 1767 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1768 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6 1769 u8 flags2; 1770 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1771 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0 1772 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1773 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2 1774 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1775 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4 1776 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1777 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6 1778 u8 flags3; 1779 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1780 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0 1781 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1782 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2 1783 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1784 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3 1785 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1786 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4 1787 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1788 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5 1789 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1790 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6 1791 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1792 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7 1793 u8 flags4; 1794 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1795 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0 1796 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1797 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1 1798 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1799 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2 1800 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1801 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3 1802 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1803 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4 1804 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1805 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5 1806 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1807 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6 1808 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1809 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7 1810 u8 byte2 /* byte2 */; 1811 __le16 word1 /* word1 */; 1812 __le32 reg0 /* reg0 */; 1813 u8 byte3 /* regpair0 */; 1814 u8 byte4 /* byte4 */; 1815 __le16 word2 /* word2 */; 1816 __le16 word3 /* word3 */; 1817 __le16 word4 /* word4 */; 1818 __le32 reg1 /* regpair1 */; 1819 __le32 reg2 /* reg2 */; 1820 }; 1821 1822 struct e5_ustorm_rdma_conn_ag_ctx 1823 { 1824 u8 reserved /* cdu_validation */; 1825 u8 byte1 /* state_and_core_id */; 1826 u8 flags0; 1827 #define E5_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1828 #define E5_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1829 #define E5_USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1830 #define E5_USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1831 #define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* timer0cf */ 1832 #define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2 1833 #define E5_USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1834 #define E5_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 1835 #define E5_USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1836 #define E5_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 1837 u8 flags1; 1838 #define E5_USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1839 #define E5_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0 1840 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 /* cf4 */ 1841 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 1842 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 /* cf5 */ 1843 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 1844 #define E5_USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1845 #define E5_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6 1846 u8 flags2; 1847 #define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf0en */ 1848 #define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 1849 #define E5_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1850 #define E5_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 1851 #define E5_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1852 #define E5_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 1853 #define E5_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1854 #define E5_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3 1855 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 /* cf4en */ 1856 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 1857 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 /* cf5en */ 1858 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 1859 #define E5_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1860 #define E5_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6 1861 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 /* rule0en */ 1862 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 1863 u8 flags3; 1864 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1 /* rule1en */ 1865 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0 1866 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1867 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 1868 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1869 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 1870 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1871 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 1872 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1873 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 1874 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1875 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 1876 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1877 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 1878 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1879 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 1880 u8 flags4; 1881 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 1882 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1883 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 1884 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1885 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 1886 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1887 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 1888 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 1889 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 1890 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 1891 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 1892 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 1893 u8 byte2 /* byte2 */; 1894 __le16 conn_dpi /* conn_dpi */; 1895 __le16 word1 /* word1 */; 1896 __le32 cq_cons /* reg0 */; 1897 __le32 cq_se_prod /* reg1 */; 1898 __le32 cq_prod /* reg2 */; 1899 __le32 reg3 /* reg3 */; 1900 __le16 int_timeout /* word2 */; 1901 __le16 word3 /* word3 */; 1902 }; 1903 1904 struct e5_xstorm_rdma_conn_ag_ctx 1905 { 1906 u8 reserved0 /* cdu_validation */; 1907 u8 state_and_core_id /* state_and_core_id */; 1908 u8 flags0; 1909 #define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1910 #define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1911 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1912 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1913 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 /* exist_in_qm2 */ 1914 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2 1915 #define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 1916 #define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 1917 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1918 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4 1919 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 /* cf_array_active */ 1920 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5 1921 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */ 1922 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6 1923 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */ 1924 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7 1925 u8 flags1; 1926 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */ 1927 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0 1928 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1 /* bit9 */ 1929 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1 1930 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 1931 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2 1932 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 1933 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3 1934 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 1935 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4 1936 #define E5_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit13 */ 1937 #define E5_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 5 1938 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */ 1939 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6 1940 #define E5_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 1941 #define E5_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 1942 u8 flags2; 1943 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1944 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0 1945 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1946 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2 1947 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1948 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4 1949 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1950 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6 1951 u8 flags3; 1952 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1953 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0 1954 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1955 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2 1956 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1957 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4 1958 #define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 1959 #define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1960 u8 flags4; 1961 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1962 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0 1963 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1964 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2 1965 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1966 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4 1967 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 1968 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6 1969 u8 flags5; 1970 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 1971 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0 1972 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 1973 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2 1974 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 1975 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4 1976 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 1977 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6 1978 u8 flags6; 1979 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 1980 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0 1981 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 1982 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2 1983 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 1984 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4 1985 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */ 1986 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6 1987 u8 flags7; 1988 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */ 1989 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0 1990 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */ 1991 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2 1992 #define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 1993 #define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4 1994 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1995 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6 1996 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1997 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7 1998 u8 flags8; 1999 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2000 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0 2001 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2002 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1 2003 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 2004 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2 2005 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 2006 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3 2007 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 2008 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4 2009 #define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 2010 #define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 2011 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 2012 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6 2013 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 2014 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7 2015 u8 flags9; 2016 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 2017 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0 2018 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 2019 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1 2020 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 2021 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2 2022 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 2023 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3 2024 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 2025 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4 2026 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 2027 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5 2028 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 2029 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6 2030 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 2031 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7 2032 u8 flags10; 2033 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 2034 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0 2035 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */ 2036 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1 2037 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */ 2038 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2 2039 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */ 2040 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3 2041 #define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 2042 #define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 2043 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 2044 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5 2045 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2046 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6 2047 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2048 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7 2049 u8 flags11; 2050 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2051 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0 2052 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2053 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1 2054 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2055 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2 2056 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2057 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3 2058 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2059 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4 2060 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2061 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5 2062 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 2063 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 2064 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 2065 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7 2066 u8 flags12; 2067 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 2068 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0 2069 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 2070 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1 2071 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 2072 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 2073 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 2074 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 2075 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 2076 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4 2077 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 2078 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5 2079 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 2080 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6 2081 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 2082 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7 2083 u8 flags13; 2084 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 2085 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0 2086 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 2087 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1 2088 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 2089 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 2090 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 2091 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 2092 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 2093 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 2094 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 2095 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 2096 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 2097 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 2098 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 2099 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 2100 u8 flags14; 2101 #define E5_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1 /* bit16 */ 2102 #define E5_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0 2103 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 2104 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1 2105 #define E5_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 2106 #define E5_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 2107 #define E5_XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1 /* bit20 */ 2108 #define E5_XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4 2109 #define E5_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 2110 #define E5_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 2111 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 2112 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6 2113 u8 byte2 /* byte2 */; 2114 __le16 physical_q0 /* physical_q0 */; 2115 __le16 word1 /* physical_q1 */; 2116 __le16 word2 /* physical_q2 */; 2117 __le16 word3 /* word3 */; 2118 __le16 word4 /* word4 */; 2119 __le16 word5 /* word5 */; 2120 __le16 conn_dpi /* conn_dpi */; 2121 u8 byte3 /* byte3 */; 2122 u8 byte4 /* byte4 */; 2123 u8 byte5 /* byte5 */; 2124 u8 byte6 /* byte6 */; 2125 __le32 reg0 /* reg0 */; 2126 __le32 reg1 /* reg1 */; 2127 __le32 reg2 /* reg2 */; 2128 __le32 snd_nxt_psn /* reg3 */; 2129 __le32 reg4 /* reg4 */; 2130 __le32 reg5 /* cf_array0 */; 2131 __le32 reg6 /* cf_array1 */; 2132 }; 2133 2134 struct e5_ystorm_rdma_conn_ag_ctx 2135 { 2136 u8 byte0 /* cdu_validation */; 2137 u8 byte1 /* state_and_core_id */; 2138 u8 flags0; 2139 #define E5_YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2140 #define E5_YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0 2141 #define E5_YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2142 #define E5_YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 2143 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2144 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2 2145 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2146 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 2147 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2148 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 2149 u8 flags1; 2150 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2151 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0 2152 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2153 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 2154 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2155 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 2156 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2157 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3 2158 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2159 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4 2160 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2161 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5 2162 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2163 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6 2164 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2165 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7 2166 u8 byte2 /* byte2 */; 2167 u8 byte3 /* byte3 */; 2168 __le16 word0 /* word0 */; 2169 __le32 reg0 /* reg0 */; 2170 __le32 reg1 /* reg1 */; 2171 __le16 word1 /* word1 */; 2172 __le16 word2 /* word2 */; 2173 __le16 word3 /* word3 */; 2174 __le16 word4 /* word4 */; 2175 __le32 reg2 /* reg2 */; 2176 __le32 reg3 /* reg3 */; 2177 }; 2178 2179 #endif /* __ECORE_HSI_RDMA__ */ 2180