1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __ECORE_HSI_ROCE__ 32 #define __ECORE_HSI_ROCE__ 33 /************************************************************************/ 34 /* Add include to ecore hsi rdma target for both roce and iwarp ecore driver */ 35 /************************************************************************/ 36 #include "ecore_hsi_rdma.h" 37 /************************************************************************/ 38 /* Add include to common roce target for both eCore and protocol roce driver */ 39 /************************************************************************/ 40 #include "roce_common.h" 41 42 /* 43 * The roce storm context of Ystorm 44 */ 45 struct ystorm_roce_conn_st_ctx 46 { 47 struct regpair temp[2]; 48 }; 49 50 /* 51 * The roce storm context of Mstorm 52 */ 53 struct pstorm_roce_conn_st_ctx 54 { 55 struct regpair temp[16]; 56 }; 57 58 /* 59 * The roce storm context of Xstorm 60 */ 61 struct xstorm_roce_conn_st_ctx 62 { 63 struct regpair temp[24]; 64 }; 65 66 /* 67 * The roce storm context of Tstorm 68 */ 69 struct tstorm_roce_conn_st_ctx 70 { 71 struct regpair temp[30]; 72 }; 73 74 /* 75 * The roce storm context of Mstorm 76 */ 77 struct mstorm_roce_conn_st_ctx 78 { 79 struct regpair temp[6]; 80 }; 81 82 /* 83 * The roce storm context of Ystorm 84 */ 85 struct ustorm_roce_conn_st_ctx 86 { 87 struct regpair temp[12]; 88 }; 89 90 /* 91 * roce connection context 92 */ 93 struct e4_roce_conn_context 94 { 95 struct ystorm_roce_conn_st_ctx ystorm_st_context /* ystorm storm context */; 96 struct regpair ystorm_st_padding[2] /* padding */; 97 struct pstorm_roce_conn_st_ctx pstorm_st_context /* pstorm storm context */; 98 struct xstorm_roce_conn_st_ctx xstorm_st_context /* xstorm storm context */; 99 struct regpair xstorm_st_padding[2] /* padding */; 100 struct e4_xstorm_rdma_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 101 struct e4_tstorm_rdma_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 102 struct timers_context timer_context /* timer context */; 103 struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 104 struct tstorm_roce_conn_st_ctx tstorm_st_context /* tstorm storm context */; 105 struct mstorm_roce_conn_st_ctx mstorm_st_context /* mstorm storm context */; 106 struct ustorm_roce_conn_st_ctx ustorm_st_context /* ustorm storm context */; 107 struct regpair ustorm_st_padding[2] /* padding */; 108 }; 109 110 111 /* 112 * roce connection context 113 */ 114 struct e5_roce_conn_context 115 { 116 struct ystorm_roce_conn_st_ctx ystorm_st_context /* ystorm storm context */; 117 struct regpair ystorm_st_padding[2] /* padding */; 118 struct pstorm_roce_conn_st_ctx pstorm_st_context /* pstorm storm context */; 119 struct xstorm_roce_conn_st_ctx xstorm_st_context /* xstorm storm context */; 120 struct regpair xstorm_st_padding[2] /* padding */; 121 struct e5_xstorm_rdma_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 122 struct e5_tstorm_rdma_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 123 struct timers_context timer_context /* timer context */; 124 struct e5_ustorm_rdma_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 125 struct tstorm_roce_conn_st_ctx tstorm_st_context /* tstorm storm context */; 126 struct mstorm_roce_conn_st_ctx mstorm_st_context /* mstorm storm context */; 127 struct ustorm_roce_conn_st_ctx ustorm_st_context /* ustorm storm context */; 128 struct regpair ustorm_st_padding[2] /* padding */; 129 }; 130 131 132 133 134 /* 135 * roce create qp requester ramrod data 136 */ 137 struct roce_create_qp_req_ramrod_data 138 { 139 __le16 flags; 140 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 /* Use roce_flavor enum */ 141 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0 142 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1 143 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2 144 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1 145 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3 146 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7 147 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT 4 148 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_MASK 0x1 149 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_SHIFT 7 150 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF 151 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 8 152 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF 153 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 12 154 u8 max_ord; 155 u8 traffic_class /* In case of RRoCE on IPv4 will be used as TOS */; 156 u8 hop_limit /* In case of RRoCE on IPv4 will be used as TTL */; 157 u8 orq_num_pages; 158 __le16 p_key; 159 __le32 flow_label; 160 __le32 dst_qp_id; 161 __le32 ack_timeout_val; 162 __le32 initial_psn; 163 __le16 mtu; 164 __le16 pd; 165 __le16 sq_num_pages; 166 __le16 low_latency_phy_queue; 167 struct regpair sq_pbl_addr; 168 struct regpair orq_pbl_addr; 169 __le16 local_mac_addr[3] /* BE order */; 170 __le16 remote_mac_addr[3] /* BE order */; 171 __le16 vlan_id; 172 __le16 udp_src_port /* Only relevant in RRoCE */; 173 __le32 src_gid[4] /* BE order. In case of RRoCE on IPv4 the high register will hold the address. Low registers must be zero! */; 174 __le32 dst_gid[4] /* BE order. In case of RRoCE on IPv4 the high register will hold the address. Low registers must be zero! */; 175 __le32 cq_cid; 176 struct regpair qp_handle_for_cqe; 177 struct regpair qp_handle_for_async; 178 u8 stats_counter_id /* Statistics counter ID to use */; 179 u8 reserved3[7]; 180 __le16 regular_latency_phy_queue; 181 __le16 dpi; 182 }; 183 184 185 /* 186 * roce create qp responder ramrod data 187 */ 188 struct roce_create_qp_resp_ramrod_data 189 { 190 __le32 flags; 191 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 /* Use roce_flavor enum */ 192 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0 193 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 194 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2 195 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 196 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3 197 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 198 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 4 199 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1 200 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT 5 201 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1 202 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6 203 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1 204 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 7 205 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7 206 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8 207 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F 208 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11 209 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK 0x1 210 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_SHIFT 16 211 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK 0x7FFF 212 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_SHIFT 17 213 __le16 xrc_domain /* SRC domain. Only applicable when xrc_flag is set */; 214 u8 max_ird; 215 u8 traffic_class /* In case of RRoCE on IPv4 will be used as TOS */; 216 u8 hop_limit /* In case of RRoCE on IPv4 will be used as TTL */; 217 u8 irq_num_pages; 218 __le16 p_key; 219 __le32 flow_label; 220 __le32 dst_qp_id; 221 u8 stats_counter_id /* Statistics counter ID to use */; 222 u8 reserved1; 223 __le16 mtu; 224 __le32 initial_psn; 225 __le16 pd; 226 __le16 rq_num_pages; 227 struct rdma_srq_id srq_id; 228 struct regpair rq_pbl_addr; 229 struct regpair irq_pbl_addr; 230 __le16 local_mac_addr[3] /* BE order */; 231 __le16 remote_mac_addr[3] /* BE order */; 232 __le16 vlan_id; 233 __le16 udp_src_port /* Only relevant in RRoCE */; 234 __le32 src_gid[4] /* BE order. In case of RRoCE on IPv4 the lower register will hold the address. High registers must be zero! */; 235 __le32 dst_gid[4] /* BE order. In case of RRoCE on IPv4 the lower register will hold the address. High registers must be zero! */; 236 struct regpair qp_handle_for_cqe; 237 struct regpair qp_handle_for_async; 238 __le16 low_latency_phy_queue; 239 u8 reserved2[2]; 240 __le32 cq_cid; 241 __le16 regular_latency_phy_queue; 242 __le16 dpi; 243 }; 244 245 246 /* 247 * roce DCQCN received statistics 248 */ 249 struct roce_dcqcn_received_stats 250 { 251 struct regpair ecn_pkt_rcv /* The number of total packets with ECN indication received */; 252 struct regpair cnp_pkt_rcv /* The number of total RoCE packets with CNP opcode received */; 253 }; 254 255 256 /* 257 * roce DCQCN sent statistics 258 */ 259 struct roce_dcqcn_sent_stats 260 { 261 struct regpair cnp_pkt_sent /* The number of total RoCE packets with CNP opcode sent */; 262 }; 263 264 265 /* 266 * RoCE destroy qp requester output params 267 */ 268 struct roce_destroy_qp_req_output_params 269 { 270 __le32 num_bound_mw; 271 __le32 cq_prod /* Completion producer value at destroy QP */; 272 }; 273 274 275 /* 276 * RoCE destroy qp requester ramrod data 277 */ 278 struct roce_destroy_qp_req_ramrod_data 279 { 280 struct regpair output_params_addr; 281 }; 282 283 284 /* 285 * RoCE destroy qp responder output params 286 */ 287 struct roce_destroy_qp_resp_output_params 288 { 289 __le32 num_invalidated_mw; 290 __le32 cq_prod /* Completion producer value at destroy QP */; 291 }; 292 293 294 /* 295 * RoCE destroy qp responder ramrod data 296 */ 297 struct roce_destroy_qp_resp_ramrod_data 298 { 299 struct regpair output_params_addr; 300 }; 301 302 303 /* 304 * roce special events statistics 305 */ 306 struct roce_events_stats 307 { 308 __le16 silent_drops; 309 __le16 rnr_naks_sent; 310 __le32 retransmit_count; 311 __le32 icrc_error_count; 312 __le32 reserved; 313 }; 314 315 316 /* 317 * ROCE slow path EQ cmd IDs 318 */ 319 enum roce_event_opcode 320 { 321 ROCE_EVENT_CREATE_QP=11, 322 ROCE_EVENT_MODIFY_QP, 323 ROCE_EVENT_QUERY_QP, 324 ROCE_EVENT_DESTROY_QP, 325 ROCE_EVENT_CREATE_UD_QP, 326 ROCE_EVENT_DESTROY_UD_QP, 327 MAX_ROCE_EVENT_OPCODE 328 }; 329 330 331 /* 332 * roce func init ramrod data 333 */ 334 struct roce_init_func_params 335 { 336 u8 ll2_queue_id /* This ll2 queue ID is used for Unreliable Datagram QP */; 337 u8 cnp_vlan_priority /* VLAN priority of DCQCN CNP packet */; 338 u8 cnp_dscp /* The value of DSCP field in IP header for CNP packets */; 339 u8 reserved; 340 __le32 cnp_send_timeout /* The minimal difference of send time between CNP packets for specific QP. Units are in microseconds */; 341 }; 342 343 344 /* 345 * roce func init ramrod data 346 */ 347 struct roce_init_func_ramrod_data 348 { 349 struct rdma_init_func_ramrod_data rdma; 350 struct roce_init_func_params roce; 351 }; 352 353 354 /* 355 * roce modify qp requester ramrod data 356 */ 357 struct roce_modify_qp_req_ramrod_data 358 { 359 __le16 flags; 360 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1 361 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0 362 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1 363 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT 1 364 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1 365 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2 366 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1 367 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT 3 368 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1 369 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 4 370 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1 371 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT 5 372 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1 373 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT 6 374 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1 375 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT 7 376 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1 377 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT 8 378 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1 379 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9 380 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7 381 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10 382 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUES_FLG_MASK 0x1 383 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUES_FLG_SHIFT 13 384 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x3 385 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 14 386 u8 fields; 387 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF 388 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0 389 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF 390 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 4 391 u8 max_ord; 392 u8 traffic_class; 393 u8 hop_limit; 394 __le16 p_key; 395 __le32 flow_label; 396 __le32 ack_timeout_val; 397 __le16 mtu; 398 __le16 reserved2; 399 __le32 reserved3[2]; 400 __le16 low_latency_phy_queue; 401 __le16 regular_latency_phy_queue; 402 __le32 src_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */; 403 __le32 dst_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */; 404 }; 405 406 407 /* 408 * roce modify qp responder ramrod data 409 */ 410 struct roce_modify_qp_resp_ramrod_data 411 { 412 __le16 flags; 413 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1 414 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0 415 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 416 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 1 417 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 418 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 2 419 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 420 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 3 421 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1 422 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT 4 423 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1 424 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 5 425 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1 426 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT 6 427 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1 428 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT 7 429 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1 430 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8 431 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1 432 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9 433 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUES_FLG_MASK 0x1 434 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUES_FLG_SHIFT 10 435 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0x1F 436 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 11 437 u8 fields; 438 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7 439 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0 440 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F 441 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3 442 u8 max_ird; 443 u8 traffic_class; 444 u8 hop_limit; 445 __le16 p_key; 446 __le32 flow_label; 447 __le16 mtu; 448 __le16 low_latency_phy_queue; 449 __le16 regular_latency_phy_queue; 450 u8 reserved2[6]; 451 __le32 src_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */; 452 __le32 dst_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */; 453 }; 454 455 456 /* 457 * RoCE query qp requester output params 458 */ 459 struct roce_query_qp_req_output_params 460 { 461 __le32 psn /* send next psn */; 462 __le32 flags; 463 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1 464 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0 465 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1 466 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1 467 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF 468 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 2 469 }; 470 471 472 /* 473 * RoCE query qp requester ramrod data 474 */ 475 struct roce_query_qp_req_ramrod_data 476 { 477 struct regpair output_params_addr; 478 }; 479 480 481 /* 482 * RoCE query qp responder output params 483 */ 484 struct roce_query_qp_resp_output_params 485 { 486 __le32 psn /* send next psn */; 487 __le32 err_flag; 488 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1 489 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0 490 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF 491 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1 492 }; 493 494 495 /* 496 * RoCE query qp responder ramrod data 497 */ 498 struct roce_query_qp_resp_ramrod_data 499 { 500 struct regpair output_params_addr; 501 }; 502 503 504 /* 505 * ROCE ramrod command IDs 506 */ 507 enum roce_ramrod_cmd_id 508 { 509 ROCE_RAMROD_CREATE_QP=11, 510 ROCE_RAMROD_MODIFY_QP, 511 ROCE_RAMROD_QUERY_QP, 512 ROCE_RAMROD_DESTROY_QP, 513 ROCE_RAMROD_CREATE_UD_QP, 514 ROCE_RAMROD_DESTROY_UD_QP, 515 MAX_ROCE_RAMROD_CMD_ID 516 }; 517 518 519 520 521 522 523 struct e4_mstorm_roce_req_conn_ag_ctx 524 { 525 u8 byte0 /* cdu_validation */; 526 u8 byte1 /* state */; 527 u8 flags0; 528 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 529 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 530 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 531 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 532 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 533 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 534 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 535 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 536 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 537 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 538 u8 flags1; 539 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 540 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 541 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 542 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 543 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 544 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 545 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 546 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 547 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 548 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 549 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 550 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 551 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 552 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 553 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 554 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 555 __le16 word0 /* word0 */; 556 __le16 word1 /* word1 */; 557 __le32 reg0 /* reg0 */; 558 __le32 reg1 /* reg1 */; 559 }; 560 561 562 struct e4_mstorm_roce_resp_conn_ag_ctx 563 { 564 u8 byte0 /* cdu_validation */; 565 u8 byte1 /* state */; 566 u8 flags0; 567 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 568 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 569 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 570 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 571 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 572 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 573 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 574 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 575 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 576 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 577 u8 flags1; 578 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 579 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 580 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 581 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 582 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 583 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 584 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 585 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 586 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 587 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 588 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 589 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 590 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 591 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 592 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 593 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 594 __le16 word0 /* word0 */; 595 __le16 word1 /* word1 */; 596 __le32 reg0 /* reg0 */; 597 __le32 reg1 /* reg1 */; 598 }; 599 600 601 struct e4_tstorm_roce_req_conn_ag_ctx 602 { 603 u8 reserved0 /* cdu_validation */; 604 u8 state /* state */; 605 u8 flags0; 606 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 607 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 608 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_MASK 0x1 /* exist_in_qm1 */ 609 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_SHIFT 1 610 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_MASK 0x1 /* bit2 */ 611 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_SHIFT 2 612 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 613 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3 614 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit4 */ 615 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 616 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 /* bit5 */ 617 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 618 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3 /* timer0cf */ 619 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6 620 u8 flags1; 621 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 622 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 0 623 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3 /* timer2cf */ 624 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2 625 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */ 626 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 627 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */ 628 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 629 u8 flags2; 630 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */ 631 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 632 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3 /* cf6 */ 633 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2 634 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3 /* cf7 */ 635 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4 636 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3 /* cf8 */ 637 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6 638 u8 flags3; 639 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3 /* cf9 */ 640 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0 641 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3 /* cf10 */ 642 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2 643 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1 /* cf0en */ 644 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4 645 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 646 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 5 647 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1 /* cf2en */ 648 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6 649 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */ 650 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 651 u8 flags4; 652 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */ 653 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 654 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */ 655 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 656 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1 /* cf6en */ 657 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2 658 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1 /* cf7en */ 659 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3 660 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1 /* cf8en */ 661 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4 662 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1 /* cf9en */ 663 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5 664 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1 /* cf10en */ 665 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6 666 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 667 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 668 u8 flags5; 669 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 670 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 671 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 672 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 673 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 674 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 675 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 676 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 677 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 678 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 679 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1 /* rule6en */ 680 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5 681 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 682 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 683 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 684 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 685 __le32 reg0 /* reg0 */; 686 __le32 snd_nxt_psn /* reg1 */; 687 __le32 snd_max_psn /* reg2 */; 688 __le32 orq_prod /* reg3 */; 689 __le32 reg4 /* reg4 */; 690 __le32 reg5 /* reg5 */; 691 __le32 reg6 /* reg6 */; 692 __le32 reg7 /* reg7 */; 693 __le32 reg8 /* reg8 */; 694 u8 tx_cqe_error_type /* byte2 */; 695 u8 orq_cache_idx /* byte3 */; 696 __le16 snd_sq_cons_th /* word0 */; 697 u8 byte4 /* byte4 */; 698 u8 byte5 /* byte5 */; 699 __le16 snd_sq_cons /* word1 */; 700 __le16 conn_dpi /* conn_dpi */; 701 __le16 word3 /* word3 */; 702 __le32 reg9 /* reg9 */; 703 __le32 reg10 /* reg10 */; 704 }; 705 706 707 struct e4_tstorm_roce_resp_conn_ag_ctx 708 { 709 u8 byte0 /* cdu_validation */; 710 u8 state /* state */; 711 u8 flags0; 712 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 713 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 714 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1 /* exist_in_qm1 */ 715 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1 716 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 717 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2 718 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 719 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3 720 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit4 */ 721 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 722 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 723 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5 724 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 725 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6 726 u8 flags1; 727 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* timer1cf */ 728 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0 729 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3 /* timer2cf */ 730 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2 731 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 732 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4 733 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */ 734 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 735 u8 flags2; 736 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */ 737 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 738 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 739 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2 740 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 741 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4 742 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 743 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6 744 u8 flags3; 745 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 746 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0 747 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 748 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2 749 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 750 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4 751 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf1en */ 752 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 5 753 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1 /* cf2en */ 754 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6 755 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 756 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7 757 u8 flags4; 758 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */ 759 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 760 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */ 761 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 762 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 763 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2 764 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 765 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3 766 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 767 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4 768 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 769 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5 770 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 771 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6 772 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 773 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 774 u8 flags5; 775 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 776 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 777 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 778 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 779 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 780 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 781 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 782 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 783 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 784 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 785 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1 /* rule6en */ 786 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5 787 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 788 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 789 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 790 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 791 __le32 psn_and_rxmit_id_echo /* reg0 */; 792 __le32 reg1 /* reg1 */; 793 __le32 reg2 /* reg2 */; 794 __le32 reg3 /* reg3 */; 795 __le32 reg4 /* reg4 */; 796 __le32 reg5 /* reg5 */; 797 __le32 reg6 /* reg6 */; 798 __le32 reg7 /* reg7 */; 799 __le32 reg8 /* reg8 */; 800 u8 tx_async_error_type /* byte2 */; 801 u8 byte3 /* byte3 */; 802 __le16 rq_cons /* word0 */; 803 u8 byte4 /* byte4 */; 804 u8 byte5 /* byte5 */; 805 __le16 rq_prod /* word1 */; 806 __le16 conn_dpi /* conn_dpi */; 807 __le16 irq_cons /* word3 */; 808 __le32 num_invlidated_mw /* reg9 */; 809 __le32 reg10 /* reg10 */; 810 }; 811 812 813 struct e4_ustorm_roce_req_conn_ag_ctx 814 { 815 u8 byte0 /* cdu_validation */; 816 u8 byte1 /* state */; 817 u8 flags0; 818 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 819 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 820 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 821 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 822 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 823 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 824 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 825 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 826 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 827 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 828 u8 flags1; 829 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 830 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0 831 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 832 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2 833 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 834 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4 835 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 836 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6 837 u8 flags2; 838 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 839 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 840 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 841 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 842 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 843 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 844 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 845 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3 846 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 847 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4 848 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 849 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5 850 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 851 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6 852 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 853 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 854 u8 flags3; 855 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 856 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 857 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 858 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 859 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 860 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 861 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 862 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 863 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 864 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 865 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 866 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5 867 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 868 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 869 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 870 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 871 u8 byte2 /* byte2 */; 872 u8 byte3 /* byte3 */; 873 __le16 word0 /* conn_dpi */; 874 __le16 word1 /* word1 */; 875 __le32 reg0 /* reg0 */; 876 __le32 reg1 /* reg1 */; 877 __le32 reg2 /* reg2 */; 878 __le32 reg3 /* reg3 */; 879 __le16 word2 /* word2 */; 880 __le16 word3 /* word3 */; 881 }; 882 883 884 struct e4_ustorm_roce_resp_conn_ag_ctx 885 { 886 u8 byte0 /* cdu_validation */; 887 u8 byte1 /* state */; 888 u8 flags0; 889 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 890 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 891 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 892 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 893 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 894 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 895 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 896 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 897 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 898 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 899 u8 flags1; 900 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 901 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0 902 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 903 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2 904 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 905 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4 906 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 907 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6 908 u8 flags2; 909 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 910 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 911 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 912 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 913 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 914 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 915 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 916 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3 917 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 918 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4 919 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 920 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5 921 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 922 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6 923 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 924 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 925 u8 flags3; 926 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 927 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 928 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 929 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 930 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 931 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 932 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 933 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 934 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 935 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 936 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 937 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5 938 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 939 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 940 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 941 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 942 u8 byte2 /* byte2 */; 943 u8 byte3 /* byte3 */; 944 __le16 word0 /* conn_dpi */; 945 __le16 word1 /* word1 */; 946 __le32 reg0 /* reg0 */; 947 __le32 reg1 /* reg1 */; 948 __le32 reg2 /* reg2 */; 949 __le32 reg3 /* reg3 */; 950 __le16 word2 /* word2 */; 951 __le16 word3 /* word3 */; 952 }; 953 954 955 struct e4_xstorm_roce_req_conn_ag_ctx 956 { 957 u8 reserved0 /* cdu_validation */; 958 u8 state /* state */; 959 u8 flags0; 960 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 961 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 962 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 963 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1 964 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 965 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2 966 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 967 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 968 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 969 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4 970 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 971 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5 972 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 973 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6 974 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 975 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7 976 u8 flags1; 977 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 978 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0 979 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 980 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1 981 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 982 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2 983 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 984 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3 985 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 986 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4 987 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 988 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5 989 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1 /* bit14 */ 990 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6 991 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 992 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 993 u8 flags2; 994 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 995 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0 996 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 997 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2 998 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 999 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4 1000 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1001 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6 1002 u8 flags3; 1003 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 /* cf4 */ 1004 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0 1005 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* cf5 */ 1006 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 1007 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3 /* cf6 */ 1008 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4 1009 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 1010 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1011 u8 flags4; 1012 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1013 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT 0 1014 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1015 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT 2 1016 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1017 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4 1018 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 1019 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6 1020 u8 flags5; 1021 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 1022 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0 1023 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 1024 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2 1025 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3 /* cf14 */ 1026 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4 1027 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 1028 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6 1029 u8 flags6; 1030 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 1031 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0 1032 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 1033 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2 1034 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 1035 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4 1036 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */ 1037 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6 1038 u8 flags7; 1039 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */ 1040 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0 1041 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */ 1042 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2 1043 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 1044 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4 1045 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1046 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6 1047 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1048 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7 1049 u8 flags8; 1050 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1051 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0 1052 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1053 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1 1054 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 /* cf4en */ 1055 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2 1056 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */ 1057 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 1058 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1 /* cf6en */ 1059 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4 1060 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 1061 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 1062 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1063 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT 6 1064 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1065 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT 7 1066 u8 flags9; 1067 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1068 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0 1069 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 1070 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1 1071 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 1072 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2 1073 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 1074 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3 1075 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1 /* cf14en */ 1076 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4 1077 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 1078 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5 1079 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 1080 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6 1081 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 1082 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7 1083 u8 flags10; 1084 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 1085 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0 1086 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */ 1087 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1 1088 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */ 1089 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2 1090 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */ 1091 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3 1092 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1093 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 1094 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 1095 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5 1096 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1097 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6 1098 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1099 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7 1100 u8 flags11; 1101 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1102 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0 1103 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1104 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1 1105 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1106 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2 1107 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1108 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3 1109 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1110 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4 1111 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1 /* rule7en */ 1112 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5 1113 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 1114 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 1115 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 1116 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7 1117 u8 flags12; 1118 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1 /* rule10en */ 1119 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0 1120 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 1121 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1 1122 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 1123 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 1124 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 1125 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 1126 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1 /* rule14en */ 1127 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4 1128 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 1129 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5 1130 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1 /* rule16en */ 1131 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6 1132 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1 /* rule17en */ 1133 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7 1134 u8 flags13; 1135 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 1136 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0 1137 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 1138 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1 1139 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 1140 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 1141 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 1142 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 1143 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 1144 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 1145 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 1146 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 1147 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 1148 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 1149 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 1150 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 1151 u8 flags14; 1152 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1 /* bit16 */ 1153 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0 1154 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 1155 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1 1156 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 1157 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 1158 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1 /* bit20 */ 1159 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4 1160 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 1161 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 1162 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 1163 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6 1164 u8 byte2 /* byte2 */; 1165 __le16 physical_q0 /* physical_q0 */; 1166 __le16 word1 /* physical_q1 */; 1167 __le16 sq_cmp_cons /* physical_q2 */; 1168 __le16 sq_cons /* word3 */; 1169 __le16 sq_prod /* word4 */; 1170 __le16 word5 /* word5 */; 1171 __le16 conn_dpi /* conn_dpi */; 1172 u8 byte3 /* byte3 */; 1173 u8 byte4 /* byte4 */; 1174 u8 byte5 /* byte5 */; 1175 u8 byte6 /* byte6 */; 1176 __le32 lsn /* reg0 */; 1177 __le32 ssn /* reg1 */; 1178 __le32 snd_una_psn /* reg2 */; 1179 __le32 snd_nxt_psn /* reg3 */; 1180 __le32 reg4 /* reg4 */; 1181 __le32 orq_cons_th /* cf_array0 */; 1182 __le32 orq_cons /* cf_array1 */; 1183 }; 1184 1185 1186 struct e4_xstorm_roce_resp_conn_ag_ctx 1187 { 1188 u8 reserved0 /* cdu_validation */; 1189 u8 state /* state */; 1190 u8 flags0; 1191 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1192 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1193 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 1194 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1 1195 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 1196 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2 1197 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 1198 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 1199 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 1200 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4 1201 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 1202 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5 1203 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 1204 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6 1205 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 1206 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7 1207 u8 flags1; 1208 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 1209 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0 1210 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 1211 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1 1212 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 1213 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2 1214 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 1215 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3 1216 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 1217 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4 1218 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 1219 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5 1220 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1 /* bit14 */ 1221 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6 1222 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 1223 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 1224 u8 flags2; 1225 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1226 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0 1227 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1228 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2 1229 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1230 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4 1231 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1232 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6 1233 u8 flags3; 1234 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3 /* cf4 */ 1235 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0 1236 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* cf5 */ 1237 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 1238 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3 /* cf6 */ 1239 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4 1240 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 1241 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1242 u8 flags4; 1243 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1244 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0 1245 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1246 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2 1247 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1248 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4 1249 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 1250 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6 1251 u8 flags5; 1252 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 1253 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0 1254 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 1255 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2 1256 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 1257 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4 1258 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 1259 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6 1260 u8 flags6; 1261 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 1262 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0 1263 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 1264 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2 1265 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 1266 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4 1267 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */ 1268 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6 1269 u8 flags7; 1270 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */ 1271 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0 1272 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */ 1273 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2 1274 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 1275 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 1276 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1277 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6 1278 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1279 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7 1280 u8 flags8; 1281 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1282 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0 1283 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1284 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1 1285 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1 /* cf4en */ 1286 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2 1287 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */ 1288 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 1289 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1 /* cf6en */ 1290 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4 1291 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 1292 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 1293 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1294 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6 1295 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1296 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7 1297 u8 flags9; 1298 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1299 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0 1300 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 1301 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1 1302 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 1303 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2 1304 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 1305 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3 1306 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 1307 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4 1308 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 1309 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5 1310 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 1311 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6 1312 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 1313 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7 1314 u8 flags10; 1315 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 1316 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0 1317 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */ 1318 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1 1319 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */ 1320 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2 1321 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */ 1322 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3 1323 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1324 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 1325 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 1326 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5 1327 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1328 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6 1329 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1330 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7 1331 u8 flags11; 1332 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1333 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0 1334 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1335 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1 1336 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1337 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2 1338 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1339 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3 1340 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1341 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4 1342 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1343 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5 1344 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 1345 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 1346 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 1347 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7 1348 u8 flags12; 1349 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1 /* rule10en */ 1350 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 0 1351 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 1352 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_SHIFT 1 1353 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 1354 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 1355 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 1356 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 1357 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 1358 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4 1359 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 1360 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5 1361 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 1362 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6 1363 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 1364 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7 1365 u8 flags13; 1366 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 1367 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0 1368 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 1369 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1 1370 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 1371 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 1372 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 1373 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 1374 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 1375 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 1376 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 1377 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 1378 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 1379 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 1380 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 1381 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 1382 u8 flags14; 1383 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 1384 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0 1385 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 1386 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1 1387 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */ 1388 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2 1389 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */ 1390 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3 1391 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */ 1392 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4 1393 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */ 1394 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5 1395 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 1396 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6 1397 u8 byte2 /* byte2 */; 1398 __le16 physical_q0 /* physical_q0 */; 1399 __le16 irq_prod_shadow /* physical_q1 */; 1400 __le16 word2 /* physical_q2 */; 1401 __le16 irq_cons /* word3 */; 1402 __le16 irq_prod /* word4 */; 1403 __le16 e5_reserved1 /* word5 */; 1404 __le16 conn_dpi /* conn_dpi */; 1405 u8 rxmit_opcode /* byte3 */; 1406 u8 byte4 /* byte4 */; 1407 u8 byte5 /* byte5 */; 1408 u8 byte6 /* byte6 */; 1409 __le32 rxmit_psn_and_id /* reg0 */; 1410 __le32 rxmit_bytes_length /* reg1 */; 1411 __le32 psn /* reg2 */; 1412 __le32 reg3 /* reg3 */; 1413 __le32 reg4 /* reg4 */; 1414 __le32 reg5 /* cf_array0 */; 1415 __le32 msn_and_syndrome /* cf_array1 */; 1416 }; 1417 1418 1419 struct e4_ystorm_roce_req_conn_ag_ctx 1420 { 1421 u8 byte0 /* cdu_validation */; 1422 u8 byte1 /* state */; 1423 u8 flags0; 1424 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1425 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 1426 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1427 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 1428 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1429 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 1430 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1431 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 1432 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1433 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 1434 u8 flags1; 1435 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1436 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 1437 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1438 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 1439 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1440 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 1441 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1442 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 1443 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1444 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 1445 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1446 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 1447 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1448 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 1449 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1450 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 1451 u8 byte2 /* byte2 */; 1452 u8 byte3 /* byte3 */; 1453 __le16 word0 /* word0 */; 1454 __le32 reg0 /* reg0 */; 1455 __le32 reg1 /* reg1 */; 1456 __le16 word1 /* word1 */; 1457 __le16 word2 /* word2 */; 1458 __le16 word3 /* word3 */; 1459 __le16 word4 /* word4 */; 1460 __le32 reg2 /* reg2 */; 1461 __le32 reg3 /* reg3 */; 1462 }; 1463 1464 1465 struct e4_ystorm_roce_resp_conn_ag_ctx 1466 { 1467 u8 byte0 /* cdu_validation */; 1468 u8 byte1 /* state */; 1469 u8 flags0; 1470 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1471 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 1472 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1473 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 1474 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1475 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 1476 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1477 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 1478 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1479 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 1480 u8 flags1; 1481 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1482 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 1483 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1484 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 1485 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1486 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 1487 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1488 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 1489 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1490 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 1491 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1492 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 1493 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1494 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 1495 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1496 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 1497 u8 byte2 /* byte2 */; 1498 u8 byte3 /* byte3 */; 1499 __le16 word0 /* word0 */; 1500 __le32 reg0 /* reg0 */; 1501 __le32 reg1 /* reg1 */; 1502 __le16 word1 /* word1 */; 1503 __le16 word2 /* word2 */; 1504 __le16 word3 /* word3 */; 1505 __le16 word4 /* word4 */; 1506 __le32 reg2 /* reg2 */; 1507 __le32 reg3 /* reg3 */; 1508 }; 1509 1510 1511 struct E5XstormRoceConnAgCtxDqExtLdPart 1512 { 1513 u8 reserved0 /* cdu_validation */; 1514 u8 state_and_core_id /* state_and_core_id */; 1515 u8 flags0; 1516 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1517 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 1518 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 1519 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1 1520 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 1521 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2 1522 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 1523 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 1524 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1 /* bit4 */ 1525 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4 1526 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1 /* cf_array_active */ 1527 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5 1528 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1 /* bit6 */ 1529 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6 1530 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1 /* bit7 */ 1531 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7 1532 u8 flags1; 1533 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1 /* bit8 */ 1534 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0 1535 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1 /* bit9 */ 1536 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1 1537 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1 /* bit10 */ 1538 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2 1539 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 /* bit11 */ 1540 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 1541 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1 /* bit12 */ 1542 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4 1543 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT13_MASK 0x1 /* bit13 */ 1544 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT13_SHIFT 5 1545 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ERROR_STATE_MASK 0x1 /* bit14 */ 1546 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ERROR_STATE_SHIFT 6 1547 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 1548 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7 1549 u8 flags2; 1550 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3 /* timer0cf */ 1551 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0 1552 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3 /* timer1cf */ 1553 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2 1554 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3 /* timer2cf */ 1555 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4 1556 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3 /* timer_stop_all */ 1557 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6 1558 u8 flags3; 1559 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_FLUSH_CF_MASK 0x3 /* cf4 */ 1560 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_FLUSH_CF_SHIFT 0 1561 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RX_ERROR_CF_MASK 0x3 /* cf5 */ 1562 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RX_ERROR_CF_SHIFT 2 1563 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SND_RXMIT_CF_MASK 0x3 /* cf6 */ 1564 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SND_RXMIT_CF_SHIFT 4 1565 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 1566 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6 1567 u8 flags4; 1568 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3 /* cf8 */ 1569 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0 1570 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3 /* cf9 */ 1571 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2 1572 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3 /* cf10 */ 1573 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4 1574 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3 /* cf11 */ 1575 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6 1576 u8 flags5; 1577 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3 /* cf12 */ 1578 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0 1579 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3 /* cf13 */ 1580 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2 1581 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FMR_ENDED_CF_MASK 0x3 /* cf14 */ 1582 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FMR_ENDED_CF_SHIFT 4 1583 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3 /* cf15 */ 1584 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6 1585 u8 flags6; 1586 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3 /* cf16 */ 1587 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0 1588 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3 /* cf_array_cf */ 1589 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2 1590 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3 /* cf18 */ 1591 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4 1592 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3 /* cf19 */ 1593 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6 1594 u8 flags7; 1595 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3 /* cf20 */ 1596 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0 1597 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3 /* cf21 */ 1598 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2 1599 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 /* cf22 */ 1600 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 1601 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 /* cf0en */ 1602 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 1603 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 /* cf1en */ 1604 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 1605 u8 flags8; 1606 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 /* cf2en */ 1607 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 1608 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 /* cf3en */ 1609 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 1610 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_FLUSH_CF_EN_MASK 0x1 /* cf4en */ 1611 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_FLUSH_CF_EN_SHIFT 2 1612 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */ 1613 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RX_ERROR_CF_EN_SHIFT 3 1614 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SND_RXMIT_CF_EN_MASK 0x1 /* cf6en */ 1615 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SND_RXMIT_CF_EN_SHIFT 4 1616 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 1617 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5 1618 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 /* cf8en */ 1619 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 1620 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 /* cf9en */ 1621 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 1622 u8 flags9; 1623 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 /* cf10en */ 1624 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 1625 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 /* cf11en */ 1626 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 1627 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 /* cf12en */ 1628 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 1629 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 /* cf13en */ 1630 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 1631 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FME_ENDED_CF_EN_MASK 0x1 /* cf14en */ 1632 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FME_ENDED_CF_EN_SHIFT 4 1633 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 /* cf15en */ 1634 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 1635 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1 /* cf16en */ 1636 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6 1637 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1 /* cf_array_cf_en */ 1638 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7 1639 u8 flags10; 1640 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1 /* cf18en */ 1641 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0 1642 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1 /* cf19en */ 1643 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1 1644 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1 /* cf20en */ 1645 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2 1646 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1 /* cf21en */ 1647 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3 1648 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1649 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 1650 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1 /* cf23en */ 1651 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5 1652 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1 /* rule0en */ 1653 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6 1654 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1 /* rule1en */ 1655 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7 1656 u8 flags11; 1657 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1 /* rule2en */ 1658 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0 1659 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1 /* rule3en */ 1660 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1 1661 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1 /* rule4en */ 1662 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2 1663 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 /* rule5en */ 1664 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 1665 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 /* rule6en */ 1666 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 1667 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E2E_CREDIT_RULE_EN_MASK 0x1 /* rule7en */ 1668 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E2E_CREDIT_RULE_EN_SHIFT 5 1669 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 /* rule8en */ 1670 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 1671 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 /* rule9en */ 1672 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 1673 u8 flags12; 1674 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_PROD_EN_MASK 0x1 /* rule10en */ 1675 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_PROD_EN_SHIFT 0 1676 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 /* rule11en */ 1677 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 1678 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 /* rule12en */ 1679 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 1680 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 /* rule13en */ 1681 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 1682 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_INV_FENCE_RULE_EN_MASK 0x1 /* rule14en */ 1683 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_INV_FENCE_RULE_EN_SHIFT 4 1684 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 /* rule15en */ 1685 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 1686 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ORQ_FENCE_RULE_EN_MASK 0x1 /* rule16en */ 1687 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ORQ_FENCE_RULE_EN_SHIFT 6 1688 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_MAX_ORD_RULE_EN_MASK 0x1 /* rule17en */ 1689 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_MAX_ORD_RULE_EN_SHIFT 7 1690 u8 flags13; 1691 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 /* rule18en */ 1692 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 1693 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 /* rule19en */ 1694 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 1695 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 /* rule20en */ 1696 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 1697 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 /* rule21en */ 1698 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 1699 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 /* rule22en */ 1700 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 1701 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 /* rule23en */ 1702 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 1703 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 /* rule24en */ 1704 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 1705 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 /* rule25en */ 1706 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 1707 u8 flags14; 1708 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_FLAG_MASK 0x1 /* bit16 */ 1709 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_FLAG_SHIFT 0 1710 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1 /* bit17 */ 1711 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1 1712 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 1713 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2 1714 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1 /* bit20 */ 1715 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4 1716 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 1717 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 1718 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3 /* cf23 */ 1719 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6 1720 u8 byte2 /* byte2 */; 1721 __le16 physical_q0 /* physical_q0 */; 1722 __le16 word1 /* physical_q1 */; 1723 __le16 sq_cmp_cons /* physical_q2 */; 1724 __le16 sq_cons /* word3 */; 1725 __le16 sq_prod /* word4 */; 1726 __le16 word5 /* word5 */; 1727 __le16 conn_dpi /* conn_dpi */; 1728 u8 byte3 /* byte3 */; 1729 u8 byte4 /* byte4 */; 1730 u8 byte5 /* byte5 */; 1731 u8 byte6 /* byte6 */; 1732 __le32 lsn /* reg0 */; 1733 __le32 ssn /* reg1 */; 1734 __le32 snd_una_psn /* reg2 */; 1735 __le32 snd_nxt_psn /* reg3 */; 1736 __le32 reg4 /* reg4 */; 1737 __le32 orq_cons_th /* cf_array0 */; 1738 __le32 orq_cons /* cf_array1 */; 1739 u8 flags15; 1740 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED1_MASK 0x1 /* bit22 */ 1741 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED1_SHIFT 0 1742 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED2_MASK 0x1 /* bit23 */ 1743 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED2_SHIFT 1 1744 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED3_MASK 0x1 /* bit24 */ 1745 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED3_SHIFT 2 1746 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED4_MASK 0x3 /* cf24 */ 1747 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED4_SHIFT 3 1748 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED5_MASK 0x1 /* cf24en */ 1749 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED5_SHIFT 5 1750 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED6_MASK 0x1 /* rule26en */ 1751 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED6_SHIFT 6 1752 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED7_MASK 0x1 /* rule27en */ 1753 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED7_SHIFT 7 1754 u8 byte7 /* byte7 */; 1755 __le16 word7 /* word7 */; 1756 __le16 word8 /* word8 */; 1757 __le16 word9 /* word9 */; 1758 __le16 word10 /* word10 */; 1759 __le16 tx_rdma_edpm_usg_cnt /* word11 */; 1760 __le32 reg7 /* reg7 */; 1761 __le32 reg8 /* reg8 */; 1762 __le32 reg9 /* reg9 */; 1763 u8 byte8 /* byte8 */; 1764 u8 byte9 /* byte9 */; 1765 u8 byte10 /* byte10 */; 1766 u8 byte11 /* byte11 */; 1767 u8 byte12 /* byte12 */; 1768 u8 byte13 /* byte13 */; 1769 u8 byte14 /* byte14 */; 1770 u8 byte15 /* byte15 */; 1771 __le32 reg10 /* reg10 */; 1772 __le32 reg11 /* reg11 */; 1773 __le32 reg12 /* reg12 */; 1774 __le32 reg13 /* reg13 */; 1775 }; 1776 1777 1778 struct e5_mstorm_roce_req_conn_ag_ctx 1779 { 1780 u8 byte0 /* cdu_validation */; 1781 u8 byte1 /* state_and_core_id */; 1782 u8 flags0; 1783 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1784 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 1785 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1786 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 1787 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1788 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 1789 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1790 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 1791 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1792 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 1793 u8 flags1; 1794 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1795 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 1796 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1797 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 1798 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1799 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 1800 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1801 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 1802 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1803 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 1804 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1805 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 1806 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1807 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 1808 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1809 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 1810 __le16 word0 /* word0 */; 1811 __le16 word1 /* word1 */; 1812 __le32 reg0 /* reg0 */; 1813 __le32 reg1 /* reg1 */; 1814 }; 1815 1816 1817 struct e5_mstorm_roce_resp_conn_ag_ctx 1818 { 1819 u8 byte0 /* cdu_validation */; 1820 u8 byte1 /* state_and_core_id */; 1821 u8 flags0; 1822 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1823 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 1824 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1825 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 1826 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1827 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 1828 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1829 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 1830 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1831 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 1832 u8 flags1; 1833 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1834 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 1835 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1836 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 1837 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1838 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 1839 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1840 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 1841 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1842 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 1843 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1844 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 1845 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1846 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 1847 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1848 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 1849 __le16 word0 /* word0 */; 1850 __le16 word1 /* word1 */; 1851 __le32 reg0 /* reg0 */; 1852 __le32 reg1 /* reg1 */; 1853 }; 1854 1855 1856 struct e5_tstorm_roce_req_conn_ag_ctx 1857 { 1858 u8 reserved0 /* cdu_validation */; 1859 u8 state_and_core_id /* state_and_core_id */; 1860 u8 flags0; 1861 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1862 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1863 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_MASK 0x1 /* exist_in_qm1 */ 1864 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_SHIFT 1 1865 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_MASK 0x1 /* bit2 */ 1866 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_SHIFT 2 1867 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1868 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3 1869 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit4 */ 1870 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 1871 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 /* bit5 */ 1872 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 1873 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3 /* timer0cf */ 1874 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6 1875 u8 flags1; 1876 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1877 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 0 1878 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3 /* timer2cf */ 1879 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2 1880 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */ 1881 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 1882 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */ 1883 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1884 u8 flags2; 1885 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */ 1886 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 1887 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3 /* cf6 */ 1888 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2 1889 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3 /* cf7 */ 1890 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4 1891 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3 /* cf8 */ 1892 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6 1893 u8 flags3; 1894 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3 /* cf9 */ 1895 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0 1896 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3 /* cf10 */ 1897 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2 1898 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1 /* cf0en */ 1899 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4 1900 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1901 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 5 1902 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1 /* cf2en */ 1903 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6 1904 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */ 1905 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 1906 u8 flags4; 1907 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */ 1908 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 1909 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */ 1910 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 1911 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1 /* cf6en */ 1912 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2 1913 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1 /* cf7en */ 1914 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3 1915 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1 /* cf8en */ 1916 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4 1917 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1 /* cf9en */ 1918 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5 1919 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1 /* cf10en */ 1920 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6 1921 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1922 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 1923 u8 flags5; 1924 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1925 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 1926 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1927 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 1928 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1929 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 1930 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1931 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 1932 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1933 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 1934 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1 /* rule6en */ 1935 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5 1936 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1937 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 1938 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1939 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 1940 u8 flags6; 1941 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 1942 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1943 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 1944 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1945 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 1946 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1947 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 1948 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 1949 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 1950 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 1951 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 1952 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 1953 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 1954 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 1955 u8 tx_cqe_error_type /* byte2 */; 1956 __le16 snd_sq_cons_th /* word0 */; 1957 __le32 reg0 /* reg0 */; 1958 __le32 snd_nxt_psn /* reg1 */; 1959 __le32 snd_max_psn /* reg2 */; 1960 __le32 orq_prod /* reg3 */; 1961 __le32 reg4 /* reg4 */; 1962 __le32 reg5 /* reg5 */; 1963 __le32 reg6 /* reg6 */; 1964 __le32 reg7 /* reg7 */; 1965 __le32 reg8 /* reg8 */; 1966 u8 orq_cache_idx /* byte3 */; 1967 u8 byte4 /* byte4 */; 1968 u8 byte5 /* byte5 */; 1969 u8 e4_reserved8 /* byte6 */; 1970 __le16 snd_sq_cons /* word1 */; 1971 __le16 word2 /* conn_dpi */; 1972 __le32 reg9 /* reg9 */; 1973 __le16 word3 /* word3 */; 1974 __le16 e4_reserved9 /* word4 */; 1975 }; 1976 1977 1978 struct e5_tstorm_roce_resp_conn_ag_ctx 1979 { 1980 u8 byte0 /* cdu_validation */; 1981 u8 state_and_core_id /* state_and_core_id */; 1982 u8 flags0; 1983 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1984 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1985 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1 /* exist_in_qm1 */ 1986 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1 1987 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1988 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2 1989 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1990 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3 1991 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit4 */ 1992 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 1993 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 1994 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5 1995 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1996 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6 1997 u8 flags1; 1998 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* timer1cf */ 1999 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0 2000 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3 /* timer2cf */ 2001 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2 2002 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2003 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4 2004 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */ 2005 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 2006 u8 flags2; 2007 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */ 2008 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 2009 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 2010 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2 2011 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 2012 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4 2013 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 2014 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6 2015 u8 flags3; 2016 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 2017 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0 2018 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 2019 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2 2020 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2021 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4 2022 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf1en */ 2023 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 5 2024 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1 /* cf2en */ 2025 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6 2026 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2027 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7 2028 u8 flags4; 2029 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */ 2030 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 2031 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */ 2032 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 2033 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 2034 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2 2035 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 2036 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3 2037 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 2038 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4 2039 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 2040 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5 2041 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 2042 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6 2043 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2044 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 2045 u8 flags5; 2046 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2047 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 2048 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2049 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 2050 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2051 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 2052 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2053 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 2054 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2055 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 2056 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1 /* rule6en */ 2057 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5 2058 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2059 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 2060 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 2061 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 2062 u8 flags6; 2063 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 2064 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 2065 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 2066 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 2067 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 2068 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 2069 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 2070 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 2071 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 2072 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 2073 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 2074 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 2075 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 2076 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 2077 u8 tx_async_error_type /* byte2 */; 2078 __le16 rq_cons /* word0 */; 2079 __le32 psn_and_rxmit_id_echo /* reg0 */; 2080 __le32 reg1 /* reg1 */; 2081 __le32 reg2 /* reg2 */; 2082 __le32 reg3 /* reg3 */; 2083 __le32 reg4 /* reg4 */; 2084 __le32 reg5 /* reg5 */; 2085 __le32 reg6 /* reg6 */; 2086 __le32 reg7 /* reg7 */; 2087 __le32 reg8 /* reg8 */; 2088 u8 byte3 /* byte3 */; 2089 u8 byte4 /* byte4 */; 2090 u8 byte5 /* byte5 */; 2091 u8 e4_reserved8 /* byte6 */; 2092 __le16 rq_prod /* word1 */; 2093 __le16 conn_dpi /* conn_dpi */; 2094 __le32 num_invlidated_mw /* reg9 */; 2095 __le16 irq_cons /* word3 */; 2096 __le16 e4_reserved9 /* word4 */; 2097 }; 2098 2099 2100 struct e5_ustorm_roce_req_conn_ag_ctx 2101 { 2102 u8 byte0 /* cdu_validation */; 2103 u8 byte1 /* state_and_core_id */; 2104 u8 flags0; 2105 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2106 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 2107 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2108 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 2109 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2110 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 2111 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2112 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 2113 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2114 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 2115 u8 flags1; 2116 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2117 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0 2118 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 2119 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2 2120 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 2121 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4 2122 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 2123 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6 2124 u8 flags2; 2125 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2126 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 2127 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2128 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 2129 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2130 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 2131 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2132 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3 2133 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 2134 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4 2135 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 2136 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5 2137 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 2138 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6 2139 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2140 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 2141 u8 flags3; 2142 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2143 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 2144 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2145 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 2146 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2147 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 2148 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2149 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 2150 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2151 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 2152 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2153 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5 2154 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2155 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 2156 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 2157 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 2158 u8 flags4; 2159 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 2160 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 2161 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 2162 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 2163 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 2164 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 2165 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 2166 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 2167 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 2168 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 2169 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 2170 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 2171 u8 byte2 /* byte2 */; 2172 __le16 word0 /* conn_dpi */; 2173 __le16 word1 /* word1 */; 2174 __le32 reg0 /* reg0 */; 2175 __le32 reg1 /* reg1 */; 2176 __le32 reg2 /* reg2 */; 2177 __le32 reg3 /* reg3 */; 2178 __le16 word2 /* word2 */; 2179 __le16 word3 /* word3 */; 2180 }; 2181 2182 2183 struct e5_ustorm_roce_resp_conn_ag_ctx 2184 { 2185 u8 byte0 /* cdu_validation */; 2186 u8 byte1 /* state_and_core_id */; 2187 u8 flags0; 2188 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2189 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 2190 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2191 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 2192 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2193 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 2194 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2195 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 2196 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2197 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 2198 u8 flags1; 2199 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2200 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0 2201 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 2202 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2 2203 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 2204 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4 2205 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 2206 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6 2207 u8 flags2; 2208 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2209 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 2210 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2211 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 2212 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2213 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 2214 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2215 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3 2216 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 2217 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4 2218 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 2219 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5 2220 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 2221 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6 2222 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2223 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 2224 u8 flags3; 2225 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2226 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 2227 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2228 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 2229 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2230 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 2231 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2232 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 2233 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2234 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 2235 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2236 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5 2237 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2238 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 2239 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 2240 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 2241 u8 flags4; 2242 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 2243 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 2244 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 2245 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 2246 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 2247 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 2248 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 2249 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 2250 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 2251 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 2252 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 2253 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 2254 u8 byte2 /* byte2 */; 2255 __le16 word0 /* conn_dpi */; 2256 __le16 word1 /* word1 */; 2257 __le32 reg0 /* reg0 */; 2258 __le32 reg1 /* reg1 */; 2259 __le32 reg2 /* reg2 */; 2260 __le32 reg3 /* reg3 */; 2261 __le16 word2 /* word2 */; 2262 __le16 word3 /* word3 */; 2263 }; 2264 2265 2266 struct e5_xstorm_roce_req_conn_ag_ctx 2267 { 2268 u8 reserved0 /* cdu_validation */; 2269 u8 state_and_core_id /* state_and_core_id */; 2270 u8 flags0; 2271 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2272 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 2273 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 2274 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1 2275 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 2276 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2 2277 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 2278 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 2279 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 2280 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4 2281 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 2282 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5 2283 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 2284 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6 2285 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 2286 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7 2287 u8 flags1; 2288 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 2289 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0 2290 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 2291 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1 2292 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 2293 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2 2294 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 2295 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3 2296 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 2297 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4 2298 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 2299 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5 2300 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1 /* bit14 */ 2301 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6 2302 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 2303 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 2304 u8 flags2; 2305 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2306 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0 2307 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2308 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2 2309 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2310 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4 2311 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2312 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6 2313 u8 flags3; 2314 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 /* cf4 */ 2315 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0 2316 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* cf5 */ 2317 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 2318 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3 /* cf6 */ 2319 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4 2320 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 2321 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 2322 u8 flags4; 2323 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 2324 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT 0 2325 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 2326 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT 2 2327 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 2328 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4 2329 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 2330 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6 2331 u8 flags5; 2332 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 2333 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0 2334 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 2335 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2 2336 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3 /* cf14 */ 2337 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4 2338 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 2339 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6 2340 u8 flags6; 2341 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 2342 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0 2343 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 2344 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2 2345 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 2346 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4 2347 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */ 2348 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6 2349 u8 flags7; 2350 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */ 2351 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0 2352 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */ 2353 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2 2354 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 2355 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4 2356 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2357 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6 2358 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2359 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7 2360 u8 flags8; 2361 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2362 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0 2363 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2364 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1 2365 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 /* cf4en */ 2366 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2 2367 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */ 2368 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 2369 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1 /* cf6en */ 2370 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4 2371 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 2372 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 2373 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 2374 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT 6 2375 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 2376 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT 7 2377 u8 flags9; 2378 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 2379 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0 2380 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 2381 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1 2382 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 2383 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2 2384 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 2385 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3 2386 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1 /* cf14en */ 2387 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4 2388 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 2389 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5 2390 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 2391 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6 2392 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 2393 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7 2394 u8 flags10; 2395 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 2396 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0 2397 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */ 2398 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1 2399 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */ 2400 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2 2401 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */ 2402 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3 2403 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 2404 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 2405 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 2406 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5 2407 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2408 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6 2409 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2410 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7 2411 u8 flags11; 2412 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2413 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0 2414 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2415 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1 2416 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2417 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2 2418 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2419 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3 2420 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2421 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4 2422 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1 /* rule7en */ 2423 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5 2424 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 2425 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 2426 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 2427 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7 2428 u8 flags12; 2429 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1 /* rule10en */ 2430 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0 2431 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 2432 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1 2433 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 2434 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 2435 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 2436 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 2437 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1 /* rule14en */ 2438 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4 2439 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 2440 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5 2441 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1 /* rule16en */ 2442 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6 2443 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1 /* rule17en */ 2444 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7 2445 u8 flags13; 2446 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 2447 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0 2448 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 2449 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1 2450 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 2451 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 2452 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 2453 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 2454 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 2455 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 2456 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 2457 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 2458 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 2459 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 2460 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 2461 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 2462 u8 flags14; 2463 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1 /* bit16 */ 2464 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0 2465 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 2466 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1 2467 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 2468 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 2469 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1 /* bit20 */ 2470 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4 2471 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 2472 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 2473 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 2474 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6 2475 u8 byte2 /* byte2 */; 2476 __le16 physical_q0 /* physical_q0 */; 2477 __le16 word1 /* physical_q1 */; 2478 __le16 sq_cmp_cons /* physical_q2 */; 2479 __le16 sq_cons /* word3 */; 2480 __le16 sq_prod /* word4 */; 2481 __le16 word5 /* word5 */; 2482 __le16 conn_dpi /* conn_dpi */; 2483 u8 byte3 /* byte3 */; 2484 u8 byte4 /* byte4 */; 2485 u8 byte5 /* byte5 */; 2486 u8 byte6 /* byte6 */; 2487 __le32 lsn /* reg0 */; 2488 __le32 ssn /* reg1 */; 2489 __le32 snd_una_psn /* reg2 */; 2490 __le32 snd_nxt_psn /* reg3 */; 2491 __le32 reg4 /* reg4 */; 2492 __le32 orq_cons_th /* cf_array0 */; 2493 __le32 orq_cons /* cf_array1 */; 2494 }; 2495 2496 2497 struct e5_xstorm_roce_resp_conn_ag_ctx 2498 { 2499 u8 reserved0 /* cdu_validation */; 2500 u8 state_and_core_id /* state_and_core_id */; 2501 u8 flags0; 2502 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2503 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 2504 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 2505 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1 2506 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 2507 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2 2508 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 2509 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 2510 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 2511 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4 2512 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 2513 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5 2514 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 2515 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6 2516 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 2517 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7 2518 u8 flags1; 2519 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 2520 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0 2521 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 2522 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1 2523 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 2524 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2 2525 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 2526 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3 2527 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 2528 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4 2529 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 2530 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5 2531 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1 /* bit14 */ 2532 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6 2533 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 2534 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 2535 u8 flags2; 2536 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2537 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0 2538 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2539 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2 2540 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2541 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4 2542 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2543 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6 2544 u8 flags3; 2545 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3 /* cf4 */ 2546 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0 2547 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* cf5 */ 2548 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 2549 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3 /* cf6 */ 2550 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4 2551 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 2552 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 2553 u8 flags4; 2554 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 2555 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0 2556 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 2557 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2 2558 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 2559 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4 2560 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 2561 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6 2562 u8 flags5; 2563 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 2564 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0 2565 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 2566 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2 2567 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 2568 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4 2569 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 2570 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6 2571 u8 flags6; 2572 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 2573 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0 2574 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 2575 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2 2576 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 2577 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4 2578 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */ 2579 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6 2580 u8 flags7; 2581 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */ 2582 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0 2583 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */ 2584 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2 2585 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 2586 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 2587 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2588 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6 2589 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2590 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7 2591 u8 flags8; 2592 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2593 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0 2594 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2595 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1 2596 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1 /* cf4en */ 2597 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2 2598 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */ 2599 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 2600 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1 /* cf6en */ 2601 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4 2602 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 2603 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 2604 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 2605 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6 2606 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 2607 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7 2608 u8 flags9; 2609 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 2610 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0 2611 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 2612 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1 2613 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 2614 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2 2615 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 2616 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3 2617 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 2618 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4 2619 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 2620 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5 2621 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 2622 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6 2623 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 2624 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7 2625 u8 flags10; 2626 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 2627 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0 2628 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */ 2629 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1 2630 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */ 2631 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2 2632 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */ 2633 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3 2634 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 2635 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 2636 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 2637 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5 2638 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2639 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6 2640 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2641 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7 2642 u8 flags11; 2643 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2644 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0 2645 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2646 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1 2647 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2648 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2 2649 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2650 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3 2651 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2652 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4 2653 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2654 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5 2655 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 2656 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 2657 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 2658 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7 2659 u8 flags12; 2660 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 2661 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_SHIFT 0 2662 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1 /* rule11en */ 2663 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 1 2664 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 2665 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 2666 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 2667 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 2668 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 2669 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4 2670 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 2671 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5 2672 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 2673 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6 2674 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 2675 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7 2676 u8 flags13; 2677 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 2678 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0 2679 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 2680 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1 2681 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 2682 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 2683 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 2684 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 2685 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 2686 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 2687 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 2688 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 2689 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 2690 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 2691 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 2692 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 2693 u8 flags14; 2694 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 2695 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0 2696 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 2697 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1 2698 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */ 2699 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2 2700 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */ 2701 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3 2702 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */ 2703 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4 2704 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */ 2705 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5 2706 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 2707 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6 2708 u8 byte2 /* byte2 */; 2709 __le16 physical_q0 /* physical_q0 */; 2710 __le16 word1 /* physical_q1 */; 2711 __le16 irq_prod /* physical_q2 */; 2712 __le16 word3 /* word3 */; 2713 __le16 word4 /* word4 */; 2714 __le16 ack_cons /* word5 */; 2715 __le16 irq_cons /* conn_dpi */; 2716 u8 rxmit_opcode /* byte3 */; 2717 u8 byte4 /* byte4 */; 2718 u8 byte5 /* byte5 */; 2719 u8 byte6 /* byte6 */; 2720 __le32 rxmit_psn_and_id /* reg0 */; 2721 __le32 rxmit_bytes_length /* reg1 */; 2722 __le32 psn /* reg2 */; 2723 __le32 reg3 /* reg3 */; 2724 __le32 reg4 /* reg4 */; 2725 __le32 reg5 /* cf_array0 */; 2726 __le32 msn_and_syndrome /* cf_array1 */; 2727 }; 2728 2729 2730 struct e5_ystorm_roce_req_conn_ag_ctx 2731 { 2732 u8 byte0 /* cdu_validation */; 2733 u8 byte1 /* state_and_core_id */; 2734 u8 flags0; 2735 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2736 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 2737 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2738 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 2739 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2740 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 2741 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2742 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 2743 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2744 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 2745 u8 flags1; 2746 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2747 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 2748 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2749 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 2750 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2751 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 2752 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2753 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 2754 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2755 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 2756 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2757 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 2758 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2759 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 2760 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2761 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 2762 u8 byte2 /* byte2 */; 2763 u8 byte3 /* byte3 */; 2764 __le16 word0 /* word0 */; 2765 __le32 reg0 /* reg0 */; 2766 __le32 reg1 /* reg1 */; 2767 __le16 word1 /* word1 */; 2768 __le16 word2 /* word2 */; 2769 __le16 word3 /* word3 */; 2770 __le16 word4 /* word4 */; 2771 __le32 reg2 /* reg2 */; 2772 __le32 reg3 /* reg3 */; 2773 }; 2774 2775 2776 struct e5_ystorm_roce_resp_conn_ag_ctx 2777 { 2778 u8 byte0 /* cdu_validation */; 2779 u8 byte1 /* state_and_core_id */; 2780 u8 flags0; 2781 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2782 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 2783 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2784 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 2785 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2786 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 2787 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2788 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 2789 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2790 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 2791 u8 flags1; 2792 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2793 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 2794 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2795 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 2796 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2797 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 2798 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2799 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 2800 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2801 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 2802 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2803 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 2804 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2805 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 2806 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2807 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 2808 u8 byte2 /* byte2 */; 2809 u8 byte3 /* byte3 */; 2810 __le16 word0 /* word0 */; 2811 __le32 reg0 /* reg0 */; 2812 __le32 reg1 /* reg1 */; 2813 __le16 word1 /* word1 */; 2814 __le16 word2 /* word2 */; 2815 __le16 word3 /* word3 */; 2816 __le16 word4 /* word4 */; 2817 __le32 reg2 /* reg2 */; 2818 __le32 reg3 /* reg3 */; 2819 }; 2820 2821 2822 /* 2823 * Roce doorbell data 2824 */ 2825 enum roce_flavor 2826 { 2827 PLAIN_ROCE /* RoCE v1 */, 2828 RROCE_IPV4 /* RoCE v2 (Routable RoCE) over ipv4 */, 2829 RROCE_IPV6 /* RoCE v2 (Routable RoCE) over ipv6 */, 2830 MAX_ROCE_FLAVOR 2831 }; 2832 2833 #endif /* __ECORE_HSI_ROCE__ */ 2834