1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef _INIT_FW_FUNCS_H 32 #define _INIT_FW_FUNCS_H 33 /* Forward declarations */ 34 35 struct init_qm_pq_params; 36 37 /** 38 * @brief ecore_qm_pf_mem_size - Prepare QM ILT sizes 39 * 40 * Returns the required host memory size in 4KB units. 41 * Must be called before all QM init HSI functions. 42 * 43 * @param num_pf_cids - number of connections used by this PF 44 * @param num_vf_cids - number of connections used by VFs of this PF 45 * @param num_tids - number of tasks used by this PF 46 * @param num_pf_pqs - number of PQs used by this PF 47 * @param num_vf_pqs - number of PQs used by VFs of this PF 48 * 49 * @return The required host memory size in 4KB units. 50 */ 51 u32 ecore_qm_pf_mem_size(u32 num_pf_cids, 52 u32 num_vf_cids, 53 u32 num_tids, 54 u16 num_pf_pqs, 55 u16 num_vf_pqs); 56 57 /** 58 * @brief ecore_qm_common_rt_init - Prepare QM runtime init values for the 59 * engine phase. 60 * 61 * @param p_hwfn - HW device data 62 * @param max_ports_per_engine - max number of ports per engine in HW 63 * @param max_phys_tcs_per_port - max number of physical TCs per port in HW 64 * @param pf_rl_en - enable per-PF rate limiters 65 * @param pf_wfq_en - enable per-PF WFQ 66 * @param vport_rl_en - enable per-VPORT rate limiters 67 * @param vport_wfq_en - enable per-VPORT WFQ 68 * @param port_params - array of size MAX_NUM_PORTS with parameters 69 * for each port 70 * 71 * @return 0 on success, -1 on error. 72 */ 73 int ecore_qm_common_rt_init(struct ecore_hwfn *p_hwfn, 74 u8 max_ports_per_engine, 75 u8 max_phys_tcs_per_port, 76 bool pf_rl_en, 77 bool pf_wfq_en, 78 bool vport_rl_en, 79 bool vport_wfq_en, 80 struct init_qm_port_params port_params[MAX_NUM_PORTS]); 81 82 /** 83 * @brief ecore_qm_pf_rt_init - Prepare QM runtime init values for the PF phase 84 * 85 * @param p_hwfn - HW device data 86 * @param p_ptt - ptt window used for writing the registers 87 * @param port_id - port ID 88 * @param pf_id - PF ID 89 * @param max_phys_tcs_per_port - max number of physical TCs per port in HW 90 * @param num_pf_cids - number of connections used by this PF 91 * @param num_vf_cids - number of connections used by VFs of this PF 92 * @param num_tids - number of tasks used by this PF 93 * @param start_pq - first Tx PQ ID associated with this PF 94 * @param num_pf_pqs - number of Tx PQs associated with this PF 95 * (non-VF) 96 * @param num_vf_pqs - number of Tx PQs associated with a VF 97 * @param start_vport - first VPORT ID associated with this PF 98 * @param num_vports - number of VPORTs associated with this PF 99 * @param pf_wfq - WFQ weight. if PF WFQ is globally disabled, 100 * the weight must be 0. otherwise, the weight 101 * must be non-zero. 102 * @param pf_rl - rate limit in Mb/sec units. a value of 0 103 * means don't configure. ignored if PF RL is 104 * globally disabled. 105 * @param pq_params - array of size (num_pf_pqs + num_vf_pqs) with 106 * parameters for each Tx PQ associated with the 107 * specified PF. 108 * @param vport_params - array of size num_vports with parameters for 109 * each associated VPORT. 110 * 111 * @return 0 on success, -1 on error. 112 */ 113 int ecore_qm_pf_rt_init(struct ecore_hwfn *p_hwfn, 114 struct ecore_ptt *p_ptt, 115 u8 port_id, 116 u8 pf_id, 117 u8 max_phys_tcs_per_port, 118 u32 num_pf_cids, 119 u32 num_vf_cids, 120 u32 num_tids, 121 u16 start_pq, 122 u16 num_pf_pqs, 123 u16 num_vf_pqs, 124 u8 start_vport, 125 u8 num_vports, 126 u16 pf_wfq, 127 u32 pf_rl, 128 struct init_qm_pq_params *pq_params, 129 struct init_qm_vport_params *vport_params); 130 131 /** 132 * @brief ecore_init_pf_wfq - Initializes the WFQ weight of the specified PF 133 * 134 * @param p_hwfn - HW device data 135 * @param p_ptt - ptt window used for writing the registers 136 * @param pf_id - PF ID 137 * @param pf_wfq - WFQ weight. Must be non-zero. 138 * 139 * @return 0 on success, -1 on error. 140 */ 141 int ecore_init_pf_wfq(struct ecore_hwfn *p_hwfn, 142 struct ecore_ptt *p_ptt, 143 u8 pf_id, 144 u16 pf_wfq); 145 146 /** 147 * @brief ecore_init_pf_rl - Initializes the rate limit of the specified PF 148 * 149 * @param p_hwfn 150 * @param p_ptt - ptt window used for writing the registers 151 * @param pf_id - PF ID 152 * @param pf_rl - rate limit in Mb/sec units 153 * 154 * @return 0 on success, -1 on error. 155 */ 156 int ecore_init_pf_rl(struct ecore_hwfn *p_hwfn, 157 struct ecore_ptt *p_ptt, 158 u8 pf_id, 159 u32 pf_rl); 160 161 /** 162 * @brief ecore_init_vport_wfq - Initializes the WFQ weight of the specified VPORT 163 * 164 * @param p_hwfn - HW device data 165 * @param p_ptt - ptt window used for writing the registers 166 * @param first_tx_pq_id - An array containing the first Tx PQ ID associated 167 * with the VPORT for each TC. This array is filled by 168 * ecore_qm_pf_rt_init 169 * @param vport_wfq - WFQ weight. Must be non-zero. 170 * 171 * @return 0 on success, -1 on error. 172 */ 173 int ecore_init_vport_wfq(struct ecore_hwfn *p_hwfn, 174 struct ecore_ptt *p_ptt, 175 u16 first_tx_pq_id[NUM_OF_TCS], 176 u16 vport_wfq); 177 178 /** 179 * @brief ecore_init_vport_rl - Initializes the rate limit of the specified 180 * VPORT. 181 * 182 * @param p_hwfn - HW device data 183 * @param p_ptt - ptt window used for writing the registers 184 * @param vport_id - VPORT ID 185 * @param vport_rl - rate limit in Mb/sec units 186 * 187 * @return 0 on success, -1 on error. 188 */ 189 int ecore_init_vport_rl(struct ecore_hwfn *p_hwfn, 190 struct ecore_ptt *p_ptt, 191 u8 vport_id, 192 u32 vport_rl); 193 194 /** 195 * @brief ecore_send_qm_stop_cmd - Sends a stop command to the QM 196 * 197 * @param p_hwfn - HW device data 198 * @param p_ptt - ptt window used for writing the registers 199 * @param is_release_cmd - true for release, false for stop. 200 * @param is_tx_pq - true for Tx PQs, false for Other PQs. 201 * @param start_pq - first PQ ID to stop 202 * @param num_pqs - Number of PQs to stop, starting from start_pq. 203 * 204 * @return bool, true if successful, false if timeout occured while waiting for 205 * QM command done. 206 */ 207 bool ecore_send_qm_stop_cmd(struct ecore_hwfn *p_hwfn, 208 struct ecore_ptt *p_ptt, 209 bool is_release_cmd, 210 bool is_tx_pq, 211 u16 start_pq, 212 u16 num_pqs); 213 214 #ifndef UNUSED_HSI_FUNC 215 216 /** 217 * @brief ecore_init_nig_ets - Initializes the NIG ETS arbiter 218 * 219 * Based on weight/priority requirements per-TC. 220 * 221 * @param p_hwfn - HW device data 222 * @param p_ptt - ptt window used for writing the registers. 223 * @param req - the NIG ETS initialization requirements. 224 * @param is_lb - if set, the loopback port arbiter is initialized, otherwise 225 * the physical port arbiter is initialized. The pure-LB TC 226 * requirements are ignored when is_lb is cleared. 227 */ 228 void ecore_init_nig_ets(struct ecore_hwfn *p_hwfn, 229 struct ecore_ptt *p_ptt, 230 struct init_ets_req* req, 231 bool is_lb); 232 233 /** 234 * @brief ecore_init_nig_lb_rl - Initializes the NIG LB RLs 235 * 236 * Based on global and per-TC rate requirements 237 * 238 * @param p_hwfn - HW device data 239 * @param p_ptt - ptt window used for writing the registers. 240 * @param req - the NIG LB RLs initialization requirements. 241 */ 242 void ecore_init_nig_lb_rl(struct ecore_hwfn *p_hwfn, 243 struct ecore_ptt *p_ptt, 244 struct init_nig_lb_rl_req* req); 245 246 #endif /* UNUSED_HSI_FUNC */ 247 248 /** 249 * @brief ecore_init_nig_pri_tc_map - Initializes the NIG priority to TC map. 250 * 251 * Assumes valid arguments. 252 * 253 * @param p_hwfn - HW device data 254 * @param p_ptt - ptt window used for writing the registers. 255 * @param req - required mapping from prioirties to TCs. 256 */ 257 void ecore_init_nig_pri_tc_map(struct ecore_hwfn *p_hwfn, 258 struct ecore_ptt *p_ptt, 259 struct init_nig_pri_tc_map_req* req); 260 261 #ifndef UNUSED_HSI_FUNC 262 263 /** 264 * @brief ecore_init_prs_ets - Initializes the PRS Rx ETS arbiter 265 * 266 * Based on weight/priority requirements per-TC. 267 * 268 * @param p_hwfn - HW device data 269 * @param p_ptt - ptt window used for writing the registers. 270 * @param req - the PRS ETS initialization requirements. 271 */ 272 void ecore_init_prs_ets(struct ecore_hwfn *p_hwfn, 273 struct ecore_ptt *p_ptt, 274 struct init_ets_req* req); 275 276 #endif /* UNUSED_HSI_FUNC */ 277 #ifndef UNUSED_HSI_FUNC 278 279 /** 280 * @brief ecore_init_brb_ram - Initializes BRB RAM sizes per TC. 281 * 282 * Based on weight/priority requirements per-TC. 283 * 284 * @param p_hwfn - HW device data 285 * @param p_ptt - ptt window used for writing the registers. 286 * @param req - the BRB RAM initialization requirements. 287 */ 288 void ecore_init_brb_ram(struct ecore_hwfn *p_hwfn, 289 struct ecore_ptt *p_ptt, 290 struct init_brb_ram_req* req); 291 292 #endif /* UNUSED_HSI_FUNC */ 293 #ifndef UNUSED_HSI_FUNC 294 295 /** 296 * @brief ecore_set_engine_mf_ovlan_eth_type - Initializes Nig,Prs,Pbf and llh 297 * ethType Regs to input ethType. Should Be called once per engine if engine 298 * is in BD mode. 299 * 300 * @param p_hwfn - HW device data 301 * @param ethType - etherType to configure 302 */ 303 void ecore_set_engine_mf_ovlan_eth_type(struct ecore_hwfn *p_hwfn, u32 ethType); 304 305 /** 306 * @brief ecore_set_port_mf_ovlan_eth_type - initializes DORQ ethType Regs to 307 * input ethType. should Be called once per port. 308 * 309 * @param p_hwfn - HW device data 310 * @param ethType - etherType to configure 311 */ 312 void ecore_set_port_mf_ovlan_eth_type(struct ecore_hwfn *p_hwfn, u32 ethType); 313 314 #endif /* UNUSED_HSI_FUNC */ 315 316 /** 317 * @brief ecore_set_vxlan_dest_port - Initializes vxlan tunnel destination udp 318 * port. 319 * 320 * @param p_hwfn - HW device data 321 * @param p_ptt - ptt window used for writing the registers. 322 * @param dest_port - vxlan destination udp port. 323 */ 324 void ecore_set_vxlan_dest_port(struct ecore_hwfn *p_hwfn, 325 struct ecore_ptt *p_ptt, 326 u16 dest_port); 327 328 /** 329 * @brief ecore_set_vxlan_enable - Enable or disable VXLAN tunnel in HW 330 * 331 * @param p_hwfn - HW device data 332 * @param p_ptt - ptt window used for writing the registers. 333 * @param vxlan_enable - vxlan enable flag. 334 */ 335 void ecore_set_vxlan_enable(struct ecore_hwfn *p_hwfn, 336 struct ecore_ptt *p_ptt, 337 bool vxlan_enable); 338 339 /** 340 * @brief ecore_set_gre_enable - Enable or disable GRE tunnel in HW 341 * 342 * @param p_hwfn - HW device data 343 * @param p_ptt - ptt window used for writing the registers. 344 * @param eth_gre_enable - eth GRE enable enable flag. 345 * @param ip_gre_enable - IP GRE enable enable flag. 346 */ 347 void ecore_set_gre_enable(struct ecore_hwfn *p_hwfn, 348 struct ecore_ptt *p_ptt, 349 bool eth_gre_enable, 350 bool ip_gre_enable); 351 352 /** 353 * @brief ecore_set_geneve_dest_port - Initializes geneve tunnel destination 354 * udp port. 355 * 356 * @param p_hwfn - HW device data 357 * @param p_ptt - ptt window used for writing the registers. 358 * @param dest_port - geneve destination udp port. 359 */ 360 void ecore_set_geneve_dest_port(struct ecore_hwfn *p_hwfn, 361 struct ecore_ptt *p_ptt, 362 u16 dest_port); 363 364 /** 365 * @brief ecore_set_geneve_enable - Enable or disable GRE tunnel in HW 366 * 367 * @param p_hwfn - HW device data 368 * @param p_ptt - ptt window used for writing the registers. 369 * @param eth_geneve_enable - eth GENEVE enable enable flag. 370 * @param ip_geneve_enable - IP GENEVE enable enable flag. 371 */ 372 void ecore_set_geneve_enable(struct ecore_hwfn *p_hwfn, 373 struct ecore_ptt *p_ptt, 374 bool eth_geneve_enable, 375 bool ip_geneve_enable); 376 377 #ifndef UNUSED_HSI_FUNC 378 379 /** 380 * @brief ecore_set_gft_event_id_cm_hdr - Configure GFT event id and cm header 381 * 382 * @param p_hwfn - HW device data 383 * @param p_ptt - ptt window used for writing the registers. 384 */ 385 void ecore_set_gft_event_id_cm_hdr(struct ecore_hwfn *p_hwfn, 386 struct ecore_ptt *p_ptt); 387 388 /** 389 * @brief ecore_set_rfs_mode_disable - Disable and configure HW for RFS 390 * 391 * @param p_hwfn - HW device data 392 * @param p_ptt - ptt window used for writing the registers. 393 * @param pf_id - pf on which to disable RFS. 394 */ 395 void ecore_set_rfs_mode_disable(struct ecore_hwfn *p_hwfn, 396 struct ecore_ptt *p_ptt, 397 u16 pf_id); 398 399 /** 400 * @brief ecore_set_rfs_mode_enable - Enable and configure HW for RFS 401 * 402 * @param p_hwfn - HW device data 403 * @param p_ptt - ptt window used for writing the registers. 404 * @param pf_id - pf on which to enable RFS. 405 * @param tcp - set profile tcp packets. 406 * @param udp - set profile udp packet. 407 * @param ipv4 - set profile ipv4 packet. 408 * @param ipv6 - set profile ipv6 packet. 409 */ 410 void ecore_set_rfs_mode_enable(struct ecore_hwfn *p_hwfn, 411 struct ecore_ptt *p_ptt, 412 u16 pf_id, 413 bool tcp, 414 bool udp, 415 bool ipv4, 416 bool ipv6); 417 418 #endif /* UNUSED_HSI_FUNC */ 419 420 /** 421 * @brief ecore_config_vf_zone_size_mode - Configure VF zone size mode. Must be 422 * used before first ETH queue started. 423 * 424 * @param p_hwfn - HW device data 425 * @param p_ptt - ptt window used for writing the registers. Don't care 426 * if runtime_init used. 427 * @param mode - VF zone size mode. Use enum vf_zone_size_mode. 428 * @param runtime_init - Set 1 to init runtime registers in engine phase. 429 * Set 0 if VF zone size mode configured after engine 430 * phase. 431 */ 432 void ecore_config_vf_zone_size_mode(struct ecore_hwfn *p_hwfn, 433 struct ecore_ptt *p_ptt, 434 u16 mode, 435 bool runtime_init); 436 437 /** 438 * @brief ecore_get_mstorm_queue_stat_offset - Get mstorm statistics offset by 439 * VF zone size mode. 440 * 441 * @param p_hwfn - HW device data 442 * @param stat_cnt_id - statistic counter id 443 * @param vf_zone_size_mode - VF zone size mode. Use enum vf_zone_size_mode. 444 */ 445 u32 ecore_get_mstorm_queue_stat_offset(struct ecore_hwfn *p_hwfn, 446 u16 stat_cnt_id, 447 u16 vf_zone_size_mode); 448 449 /** 450 * @brief ecore_get_mstorm_eth_vf_prods_offset - VF producer offset by VF zone 451 * size mode. 452 * 453 * @param p_hwfn - HW device data 454 * @param vf_id - vf id. 455 * @param vf_queue_id - per VF rx queue id. 456 * @param vf_zone_size_mode - vf zone size mode. Use enum vf_zone_size_mode. 457 */ 458 u32 ecore_get_mstorm_eth_vf_prods_offset(struct ecore_hwfn *p_hwfn, 459 u8 vf_id, 460 u8 vf_queue_id, 461 u16 vf_zone_size_mode); 462 463 /** 464 * @brief ecore_enable_context_validation - Enable and configure context 465 * validation. 466 * 467 * @param p_hwfn - HW device data 468 * @param p_ptt - ptt window used for writing the registers. 469 */ 470 void ecore_enable_context_validation(struct ecore_hwfn *p_hwfn, 471 struct ecore_ptt *p_ptt); 472 473 /** 474 * @brief ecore_calc_session_ctx_validation - Calcualte validation byte for 475 * session context. 476 * 477 * @param p_ctx_mem - pointer to context memory. 478 * @param ctx_size - context size. 479 * @param ctx_type - context type. 480 * @param cid - context cid. 481 */ 482 void ecore_calc_session_ctx_validation(void *p_ctx_mem, u16 ctx_size, 483 u8 ctx_type, u32 cid); 484 485 /** 486 * @brief ecore_calc_task_ctx_validation - Calcualte validation byte for task 487 * context. 488 * 489 * @param p_ctx_mem - pointer to context memory. 490 * @param ctx_size - context size. 491 * @param ctx_type - context type. 492 * @param tid - context tid. 493 */ 494 void ecore_calc_task_ctx_validation(void *p_ctx_mem, u16 ctx_size, u8 ctx_type, 495 u32 tid); 496 497 /** 498 * @brief ecore_memset_session_ctx - Memset session context to 0 while 499 * preserving validation bytes. 500 * 501 * @param p_hwfn - HW device data 502 * @param p_ctx_mem - pointer to context memory. 503 * @param ctx_size - size to initialzie. 504 * @param ctx_type - context type. 505 */ 506 void ecore_memset_session_ctx(void *p_ctx_mem, 507 u32 ctx_size, 508 u8 ctx_type); 509 510 /** 511 * @brief ecore_memset_task_ctx - Memset task context to 0 while preserving 512 * validation bytes. 513 * 514 * @param p_ctx_mem - pointer to context memory. 515 * @param ctx_size - size to initialzie. 516 * @param ctx_type - context type. 517 */ 518 void ecore_memset_task_ctx(void *p_ctx_mem, 519 u32 ctx_size, 520 u8 ctx_type); 521 522 #endif 523