111e25f0dSDavid C Somayajulu /* 211e25f0dSDavid C Somayajulu * Copyright (c) 2017-2018 Cavium, Inc. 311e25f0dSDavid C Somayajulu * All rights reserved. 411e25f0dSDavid C Somayajulu * 511e25f0dSDavid C Somayajulu * Redistribution and use in source and binary forms, with or without 611e25f0dSDavid C Somayajulu * modification, are permitted provided that the following conditions 711e25f0dSDavid C Somayajulu * are met: 811e25f0dSDavid C Somayajulu * 911e25f0dSDavid C Somayajulu * 1. Redistributions of source code must retain the above copyright 1011e25f0dSDavid C Somayajulu * notice, this list of conditions and the following disclaimer. 1111e25f0dSDavid C Somayajulu * 2. Redistributions in binary form must reproduce the above copyright 1211e25f0dSDavid C Somayajulu * notice, this list of conditions and the following disclaimer in the 1311e25f0dSDavid C Somayajulu * documentation and/or other materials provided with the distribution. 1411e25f0dSDavid C Somayajulu * 1511e25f0dSDavid C Somayajulu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 1611e25f0dSDavid C Somayajulu * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1711e25f0dSDavid C Somayajulu * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1811e25f0dSDavid C Somayajulu * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 1911e25f0dSDavid C Somayajulu * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2011e25f0dSDavid C Somayajulu * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2111e25f0dSDavid C Somayajulu * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2211e25f0dSDavid C Somayajulu * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2311e25f0dSDavid C Somayajulu * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2411e25f0dSDavid C Somayajulu * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2511e25f0dSDavid C Somayajulu * POSSIBILITY OF SUCH DAMAGE. 2611e25f0dSDavid C Somayajulu */ 2711e25f0dSDavid C Somayajulu /* 2811e25f0dSDavid C Somayajulu * File : ecore_int.c 2911e25f0dSDavid C Somayajulu */ 3011e25f0dSDavid C Somayajulu #include <sys/cdefs.h> 3111e25f0dSDavid C Somayajulu __FBSDID("$FreeBSD$"); 3211e25f0dSDavid C Somayajulu 3311e25f0dSDavid C Somayajulu #include "bcm_osal.h" 3411e25f0dSDavid C Somayajulu #include "ecore.h" 3511e25f0dSDavid C Somayajulu #include "ecore_spq.h" 3611e25f0dSDavid C Somayajulu #include "reg_addr.h" 3711e25f0dSDavid C Somayajulu #include "ecore_gtt_reg_addr.h" 3811e25f0dSDavid C Somayajulu #include "ecore_init_ops.h" 3911e25f0dSDavid C Somayajulu #include "ecore_rt_defs.h" 4011e25f0dSDavid C Somayajulu #include "ecore_int.h" 4111e25f0dSDavid C Somayajulu #include "reg_addr.h" 4211e25f0dSDavid C Somayajulu #include "ecore_hw.h" 4311e25f0dSDavid C Somayajulu #include "ecore_sriov.h" 4411e25f0dSDavid C Somayajulu #include "ecore_vf.h" 4511e25f0dSDavid C Somayajulu #include "ecore_hw_defs.h" 4611e25f0dSDavid C Somayajulu #include "ecore_hsi_common.h" 4711e25f0dSDavid C Somayajulu #include "ecore_mcp.h" 4811e25f0dSDavid C Somayajulu #include "ecore_dbg_fw_funcs.h" 4911e25f0dSDavid C Somayajulu 5011e25f0dSDavid C Somayajulu #ifdef DIAG 5111e25f0dSDavid C Somayajulu /* This is nasty, but diag is using the drv_dbg_fw_funcs.c [non-ecore flavor], 5211e25f0dSDavid C Somayajulu * and so the functions are lacking ecore prefix. 5311e25f0dSDavid C Somayajulu * If there would be other clients needing this [or if the content that isn't 5411e25f0dSDavid C Somayajulu * really optional there would increase], we'll need to re-think this. 5511e25f0dSDavid C Somayajulu */ 5611e25f0dSDavid C Somayajulu enum dbg_status dbg_read_attn(struct ecore_hwfn *dev, 5711e25f0dSDavid C Somayajulu struct ecore_ptt *ptt, 5811e25f0dSDavid C Somayajulu enum block_id block, 5911e25f0dSDavid C Somayajulu enum dbg_attn_type attn_type, 6011e25f0dSDavid C Somayajulu bool clear_status, 6111e25f0dSDavid C Somayajulu struct dbg_attn_block_result *results); 6211e25f0dSDavid C Somayajulu 6311e25f0dSDavid C Somayajulu enum dbg_status dbg_parse_attn(struct ecore_hwfn *dev, 6411e25f0dSDavid C Somayajulu struct dbg_attn_block_result *results); 6511e25f0dSDavid C Somayajulu 669efd0ba7SDavid C Somayajulu const char* dbg_get_status_str(enum dbg_status status); 679efd0ba7SDavid C Somayajulu 6811e25f0dSDavid C Somayajulu #define ecore_dbg_read_attn(hwfn, ptt, id, type, clear, results) \ 6911e25f0dSDavid C Somayajulu dbg_read_attn(hwfn, ptt, id, type, clear, results) 7011e25f0dSDavid C Somayajulu #define ecore_dbg_parse_attn(hwfn, results) \ 7111e25f0dSDavid C Somayajulu dbg_parse_attn(hwfn, results) 729efd0ba7SDavid C Somayajulu #define ecore_dbg_get_status_str(status) \ 739efd0ba7SDavid C Somayajulu dbg_get_status_str(status) 7411e25f0dSDavid C Somayajulu #endif 7511e25f0dSDavid C Somayajulu 7611e25f0dSDavid C Somayajulu struct ecore_pi_info { 7711e25f0dSDavid C Somayajulu ecore_int_comp_cb_t comp_cb; 7811e25f0dSDavid C Somayajulu void *cookie; /* Will be sent to the completion callback function */ 7911e25f0dSDavid C Somayajulu }; 8011e25f0dSDavid C Somayajulu 8111e25f0dSDavid C Somayajulu struct ecore_sb_sp_info { 8211e25f0dSDavid C Somayajulu struct ecore_sb_info sb_info; 8311e25f0dSDavid C Somayajulu /* per protocol index data */ 849efd0ba7SDavid C Somayajulu struct ecore_pi_info pi_info_arr[PIS_PER_SB_E4]; 8511e25f0dSDavid C Somayajulu }; 8611e25f0dSDavid C Somayajulu 8711e25f0dSDavid C Somayajulu enum ecore_attention_type { 8811e25f0dSDavid C Somayajulu ECORE_ATTN_TYPE_ATTN, 8911e25f0dSDavid C Somayajulu ECORE_ATTN_TYPE_PARITY, 9011e25f0dSDavid C Somayajulu }; 9111e25f0dSDavid C Somayajulu 9211e25f0dSDavid C Somayajulu #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \ 9311e25f0dSDavid C Somayajulu ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn) 9411e25f0dSDavid C Somayajulu 9511e25f0dSDavid C Somayajulu struct aeu_invert_reg_bit { 9611e25f0dSDavid C Somayajulu char bit_name[30]; 9711e25f0dSDavid C Somayajulu 9811e25f0dSDavid C Somayajulu #define ATTENTION_PARITY (1 << 0) 9911e25f0dSDavid C Somayajulu 10011e25f0dSDavid C Somayajulu #define ATTENTION_LENGTH_MASK (0x00000ff0) 10111e25f0dSDavid C Somayajulu #define ATTENTION_LENGTH_SHIFT (4) 10211e25f0dSDavid C Somayajulu #define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \ 10311e25f0dSDavid C Somayajulu ATTENTION_LENGTH_SHIFT) 10411e25f0dSDavid C Somayajulu #define ATTENTION_SINGLE (1 << ATTENTION_LENGTH_SHIFT) 10511e25f0dSDavid C Somayajulu #define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY) 10611e25f0dSDavid C Somayajulu #define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \ 10711e25f0dSDavid C Somayajulu ATTENTION_PARITY) 10811e25f0dSDavid C Somayajulu 10911e25f0dSDavid C Somayajulu /* Multiple bits start with this offset */ 11011e25f0dSDavid C Somayajulu #define ATTENTION_OFFSET_MASK (0x000ff000) 11111e25f0dSDavid C Somayajulu #define ATTENTION_OFFSET_SHIFT (12) 11211e25f0dSDavid C Somayajulu 11311e25f0dSDavid C Somayajulu #define ATTENTION_BB_MASK (0x00700000) 11411e25f0dSDavid C Somayajulu #define ATTENTION_BB_SHIFT (20) 11511e25f0dSDavid C Somayajulu #define ATTENTION_BB(value) (value << ATTENTION_BB_SHIFT) 11611e25f0dSDavid C Somayajulu #define ATTENTION_BB_DIFFERENT (1 << 23) 11711e25f0dSDavid C Somayajulu 11811e25f0dSDavid C Somayajulu #define ATTENTION_CLEAR_ENABLE (1 << 28) 11911e25f0dSDavid C Somayajulu unsigned int flags; 12011e25f0dSDavid C Somayajulu 12111e25f0dSDavid C Somayajulu /* Callback to call if attention will be triggered */ 12211e25f0dSDavid C Somayajulu enum _ecore_status_t (*cb)(struct ecore_hwfn *p_hwfn); 12311e25f0dSDavid C Somayajulu 12411e25f0dSDavid C Somayajulu enum block_id block_index; 12511e25f0dSDavid C Somayajulu }; 12611e25f0dSDavid C Somayajulu 12711e25f0dSDavid C Somayajulu struct aeu_invert_reg { 12811e25f0dSDavid C Somayajulu struct aeu_invert_reg_bit bits[32]; 12911e25f0dSDavid C Somayajulu }; 13011e25f0dSDavid C Somayajulu 13111e25f0dSDavid C Somayajulu #define MAX_ATTN_GRPS (8) 13211e25f0dSDavid C Somayajulu #define NUM_ATTN_REGS (9) 13311e25f0dSDavid C Somayajulu 13411e25f0dSDavid C Somayajulu static enum _ecore_status_t ecore_mcp_attn_cb(struct ecore_hwfn *p_hwfn) 13511e25f0dSDavid C Somayajulu { 13611e25f0dSDavid C Somayajulu u32 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE); 13711e25f0dSDavid C Somayajulu 13811e25f0dSDavid C Somayajulu DP_INFO(p_hwfn->p_dev, "MCP_REG_CPU_STATE: %08x - Masking...\n", 13911e25f0dSDavid C Somayajulu tmp); 14011e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 14111e25f0dSDavid C Somayajulu 0xffffffff); 14211e25f0dSDavid C Somayajulu 14311e25f0dSDavid C Somayajulu return ECORE_SUCCESS; 14411e25f0dSDavid C Somayajulu } 14511e25f0dSDavid C Somayajulu 14611e25f0dSDavid C Somayajulu #define ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK (0x3c000) 14711e25f0dSDavid C Somayajulu #define ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT (14) 14811e25f0dSDavid C Somayajulu #define ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK (0x03fc0) 14911e25f0dSDavid C Somayajulu #define ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT (6) 15011e25f0dSDavid C Somayajulu #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK (0x00020) 15111e25f0dSDavid C Somayajulu #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT (5) 15211e25f0dSDavid C Somayajulu #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK (0x0001e) 15311e25f0dSDavid C Somayajulu #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT (1) 15411e25f0dSDavid C Somayajulu #define ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK (0x1) 15511e25f0dSDavid C Somayajulu #define ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT (0) 15611e25f0dSDavid C Somayajulu #define ECORE_PSWHST_ATTENTION_VF_DISABLED (0x1) 15711e25f0dSDavid C Somayajulu #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1) 15811e25f0dSDavid C Somayajulu #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1) 15911e25f0dSDavid C Somayajulu #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0) 16011e25f0dSDavid C Somayajulu #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0x1e) 16111e25f0dSDavid C Somayajulu #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1) 16211e25f0dSDavid C Somayajulu #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK (0x20) 16311e25f0dSDavid C Somayajulu #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT (5) 16411e25f0dSDavid C Somayajulu #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK (0x3fc0) 16511e25f0dSDavid C Somayajulu #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT (6) 16611e25f0dSDavid C Somayajulu #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK (0x3c000) 16711e25f0dSDavid C Somayajulu #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT (14) 16811e25f0dSDavid C Somayajulu #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK (0x3fc0000) 16911e25f0dSDavid C Somayajulu #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT (18) 17011e25f0dSDavid C Somayajulu static enum _ecore_status_t ecore_pswhst_attn_cb(struct ecore_hwfn *p_hwfn) 17111e25f0dSDavid C Somayajulu { 17211e25f0dSDavid C Somayajulu u32 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, PSWHST_REG_VF_DISABLED_ERROR_VALID); 17311e25f0dSDavid C Somayajulu 17411e25f0dSDavid C Somayajulu /* Disabled VF access */ 17511e25f0dSDavid C Somayajulu if (tmp & ECORE_PSWHST_ATTENTION_VF_DISABLED) { 17611e25f0dSDavid C Somayajulu u32 addr, data; 17711e25f0dSDavid C Somayajulu 17811e25f0dSDavid C Somayajulu addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 17911e25f0dSDavid C Somayajulu PSWHST_REG_VF_DISABLED_ERROR_ADDRESS); 18011e25f0dSDavid C Somayajulu data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 18111e25f0dSDavid C Somayajulu PSWHST_REG_VF_DISABLED_ERROR_DATA); 18211e25f0dSDavid C Somayajulu DP_INFO(p_hwfn->p_dev, "PF[0x%02x] VF [0x%02x] [Valid 0x%02x] Client [0x%02x] Write [0x%02x] Addr [0x%08x]\n", 18311e25f0dSDavid C Somayajulu (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK) >> 18411e25f0dSDavid C Somayajulu ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT), 18511e25f0dSDavid C Somayajulu (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK) >> 18611e25f0dSDavid C Somayajulu ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT), 18711e25f0dSDavid C Somayajulu (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK) >> 18811e25f0dSDavid C Somayajulu ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT), 18911e25f0dSDavid C Somayajulu (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK) >> 19011e25f0dSDavid C Somayajulu ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT), 19111e25f0dSDavid C Somayajulu (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK) >> 19211e25f0dSDavid C Somayajulu ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT), 19311e25f0dSDavid C Somayajulu addr); 19411e25f0dSDavid C Somayajulu } 19511e25f0dSDavid C Somayajulu 19611e25f0dSDavid C Somayajulu tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 19711e25f0dSDavid C Somayajulu PSWHST_REG_INCORRECT_ACCESS_VALID); 19811e25f0dSDavid C Somayajulu if (tmp & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS) { 19911e25f0dSDavid C Somayajulu u32 addr, data, length; 20011e25f0dSDavid C Somayajulu 20111e25f0dSDavid C Somayajulu addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 20211e25f0dSDavid C Somayajulu PSWHST_REG_INCORRECT_ACCESS_ADDRESS); 20311e25f0dSDavid C Somayajulu data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 20411e25f0dSDavid C Somayajulu PSWHST_REG_INCORRECT_ACCESS_DATA); 20511e25f0dSDavid C Somayajulu length = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 20611e25f0dSDavid C Somayajulu PSWHST_REG_INCORRECT_ACCESS_LENGTH); 20711e25f0dSDavid C Somayajulu 20811e25f0dSDavid C Somayajulu DP_INFO(p_hwfn->p_dev, "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n", 20911e25f0dSDavid C Somayajulu addr, length, 21011e25f0dSDavid C Somayajulu (u8)((data & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK) >> 21111e25f0dSDavid C Somayajulu ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT), 21211e25f0dSDavid C Somayajulu (u8)((data & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK) >> 21311e25f0dSDavid C Somayajulu ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT), 21411e25f0dSDavid C Somayajulu (u8)((data & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK) >> 21511e25f0dSDavid C Somayajulu ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT), 21611e25f0dSDavid C Somayajulu (u8)((data & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK) >> 21711e25f0dSDavid C Somayajulu ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT), 21811e25f0dSDavid C Somayajulu (u8)((data & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK) >> 21911e25f0dSDavid C Somayajulu ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT), 22011e25f0dSDavid C Somayajulu (u8)((data & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK) >> 22111e25f0dSDavid C Somayajulu ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT), 22211e25f0dSDavid C Somayajulu data); 22311e25f0dSDavid C Somayajulu } 22411e25f0dSDavid C Somayajulu 22511e25f0dSDavid C Somayajulu /* TODO - We know 'some' of these are legal due to virtualization, 22611e25f0dSDavid C Somayajulu * but is it true for all of them? 22711e25f0dSDavid C Somayajulu */ 22811e25f0dSDavid C Somayajulu return ECORE_SUCCESS; 22911e25f0dSDavid C Somayajulu } 23011e25f0dSDavid C Somayajulu 23111e25f0dSDavid C Somayajulu #define ECORE_GRC_ATTENTION_VALID_BIT (1 << 0) 23211e25f0dSDavid C Somayajulu #define ECORE_GRC_ATTENTION_ADDRESS_MASK (0x7fffff << 0) 23311e25f0dSDavid C Somayajulu #define ECORE_GRC_ATTENTION_RDWR_BIT (1 << 23) 23411e25f0dSDavid C Somayajulu #define ECORE_GRC_ATTENTION_MASTER_MASK (0xf << 24) 23511e25f0dSDavid C Somayajulu #define ECORE_GRC_ATTENTION_MASTER_SHIFT (24) 23611e25f0dSDavid C Somayajulu #define ECORE_GRC_ATTENTION_PF_MASK (0xf) 23711e25f0dSDavid C Somayajulu #define ECORE_GRC_ATTENTION_VF_MASK (0xff << 4) 23811e25f0dSDavid C Somayajulu #define ECORE_GRC_ATTENTION_VF_SHIFT (4) 23911e25f0dSDavid C Somayajulu #define ECORE_GRC_ATTENTION_PRIV_MASK (0x3 << 14) 24011e25f0dSDavid C Somayajulu #define ECORE_GRC_ATTENTION_PRIV_SHIFT (14) 24111e25f0dSDavid C Somayajulu #define ECORE_GRC_ATTENTION_PRIV_VF (0) 24211e25f0dSDavid C Somayajulu static const char* grc_timeout_attn_master_to_str(u8 master) 24311e25f0dSDavid C Somayajulu { 24411e25f0dSDavid C Somayajulu switch(master) { 24511e25f0dSDavid C Somayajulu case 1: return "PXP"; 24611e25f0dSDavid C Somayajulu case 2: return "MCP"; 24711e25f0dSDavid C Somayajulu case 3: return "MSDM"; 24811e25f0dSDavid C Somayajulu case 4: return "PSDM"; 24911e25f0dSDavid C Somayajulu case 5: return "YSDM"; 25011e25f0dSDavid C Somayajulu case 6: return "USDM"; 25111e25f0dSDavid C Somayajulu case 7: return "TSDM"; 25211e25f0dSDavid C Somayajulu case 8: return "XSDM"; 25311e25f0dSDavid C Somayajulu case 9: return "DBU"; 25411e25f0dSDavid C Somayajulu case 10: return "DMAE"; 25511e25f0dSDavid C Somayajulu default: 2569efd0ba7SDavid C Somayajulu return "Unkown"; 25711e25f0dSDavid C Somayajulu } 25811e25f0dSDavid C Somayajulu } 25911e25f0dSDavid C Somayajulu 26011e25f0dSDavid C Somayajulu static enum _ecore_status_t ecore_grc_attn_cb(struct ecore_hwfn *p_hwfn) 26111e25f0dSDavid C Somayajulu { 26211e25f0dSDavid C Somayajulu u32 tmp, tmp2; 26311e25f0dSDavid C Somayajulu 26411e25f0dSDavid C Somayajulu /* We've already cleared the timeout interrupt register, so we learn 26511e25f0dSDavid C Somayajulu * of interrupts via the validity register 26611e25f0dSDavid C Somayajulu */ 26711e25f0dSDavid C Somayajulu tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 26811e25f0dSDavid C Somayajulu GRC_REG_TIMEOUT_ATTN_ACCESS_VALID); 26911e25f0dSDavid C Somayajulu if (!(tmp & ECORE_GRC_ATTENTION_VALID_BIT)) 27011e25f0dSDavid C Somayajulu goto out; 27111e25f0dSDavid C Somayajulu 27211e25f0dSDavid C Somayajulu /* Read the GRC timeout information */ 27311e25f0dSDavid C Somayajulu tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 27411e25f0dSDavid C Somayajulu GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0); 27511e25f0dSDavid C Somayajulu tmp2 = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 27611e25f0dSDavid C Somayajulu GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1); 27711e25f0dSDavid C Somayajulu 2789efd0ba7SDavid C Somayajulu DP_NOTICE(p_hwfn->p_dev, false, 27911e25f0dSDavid C Somayajulu "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n", 28011e25f0dSDavid C Somayajulu tmp2, tmp, 2819efd0ba7SDavid C Somayajulu (tmp & ECORE_GRC_ATTENTION_RDWR_BIT) ? "Write to" 2829efd0ba7SDavid C Somayajulu : "Read from", 28311e25f0dSDavid C Somayajulu (tmp & ECORE_GRC_ATTENTION_ADDRESS_MASK) << 2, 28411e25f0dSDavid C Somayajulu grc_timeout_attn_master_to_str((tmp & ECORE_GRC_ATTENTION_MASTER_MASK) >> 28511e25f0dSDavid C Somayajulu ECORE_GRC_ATTENTION_MASTER_SHIFT), 28611e25f0dSDavid C Somayajulu (tmp2 & ECORE_GRC_ATTENTION_PF_MASK), 28711e25f0dSDavid C Somayajulu (((tmp2 & ECORE_GRC_ATTENTION_PRIV_MASK) >> 28811e25f0dSDavid C Somayajulu ECORE_GRC_ATTENTION_PRIV_SHIFT) == 28911e25f0dSDavid C Somayajulu ECORE_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant:)", 29011e25f0dSDavid C Somayajulu (tmp2 & ECORE_GRC_ATTENTION_VF_MASK) >> 29111e25f0dSDavid C Somayajulu ECORE_GRC_ATTENTION_VF_SHIFT); 29211e25f0dSDavid C Somayajulu 29311e25f0dSDavid C Somayajulu out: 29411e25f0dSDavid C Somayajulu /* Regardles of anything else, clean the validity bit */ 29511e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, 29611e25f0dSDavid C Somayajulu GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0); 29711e25f0dSDavid C Somayajulu return ECORE_SUCCESS; 29811e25f0dSDavid C Somayajulu } 29911e25f0dSDavid C Somayajulu 30011e25f0dSDavid C Somayajulu #define ECORE_PGLUE_ATTENTION_VALID (1 << 29) 30111e25f0dSDavid C Somayajulu #define ECORE_PGLUE_ATTENTION_RD_VALID (1 << 26) 30211e25f0dSDavid C Somayajulu #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf << 20) 30311e25f0dSDavid C Somayajulu #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20) 30411e25f0dSDavid C Somayajulu #define ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID (1 << 19) 30511e25f0dSDavid C Somayajulu #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff << 24) 30611e25f0dSDavid C Somayajulu #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24) 30711e25f0dSDavid C Somayajulu #define ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR (1 << 21) 30811e25f0dSDavid C Somayajulu #define ECORE_PGLUE_ATTENTION_DETAILS2_BME (1 << 22) 30911e25f0dSDavid C Somayajulu #define ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN (1 << 23) 31011e25f0dSDavid C Somayajulu #define ECORE_PGLUE_ATTENTION_ICPL_VALID (1 << 23) 31111e25f0dSDavid C Somayajulu #define ECORE_PGLUE_ATTENTION_ZLR_VALID (1 << 25) 31211e25f0dSDavid C Somayajulu #define ECORE_PGLUE_ATTENTION_ILT_VALID (1 << 23) 31311e25f0dSDavid C Somayajulu static enum _ecore_status_t ecore_pglub_rbc_attn_cb(struct ecore_hwfn *p_hwfn) 31411e25f0dSDavid C Somayajulu { 31511e25f0dSDavid C Somayajulu u32 tmp; 31611e25f0dSDavid C Somayajulu 31711e25f0dSDavid C Somayajulu tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 31811e25f0dSDavid C Somayajulu PGLUE_B_REG_TX_ERR_WR_DETAILS2); 31911e25f0dSDavid C Somayajulu if (tmp & ECORE_PGLUE_ATTENTION_VALID) { 32011e25f0dSDavid C Somayajulu u32 addr_lo, addr_hi, details; 32111e25f0dSDavid C Somayajulu 32211e25f0dSDavid C Somayajulu addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 32311e25f0dSDavid C Somayajulu PGLUE_B_REG_TX_ERR_WR_ADD_31_0); 32411e25f0dSDavid C Somayajulu addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 32511e25f0dSDavid C Somayajulu PGLUE_B_REG_TX_ERR_WR_ADD_63_32); 32611e25f0dSDavid C Somayajulu details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 32711e25f0dSDavid C Somayajulu PGLUE_B_REG_TX_ERR_WR_DETAILS); 32811e25f0dSDavid C Somayajulu 32911e25f0dSDavid C Somayajulu DP_INFO(p_hwfn, "Illegal write by chip to [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 33011e25f0dSDavid C Somayajulu addr_hi, addr_lo, details, 33111e25f0dSDavid C Somayajulu (u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >> ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT), 33211e25f0dSDavid C Somayajulu (u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >> ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT), 33311e25f0dSDavid C Somayajulu (u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0), 33411e25f0dSDavid C Somayajulu tmp, 33511e25f0dSDavid C Somayajulu (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0), 33611e25f0dSDavid C Somayajulu (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0), 33711e25f0dSDavid C Somayajulu (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0)); 33811e25f0dSDavid C Somayajulu } 33911e25f0dSDavid C Somayajulu 34011e25f0dSDavid C Somayajulu tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 34111e25f0dSDavid C Somayajulu PGLUE_B_REG_TX_ERR_RD_DETAILS2); 34211e25f0dSDavid C Somayajulu if (tmp & ECORE_PGLUE_ATTENTION_RD_VALID) { 34311e25f0dSDavid C Somayajulu u32 addr_lo, addr_hi, details; 34411e25f0dSDavid C Somayajulu 34511e25f0dSDavid C Somayajulu addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 34611e25f0dSDavid C Somayajulu PGLUE_B_REG_TX_ERR_RD_ADD_31_0); 34711e25f0dSDavid C Somayajulu addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 34811e25f0dSDavid C Somayajulu PGLUE_B_REG_TX_ERR_RD_ADD_63_32); 34911e25f0dSDavid C Somayajulu details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 35011e25f0dSDavid C Somayajulu PGLUE_B_REG_TX_ERR_RD_DETAILS); 35111e25f0dSDavid C Somayajulu 35211e25f0dSDavid C Somayajulu DP_INFO(p_hwfn, "Illegal read by chip from [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 35311e25f0dSDavid C Somayajulu addr_hi, addr_lo, details, 35411e25f0dSDavid C Somayajulu (u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >> ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT), 35511e25f0dSDavid C Somayajulu (u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >> ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT), 35611e25f0dSDavid C Somayajulu (u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0), 35711e25f0dSDavid C Somayajulu tmp, 35811e25f0dSDavid C Somayajulu (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0), 35911e25f0dSDavid C Somayajulu (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0), 36011e25f0dSDavid C Somayajulu (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0)); 36111e25f0dSDavid C Somayajulu } 36211e25f0dSDavid C Somayajulu 36311e25f0dSDavid C Somayajulu tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 36411e25f0dSDavid C Somayajulu PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL); 36511e25f0dSDavid C Somayajulu if (tmp & ECORE_PGLUE_ATTENTION_ICPL_VALID) 36611e25f0dSDavid C Somayajulu DP_INFO(p_hwfn, "ICPL eror - %08x\n", tmp); 36711e25f0dSDavid C Somayajulu 36811e25f0dSDavid C Somayajulu tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 36911e25f0dSDavid C Somayajulu PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS); 37011e25f0dSDavid C Somayajulu if (tmp & ECORE_PGLUE_ATTENTION_ZLR_VALID) { 37111e25f0dSDavid C Somayajulu u32 addr_hi, addr_lo; 37211e25f0dSDavid C Somayajulu 37311e25f0dSDavid C Somayajulu addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 37411e25f0dSDavid C Somayajulu PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0); 37511e25f0dSDavid C Somayajulu addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 37611e25f0dSDavid C Somayajulu PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32); 37711e25f0dSDavid C Somayajulu 37811e25f0dSDavid C Somayajulu DP_INFO(p_hwfn, "ICPL eror - %08x [Address %08x:%08x]\n", 37911e25f0dSDavid C Somayajulu tmp, addr_hi, addr_lo); 38011e25f0dSDavid C Somayajulu } 38111e25f0dSDavid C Somayajulu 38211e25f0dSDavid C Somayajulu tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 38311e25f0dSDavid C Somayajulu PGLUE_B_REG_VF_ILT_ERR_DETAILS2); 38411e25f0dSDavid C Somayajulu if (tmp & ECORE_PGLUE_ATTENTION_ILT_VALID) { 38511e25f0dSDavid C Somayajulu u32 addr_hi, addr_lo, details; 38611e25f0dSDavid C Somayajulu 38711e25f0dSDavid C Somayajulu addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 38811e25f0dSDavid C Somayajulu PGLUE_B_REG_VF_ILT_ERR_ADD_31_0); 38911e25f0dSDavid C Somayajulu addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 39011e25f0dSDavid C Somayajulu PGLUE_B_REG_VF_ILT_ERR_ADD_63_32); 39111e25f0dSDavid C Somayajulu details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 39211e25f0dSDavid C Somayajulu PGLUE_B_REG_VF_ILT_ERR_DETAILS); 39311e25f0dSDavid C Somayajulu 39411e25f0dSDavid C Somayajulu DP_INFO(p_hwfn, "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n", 39511e25f0dSDavid C Somayajulu details, tmp, addr_hi, addr_lo); 39611e25f0dSDavid C Somayajulu } 39711e25f0dSDavid C Somayajulu 39811e25f0dSDavid C Somayajulu /* Clear the indications */ 39911e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, 40011e25f0dSDavid C Somayajulu PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2)); 40111e25f0dSDavid C Somayajulu 40211e25f0dSDavid C Somayajulu return ECORE_SUCCESS; 40311e25f0dSDavid C Somayajulu } 40411e25f0dSDavid C Somayajulu 40511e25f0dSDavid C Somayajulu static enum _ecore_status_t ecore_fw_assertion(struct ecore_hwfn *p_hwfn) 40611e25f0dSDavid C Somayajulu { 40711e25f0dSDavid C Somayajulu DP_NOTICE(p_hwfn, false, "FW assertion!\n"); 40811e25f0dSDavid C Somayajulu 40911e25f0dSDavid C Somayajulu ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FW_ASSERT); 41011e25f0dSDavid C Somayajulu 41111e25f0dSDavid C Somayajulu return ECORE_INVAL; 41211e25f0dSDavid C Somayajulu } 41311e25f0dSDavid C Somayajulu 41411e25f0dSDavid C Somayajulu static enum _ecore_status_t 41511e25f0dSDavid C Somayajulu ecore_general_attention_35(struct ecore_hwfn *p_hwfn) 41611e25f0dSDavid C Somayajulu { 41711e25f0dSDavid C Somayajulu DP_INFO(p_hwfn, "General attention 35!\n"); 41811e25f0dSDavid C Somayajulu 41911e25f0dSDavid C Somayajulu return ECORE_SUCCESS; 42011e25f0dSDavid C Somayajulu } 42111e25f0dSDavid C Somayajulu 42211e25f0dSDavid C Somayajulu #define ECORE_DORQ_ATTENTION_REASON_MASK (0xfffff) 42311e25f0dSDavid C Somayajulu #define ECORE_DORQ_ATTENTION_OPAQUE_MASK (0xffff) 4249efd0ba7SDavid C Somayajulu #define ECORE_DORQ_ATTENTION_OPAQUE_SHIFT (0x0) 4259efd0ba7SDavid C Somayajulu #define ECORE_DORQ_ATTENTION_SIZE_MASK (0x7f) 42611e25f0dSDavid C Somayajulu #define ECORE_DORQ_ATTENTION_SIZE_SHIFT (16) 42711e25f0dSDavid C Somayajulu 4289efd0ba7SDavid C Somayajulu #define ECORE_DB_REC_COUNT 10 4299efd0ba7SDavid C Somayajulu #define ECORE_DB_REC_INTERVAL 100 4309efd0ba7SDavid C Somayajulu 4319efd0ba7SDavid C Somayajulu /* assumes sticky overflow indication was set for this PF */ 4329efd0ba7SDavid C Somayajulu static enum _ecore_status_t ecore_db_rec_attn(struct ecore_hwfn *p_hwfn, 4339efd0ba7SDavid C Somayajulu struct ecore_ptt *p_ptt) 4349efd0ba7SDavid C Somayajulu { 4359efd0ba7SDavid C Somayajulu u8 count = ECORE_DB_REC_COUNT; 4369efd0ba7SDavid C Somayajulu u32 usage = 1; 4379efd0ba7SDavid C Somayajulu 4389efd0ba7SDavid C Somayajulu /* wait for usage to zero or count to run out. This is necessary since 4399efd0ba7SDavid C Somayajulu * EDPM doorbell transactions can take multiple 64b cycles, and as such 4409efd0ba7SDavid C Somayajulu * can "split" over the pci. Possibly, the doorbell drop can happen with 4419efd0ba7SDavid C Somayajulu * half an EDPM in the queue and other half dropped. Another EDPM 4429efd0ba7SDavid C Somayajulu * doorbell to the same address (from doorbell recovery mechanism or 4439efd0ba7SDavid C Somayajulu * from the doorbelling entity) could have first half dropped and second 4449efd0ba7SDavid C Somayajulu * half interperted as continuation of the first. To prevent such 4459efd0ba7SDavid C Somayajulu * malformed doorbells from reaching the device, flush the queue before 4469efd0ba7SDavid C Somayajulu * releaseing the overflow sticky indication. 4479efd0ba7SDavid C Somayajulu */ 4489efd0ba7SDavid C Somayajulu while (count-- && usage) { 4499efd0ba7SDavid C Somayajulu usage = ecore_rd(p_hwfn, p_ptt, DORQ_REG_PF_USAGE_CNT); 4509efd0ba7SDavid C Somayajulu OSAL_UDELAY(ECORE_DB_REC_INTERVAL); 4519efd0ba7SDavid C Somayajulu } 4529efd0ba7SDavid C Somayajulu 4539efd0ba7SDavid C Somayajulu /* should have been depleted by now */ 4549efd0ba7SDavid C Somayajulu if (usage) { 4559efd0ba7SDavid C Somayajulu DP_NOTICE(p_hwfn->p_dev, false, 4569efd0ba7SDavid C Somayajulu "DB recovery: doorbell usage failed to zero after %d usec. usage was %x\n", 4579efd0ba7SDavid C Somayajulu ECORE_DB_REC_INTERVAL * ECORE_DB_REC_COUNT, usage); 4589efd0ba7SDavid C Somayajulu return ECORE_TIMEOUT; 4599efd0ba7SDavid C Somayajulu } 4609efd0ba7SDavid C Somayajulu 4619efd0ba7SDavid C Somayajulu /* flush any pedning (e)dpm as they may never arrive */ 4629efd0ba7SDavid C Somayajulu ecore_wr(p_hwfn, p_ptt, DORQ_REG_DPM_FORCE_ABORT, 0x1); 4639efd0ba7SDavid C Somayajulu 4649efd0ba7SDavid C Somayajulu /* release overflow sticky indication (stop silently dropping everything) */ 4659efd0ba7SDavid C Somayajulu ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0); 4669efd0ba7SDavid C Somayajulu 4679efd0ba7SDavid C Somayajulu /* repeat all last doorbells (doorbell drop recovery) */ 4689efd0ba7SDavid C Somayajulu ecore_db_recovery_execute(p_hwfn, DB_REC_REAL_DEAL); 4699efd0ba7SDavid C Somayajulu 4709efd0ba7SDavid C Somayajulu return ECORE_SUCCESS; 4719efd0ba7SDavid C Somayajulu } 4729efd0ba7SDavid C Somayajulu 47311e25f0dSDavid C Somayajulu static enum _ecore_status_t ecore_dorq_attn_cb(struct ecore_hwfn *p_hwfn) 47411e25f0dSDavid C Somayajulu { 4759efd0ba7SDavid C Somayajulu u32 int_sts, first_drop_reason, details, address, overflow, 4769efd0ba7SDavid C Somayajulu all_drops_reason; 4779efd0ba7SDavid C Somayajulu struct ecore_ptt *p_ptt = p_hwfn->p_dpc_ptt; 4789efd0ba7SDavid C Somayajulu enum _ecore_status_t rc; 47911e25f0dSDavid C Somayajulu 4809efd0ba7SDavid C Somayajulu int_sts = ecore_rd(p_hwfn, p_ptt, DORQ_REG_INT_STS); 4819efd0ba7SDavid C Somayajulu DP_NOTICE(p_hwfn->p_dev, false, "DORQ attention. int_sts was %x\n", 4829efd0ba7SDavid C Somayajulu int_sts); 4839efd0ba7SDavid C Somayajulu 4849efd0ba7SDavid C Somayajulu /* check if db_drop or overflow happened */ 4859efd0ba7SDavid C Somayajulu if (int_sts & (DORQ_REG_INT_STS_DB_DROP | 4869efd0ba7SDavid C Somayajulu DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR)) { 4879efd0ba7SDavid C Somayajulu 4889efd0ba7SDavid C Somayajulu /* obtain data about db drop/overflow */ 4899efd0ba7SDavid C Somayajulu first_drop_reason = ecore_rd(p_hwfn, p_ptt, 4909efd0ba7SDavid C Somayajulu DORQ_REG_DB_DROP_REASON) & 49111e25f0dSDavid C Somayajulu ECORE_DORQ_ATTENTION_REASON_MASK; 4929efd0ba7SDavid C Somayajulu details = ecore_rd(p_hwfn, p_ptt, 49311e25f0dSDavid C Somayajulu DORQ_REG_DB_DROP_DETAILS); 4949efd0ba7SDavid C Somayajulu address = ecore_rd(p_hwfn, p_ptt, 4959efd0ba7SDavid C Somayajulu DORQ_REG_DB_DROP_DETAILS_ADDRESS); 4969efd0ba7SDavid C Somayajulu overflow = ecore_rd(p_hwfn, p_ptt, 4979efd0ba7SDavid C Somayajulu DORQ_REG_PF_OVFL_STICKY); 4989efd0ba7SDavid C Somayajulu all_drops_reason = ecore_rd(p_hwfn, p_ptt, 4999efd0ba7SDavid C Somayajulu DORQ_REG_DB_DROP_DETAILS_REASON); 50011e25f0dSDavid C Somayajulu 5019efd0ba7SDavid C Somayajulu /* log info */ 5029efd0ba7SDavid C Somayajulu DP_NOTICE(p_hwfn->p_dev, false, 5039efd0ba7SDavid C Somayajulu "Doorbell drop occurred\n" 5049efd0ba7SDavid C Somayajulu "Address\t\t0x%08x\t(second BAR address)\n" 5059efd0ba7SDavid C Somayajulu "FID\t\t0x%04x\t\t(Opaque FID)\n" 5069efd0ba7SDavid C Somayajulu "Size\t\t0x%04x\t\t(in bytes)\n" 5079efd0ba7SDavid C Somayajulu "1st drop reason\t0x%08x\t(details on first drop since last handling)\n" 5089efd0ba7SDavid C Somayajulu "Sticky reasons\t0x%08x\t(all drop reasons since last handling)\n" 5099efd0ba7SDavid C Somayajulu "Overflow\t0x%x\t\t(a per PF indication)\n", 5109efd0ba7SDavid C Somayajulu address, GET_FIELD(details, ECORE_DORQ_ATTENTION_OPAQUE), 5119efd0ba7SDavid C Somayajulu GET_FIELD(details, ECORE_DORQ_ATTENTION_SIZE) * 4, 5129efd0ba7SDavid C Somayajulu first_drop_reason, all_drops_reason, overflow); 5139efd0ba7SDavid C Somayajulu 5149efd0ba7SDavid C Somayajulu /* if this PF caused overflow, initiate recovery */ 5159efd0ba7SDavid C Somayajulu if (overflow) { 5169efd0ba7SDavid C Somayajulu rc = ecore_db_rec_attn(p_hwfn, p_ptt); 5179efd0ba7SDavid C Somayajulu if (rc != ECORE_SUCCESS) 5189efd0ba7SDavid C Somayajulu return rc; 51911e25f0dSDavid C Somayajulu } 52011e25f0dSDavid C Somayajulu 5219efd0ba7SDavid C Somayajulu /* clear the doorbell drop details and prepare for next drop */ 5229efd0ba7SDavid C Somayajulu ecore_wr(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS_REL, 0); 5239efd0ba7SDavid C Somayajulu 5249efd0ba7SDavid C Somayajulu /* mark interrupt as handeld (note: even if drop was due to a diffrent 5259efd0ba7SDavid C Somayajulu * reason than overflow we mark as handled) 5269efd0ba7SDavid C Somayajulu */ 5279efd0ba7SDavid C Somayajulu ecore_wr(p_hwfn, p_ptt, DORQ_REG_INT_STS_WR, 5289efd0ba7SDavid C Somayajulu DORQ_REG_INT_STS_DB_DROP | DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR); 5299efd0ba7SDavid C Somayajulu 5309efd0ba7SDavid C Somayajulu /* if there are no indications otherthan drop indications, success */ 5319efd0ba7SDavid C Somayajulu if ((int_sts & ~(DORQ_REG_INT_STS_DB_DROP | 5329efd0ba7SDavid C Somayajulu DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR | 5339efd0ba7SDavid C Somayajulu DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) == 0) 5349efd0ba7SDavid C Somayajulu return ECORE_SUCCESS; 5359efd0ba7SDavid C Somayajulu } 5369efd0ba7SDavid C Somayajulu 5379efd0ba7SDavid C Somayajulu /* some other indication was present - non recoverable */ 5389efd0ba7SDavid C Somayajulu DP_INFO(p_hwfn, "DORQ fatal attention\n"); 5399efd0ba7SDavid C Somayajulu 54011e25f0dSDavid C Somayajulu return ECORE_INVAL; 54111e25f0dSDavid C Somayajulu } 54211e25f0dSDavid C Somayajulu 54311e25f0dSDavid C Somayajulu static enum _ecore_status_t ecore_tm_attn_cb(struct ecore_hwfn *p_hwfn) 54411e25f0dSDavid C Somayajulu { 54511e25f0dSDavid C Somayajulu #ifndef ASIC_ONLY 54611e25f0dSDavid C Somayajulu if (CHIP_REV_IS_EMUL_B0(p_hwfn->p_dev)) { 54711e25f0dSDavid C Somayajulu u32 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 54811e25f0dSDavid C Somayajulu TM_REG_INT_STS_1); 54911e25f0dSDavid C Somayajulu 55011e25f0dSDavid C Somayajulu if (val & ~(TM_REG_INT_STS_1_PEND_TASK_SCAN | 55111e25f0dSDavid C Somayajulu TM_REG_INT_STS_1_PEND_CONN_SCAN)) 55211e25f0dSDavid C Somayajulu return ECORE_INVAL; 55311e25f0dSDavid C Somayajulu 55411e25f0dSDavid C Somayajulu if (val & (TM_REG_INT_STS_1_PEND_TASK_SCAN | 55511e25f0dSDavid C Somayajulu TM_REG_INT_STS_1_PEND_CONN_SCAN)) 55611e25f0dSDavid C Somayajulu DP_INFO(p_hwfn, "TM attention on emulation - most likely results of clock-ratios\n"); 55711e25f0dSDavid C Somayajulu val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1); 55811e25f0dSDavid C Somayajulu val |= TM_REG_INT_MASK_1_PEND_CONN_SCAN | 55911e25f0dSDavid C Somayajulu TM_REG_INT_MASK_1_PEND_TASK_SCAN; 56011e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1, val); 56111e25f0dSDavid C Somayajulu 56211e25f0dSDavid C Somayajulu return ECORE_SUCCESS; 56311e25f0dSDavid C Somayajulu } 56411e25f0dSDavid C Somayajulu #endif 56511e25f0dSDavid C Somayajulu 56611e25f0dSDavid C Somayajulu return ECORE_INVAL; 56711e25f0dSDavid C Somayajulu } 56811e25f0dSDavid C Somayajulu 56911e25f0dSDavid C Somayajulu /* Instead of major changes to the data-structure, we have a some 'special' 57011e25f0dSDavid C Somayajulu * identifiers for sources that changed meaning between adapters. 57111e25f0dSDavid C Somayajulu */ 57211e25f0dSDavid C Somayajulu enum aeu_invert_reg_special_type { 57311e25f0dSDavid C Somayajulu AEU_INVERT_REG_SPECIAL_CNIG_0, 57411e25f0dSDavid C Somayajulu AEU_INVERT_REG_SPECIAL_CNIG_1, 57511e25f0dSDavid C Somayajulu AEU_INVERT_REG_SPECIAL_CNIG_2, 57611e25f0dSDavid C Somayajulu AEU_INVERT_REG_SPECIAL_CNIG_3, 57711e25f0dSDavid C Somayajulu AEU_INVERT_REG_SPECIAL_MAX, 57811e25f0dSDavid C Somayajulu }; 57911e25f0dSDavid C Somayajulu 58011e25f0dSDavid C Somayajulu static struct aeu_invert_reg_bit 58111e25f0dSDavid C Somayajulu aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = { 58211e25f0dSDavid C Somayajulu {"CNIG port 0", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG}, 58311e25f0dSDavid C Somayajulu {"CNIG port 1", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG}, 58411e25f0dSDavid C Somayajulu {"CNIG port 2", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG}, 58511e25f0dSDavid C Somayajulu {"CNIG port 3", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG}, 58611e25f0dSDavid C Somayajulu }; 58711e25f0dSDavid C Somayajulu 58811e25f0dSDavid C Somayajulu /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */ 58911e25f0dSDavid C Somayajulu static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = 59011e25f0dSDavid C Somayajulu { 59111e25f0dSDavid C Somayajulu { 59211e25f0dSDavid C Somayajulu { /* After Invert 1 */ 59311e25f0dSDavid C Somayajulu {"GPIO0 function%d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL, MAX_BLOCK_ID}, 59411e25f0dSDavid C Somayajulu } 59511e25f0dSDavid C Somayajulu }, 59611e25f0dSDavid C Somayajulu 59711e25f0dSDavid C Somayajulu { 59811e25f0dSDavid C Somayajulu { /* After Invert 2 */ 59911e25f0dSDavid C Somayajulu {"PGLUE config_space", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID}, 60011e25f0dSDavid C Somayajulu {"PGLUE misc_flr", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID}, 60111e25f0dSDavid C Somayajulu {"PGLUE B RBC", ATTENTION_PAR_INT, ecore_pglub_rbc_attn_cb, BLOCK_PGLUE_B}, 60211e25f0dSDavid C Somayajulu {"PGLUE misc_mctp", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID}, 60311e25f0dSDavid C Somayajulu {"Flash event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID}, 60411e25f0dSDavid C Somayajulu {"SMB event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID}, 60511e25f0dSDavid C Somayajulu {"Main Power", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID}, 60611e25f0dSDavid C Somayajulu {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) | (1 << ATTENTION_OFFSET_SHIFT), OSAL_NULL, MAX_BLOCK_ID}, 60711e25f0dSDavid C Somayajulu {"PCIE glue/PXP VPD %d", (16 << ATTENTION_LENGTH_SHIFT), OSAL_NULL, BLOCK_PGLCS}, 60811e25f0dSDavid C Somayajulu } 60911e25f0dSDavid C Somayajulu }, 61011e25f0dSDavid C Somayajulu 61111e25f0dSDavid C Somayajulu { 61211e25f0dSDavid C Somayajulu { /* After Invert 3 */ 61311e25f0dSDavid C Somayajulu {"General Attention %d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL, MAX_BLOCK_ID}, 61411e25f0dSDavid C Somayajulu } 61511e25f0dSDavid C Somayajulu }, 61611e25f0dSDavid C Somayajulu 61711e25f0dSDavid C Somayajulu { 61811e25f0dSDavid C Somayajulu { /* After Invert 4 */ 61911e25f0dSDavid C Somayajulu {"General Attention 32", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE, ecore_fw_assertion, MAX_BLOCK_ID}, 62011e25f0dSDavid C Somayajulu {"General Attention %d", (2 << ATTENTION_LENGTH_SHIFT) | (33 << ATTENTION_OFFSET_SHIFT), OSAL_NULL, MAX_BLOCK_ID}, 62111e25f0dSDavid C Somayajulu {"General Attention 35", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE, ecore_general_attention_35, MAX_BLOCK_ID}, 62211e25f0dSDavid C Somayajulu {"NWS Parity", ATTENTION_PAR | ATTENTION_BB_DIFFERENT | 62311e25f0dSDavid C Somayajulu ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0) , OSAL_NULL, BLOCK_NWS}, 62411e25f0dSDavid C Somayajulu {"NWS Interrupt", ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT | 62511e25f0dSDavid C Somayajulu ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1), OSAL_NULL, BLOCK_NWS}, 62611e25f0dSDavid C Somayajulu {"NWM Parity", ATTENTION_PAR | ATTENTION_BB_DIFFERENT | 62711e25f0dSDavid C Somayajulu ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2), OSAL_NULL, BLOCK_NWM}, 62811e25f0dSDavid C Somayajulu {"NWM Interrupt", ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT | 62911e25f0dSDavid C Somayajulu ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3), OSAL_NULL, BLOCK_NWM}, 63011e25f0dSDavid C Somayajulu {"MCP CPU", ATTENTION_SINGLE, ecore_mcp_attn_cb, MAX_BLOCK_ID}, 63111e25f0dSDavid C Somayajulu {"MCP Watchdog timer", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID}, 63211e25f0dSDavid C Somayajulu {"MCP M2P", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID}, 63311e25f0dSDavid C Somayajulu {"AVS stop status ready", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID}, 63411e25f0dSDavid C Somayajulu {"MSTAT", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID}, 63511e25f0dSDavid C Somayajulu {"MSTAT per-path", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID}, 63611e25f0dSDavid C Somayajulu {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), OSAL_NULL, MAX_BLOCK_ID }, 63711e25f0dSDavid C Somayajulu {"NIG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NIG}, 63811e25f0dSDavid C Somayajulu {"BMB/OPTE/MCP", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BMB}, 63911e25f0dSDavid C Somayajulu {"BTB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BTB}, 64011e25f0dSDavid C Somayajulu {"BRB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BRB}, 64111e25f0dSDavid C Somayajulu {"PRS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRS}, 64211e25f0dSDavid C Somayajulu } 64311e25f0dSDavid C Somayajulu }, 64411e25f0dSDavid C Somayajulu 64511e25f0dSDavid C Somayajulu { 64611e25f0dSDavid C Somayajulu { /* After Invert 5 */ 64711e25f0dSDavid C Somayajulu {"SRC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_SRC}, 64811e25f0dSDavid C Somayajulu {"PB Client1", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB1}, 64911e25f0dSDavid C Somayajulu {"PB Client2", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB2}, 65011e25f0dSDavid C Somayajulu {"RPB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RPB}, 65111e25f0dSDavid C Somayajulu {"PBF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF}, 65211e25f0dSDavid C Somayajulu {"QM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_QM}, 65311e25f0dSDavid C Somayajulu {"TM", ATTENTION_PAR_INT, ecore_tm_attn_cb, BLOCK_TM}, 65411e25f0dSDavid C Somayajulu {"MCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MCM}, 65511e25f0dSDavid C Somayajulu {"MSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSDM}, 65611e25f0dSDavid C Somayajulu {"MSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSEM}, 65711e25f0dSDavid C Somayajulu {"PCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PCM}, 65811e25f0dSDavid C Somayajulu {"PSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSDM}, 65911e25f0dSDavid C Somayajulu {"PSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSEM}, 66011e25f0dSDavid C Somayajulu {"TCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCM}, 66111e25f0dSDavid C Somayajulu {"TSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TSDM}, 66211e25f0dSDavid C Somayajulu {"TSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TSEM}, 66311e25f0dSDavid C Somayajulu } 66411e25f0dSDavid C Somayajulu }, 66511e25f0dSDavid C Somayajulu 66611e25f0dSDavid C Somayajulu { 66711e25f0dSDavid C Somayajulu { /* After Invert 6 */ 66811e25f0dSDavid C Somayajulu {"UCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_UCM}, 66911e25f0dSDavid C Somayajulu {"USDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USDM}, 67011e25f0dSDavid C Somayajulu {"USEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USEM}, 67111e25f0dSDavid C Somayajulu {"XCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XCM}, 67211e25f0dSDavid C Somayajulu {"XSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSDM}, 67311e25f0dSDavid C Somayajulu {"XSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSEM}, 67411e25f0dSDavid C Somayajulu {"YCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YCM}, 67511e25f0dSDavid C Somayajulu {"YSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSDM}, 67611e25f0dSDavid C Somayajulu {"YSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSEM}, 67711e25f0dSDavid C Somayajulu {"XYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XYLD}, 67811e25f0dSDavid C Somayajulu {"TMLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TMLD}, 67911e25f0dSDavid C Somayajulu {"MYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MULD}, 68011e25f0dSDavid C Somayajulu {"YULD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YULD}, 68111e25f0dSDavid C Somayajulu {"DORQ", ATTENTION_PAR_INT, ecore_dorq_attn_cb, BLOCK_DORQ}, 68211e25f0dSDavid C Somayajulu {"DBG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DBG}, 68311e25f0dSDavid C Somayajulu {"IPC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IPC}, 68411e25f0dSDavid C Somayajulu } 68511e25f0dSDavid C Somayajulu }, 68611e25f0dSDavid C Somayajulu 68711e25f0dSDavid C Somayajulu { 68811e25f0dSDavid C Somayajulu { /* After Invert 7 */ 68911e25f0dSDavid C Somayajulu {"CCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CCFC}, 69011e25f0dSDavid C Somayajulu {"CDU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CDU}, 69111e25f0dSDavid C Somayajulu {"DMAE", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DMAE}, 69211e25f0dSDavid C Somayajulu {"IGU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IGU}, 69311e25f0dSDavid C Somayajulu {"ATC", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID}, 69411e25f0dSDavid C Somayajulu {"CAU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CAU}, 69511e25f0dSDavid C Somayajulu {"PTU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PTU}, 69611e25f0dSDavid C Somayajulu {"PRM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRM}, 69711e25f0dSDavid C Somayajulu {"TCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCFC}, 69811e25f0dSDavid C Somayajulu {"RDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RDIF}, 69911e25f0dSDavid C Somayajulu {"TDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TDIF}, 70011e25f0dSDavid C Somayajulu {"RSS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RSS}, 70111e25f0dSDavid C Somayajulu {"MISC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISC}, 70211e25f0dSDavid C Somayajulu {"MISCS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISCS}, 70311e25f0dSDavid C Somayajulu {"PCIE", ATTENTION_PAR, OSAL_NULL, BLOCK_PCIE}, 70411e25f0dSDavid C Somayajulu {"Vaux PCI core", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS}, 70511e25f0dSDavid C Somayajulu {"PSWRQ", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ}, 70611e25f0dSDavid C Somayajulu } 70711e25f0dSDavid C Somayajulu }, 70811e25f0dSDavid C Somayajulu 70911e25f0dSDavid C Somayajulu { 71011e25f0dSDavid C Somayajulu { /* After Invert 8 */ 71111e25f0dSDavid C Somayajulu {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ2}, 71211e25f0dSDavid C Somayajulu {"PSWWR", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR}, 71311e25f0dSDavid C Somayajulu {"PSWWR (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR2}, 71411e25f0dSDavid C Somayajulu {"PSWRD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD}, 71511e25f0dSDavid C Somayajulu {"PSWRD (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD2}, 71611e25f0dSDavid C Somayajulu {"PSWHST", ATTENTION_PAR_INT, ecore_pswhst_attn_cb, BLOCK_PSWHST}, 71711e25f0dSDavid C Somayajulu {"PSWHST (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWHST2}, 71811e25f0dSDavid C Somayajulu {"GRC", ATTENTION_PAR_INT, ecore_grc_attn_cb, BLOCK_GRC}, 71911e25f0dSDavid C Somayajulu {"CPMU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CPMU}, 72011e25f0dSDavid C Somayajulu {"NCSI", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NCSI}, 72111e25f0dSDavid C Somayajulu {"MSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID}, 72211e25f0dSDavid C Somayajulu {"PSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID}, 72311e25f0dSDavid C Somayajulu {"TSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID}, 72411e25f0dSDavid C Somayajulu {"USEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID}, 72511e25f0dSDavid C Somayajulu {"XSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID}, 72611e25f0dSDavid C Somayajulu {"YSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID}, 72711e25f0dSDavid C Somayajulu {"pxp_misc_mps", ATTENTION_PAR, OSAL_NULL, BLOCK_PGLCS}, 72811e25f0dSDavid C Somayajulu {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS}, 72911e25f0dSDavid C Somayajulu {"PERST_B assertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID}, 73011e25f0dSDavid C Somayajulu {"PERST_B deassertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID}, 73111e25f0dSDavid C Somayajulu {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), OSAL_NULL, MAX_BLOCK_ID }, 73211e25f0dSDavid C Somayajulu } 73311e25f0dSDavid C Somayajulu }, 73411e25f0dSDavid C Somayajulu 73511e25f0dSDavid C Somayajulu { 73611e25f0dSDavid C Somayajulu { /* After Invert 9 */ 73711e25f0dSDavid C Somayajulu {"MCP Latched memory", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID}, 73811e25f0dSDavid C Somayajulu {"MCP Latched scratchpad cache", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID}, 73911e25f0dSDavid C Somayajulu {"MCP Latched ump_tx", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID}, 74011e25f0dSDavid C Somayajulu {"MCP Latched scratchpad", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID}, 74111e25f0dSDavid C Somayajulu {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), OSAL_NULL, MAX_BLOCK_ID }, 74211e25f0dSDavid C Somayajulu } 74311e25f0dSDavid C Somayajulu }, 74411e25f0dSDavid C Somayajulu 74511e25f0dSDavid C Somayajulu }; 74611e25f0dSDavid C Somayajulu 74711e25f0dSDavid C Somayajulu static struct aeu_invert_reg_bit * 74811e25f0dSDavid C Somayajulu ecore_int_aeu_translate(struct ecore_hwfn *p_hwfn, 74911e25f0dSDavid C Somayajulu struct aeu_invert_reg_bit *p_bit) 75011e25f0dSDavid C Somayajulu { 75111e25f0dSDavid C Somayajulu if (!ECORE_IS_BB(p_hwfn->p_dev)) 75211e25f0dSDavid C Somayajulu return p_bit; 75311e25f0dSDavid C Somayajulu 75411e25f0dSDavid C Somayajulu if (!(p_bit->flags & ATTENTION_BB_DIFFERENT)) 75511e25f0dSDavid C Somayajulu return p_bit; 75611e25f0dSDavid C Somayajulu 75711e25f0dSDavid C Somayajulu return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >> 75811e25f0dSDavid C Somayajulu ATTENTION_BB_SHIFT]; 75911e25f0dSDavid C Somayajulu } 76011e25f0dSDavid C Somayajulu 76111e25f0dSDavid C Somayajulu static bool ecore_int_is_parity_flag(struct ecore_hwfn *p_hwfn, 76211e25f0dSDavid C Somayajulu struct aeu_invert_reg_bit *p_bit) 76311e25f0dSDavid C Somayajulu { 76411e25f0dSDavid C Somayajulu return !!(ecore_int_aeu_translate(p_hwfn, p_bit)->flags & 76511e25f0dSDavid C Somayajulu ATTENTION_PARITY); 76611e25f0dSDavid C Somayajulu } 76711e25f0dSDavid C Somayajulu 76811e25f0dSDavid C Somayajulu #define ATTN_STATE_BITS (0xfff) 76911e25f0dSDavid C Somayajulu #define ATTN_BITS_MASKABLE (0x3ff) 77011e25f0dSDavid C Somayajulu struct ecore_sb_attn_info { 77111e25f0dSDavid C Somayajulu /* Virtual & Physical address of the SB */ 77211e25f0dSDavid C Somayajulu struct atten_status_block *sb_attn; 77311e25f0dSDavid C Somayajulu dma_addr_t sb_phys; 77411e25f0dSDavid C Somayajulu 77511e25f0dSDavid C Somayajulu /* Last seen running index */ 77611e25f0dSDavid C Somayajulu u16 index; 77711e25f0dSDavid C Somayajulu 77811e25f0dSDavid C Somayajulu /* A mask of the AEU bits resulting in a parity error */ 77911e25f0dSDavid C Somayajulu u32 parity_mask[NUM_ATTN_REGS]; 78011e25f0dSDavid C Somayajulu 78111e25f0dSDavid C Somayajulu /* A pointer to the attention description structure */ 78211e25f0dSDavid C Somayajulu struct aeu_invert_reg *p_aeu_desc; 78311e25f0dSDavid C Somayajulu 78411e25f0dSDavid C Somayajulu /* Previously asserted attentions, which are still unasserted */ 78511e25f0dSDavid C Somayajulu u16 known_attn; 78611e25f0dSDavid C Somayajulu 78711e25f0dSDavid C Somayajulu /* Cleanup address for the link's general hw attention */ 78811e25f0dSDavid C Somayajulu u32 mfw_attn_addr; 78911e25f0dSDavid C Somayajulu }; 79011e25f0dSDavid C Somayajulu 79111e25f0dSDavid C Somayajulu static u16 ecore_attn_update_idx(struct ecore_hwfn *p_hwfn, 79211e25f0dSDavid C Somayajulu struct ecore_sb_attn_info *p_sb_desc) 79311e25f0dSDavid C Somayajulu { 79411e25f0dSDavid C Somayajulu u16 rc = 0, index; 79511e25f0dSDavid C Somayajulu 79611e25f0dSDavid C Somayajulu OSAL_MMIOWB(p_hwfn->p_dev); 79711e25f0dSDavid C Somayajulu 79811e25f0dSDavid C Somayajulu index = OSAL_LE16_TO_CPU(p_sb_desc->sb_attn->sb_index); 79911e25f0dSDavid C Somayajulu if (p_sb_desc->index != index) { 80011e25f0dSDavid C Somayajulu p_sb_desc->index = index; 80111e25f0dSDavid C Somayajulu rc = ECORE_SB_ATT_IDX; 80211e25f0dSDavid C Somayajulu } 80311e25f0dSDavid C Somayajulu 80411e25f0dSDavid C Somayajulu OSAL_MMIOWB(p_hwfn->p_dev); 80511e25f0dSDavid C Somayajulu 80611e25f0dSDavid C Somayajulu return rc; 80711e25f0dSDavid C Somayajulu } 80811e25f0dSDavid C Somayajulu 80911e25f0dSDavid C Somayajulu /** 81011e25f0dSDavid C Somayajulu * @brief ecore_int_assertion - handles asserted attention bits 81111e25f0dSDavid C Somayajulu * 81211e25f0dSDavid C Somayajulu * @param p_hwfn 81311e25f0dSDavid C Somayajulu * @param asserted_bits newly asserted bits 81411e25f0dSDavid C Somayajulu * @return enum _ecore_status_t 81511e25f0dSDavid C Somayajulu */ 81611e25f0dSDavid C Somayajulu static enum _ecore_status_t ecore_int_assertion(struct ecore_hwfn *p_hwfn, 81711e25f0dSDavid C Somayajulu u16 asserted_bits) 81811e25f0dSDavid C Somayajulu { 81911e25f0dSDavid C Somayajulu struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 82011e25f0dSDavid C Somayajulu u32 igu_mask; 82111e25f0dSDavid C Somayajulu 82211e25f0dSDavid C Somayajulu /* Mask the source of the attention in the IGU */ 82311e25f0dSDavid C Somayajulu igu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 82411e25f0dSDavid C Somayajulu IGU_REG_ATTENTION_ENABLE); 82511e25f0dSDavid C Somayajulu DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n", 82611e25f0dSDavid C Somayajulu igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE)); 82711e25f0dSDavid C Somayajulu igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE); 82811e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask); 82911e25f0dSDavid C Somayajulu 83011e25f0dSDavid C Somayajulu DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, 83111e25f0dSDavid C Somayajulu "inner known ATTN state: 0x%04x --> 0x%04x\n", 83211e25f0dSDavid C Somayajulu sb_attn_sw->known_attn, 83311e25f0dSDavid C Somayajulu sb_attn_sw->known_attn | asserted_bits); 83411e25f0dSDavid C Somayajulu sb_attn_sw->known_attn |= asserted_bits; 83511e25f0dSDavid C Somayajulu 83611e25f0dSDavid C Somayajulu /* Handle MCP events */ 83711e25f0dSDavid C Somayajulu if (asserted_bits & 0x100) { 83811e25f0dSDavid C Somayajulu ecore_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt); 83911e25f0dSDavid C Somayajulu /* Clean the MCP attention */ 84011e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, 84111e25f0dSDavid C Somayajulu sb_attn_sw->mfw_attn_addr, 0); 84211e25f0dSDavid C Somayajulu } 84311e25f0dSDavid C Somayajulu 84411e25f0dSDavid C Somayajulu /* FIXME - this will change once we'll have GOOD gtt definitions */ 84511e25f0dSDavid C Somayajulu DIRECT_REG_WR(p_hwfn, 84611e25f0dSDavid C Somayajulu (u8 OSAL_IOMEM*)p_hwfn->regview + 84711e25f0dSDavid C Somayajulu GTT_BAR0_MAP_REG_IGU_CMD + 84811e25f0dSDavid C Somayajulu ((IGU_CMD_ATTN_BIT_SET_UPPER - 84911e25f0dSDavid C Somayajulu IGU_CMD_INT_ACK_BASE) << 3), (u32)asserted_bits); 85011e25f0dSDavid C Somayajulu 85111e25f0dSDavid C Somayajulu DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "set cmd IGU: 0x%04x\n", 85211e25f0dSDavid C Somayajulu asserted_bits); 85311e25f0dSDavid C Somayajulu 85411e25f0dSDavid C Somayajulu return ECORE_SUCCESS; 85511e25f0dSDavid C Somayajulu } 85611e25f0dSDavid C Somayajulu 85711e25f0dSDavid C Somayajulu static void ecore_int_attn_print(struct ecore_hwfn *p_hwfn, 85811e25f0dSDavid C Somayajulu enum block_id id, enum dbg_attn_type type, 85911e25f0dSDavid C Somayajulu bool b_clear) 86011e25f0dSDavid C Somayajulu { 86111e25f0dSDavid C Somayajulu struct dbg_attn_block_result attn_results; 86211e25f0dSDavid C Somayajulu enum dbg_status status; 86311e25f0dSDavid C Somayajulu 86411e25f0dSDavid C Somayajulu OSAL_MEMSET(&attn_results, 0, sizeof(attn_results)); 86511e25f0dSDavid C Somayajulu 86611e25f0dSDavid C Somayajulu status = ecore_dbg_read_attn(p_hwfn, p_hwfn->p_dpc_ptt, id, type, 86711e25f0dSDavid C Somayajulu b_clear, &attn_results); 8689efd0ba7SDavid C Somayajulu #ifdef ATTN_DESC 86911e25f0dSDavid C Somayajulu if (status != DBG_STATUS_OK) 87011e25f0dSDavid C Somayajulu DP_NOTICE(p_hwfn, true, 8719efd0ba7SDavid C Somayajulu "Failed to parse attention information [status: %s]\n", 8729efd0ba7SDavid C Somayajulu ecore_dbg_get_status_str(status)); 87311e25f0dSDavid C Somayajulu else 87411e25f0dSDavid C Somayajulu ecore_dbg_parse_attn(p_hwfn, &attn_results); 87511e25f0dSDavid C Somayajulu #else 8769efd0ba7SDavid C Somayajulu if (status != DBG_STATUS_OK) 8779efd0ba7SDavid C Somayajulu DP_NOTICE(p_hwfn, true, 8789efd0ba7SDavid C Somayajulu "Failed to parse attention information [status: %d]\n", 8799efd0ba7SDavid C Somayajulu status); 8809efd0ba7SDavid C Somayajulu else 88111e25f0dSDavid C Somayajulu ecore_dbg_print_attn(p_hwfn, &attn_results); 88211e25f0dSDavid C Somayajulu #endif 88311e25f0dSDavid C Somayajulu } 88411e25f0dSDavid C Somayajulu 88511e25f0dSDavid C Somayajulu /** 88611e25f0dSDavid C Somayajulu * @brief ecore_int_deassertion_aeu_bit - handles the effects of a single 88711e25f0dSDavid C Somayajulu * cause of the attention 88811e25f0dSDavid C Somayajulu * 88911e25f0dSDavid C Somayajulu * @param p_hwfn 89011e25f0dSDavid C Somayajulu * @param p_aeu - descriptor of an AEU bit which caused the attention 89111e25f0dSDavid C Somayajulu * @param aeu_en_reg - register offset of the AEU enable reg. which configured 89211e25f0dSDavid C Somayajulu * this bit to this group. 89311e25f0dSDavid C Somayajulu * @param bit_index - index of this bit in the aeu_en_reg 89411e25f0dSDavid C Somayajulu * 89511e25f0dSDavid C Somayajulu * @return enum _ecore_status_t 89611e25f0dSDavid C Somayajulu */ 89711e25f0dSDavid C Somayajulu static enum _ecore_status_t 89811e25f0dSDavid C Somayajulu ecore_int_deassertion_aeu_bit(struct ecore_hwfn *p_hwfn, 89911e25f0dSDavid C Somayajulu struct aeu_invert_reg_bit *p_aeu, 90011e25f0dSDavid C Somayajulu u32 aeu_en_reg, 90111e25f0dSDavid C Somayajulu const char *p_bit_name, 90211e25f0dSDavid C Somayajulu u32 bitmask) 90311e25f0dSDavid C Somayajulu { 90411e25f0dSDavid C Somayajulu enum _ecore_status_t rc = ECORE_INVAL; 90511e25f0dSDavid C Somayajulu bool b_fatal = false; 90611e25f0dSDavid C Somayajulu 90711e25f0dSDavid C Somayajulu DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n", 90811e25f0dSDavid C Somayajulu p_bit_name, bitmask); 90911e25f0dSDavid C Somayajulu 91011e25f0dSDavid C Somayajulu /* Call callback before clearing the interrupt status */ 91111e25f0dSDavid C Somayajulu if (p_aeu->cb) { 91211e25f0dSDavid C Somayajulu DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n", 91311e25f0dSDavid C Somayajulu p_bit_name); 91411e25f0dSDavid C Somayajulu rc = p_aeu->cb(p_hwfn); 91511e25f0dSDavid C Somayajulu } 91611e25f0dSDavid C Somayajulu 91711e25f0dSDavid C Somayajulu if (rc != ECORE_SUCCESS) 91811e25f0dSDavid C Somayajulu b_fatal = true; 91911e25f0dSDavid C Somayajulu 92011e25f0dSDavid C Somayajulu /* Print HW block interrupt registers */ 92111e25f0dSDavid C Somayajulu if (p_aeu->block_index != MAX_BLOCK_ID) 92211e25f0dSDavid C Somayajulu ecore_int_attn_print(p_hwfn, p_aeu->block_index, 92311e25f0dSDavid C Somayajulu ATTN_TYPE_INTERRUPT, !b_fatal); 92411e25f0dSDavid C Somayajulu 92511e25f0dSDavid C Somayajulu /* Reach assertion if attention is fatal */ 92611e25f0dSDavid C Somayajulu if (b_fatal) { 92711e25f0dSDavid C Somayajulu DP_NOTICE(p_hwfn, true, "`%s': Fatal attention\n", 92811e25f0dSDavid C Somayajulu p_bit_name); 92911e25f0dSDavid C Somayajulu 93011e25f0dSDavid C Somayajulu ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN); 93111e25f0dSDavid C Somayajulu } 93211e25f0dSDavid C Somayajulu 93311e25f0dSDavid C Somayajulu /* Prevent this Attention from being asserted in the future */ 93411e25f0dSDavid C Somayajulu if (p_aeu->flags & ATTENTION_CLEAR_ENABLE || 93511e25f0dSDavid C Somayajulu p_hwfn->p_dev->attn_clr_en) { 93611e25f0dSDavid C Somayajulu u32 val; 93711e25f0dSDavid C Somayajulu u32 mask = ~bitmask; 93811e25f0dSDavid C Somayajulu val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 93911e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & mask)); 94011e25f0dSDavid C Somayajulu DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n", 94111e25f0dSDavid C Somayajulu p_bit_name); 94211e25f0dSDavid C Somayajulu } 94311e25f0dSDavid C Somayajulu 94411e25f0dSDavid C Somayajulu return rc; 94511e25f0dSDavid C Somayajulu } 94611e25f0dSDavid C Somayajulu 94711e25f0dSDavid C Somayajulu /** 94811e25f0dSDavid C Somayajulu * @brief ecore_int_deassertion_parity - handle a single parity AEU source 94911e25f0dSDavid C Somayajulu * 95011e25f0dSDavid C Somayajulu * @param p_hwfn 95111e25f0dSDavid C Somayajulu * @param p_aeu - descriptor of an AEU bit which caused the parity 95211e25f0dSDavid C Somayajulu * @param aeu_en_reg - address of the AEU enable register 95311e25f0dSDavid C Somayajulu * @param bit_index 95411e25f0dSDavid C Somayajulu */ 95511e25f0dSDavid C Somayajulu static void ecore_int_deassertion_parity(struct ecore_hwfn *p_hwfn, 95611e25f0dSDavid C Somayajulu struct aeu_invert_reg_bit *p_aeu, 95711e25f0dSDavid C Somayajulu u32 aeu_en_reg, u8 bit_index) 95811e25f0dSDavid C Somayajulu { 95911e25f0dSDavid C Somayajulu u32 block_id = p_aeu->block_index, mask, val; 96011e25f0dSDavid C Somayajulu 96111e25f0dSDavid C Somayajulu DP_NOTICE(p_hwfn->p_dev, false, 96211e25f0dSDavid C Somayajulu "%s parity attention is set [address 0x%08x, bit %d]\n", 96311e25f0dSDavid C Somayajulu p_aeu->bit_name, aeu_en_reg, bit_index); 96411e25f0dSDavid C Somayajulu 96511e25f0dSDavid C Somayajulu if (block_id == MAX_BLOCK_ID) 96611e25f0dSDavid C Somayajulu return; 96711e25f0dSDavid C Somayajulu 96811e25f0dSDavid C Somayajulu ecore_int_attn_print(p_hwfn, block_id, 96911e25f0dSDavid C Somayajulu ATTN_TYPE_PARITY, false); 97011e25f0dSDavid C Somayajulu 97111e25f0dSDavid C Somayajulu /* In A0, there's a single parity bit for several blocks */ 97211e25f0dSDavid C Somayajulu if (block_id == BLOCK_BTB) { 97311e25f0dSDavid C Somayajulu ecore_int_attn_print(p_hwfn, BLOCK_OPTE, 97411e25f0dSDavid C Somayajulu ATTN_TYPE_PARITY, false); 97511e25f0dSDavid C Somayajulu ecore_int_attn_print(p_hwfn, BLOCK_MCP, 97611e25f0dSDavid C Somayajulu ATTN_TYPE_PARITY, false); 97711e25f0dSDavid C Somayajulu } 97811e25f0dSDavid C Somayajulu 97911e25f0dSDavid C Somayajulu /* Prevent this parity error from being re-asserted */ 98011e25f0dSDavid C Somayajulu mask = ~(0x1 << bit_index); 98111e25f0dSDavid C Somayajulu val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 98211e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask); 98311e25f0dSDavid C Somayajulu DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n", 98411e25f0dSDavid C Somayajulu p_aeu->bit_name); 98511e25f0dSDavid C Somayajulu } 98611e25f0dSDavid C Somayajulu 98711e25f0dSDavid C Somayajulu /** 98811e25f0dSDavid C Somayajulu * @brief - handles deassertion of previously asserted attentions. 98911e25f0dSDavid C Somayajulu * 99011e25f0dSDavid C Somayajulu * @param p_hwfn 99111e25f0dSDavid C Somayajulu * @param deasserted_bits - newly deasserted bits 99211e25f0dSDavid C Somayajulu * @return enum _ecore_status_t 99311e25f0dSDavid C Somayajulu * 99411e25f0dSDavid C Somayajulu */ 99511e25f0dSDavid C Somayajulu static enum _ecore_status_t ecore_int_deassertion(struct ecore_hwfn *p_hwfn, 99611e25f0dSDavid C Somayajulu u16 deasserted_bits) 99711e25f0dSDavid C Somayajulu { 99811e25f0dSDavid C Somayajulu struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 99911e25f0dSDavid C Somayajulu u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask, aeu_en, en; 100011e25f0dSDavid C Somayajulu u8 i, j, k, bit_idx; 100111e25f0dSDavid C Somayajulu enum _ecore_status_t rc = ECORE_SUCCESS; 100211e25f0dSDavid C Somayajulu 100311e25f0dSDavid C Somayajulu /* Read the attention registers in the AEU */ 100411e25f0dSDavid C Somayajulu for (i = 0; i < NUM_ATTN_REGS; i++) { 100511e25f0dSDavid C Somayajulu aeu_inv_arr[i] = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 100611e25f0dSDavid C Somayajulu MISC_REG_AEU_AFTER_INVERT_1_IGU + 100711e25f0dSDavid C Somayajulu i * 0x4); 100811e25f0dSDavid C Somayajulu DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, 100911e25f0dSDavid C Somayajulu "Deasserted bits [%d]: %08x\n", 101011e25f0dSDavid C Somayajulu i, aeu_inv_arr[i]); 101111e25f0dSDavid C Somayajulu } 101211e25f0dSDavid C Somayajulu 101311e25f0dSDavid C Somayajulu /* Handle parity attentions first */ 101411e25f0dSDavid C Somayajulu for (i = 0; i < NUM_ATTN_REGS; i++) 101511e25f0dSDavid C Somayajulu { 101611e25f0dSDavid C Somayajulu struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i]; 101711e25f0dSDavid C Somayajulu u32 parities; 101811e25f0dSDavid C Somayajulu 101911e25f0dSDavid C Somayajulu aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + i * sizeof(u32); 102011e25f0dSDavid C Somayajulu en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 102111e25f0dSDavid C Somayajulu parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en; 102211e25f0dSDavid C Somayajulu 102311e25f0dSDavid C Somayajulu /* Skip register in which no parity bit is currently set */ 102411e25f0dSDavid C Somayajulu if (!parities) 102511e25f0dSDavid C Somayajulu continue; 102611e25f0dSDavid C Somayajulu 102711e25f0dSDavid C Somayajulu for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 102811e25f0dSDavid C Somayajulu struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j]; 102911e25f0dSDavid C Somayajulu 103011e25f0dSDavid C Somayajulu if (ecore_int_is_parity_flag(p_hwfn, p_bit) && 103111e25f0dSDavid C Somayajulu !!(parities & (1 << bit_idx))) 103211e25f0dSDavid C Somayajulu ecore_int_deassertion_parity(p_hwfn, p_bit, 103311e25f0dSDavid C Somayajulu aeu_en, bit_idx); 103411e25f0dSDavid C Somayajulu 103511e25f0dSDavid C Somayajulu bit_idx += ATTENTION_LENGTH(p_bit->flags); 103611e25f0dSDavid C Somayajulu } 103711e25f0dSDavid C Somayajulu } 103811e25f0dSDavid C Somayajulu 103911e25f0dSDavid C Somayajulu /* Find non-parity cause for attention and act */ 104011e25f0dSDavid C Somayajulu for (k = 0; k < MAX_ATTN_GRPS; k++) { 104111e25f0dSDavid C Somayajulu struct aeu_invert_reg_bit *p_aeu; 104211e25f0dSDavid C Somayajulu 104311e25f0dSDavid C Somayajulu /* Handle only groups whose attention is currently deasserted */ 104411e25f0dSDavid C Somayajulu if (!(deasserted_bits & (1 << k))) 104511e25f0dSDavid C Somayajulu continue; 104611e25f0dSDavid C Somayajulu 104711e25f0dSDavid C Somayajulu for (i = 0; i < NUM_ATTN_REGS; i++) { 104811e25f0dSDavid C Somayajulu u32 bits; 104911e25f0dSDavid C Somayajulu 105011e25f0dSDavid C Somayajulu aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + 105111e25f0dSDavid C Somayajulu i * sizeof(u32) + 105211e25f0dSDavid C Somayajulu k * sizeof(u32) * NUM_ATTN_REGS; 105311e25f0dSDavid C Somayajulu en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 105411e25f0dSDavid C Somayajulu bits = aeu_inv_arr[i] & en; 105511e25f0dSDavid C Somayajulu 105611e25f0dSDavid C Somayajulu /* Skip if no bit from this group is currently set */ 105711e25f0dSDavid C Somayajulu if (!bits) 105811e25f0dSDavid C Somayajulu continue; 105911e25f0dSDavid C Somayajulu 106011e25f0dSDavid C Somayajulu /* Find all set bits from current register which belong 106111e25f0dSDavid C Somayajulu * to current group, making them responsible for the 106211e25f0dSDavid C Somayajulu * previous assertion. 106311e25f0dSDavid C Somayajulu */ 106411e25f0dSDavid C Somayajulu for (j = 0, bit_idx = 0; bit_idx < 32; j++) 106511e25f0dSDavid C Somayajulu { 106611e25f0dSDavid C Somayajulu long unsigned int bitmask; 106711e25f0dSDavid C Somayajulu u8 bit, bit_len; 106811e25f0dSDavid C Somayajulu 106911e25f0dSDavid C Somayajulu /* Need to account bits with changed meaning */ 107011e25f0dSDavid C Somayajulu p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j]; 107111e25f0dSDavid C Somayajulu p_aeu = ecore_int_aeu_translate(p_hwfn, p_aeu); 107211e25f0dSDavid C Somayajulu 107311e25f0dSDavid C Somayajulu bit = bit_idx; 107411e25f0dSDavid C Somayajulu bit_len = ATTENTION_LENGTH(p_aeu->flags); 107511e25f0dSDavid C Somayajulu if (ecore_int_is_parity_flag(p_hwfn, p_aeu)) { 107611e25f0dSDavid C Somayajulu /* Skip Parity */ 107711e25f0dSDavid C Somayajulu bit++; 107811e25f0dSDavid C Somayajulu bit_len--; 107911e25f0dSDavid C Somayajulu } 108011e25f0dSDavid C Somayajulu 108111e25f0dSDavid C Somayajulu /* Find the bits relating to HW-block, then 108211e25f0dSDavid C Somayajulu * shift so they'll become LSB. 108311e25f0dSDavid C Somayajulu */ 108411e25f0dSDavid C Somayajulu bitmask = bits & (((1 << bit_len) - 1) << bit); 108511e25f0dSDavid C Somayajulu bitmask >>= bit; 108611e25f0dSDavid C Somayajulu 108711e25f0dSDavid C Somayajulu if (bitmask) { 108811e25f0dSDavid C Somayajulu u32 flags = p_aeu->flags; 108911e25f0dSDavid C Somayajulu char bit_name[30]; 109011e25f0dSDavid C Somayajulu u8 num; 109111e25f0dSDavid C Somayajulu 109211e25f0dSDavid C Somayajulu num = (u8)OSAL_FIND_FIRST_BIT(&bitmask, 109311e25f0dSDavid C Somayajulu bit_len); 109411e25f0dSDavid C Somayajulu 109511e25f0dSDavid C Somayajulu /* Some bits represent more than a 109611e25f0dSDavid C Somayajulu * a single interrupt. Correctly print 109711e25f0dSDavid C Somayajulu * their name. 109811e25f0dSDavid C Somayajulu */ 109911e25f0dSDavid C Somayajulu if (ATTENTION_LENGTH(flags) > 2 || 110011e25f0dSDavid C Somayajulu ((flags & ATTENTION_PAR_INT) && 110111e25f0dSDavid C Somayajulu ATTENTION_LENGTH(flags) > 1)) 110211e25f0dSDavid C Somayajulu OSAL_SNPRINTF(bit_name, 30, 110311e25f0dSDavid C Somayajulu p_aeu->bit_name, 110411e25f0dSDavid C Somayajulu num); 110511e25f0dSDavid C Somayajulu else 110611e25f0dSDavid C Somayajulu OSAL_STRNCPY(bit_name, 110711e25f0dSDavid C Somayajulu p_aeu->bit_name, 110811e25f0dSDavid C Somayajulu 30); 110911e25f0dSDavid C Somayajulu 111011e25f0dSDavid C Somayajulu /* We now need to pass bitmask in its 111111e25f0dSDavid C Somayajulu * correct position. 111211e25f0dSDavid C Somayajulu */ 111311e25f0dSDavid C Somayajulu bitmask <<= bit; 111411e25f0dSDavid C Somayajulu 111511e25f0dSDavid C Somayajulu /* Handle source of the attention */ 111611e25f0dSDavid C Somayajulu ecore_int_deassertion_aeu_bit(p_hwfn, 111711e25f0dSDavid C Somayajulu p_aeu, 111811e25f0dSDavid C Somayajulu aeu_en, 111911e25f0dSDavid C Somayajulu bit_name, 112011e25f0dSDavid C Somayajulu bitmask); 112111e25f0dSDavid C Somayajulu } 112211e25f0dSDavid C Somayajulu 112311e25f0dSDavid C Somayajulu bit_idx += ATTENTION_LENGTH(p_aeu->flags); 112411e25f0dSDavid C Somayajulu } 112511e25f0dSDavid C Somayajulu } 112611e25f0dSDavid C Somayajulu } 112711e25f0dSDavid C Somayajulu 112811e25f0dSDavid C Somayajulu /* Clear IGU indication for the deasserted bits */ 112911e25f0dSDavid C Somayajulu /* FIXME - this will change once we'll have GOOD gtt definitions */ 113011e25f0dSDavid C Somayajulu DIRECT_REG_WR(p_hwfn, 113111e25f0dSDavid C Somayajulu (u8 OSAL_IOMEM*)p_hwfn->regview + 113211e25f0dSDavid C Somayajulu GTT_BAR0_MAP_REG_IGU_CMD + 113311e25f0dSDavid C Somayajulu ((IGU_CMD_ATTN_BIT_CLR_UPPER - 113411e25f0dSDavid C Somayajulu IGU_CMD_INT_ACK_BASE) << 3), 113511e25f0dSDavid C Somayajulu ~((u32)deasserted_bits)); 113611e25f0dSDavid C Somayajulu 113711e25f0dSDavid C Somayajulu /* Unmask deasserted attentions in IGU */ 113811e25f0dSDavid C Somayajulu aeu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, 113911e25f0dSDavid C Somayajulu IGU_REG_ATTENTION_ENABLE); 114011e25f0dSDavid C Somayajulu aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE); 114111e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask); 114211e25f0dSDavid C Somayajulu 114311e25f0dSDavid C Somayajulu /* Clear deassertion from inner state */ 114411e25f0dSDavid C Somayajulu sb_attn_sw->known_attn &= ~deasserted_bits; 114511e25f0dSDavid C Somayajulu 114611e25f0dSDavid C Somayajulu return rc; 114711e25f0dSDavid C Somayajulu } 114811e25f0dSDavid C Somayajulu 114911e25f0dSDavid C Somayajulu static enum _ecore_status_t ecore_int_attentions(struct ecore_hwfn *p_hwfn) 115011e25f0dSDavid C Somayajulu { 115111e25f0dSDavid C Somayajulu struct ecore_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn; 115211e25f0dSDavid C Somayajulu struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn; 115311e25f0dSDavid C Somayajulu u16 index = 0, asserted_bits, deasserted_bits; 115411e25f0dSDavid C Somayajulu u32 attn_bits = 0, attn_acks = 0; 115511e25f0dSDavid C Somayajulu enum _ecore_status_t rc = ECORE_SUCCESS; 115611e25f0dSDavid C Somayajulu 115711e25f0dSDavid C Somayajulu /* Read current attention bits/acks - safeguard against attentions 115811e25f0dSDavid C Somayajulu * by guaranting work on a synchronized timeframe 115911e25f0dSDavid C Somayajulu */ 116011e25f0dSDavid C Somayajulu do { 116111e25f0dSDavid C Somayajulu index = OSAL_LE16_TO_CPU(p_sb_attn->sb_index); 116211e25f0dSDavid C Somayajulu attn_bits = OSAL_LE32_TO_CPU(p_sb_attn->atten_bits); 116311e25f0dSDavid C Somayajulu attn_acks = OSAL_LE32_TO_CPU(p_sb_attn->atten_ack); 116411e25f0dSDavid C Somayajulu } while (index != OSAL_LE16_TO_CPU(p_sb_attn->sb_index)); 116511e25f0dSDavid C Somayajulu p_sb_attn->sb_index = index; 116611e25f0dSDavid C Somayajulu 116711e25f0dSDavid C Somayajulu /* Attention / Deassertion are meaningful (and in correct state) 116811e25f0dSDavid C Somayajulu * only when they differ and consistent with known state - deassertion 116911e25f0dSDavid C Somayajulu * when previous attention & current ack, and assertion when current 117011e25f0dSDavid C Somayajulu * attention with no previous attention 117111e25f0dSDavid C Somayajulu */ 117211e25f0dSDavid C Somayajulu asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) & 117311e25f0dSDavid C Somayajulu ~p_sb_attn_sw->known_attn; 117411e25f0dSDavid C Somayajulu deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) & 117511e25f0dSDavid C Somayajulu p_sb_attn_sw->known_attn; 117611e25f0dSDavid C Somayajulu 117711e25f0dSDavid C Somayajulu if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) 117811e25f0dSDavid C Somayajulu DP_INFO(p_hwfn, 117911e25f0dSDavid C Somayajulu "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n", 118011e25f0dSDavid C Somayajulu index, attn_bits, attn_acks, asserted_bits, 118111e25f0dSDavid C Somayajulu deasserted_bits, p_sb_attn_sw->known_attn); 118211e25f0dSDavid C Somayajulu else if (asserted_bits == 0x100) 118311e25f0dSDavid C Somayajulu DP_INFO(p_hwfn, 118411e25f0dSDavid C Somayajulu "MFW indication via attention\n"); 118511e25f0dSDavid C Somayajulu else 118611e25f0dSDavid C Somayajulu DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, 118711e25f0dSDavid C Somayajulu "MFW indication [deassertion]\n"); 118811e25f0dSDavid C Somayajulu 118911e25f0dSDavid C Somayajulu if (asserted_bits) { 119011e25f0dSDavid C Somayajulu rc = ecore_int_assertion(p_hwfn, asserted_bits); 119111e25f0dSDavid C Somayajulu if (rc) 119211e25f0dSDavid C Somayajulu return rc; 119311e25f0dSDavid C Somayajulu } 119411e25f0dSDavid C Somayajulu 119511e25f0dSDavid C Somayajulu if (deasserted_bits) 119611e25f0dSDavid C Somayajulu rc = ecore_int_deassertion(p_hwfn, deasserted_bits); 119711e25f0dSDavid C Somayajulu 119811e25f0dSDavid C Somayajulu return rc; 119911e25f0dSDavid C Somayajulu } 120011e25f0dSDavid C Somayajulu 120111e25f0dSDavid C Somayajulu static void ecore_sb_ack_attn(struct ecore_hwfn *p_hwfn, 120211e25f0dSDavid C Somayajulu void OSAL_IOMEM *igu_addr, u32 ack_cons) 120311e25f0dSDavid C Somayajulu { 120411e25f0dSDavid C Somayajulu struct igu_prod_cons_update igu_ack = { 0 }; 120511e25f0dSDavid C Somayajulu 120611e25f0dSDavid C Somayajulu igu_ack.sb_id_and_flags = 120711e25f0dSDavid C Somayajulu ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 120811e25f0dSDavid C Somayajulu (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 120911e25f0dSDavid C Somayajulu (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 121011e25f0dSDavid C Somayajulu (IGU_SEG_ACCESS_ATTN << 121111e25f0dSDavid C Somayajulu IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 121211e25f0dSDavid C Somayajulu 121311e25f0dSDavid C Somayajulu DIRECT_REG_WR(p_hwfn, igu_addr, igu_ack.sb_id_and_flags); 121411e25f0dSDavid C Somayajulu 121511e25f0dSDavid C Somayajulu /* Both segments (interrupts & acks) are written to same place address; 121611e25f0dSDavid C Somayajulu * Need to guarantee all commands will be received (in-order) by HW. 121711e25f0dSDavid C Somayajulu */ 121811e25f0dSDavid C Somayajulu OSAL_MMIOWB(p_hwfn->p_dev); 121911e25f0dSDavid C Somayajulu OSAL_BARRIER(p_hwfn->p_dev); 122011e25f0dSDavid C Somayajulu } 122111e25f0dSDavid C Somayajulu 122211e25f0dSDavid C Somayajulu void ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie) 122311e25f0dSDavid C Somayajulu { 122411e25f0dSDavid C Somayajulu struct ecore_hwfn *p_hwfn = (struct ecore_hwfn *)hwfn_cookie; 122511e25f0dSDavid C Somayajulu struct ecore_pi_info *pi_info = OSAL_NULL; 122611e25f0dSDavid C Somayajulu struct ecore_sb_attn_info *sb_attn; 122711e25f0dSDavid C Somayajulu struct ecore_sb_info *sb_info; 122811e25f0dSDavid C Somayajulu int arr_size; 122911e25f0dSDavid C Somayajulu u16 rc = 0; 123011e25f0dSDavid C Somayajulu 123111e25f0dSDavid C Somayajulu if (!p_hwfn) 123211e25f0dSDavid C Somayajulu return; 123311e25f0dSDavid C Somayajulu 123411e25f0dSDavid C Somayajulu if (!p_hwfn->p_sp_sb) { 123511e25f0dSDavid C Somayajulu DP_ERR(p_hwfn->p_dev, "DPC called - no p_sp_sb\n"); 123611e25f0dSDavid C Somayajulu return; 123711e25f0dSDavid C Somayajulu } 123811e25f0dSDavid C Somayajulu 123911e25f0dSDavid C Somayajulu sb_info = &p_hwfn->p_sp_sb->sb_info; 124011e25f0dSDavid C Somayajulu arr_size = OSAL_ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr); 124111e25f0dSDavid C Somayajulu if (!sb_info) { 124211e25f0dSDavid C Somayajulu DP_ERR(p_hwfn->p_dev, "Status block is NULL - cannot ack interrupts\n"); 124311e25f0dSDavid C Somayajulu return; 124411e25f0dSDavid C Somayajulu } 124511e25f0dSDavid C Somayajulu 124611e25f0dSDavid C Somayajulu if (!p_hwfn->p_sb_attn) { 124711e25f0dSDavid C Somayajulu DP_ERR(p_hwfn->p_dev, "DPC called - no p_sb_attn"); 124811e25f0dSDavid C Somayajulu return; 124911e25f0dSDavid C Somayajulu } 125011e25f0dSDavid C Somayajulu sb_attn = p_hwfn->p_sb_attn; 125111e25f0dSDavid C Somayajulu 125211e25f0dSDavid C Somayajulu DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "DPC Called! (hwfn %p %d)\n", 125311e25f0dSDavid C Somayajulu p_hwfn, p_hwfn->my_id); 125411e25f0dSDavid C Somayajulu 125511e25f0dSDavid C Somayajulu /* Disable ack for def status block. Required both for msix + 125611e25f0dSDavid C Somayajulu * inta in non-mask mode, in inta does no harm. 125711e25f0dSDavid C Somayajulu */ 125811e25f0dSDavid C Somayajulu ecore_sb_ack(sb_info, IGU_INT_DISABLE, 0); 125911e25f0dSDavid C Somayajulu 126011e25f0dSDavid C Somayajulu /* Gather Interrupts/Attentions information */ 126111e25f0dSDavid C Somayajulu if (!sb_info->sb_virt) { 126211e25f0dSDavid C Somayajulu DP_ERR(p_hwfn->p_dev, "Interrupt Status block is NULL - cannot check for new interrupts!\n"); 126311e25f0dSDavid C Somayajulu } else { 126411e25f0dSDavid C Somayajulu u32 tmp_index = sb_info->sb_ack; 126511e25f0dSDavid C Somayajulu rc = ecore_sb_update_sb_idx(sb_info); 126611e25f0dSDavid C Somayajulu DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_INTR, 126711e25f0dSDavid C Somayajulu "Interrupt indices: 0x%08x --> 0x%08x\n", 126811e25f0dSDavid C Somayajulu tmp_index, sb_info->sb_ack); 126911e25f0dSDavid C Somayajulu } 127011e25f0dSDavid C Somayajulu 127111e25f0dSDavid C Somayajulu if (!sb_attn || !sb_attn->sb_attn) { 127211e25f0dSDavid C Somayajulu DP_ERR(p_hwfn->p_dev, "Attentions Status block is NULL - cannot check for new attentions!\n"); 127311e25f0dSDavid C Somayajulu } else { 127411e25f0dSDavid C Somayajulu u16 tmp_index = sb_attn->index; 127511e25f0dSDavid C Somayajulu 127611e25f0dSDavid C Somayajulu rc |= ecore_attn_update_idx(p_hwfn, sb_attn); 127711e25f0dSDavid C Somayajulu DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_INTR, 127811e25f0dSDavid C Somayajulu "Attention indices: 0x%08x --> 0x%08x\n", 127911e25f0dSDavid C Somayajulu tmp_index, sb_attn->index); 128011e25f0dSDavid C Somayajulu } 128111e25f0dSDavid C Somayajulu 128211e25f0dSDavid C Somayajulu /* Check if we expect interrupts at this time. if not just ack them */ 128311e25f0dSDavid C Somayajulu if (!(rc & ECORE_SB_EVENT_MASK)) { 128411e25f0dSDavid C Somayajulu ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1); 128511e25f0dSDavid C Somayajulu return; 128611e25f0dSDavid C Somayajulu } 128711e25f0dSDavid C Somayajulu 128811e25f0dSDavid C Somayajulu /* Check the validity of the DPC ptt. If not ack interrupts and fail */ 128911e25f0dSDavid C Somayajulu if (!p_hwfn->p_dpc_ptt) { 129011e25f0dSDavid C Somayajulu DP_NOTICE(p_hwfn->p_dev, true, "Failed to allocate PTT\n"); 129111e25f0dSDavid C Somayajulu ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1); 129211e25f0dSDavid C Somayajulu return; 129311e25f0dSDavid C Somayajulu } 129411e25f0dSDavid C Somayajulu 129511e25f0dSDavid C Somayajulu if (rc & ECORE_SB_ATT_IDX) 129611e25f0dSDavid C Somayajulu ecore_int_attentions(p_hwfn); 129711e25f0dSDavid C Somayajulu 129811e25f0dSDavid C Somayajulu if (rc & ECORE_SB_IDX) { 129911e25f0dSDavid C Somayajulu int pi; 130011e25f0dSDavid C Somayajulu 130111e25f0dSDavid C Somayajulu /* Since we only looked at the SB index, it's possible more 130211e25f0dSDavid C Somayajulu * than a single protocol-index on the SB incremented. 130311e25f0dSDavid C Somayajulu * Iterate over all configured protocol indices and check 130411e25f0dSDavid C Somayajulu * whether something happened for each. 130511e25f0dSDavid C Somayajulu */ 130611e25f0dSDavid C Somayajulu for (pi = 0; pi < arr_size; pi++) { 130711e25f0dSDavid C Somayajulu pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi]; 130811e25f0dSDavid C Somayajulu if (pi_info->comp_cb != OSAL_NULL) 130911e25f0dSDavid C Somayajulu pi_info->comp_cb(p_hwfn, pi_info->cookie); 131011e25f0dSDavid C Somayajulu } 131111e25f0dSDavid C Somayajulu } 131211e25f0dSDavid C Somayajulu 131311e25f0dSDavid C Somayajulu if (sb_attn && (rc & ECORE_SB_ATT_IDX)) { 131411e25f0dSDavid C Somayajulu /* This should be done before the interrupts are enabled, 131511e25f0dSDavid C Somayajulu * since otherwise a new attention will be generated. 131611e25f0dSDavid C Somayajulu */ 131711e25f0dSDavid C Somayajulu ecore_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index); 131811e25f0dSDavid C Somayajulu } 131911e25f0dSDavid C Somayajulu 132011e25f0dSDavid C Somayajulu ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1); 132111e25f0dSDavid C Somayajulu } 132211e25f0dSDavid C Somayajulu 132311e25f0dSDavid C Somayajulu static void ecore_int_sb_attn_free(struct ecore_hwfn *p_hwfn) 132411e25f0dSDavid C Somayajulu { 132511e25f0dSDavid C Somayajulu struct ecore_sb_attn_info *p_sb = p_hwfn->p_sb_attn; 132611e25f0dSDavid C Somayajulu 132711e25f0dSDavid C Somayajulu if (!p_sb) 132811e25f0dSDavid C Somayajulu return; 132911e25f0dSDavid C Somayajulu 133011e25f0dSDavid C Somayajulu if (p_sb->sb_attn) { 133111e25f0dSDavid C Somayajulu OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, p_sb->sb_attn, 133211e25f0dSDavid C Somayajulu p_sb->sb_phys, 133311e25f0dSDavid C Somayajulu SB_ATTN_ALIGNED_SIZE(p_hwfn)); 133411e25f0dSDavid C Somayajulu } 133511e25f0dSDavid C Somayajulu 133611e25f0dSDavid C Somayajulu OSAL_FREE(p_hwfn->p_dev, p_sb); 133711e25f0dSDavid C Somayajulu p_hwfn->p_sb_attn = OSAL_NULL; 133811e25f0dSDavid C Somayajulu } 133911e25f0dSDavid C Somayajulu 134011e25f0dSDavid C Somayajulu static void ecore_int_sb_attn_setup(struct ecore_hwfn *p_hwfn, 134111e25f0dSDavid C Somayajulu struct ecore_ptt *p_ptt) 134211e25f0dSDavid C Somayajulu { 134311e25f0dSDavid C Somayajulu struct ecore_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 134411e25f0dSDavid C Somayajulu 134511e25f0dSDavid C Somayajulu OSAL_MEMSET(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn)); 134611e25f0dSDavid C Somayajulu 134711e25f0dSDavid C Somayajulu sb_info->index = 0; 134811e25f0dSDavid C Somayajulu sb_info->known_attn = 0; 134911e25f0dSDavid C Somayajulu 135011e25f0dSDavid C Somayajulu /* Configure Attention Status Block in IGU */ 135111e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L, 135211e25f0dSDavid C Somayajulu DMA_LO(p_hwfn->p_sb_attn->sb_phys)); 135311e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H, 135411e25f0dSDavid C Somayajulu DMA_HI(p_hwfn->p_sb_attn->sb_phys)); 135511e25f0dSDavid C Somayajulu } 135611e25f0dSDavid C Somayajulu 135711e25f0dSDavid C Somayajulu static void ecore_int_sb_attn_init(struct ecore_hwfn *p_hwfn, 135811e25f0dSDavid C Somayajulu struct ecore_ptt *p_ptt, 135911e25f0dSDavid C Somayajulu void *sb_virt_addr, 136011e25f0dSDavid C Somayajulu dma_addr_t sb_phy_addr) 136111e25f0dSDavid C Somayajulu { 136211e25f0dSDavid C Somayajulu struct ecore_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 136311e25f0dSDavid C Somayajulu int i, j, k; 136411e25f0dSDavid C Somayajulu 136511e25f0dSDavid C Somayajulu sb_info->sb_attn = sb_virt_addr; 136611e25f0dSDavid C Somayajulu sb_info->sb_phys = sb_phy_addr; 136711e25f0dSDavid C Somayajulu 136811e25f0dSDavid C Somayajulu /* Set the pointer to the AEU descriptors */ 136911e25f0dSDavid C Somayajulu sb_info->p_aeu_desc = aeu_descs; 137011e25f0dSDavid C Somayajulu 137111e25f0dSDavid C Somayajulu /* Calculate Parity Masks */ 137211e25f0dSDavid C Somayajulu OSAL_MEMSET(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS); 137311e25f0dSDavid C Somayajulu for (i = 0; i < NUM_ATTN_REGS; i++) { 137411e25f0dSDavid C Somayajulu /* j is array index, k is bit index */ 137511e25f0dSDavid C Somayajulu for (j = 0, k = 0; k < 32; j++) { 137611e25f0dSDavid C Somayajulu struct aeu_invert_reg_bit *p_aeu; 137711e25f0dSDavid C Somayajulu 137811e25f0dSDavid C Somayajulu p_aeu = &aeu_descs[i].bits[j]; 137911e25f0dSDavid C Somayajulu if (ecore_int_is_parity_flag(p_hwfn, p_aeu)) 138011e25f0dSDavid C Somayajulu sb_info->parity_mask[i] |= 1 << k; 138111e25f0dSDavid C Somayajulu 138211e25f0dSDavid C Somayajulu k += ATTENTION_LENGTH(p_aeu->flags); 138311e25f0dSDavid C Somayajulu } 138411e25f0dSDavid C Somayajulu DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, 138511e25f0dSDavid C Somayajulu "Attn Mask [Reg %d]: 0x%08x\n", 138611e25f0dSDavid C Somayajulu i, sb_info->parity_mask[i]); 138711e25f0dSDavid C Somayajulu } 138811e25f0dSDavid C Somayajulu 138911e25f0dSDavid C Somayajulu /* Set the address of cleanup for the mcp attention */ 139011e25f0dSDavid C Somayajulu sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) + 139111e25f0dSDavid C Somayajulu MISC_REG_AEU_GENERAL_ATTN_0; 139211e25f0dSDavid C Somayajulu 139311e25f0dSDavid C Somayajulu ecore_int_sb_attn_setup(p_hwfn, p_ptt); 139411e25f0dSDavid C Somayajulu } 139511e25f0dSDavid C Somayajulu 139611e25f0dSDavid C Somayajulu static enum _ecore_status_t ecore_int_sb_attn_alloc(struct ecore_hwfn *p_hwfn, 139711e25f0dSDavid C Somayajulu struct ecore_ptt *p_ptt) 139811e25f0dSDavid C Somayajulu { 139911e25f0dSDavid C Somayajulu struct ecore_dev *p_dev = p_hwfn->p_dev; 140011e25f0dSDavid C Somayajulu struct ecore_sb_attn_info *p_sb; 140111e25f0dSDavid C Somayajulu dma_addr_t p_phys = 0; 140211e25f0dSDavid C Somayajulu void *p_virt; 140311e25f0dSDavid C Somayajulu 140411e25f0dSDavid C Somayajulu /* SB struct */ 140511e25f0dSDavid C Somayajulu p_sb = OSAL_ALLOC(p_dev, GFP_KERNEL, sizeof(*p_sb)); 140611e25f0dSDavid C Somayajulu if (!p_sb) { 140711e25f0dSDavid C Somayajulu DP_NOTICE(p_dev, true, "Failed to allocate `struct ecore_sb_attn_info'\n"); 140811e25f0dSDavid C Somayajulu return ECORE_NOMEM; 140911e25f0dSDavid C Somayajulu } 141011e25f0dSDavid C Somayajulu 141111e25f0dSDavid C Somayajulu /* SB ring */ 141211e25f0dSDavid C Somayajulu p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, 141311e25f0dSDavid C Somayajulu SB_ATTN_ALIGNED_SIZE(p_hwfn)); 141411e25f0dSDavid C Somayajulu if (!p_virt) { 141511e25f0dSDavid C Somayajulu DP_NOTICE(p_dev, true, "Failed to allocate status block (attentions)\n"); 141611e25f0dSDavid C Somayajulu OSAL_FREE(p_dev, p_sb); 141711e25f0dSDavid C Somayajulu return ECORE_NOMEM; 141811e25f0dSDavid C Somayajulu } 141911e25f0dSDavid C Somayajulu 142011e25f0dSDavid C Somayajulu /* Attention setup */ 142111e25f0dSDavid C Somayajulu p_hwfn->p_sb_attn = p_sb; 142211e25f0dSDavid C Somayajulu ecore_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys); 142311e25f0dSDavid C Somayajulu 142411e25f0dSDavid C Somayajulu return ECORE_SUCCESS; 142511e25f0dSDavid C Somayajulu } 142611e25f0dSDavid C Somayajulu 142711e25f0dSDavid C Somayajulu /* coalescing timeout = timeset << (timer_res + 1) */ 142811e25f0dSDavid C Somayajulu #define ECORE_CAU_DEF_RX_USECS 24 142911e25f0dSDavid C Somayajulu #define ECORE_CAU_DEF_TX_USECS 48 143011e25f0dSDavid C Somayajulu 143111e25f0dSDavid C Somayajulu void ecore_init_cau_sb_entry(struct ecore_hwfn *p_hwfn, 143211e25f0dSDavid C Somayajulu struct cau_sb_entry *p_sb_entry, 143311e25f0dSDavid C Somayajulu u8 pf_id, u16 vf_number, u8 vf_valid) 143411e25f0dSDavid C Somayajulu { 143511e25f0dSDavid C Somayajulu struct ecore_dev *p_dev = p_hwfn->p_dev; 143611e25f0dSDavid C Somayajulu u32 cau_state; 143711e25f0dSDavid C Somayajulu u8 timer_res; 143811e25f0dSDavid C Somayajulu 143911e25f0dSDavid C Somayajulu OSAL_MEMSET(p_sb_entry, 0, sizeof(*p_sb_entry)); 144011e25f0dSDavid C Somayajulu 144111e25f0dSDavid C Somayajulu SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id); 144211e25f0dSDavid C Somayajulu SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number); 144311e25f0dSDavid C Somayajulu SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid); 144411e25f0dSDavid C Somayajulu SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F); 144511e25f0dSDavid C Somayajulu SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F); 144611e25f0dSDavid C Somayajulu 144711e25f0dSDavid C Somayajulu cau_state = CAU_HC_DISABLE_STATE; 144811e25f0dSDavid C Somayajulu 144911e25f0dSDavid C Somayajulu if (p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) { 145011e25f0dSDavid C Somayajulu cau_state = CAU_HC_ENABLE_STATE; 145111e25f0dSDavid C Somayajulu if (!p_dev->rx_coalesce_usecs) 145211e25f0dSDavid C Somayajulu p_dev->rx_coalesce_usecs = ECORE_CAU_DEF_RX_USECS; 145311e25f0dSDavid C Somayajulu if (!p_dev->tx_coalesce_usecs) 145411e25f0dSDavid C Somayajulu p_dev->tx_coalesce_usecs = ECORE_CAU_DEF_TX_USECS; 145511e25f0dSDavid C Somayajulu } 145611e25f0dSDavid C Somayajulu 145711e25f0dSDavid C Somayajulu /* Coalesce = (timeset << timer-res), timeset is 7bit wide */ 145811e25f0dSDavid C Somayajulu if (p_dev->rx_coalesce_usecs <= 0x7F) 145911e25f0dSDavid C Somayajulu timer_res = 0; 146011e25f0dSDavid C Somayajulu else if (p_dev->rx_coalesce_usecs <= 0xFF) 146111e25f0dSDavid C Somayajulu timer_res = 1; 146211e25f0dSDavid C Somayajulu else 146311e25f0dSDavid C Somayajulu timer_res = 2; 146411e25f0dSDavid C Somayajulu SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 146511e25f0dSDavid C Somayajulu 146611e25f0dSDavid C Somayajulu if (p_dev->tx_coalesce_usecs <= 0x7F) 146711e25f0dSDavid C Somayajulu timer_res = 0; 146811e25f0dSDavid C Somayajulu else if (p_dev->tx_coalesce_usecs <= 0xFF) 146911e25f0dSDavid C Somayajulu timer_res = 1; 147011e25f0dSDavid C Somayajulu else 147111e25f0dSDavid C Somayajulu timer_res = 2; 147211e25f0dSDavid C Somayajulu SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 147311e25f0dSDavid C Somayajulu 147411e25f0dSDavid C Somayajulu SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state); 147511e25f0dSDavid C Somayajulu SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state); 147611e25f0dSDavid C Somayajulu } 147711e25f0dSDavid C Somayajulu 147811e25f0dSDavid C Somayajulu static void _ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn, 147911e25f0dSDavid C Somayajulu struct ecore_ptt *p_ptt, 148011e25f0dSDavid C Somayajulu u16 igu_sb_id, u32 pi_index, 148111e25f0dSDavid C Somayajulu enum ecore_coalescing_fsm coalescing_fsm, 148211e25f0dSDavid C Somayajulu u8 timeset) 148311e25f0dSDavid C Somayajulu { 148411e25f0dSDavid C Somayajulu struct cau_pi_entry pi_entry; 148511e25f0dSDavid C Somayajulu u32 sb_offset, pi_offset; 148611e25f0dSDavid C Somayajulu 148711e25f0dSDavid C Somayajulu if (IS_VF(p_hwfn->p_dev)) 148811e25f0dSDavid C Somayajulu return;/* @@@TBD MichalK- VF CAU... */ 148911e25f0dSDavid C Somayajulu 14909efd0ba7SDavid C Somayajulu sb_offset = igu_sb_id * PIS_PER_SB_E4; 149111e25f0dSDavid C Somayajulu OSAL_MEMSET(&pi_entry, 0, sizeof(struct cau_pi_entry)); 149211e25f0dSDavid C Somayajulu 149311e25f0dSDavid C Somayajulu SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset); 149411e25f0dSDavid C Somayajulu if (coalescing_fsm == ECORE_COAL_RX_STATE_MACHINE) 149511e25f0dSDavid C Somayajulu SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0); 149611e25f0dSDavid C Somayajulu else 149711e25f0dSDavid C Somayajulu SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1); 149811e25f0dSDavid C Somayajulu 149911e25f0dSDavid C Somayajulu pi_offset = sb_offset + pi_index; 150011e25f0dSDavid C Somayajulu if (p_hwfn->hw_init_done) { 150111e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_ptt, 150211e25f0dSDavid C Somayajulu CAU_REG_PI_MEMORY + pi_offset * sizeof(u32), 150311e25f0dSDavid C Somayajulu *((u32 *)&(pi_entry))); 150411e25f0dSDavid C Somayajulu } else { 150511e25f0dSDavid C Somayajulu STORE_RT_REG(p_hwfn, 150611e25f0dSDavid C Somayajulu CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset, 150711e25f0dSDavid C Somayajulu *((u32 *)&(pi_entry))); 150811e25f0dSDavid C Somayajulu } 150911e25f0dSDavid C Somayajulu } 151011e25f0dSDavid C Somayajulu 151111e25f0dSDavid C Somayajulu void ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn, 151211e25f0dSDavid C Somayajulu struct ecore_ptt *p_ptt, 151311e25f0dSDavid C Somayajulu struct ecore_sb_info *p_sb, u32 pi_index, 151411e25f0dSDavid C Somayajulu enum ecore_coalescing_fsm coalescing_fsm, 151511e25f0dSDavid C Somayajulu u8 timeset) 151611e25f0dSDavid C Somayajulu { 151711e25f0dSDavid C Somayajulu _ecore_int_cau_conf_pi(p_hwfn, p_ptt, p_sb->igu_sb_id, 151811e25f0dSDavid C Somayajulu pi_index, coalescing_fsm, timeset); 151911e25f0dSDavid C Somayajulu } 152011e25f0dSDavid C Somayajulu 152111e25f0dSDavid C Somayajulu void ecore_int_cau_conf_sb(struct ecore_hwfn *p_hwfn, 152211e25f0dSDavid C Somayajulu struct ecore_ptt *p_ptt, 152311e25f0dSDavid C Somayajulu dma_addr_t sb_phys, u16 igu_sb_id, 152411e25f0dSDavid C Somayajulu u16 vf_number, u8 vf_valid) 152511e25f0dSDavid C Somayajulu { 152611e25f0dSDavid C Somayajulu struct cau_sb_entry sb_entry; 152711e25f0dSDavid C Somayajulu 152811e25f0dSDavid C Somayajulu ecore_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id, 152911e25f0dSDavid C Somayajulu vf_number, vf_valid); 153011e25f0dSDavid C Somayajulu 153111e25f0dSDavid C Somayajulu if (p_hwfn->hw_init_done) { 153211e25f0dSDavid C Somayajulu /* Wide-bus, initialize via DMAE */ 153311e25f0dSDavid C Somayajulu u64 phys_addr = (u64)sb_phys; 153411e25f0dSDavid C Somayajulu 153511e25f0dSDavid C Somayajulu ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&phys_addr, 153611e25f0dSDavid C Somayajulu CAU_REG_SB_ADDR_MEMORY + 153711e25f0dSDavid C Somayajulu igu_sb_id * sizeof(u64), 2, 0); 153811e25f0dSDavid C Somayajulu ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&sb_entry, 153911e25f0dSDavid C Somayajulu CAU_REG_SB_VAR_MEMORY + 154011e25f0dSDavid C Somayajulu igu_sb_id * sizeof(u64), 2, 0); 154111e25f0dSDavid C Somayajulu } else { 154211e25f0dSDavid C Somayajulu /* Initialize Status Block Address */ 154311e25f0dSDavid C Somayajulu STORE_RT_REG_AGG(p_hwfn, 154411e25f0dSDavid C Somayajulu CAU_REG_SB_ADDR_MEMORY_RT_OFFSET+igu_sb_id*2, 154511e25f0dSDavid C Somayajulu sb_phys); 154611e25f0dSDavid C Somayajulu 154711e25f0dSDavid C Somayajulu STORE_RT_REG_AGG(p_hwfn, 154811e25f0dSDavid C Somayajulu CAU_REG_SB_VAR_MEMORY_RT_OFFSET+igu_sb_id*2, 154911e25f0dSDavid C Somayajulu sb_entry); 155011e25f0dSDavid C Somayajulu } 155111e25f0dSDavid C Somayajulu 155211e25f0dSDavid C Somayajulu /* Configure pi coalescing if set */ 155311e25f0dSDavid C Somayajulu if (p_hwfn->p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) { 155411e25f0dSDavid C Somayajulu /* eth will open queues for all tcs, so configure all of them 155511e25f0dSDavid C Somayajulu * properly, rather than just the active ones 155611e25f0dSDavid C Somayajulu */ 155711e25f0dSDavid C Somayajulu u8 num_tc = p_hwfn->hw_info.num_hw_tc; 155811e25f0dSDavid C Somayajulu 155911e25f0dSDavid C Somayajulu u8 timeset, timer_res; 156011e25f0dSDavid C Somayajulu u8 i; 156111e25f0dSDavid C Somayajulu 156211e25f0dSDavid C Somayajulu /* timeset = (coalesce >> timer-res), timeset is 7bit wide */ 156311e25f0dSDavid C Somayajulu if (p_hwfn->p_dev->rx_coalesce_usecs <= 0x7F) 156411e25f0dSDavid C Somayajulu timer_res = 0; 156511e25f0dSDavid C Somayajulu else if (p_hwfn->p_dev->rx_coalesce_usecs <= 0xFF) 156611e25f0dSDavid C Somayajulu timer_res = 1; 156711e25f0dSDavid C Somayajulu else 156811e25f0dSDavid C Somayajulu timer_res = 2; 156911e25f0dSDavid C Somayajulu timeset = (u8)(p_hwfn->p_dev->rx_coalesce_usecs >> timer_res); 157011e25f0dSDavid C Somayajulu _ecore_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI, 157111e25f0dSDavid C Somayajulu ECORE_COAL_RX_STATE_MACHINE, 157211e25f0dSDavid C Somayajulu timeset); 157311e25f0dSDavid C Somayajulu 157411e25f0dSDavid C Somayajulu if (p_hwfn->p_dev->tx_coalesce_usecs <= 0x7F) 157511e25f0dSDavid C Somayajulu timer_res = 0; 157611e25f0dSDavid C Somayajulu else if (p_hwfn->p_dev->tx_coalesce_usecs <= 0xFF) 157711e25f0dSDavid C Somayajulu timer_res = 1; 157811e25f0dSDavid C Somayajulu else 157911e25f0dSDavid C Somayajulu timer_res = 2; 158011e25f0dSDavid C Somayajulu timeset = (u8)(p_hwfn->p_dev->tx_coalesce_usecs >> timer_res); 158111e25f0dSDavid C Somayajulu for (i = 0; i < num_tc; i++) { 158211e25f0dSDavid C Somayajulu _ecore_int_cau_conf_pi(p_hwfn, p_ptt, 158311e25f0dSDavid C Somayajulu igu_sb_id, TX_PI(i), 158411e25f0dSDavid C Somayajulu ECORE_COAL_TX_STATE_MACHINE, 158511e25f0dSDavid C Somayajulu timeset); 158611e25f0dSDavid C Somayajulu } 158711e25f0dSDavid C Somayajulu } 158811e25f0dSDavid C Somayajulu } 158911e25f0dSDavid C Somayajulu 159011e25f0dSDavid C Somayajulu void ecore_int_sb_setup(struct ecore_hwfn *p_hwfn, 159111e25f0dSDavid C Somayajulu struct ecore_ptt *p_ptt, 159211e25f0dSDavid C Somayajulu struct ecore_sb_info *sb_info) 159311e25f0dSDavid C Somayajulu { 159411e25f0dSDavid C Somayajulu /* zero status block and ack counter */ 159511e25f0dSDavid C Somayajulu sb_info->sb_ack = 0; 159611e25f0dSDavid C Somayajulu OSAL_MEMSET(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 159711e25f0dSDavid C Somayajulu 159811e25f0dSDavid C Somayajulu if (IS_PF(p_hwfn->p_dev)) 159911e25f0dSDavid C Somayajulu ecore_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys, 160011e25f0dSDavid C Somayajulu sb_info->igu_sb_id, 0, 0); 160111e25f0dSDavid C Somayajulu } 160211e25f0dSDavid C Somayajulu 160311e25f0dSDavid C Somayajulu struct ecore_igu_block * 160411e25f0dSDavid C Somayajulu ecore_get_igu_free_sb(struct ecore_hwfn *p_hwfn, bool b_is_pf) 160511e25f0dSDavid C Somayajulu { 160611e25f0dSDavid C Somayajulu struct ecore_igu_block *p_block; 160711e25f0dSDavid C Somayajulu u16 igu_id; 160811e25f0dSDavid C Somayajulu 160911e25f0dSDavid C Somayajulu for (igu_id = 0; igu_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev); 161011e25f0dSDavid C Somayajulu igu_id++) { 161111e25f0dSDavid C Somayajulu p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id]; 161211e25f0dSDavid C Somayajulu 161311e25f0dSDavid C Somayajulu if (!(p_block->status & ECORE_IGU_STATUS_VALID) || 161411e25f0dSDavid C Somayajulu !(p_block->status & ECORE_IGU_STATUS_FREE)) 161511e25f0dSDavid C Somayajulu continue; 161611e25f0dSDavid C Somayajulu 161711e25f0dSDavid C Somayajulu if (!!(p_block->status & ECORE_IGU_STATUS_PF) == 161811e25f0dSDavid C Somayajulu b_is_pf) 161911e25f0dSDavid C Somayajulu return p_block; 162011e25f0dSDavid C Somayajulu } 162111e25f0dSDavid C Somayajulu 162211e25f0dSDavid C Somayajulu return OSAL_NULL; 162311e25f0dSDavid C Somayajulu } 162411e25f0dSDavid C Somayajulu 162511e25f0dSDavid C Somayajulu static u16 ecore_get_pf_igu_sb_id(struct ecore_hwfn *p_hwfn, 162611e25f0dSDavid C Somayajulu u16 vector_id) 162711e25f0dSDavid C Somayajulu { 162811e25f0dSDavid C Somayajulu struct ecore_igu_block *p_block; 162911e25f0dSDavid C Somayajulu u16 igu_id; 163011e25f0dSDavid C Somayajulu 163111e25f0dSDavid C Somayajulu for (igu_id = 0; igu_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev); 163211e25f0dSDavid C Somayajulu igu_id++) { 163311e25f0dSDavid C Somayajulu p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id]; 163411e25f0dSDavid C Somayajulu 163511e25f0dSDavid C Somayajulu if (!(p_block->status & ECORE_IGU_STATUS_VALID) || 163611e25f0dSDavid C Somayajulu !p_block->is_pf || 163711e25f0dSDavid C Somayajulu p_block->vector_number != vector_id) 163811e25f0dSDavid C Somayajulu continue; 163911e25f0dSDavid C Somayajulu 164011e25f0dSDavid C Somayajulu return igu_id; 164111e25f0dSDavid C Somayajulu } 164211e25f0dSDavid C Somayajulu 164311e25f0dSDavid C Somayajulu return ECORE_SB_INVALID_IDX; 164411e25f0dSDavid C Somayajulu } 164511e25f0dSDavid C Somayajulu 164611e25f0dSDavid C Somayajulu u16 ecore_get_igu_sb_id(struct ecore_hwfn *p_hwfn, u16 sb_id) 164711e25f0dSDavid C Somayajulu { 164811e25f0dSDavid C Somayajulu u16 igu_sb_id; 164911e25f0dSDavid C Somayajulu 165011e25f0dSDavid C Somayajulu /* Assuming continuous set of IGU SBs dedicated for given PF */ 165111e25f0dSDavid C Somayajulu if (sb_id == ECORE_SP_SB_ID) 165211e25f0dSDavid C Somayajulu igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id; 165311e25f0dSDavid C Somayajulu else if (IS_PF(p_hwfn->p_dev)) 165411e25f0dSDavid C Somayajulu igu_sb_id = ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1); 165511e25f0dSDavid C Somayajulu else 165611e25f0dSDavid C Somayajulu igu_sb_id = ecore_vf_get_igu_sb_id(p_hwfn, sb_id); 165711e25f0dSDavid C Somayajulu 165811e25f0dSDavid C Somayajulu if (igu_sb_id == ECORE_SB_INVALID_IDX) 165911e25f0dSDavid C Somayajulu DP_NOTICE(p_hwfn, true, 166011e25f0dSDavid C Somayajulu "Slowpath SB vector %04x doesn't exist\n", 166111e25f0dSDavid C Somayajulu sb_id); 166211e25f0dSDavid C Somayajulu else if (sb_id == ECORE_SP_SB_ID) 166311e25f0dSDavid C Somayajulu DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, 166411e25f0dSDavid C Somayajulu "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id); 166511e25f0dSDavid C Somayajulu else 166611e25f0dSDavid C Somayajulu DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, 166711e25f0dSDavid C Somayajulu "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id); 166811e25f0dSDavid C Somayajulu 166911e25f0dSDavid C Somayajulu return igu_sb_id; 167011e25f0dSDavid C Somayajulu } 167111e25f0dSDavid C Somayajulu 167211e25f0dSDavid C Somayajulu enum _ecore_status_t ecore_int_sb_init(struct ecore_hwfn *p_hwfn, 167311e25f0dSDavid C Somayajulu struct ecore_ptt *p_ptt, 167411e25f0dSDavid C Somayajulu struct ecore_sb_info *sb_info, 167511e25f0dSDavid C Somayajulu void *sb_virt_addr, 167611e25f0dSDavid C Somayajulu dma_addr_t sb_phy_addr, 167711e25f0dSDavid C Somayajulu u16 sb_id) 167811e25f0dSDavid C Somayajulu { 167911e25f0dSDavid C Somayajulu sb_info->sb_virt = sb_virt_addr; 168011e25f0dSDavid C Somayajulu sb_info->sb_phys = sb_phy_addr; 168111e25f0dSDavid C Somayajulu 168211e25f0dSDavid C Somayajulu sb_info->igu_sb_id = ecore_get_igu_sb_id(p_hwfn, sb_id); 168311e25f0dSDavid C Somayajulu 168411e25f0dSDavid C Somayajulu if (sb_info->igu_sb_id == ECORE_SB_INVALID_IDX) 168511e25f0dSDavid C Somayajulu return ECORE_INVAL; 168611e25f0dSDavid C Somayajulu 168711e25f0dSDavid C Somayajulu /* Let the igu info reference the client's SB info */ 168811e25f0dSDavid C Somayajulu if (sb_id != ECORE_SP_SB_ID) { 168911e25f0dSDavid C Somayajulu if (IS_PF(p_hwfn->p_dev)) { 169011e25f0dSDavid C Somayajulu struct ecore_igu_info *p_info; 169111e25f0dSDavid C Somayajulu struct ecore_igu_block *p_block; 169211e25f0dSDavid C Somayajulu 169311e25f0dSDavid C Somayajulu p_info = p_hwfn->hw_info.p_igu_info; 169411e25f0dSDavid C Somayajulu p_block = &p_info->entry[sb_info->igu_sb_id]; 169511e25f0dSDavid C Somayajulu 169611e25f0dSDavid C Somayajulu p_block->sb_info = sb_info; 169711e25f0dSDavid C Somayajulu p_block->status &= ~ECORE_IGU_STATUS_FREE; 169811e25f0dSDavid C Somayajulu p_info->usage.free_cnt--; 169911e25f0dSDavid C Somayajulu } else { 170011e25f0dSDavid C Somayajulu ecore_vf_set_sb_info(p_hwfn, sb_id, sb_info); 170111e25f0dSDavid C Somayajulu } 170211e25f0dSDavid C Somayajulu } 170311e25f0dSDavid C Somayajulu 170411e25f0dSDavid C Somayajulu #ifdef ECORE_CONFIG_DIRECT_HWFN 170511e25f0dSDavid C Somayajulu sb_info->p_hwfn = p_hwfn; 170611e25f0dSDavid C Somayajulu #endif 170711e25f0dSDavid C Somayajulu sb_info->p_dev = p_hwfn->p_dev; 170811e25f0dSDavid C Somayajulu 170911e25f0dSDavid C Somayajulu /* The igu address will hold the absolute address that needs to be 171011e25f0dSDavid C Somayajulu * written to for a specific status block 171111e25f0dSDavid C Somayajulu */ 171211e25f0dSDavid C Somayajulu if (IS_PF(p_hwfn->p_dev)) { 171311e25f0dSDavid C Somayajulu sb_info->igu_addr = (u8 OSAL_IOMEM*)p_hwfn->regview + 171411e25f0dSDavid C Somayajulu GTT_BAR0_MAP_REG_IGU_CMD + 171511e25f0dSDavid C Somayajulu (sb_info->igu_sb_id << 3); 171611e25f0dSDavid C Somayajulu 171711e25f0dSDavid C Somayajulu } else { 171811e25f0dSDavid C Somayajulu sb_info->igu_addr = 171911e25f0dSDavid C Somayajulu (u8 OSAL_IOMEM*)p_hwfn->regview + 172011e25f0dSDavid C Somayajulu PXP_VF_BAR0_START_IGU + 172111e25f0dSDavid C Somayajulu ((IGU_CMD_INT_ACK_BASE + sb_info->igu_sb_id) << 3); 172211e25f0dSDavid C Somayajulu } 172311e25f0dSDavid C Somayajulu 172411e25f0dSDavid C Somayajulu sb_info->flags |= ECORE_SB_INFO_INIT; 172511e25f0dSDavid C Somayajulu 172611e25f0dSDavid C Somayajulu ecore_int_sb_setup(p_hwfn, p_ptt, sb_info); 172711e25f0dSDavid C Somayajulu 172811e25f0dSDavid C Somayajulu return ECORE_SUCCESS; 172911e25f0dSDavid C Somayajulu } 173011e25f0dSDavid C Somayajulu 173111e25f0dSDavid C Somayajulu enum _ecore_status_t ecore_int_sb_release(struct ecore_hwfn *p_hwfn, 173211e25f0dSDavid C Somayajulu struct ecore_sb_info *sb_info, 173311e25f0dSDavid C Somayajulu u16 sb_id) 173411e25f0dSDavid C Somayajulu { 173511e25f0dSDavid C Somayajulu struct ecore_igu_info *p_info; 173611e25f0dSDavid C Somayajulu struct ecore_igu_block *p_block; 173711e25f0dSDavid C Somayajulu 173811e25f0dSDavid C Somayajulu if (sb_info == OSAL_NULL) 173911e25f0dSDavid C Somayajulu return ECORE_SUCCESS; 174011e25f0dSDavid C Somayajulu 174111e25f0dSDavid C Somayajulu /* zero status block and ack counter */ 174211e25f0dSDavid C Somayajulu sb_info->sb_ack = 0; 174311e25f0dSDavid C Somayajulu OSAL_MEMSET(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 174411e25f0dSDavid C Somayajulu 174511e25f0dSDavid C Somayajulu if (IS_VF(p_hwfn->p_dev)) { 174611e25f0dSDavid C Somayajulu ecore_vf_set_sb_info(p_hwfn, sb_id, OSAL_NULL); 174711e25f0dSDavid C Somayajulu return ECORE_SUCCESS; 174811e25f0dSDavid C Somayajulu } 174911e25f0dSDavid C Somayajulu 175011e25f0dSDavid C Somayajulu p_info = p_hwfn->hw_info.p_igu_info; 175111e25f0dSDavid C Somayajulu p_block = &p_info->entry[sb_info->igu_sb_id]; 175211e25f0dSDavid C Somayajulu 175311e25f0dSDavid C Somayajulu /* Vector 0 is reserved to Default SB */ 175411e25f0dSDavid C Somayajulu if (p_block->vector_number == 0) { 175511e25f0dSDavid C Somayajulu DP_ERR(p_hwfn, "Do Not free sp sb using this function"); 175611e25f0dSDavid C Somayajulu return ECORE_INVAL; 175711e25f0dSDavid C Somayajulu } 175811e25f0dSDavid C Somayajulu 175911e25f0dSDavid C Somayajulu /* Lose reference to client's SB info, and fix counters */ 176011e25f0dSDavid C Somayajulu p_block->sb_info = OSAL_NULL; 176111e25f0dSDavid C Somayajulu p_block->status |= ECORE_IGU_STATUS_FREE; 176211e25f0dSDavid C Somayajulu p_info->usage.free_cnt++; 176311e25f0dSDavid C Somayajulu 176411e25f0dSDavid C Somayajulu return ECORE_SUCCESS; 176511e25f0dSDavid C Somayajulu } 176611e25f0dSDavid C Somayajulu 176711e25f0dSDavid C Somayajulu static void ecore_int_sp_sb_free(struct ecore_hwfn *p_hwfn) 176811e25f0dSDavid C Somayajulu { 176911e25f0dSDavid C Somayajulu struct ecore_sb_sp_info *p_sb = p_hwfn->p_sp_sb; 177011e25f0dSDavid C Somayajulu 177111e25f0dSDavid C Somayajulu if (!p_sb) 177211e25f0dSDavid C Somayajulu return; 177311e25f0dSDavid C Somayajulu 177411e25f0dSDavid C Somayajulu if (p_sb->sb_info.sb_virt) { 177511e25f0dSDavid C Somayajulu OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, 177611e25f0dSDavid C Somayajulu p_sb->sb_info.sb_virt, 177711e25f0dSDavid C Somayajulu p_sb->sb_info.sb_phys, 177811e25f0dSDavid C Somayajulu SB_ALIGNED_SIZE(p_hwfn)); 177911e25f0dSDavid C Somayajulu } 178011e25f0dSDavid C Somayajulu 178111e25f0dSDavid C Somayajulu OSAL_FREE(p_hwfn->p_dev, p_sb); 178211e25f0dSDavid C Somayajulu p_hwfn->p_sp_sb = OSAL_NULL; 178311e25f0dSDavid C Somayajulu } 178411e25f0dSDavid C Somayajulu 178511e25f0dSDavid C Somayajulu static enum _ecore_status_t ecore_int_sp_sb_alloc(struct ecore_hwfn *p_hwfn, 178611e25f0dSDavid C Somayajulu struct ecore_ptt *p_ptt) 178711e25f0dSDavid C Somayajulu { 178811e25f0dSDavid C Somayajulu struct ecore_sb_sp_info *p_sb; 178911e25f0dSDavid C Somayajulu dma_addr_t p_phys = 0; 179011e25f0dSDavid C Somayajulu void *p_virt; 179111e25f0dSDavid C Somayajulu 179211e25f0dSDavid C Somayajulu /* SB struct */ 179311e25f0dSDavid C Somayajulu p_sb = OSAL_ALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_sb)); 179411e25f0dSDavid C Somayajulu if (!p_sb) { 179511e25f0dSDavid C Somayajulu DP_NOTICE(p_hwfn, true, "Failed to allocate `struct ecore_sb_info'\n"); 179611e25f0dSDavid C Somayajulu return ECORE_NOMEM; 179711e25f0dSDavid C Somayajulu } 179811e25f0dSDavid C Somayajulu 179911e25f0dSDavid C Somayajulu /* SB ring */ 180011e25f0dSDavid C Somayajulu p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, 180111e25f0dSDavid C Somayajulu &p_phys, 180211e25f0dSDavid C Somayajulu SB_ALIGNED_SIZE(p_hwfn)); 180311e25f0dSDavid C Somayajulu if (!p_virt) { 180411e25f0dSDavid C Somayajulu DP_NOTICE(p_hwfn, true, "Failed to allocate status block\n"); 180511e25f0dSDavid C Somayajulu OSAL_FREE(p_hwfn->p_dev, p_sb); 180611e25f0dSDavid C Somayajulu return ECORE_NOMEM; 180711e25f0dSDavid C Somayajulu } 180811e25f0dSDavid C Somayajulu 180911e25f0dSDavid C Somayajulu 181011e25f0dSDavid C Somayajulu /* Status Block setup */ 181111e25f0dSDavid C Somayajulu p_hwfn->p_sp_sb = p_sb; 181211e25f0dSDavid C Somayajulu ecore_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, 181311e25f0dSDavid C Somayajulu p_virt, p_phys, ECORE_SP_SB_ID); 181411e25f0dSDavid C Somayajulu 181511e25f0dSDavid C Somayajulu OSAL_MEMSET(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr)); 181611e25f0dSDavid C Somayajulu 181711e25f0dSDavid C Somayajulu return ECORE_SUCCESS; 181811e25f0dSDavid C Somayajulu } 181911e25f0dSDavid C Somayajulu 182011e25f0dSDavid C Somayajulu enum _ecore_status_t ecore_int_register_cb(struct ecore_hwfn *p_hwfn, 182111e25f0dSDavid C Somayajulu ecore_int_comp_cb_t comp_cb, 182211e25f0dSDavid C Somayajulu void *cookie, 182311e25f0dSDavid C Somayajulu u8 *sb_idx, 182411e25f0dSDavid C Somayajulu __le16 **p_fw_cons) 182511e25f0dSDavid C Somayajulu { 182611e25f0dSDavid C Somayajulu struct ecore_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 182711e25f0dSDavid C Somayajulu enum _ecore_status_t rc = ECORE_NOMEM; 182811e25f0dSDavid C Somayajulu u8 pi; 182911e25f0dSDavid C Somayajulu 183011e25f0dSDavid C Somayajulu /* Look for a free index */ 183111e25f0dSDavid C Somayajulu for (pi = 0; pi < OSAL_ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) { 183211e25f0dSDavid C Somayajulu if (p_sp_sb->pi_info_arr[pi].comp_cb != OSAL_NULL) 183311e25f0dSDavid C Somayajulu continue; 183411e25f0dSDavid C Somayajulu 183511e25f0dSDavid C Somayajulu p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb; 183611e25f0dSDavid C Somayajulu p_sp_sb->pi_info_arr[pi].cookie = cookie; 183711e25f0dSDavid C Somayajulu *sb_idx = pi; 183811e25f0dSDavid C Somayajulu *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi]; 183911e25f0dSDavid C Somayajulu rc = ECORE_SUCCESS; 184011e25f0dSDavid C Somayajulu break; 184111e25f0dSDavid C Somayajulu } 184211e25f0dSDavid C Somayajulu 184311e25f0dSDavid C Somayajulu return rc; 184411e25f0dSDavid C Somayajulu } 184511e25f0dSDavid C Somayajulu 184611e25f0dSDavid C Somayajulu enum _ecore_status_t ecore_int_unregister_cb(struct ecore_hwfn *p_hwfn, 184711e25f0dSDavid C Somayajulu u8 pi) 184811e25f0dSDavid C Somayajulu { 184911e25f0dSDavid C Somayajulu struct ecore_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 185011e25f0dSDavid C Somayajulu 185111e25f0dSDavid C Somayajulu if (p_sp_sb->pi_info_arr[pi].comp_cb == OSAL_NULL) 185211e25f0dSDavid C Somayajulu return ECORE_NOMEM; 185311e25f0dSDavid C Somayajulu 185411e25f0dSDavid C Somayajulu p_sp_sb->pi_info_arr[pi].comp_cb = OSAL_NULL; 185511e25f0dSDavid C Somayajulu p_sp_sb->pi_info_arr[pi].cookie = OSAL_NULL; 185611e25f0dSDavid C Somayajulu 185711e25f0dSDavid C Somayajulu return ECORE_SUCCESS; 185811e25f0dSDavid C Somayajulu } 185911e25f0dSDavid C Somayajulu 186011e25f0dSDavid C Somayajulu u16 ecore_int_get_sp_sb_id(struct ecore_hwfn *p_hwfn) 186111e25f0dSDavid C Somayajulu { 186211e25f0dSDavid C Somayajulu return p_hwfn->p_sp_sb->sb_info.igu_sb_id; 186311e25f0dSDavid C Somayajulu } 186411e25f0dSDavid C Somayajulu 186511e25f0dSDavid C Somayajulu void ecore_int_igu_enable_int(struct ecore_hwfn *p_hwfn, 186611e25f0dSDavid C Somayajulu struct ecore_ptt *p_ptt, 186711e25f0dSDavid C Somayajulu enum ecore_int_mode int_mode) 186811e25f0dSDavid C Somayajulu { 186911e25f0dSDavid C Somayajulu u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN; 187011e25f0dSDavid C Somayajulu 187111e25f0dSDavid C Somayajulu #ifndef ASIC_ONLY 187211e25f0dSDavid C Somayajulu if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) { 187311e25f0dSDavid C Somayajulu DP_INFO(p_hwfn, "FPGA - don't enable ATTN generation in IGU\n"); 187411e25f0dSDavid C Somayajulu igu_pf_conf &= ~IGU_PF_CONF_ATTN_BIT_EN; 187511e25f0dSDavid C Somayajulu } 187611e25f0dSDavid C Somayajulu #endif 187711e25f0dSDavid C Somayajulu 187811e25f0dSDavid C Somayajulu p_hwfn->p_dev->int_mode = int_mode; 187911e25f0dSDavid C Somayajulu switch (p_hwfn->p_dev->int_mode) { 188011e25f0dSDavid C Somayajulu case ECORE_INT_MODE_INTA: 188111e25f0dSDavid C Somayajulu igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN; 188211e25f0dSDavid C Somayajulu igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 188311e25f0dSDavid C Somayajulu break; 188411e25f0dSDavid C Somayajulu 188511e25f0dSDavid C Somayajulu case ECORE_INT_MODE_MSI: 188611e25f0dSDavid C Somayajulu igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 188711e25f0dSDavid C Somayajulu igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 188811e25f0dSDavid C Somayajulu break; 188911e25f0dSDavid C Somayajulu 189011e25f0dSDavid C Somayajulu case ECORE_INT_MODE_MSIX: 189111e25f0dSDavid C Somayajulu igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 189211e25f0dSDavid C Somayajulu break; 189311e25f0dSDavid C Somayajulu case ECORE_INT_MODE_POLL: 189411e25f0dSDavid C Somayajulu break; 189511e25f0dSDavid C Somayajulu } 189611e25f0dSDavid C Somayajulu 189711e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf); 189811e25f0dSDavid C Somayajulu } 189911e25f0dSDavid C Somayajulu 190011e25f0dSDavid C Somayajulu static void ecore_int_igu_enable_attn(struct ecore_hwfn *p_hwfn, 190111e25f0dSDavid C Somayajulu struct ecore_ptt *p_ptt) 190211e25f0dSDavid C Somayajulu { 190311e25f0dSDavid C Somayajulu #ifndef ASIC_ONLY 190411e25f0dSDavid C Somayajulu if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) { 190511e25f0dSDavid C Somayajulu DP_INFO(p_hwfn, "FPGA - Don't enable Attentions in IGU and MISC\n"); 190611e25f0dSDavid C Somayajulu return; 190711e25f0dSDavid C Somayajulu } 190811e25f0dSDavid C Somayajulu #endif 190911e25f0dSDavid C Somayajulu 191011e25f0dSDavid C Somayajulu /* Configure AEU signal change to produce attentions */ 191111e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0); 191211e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff); 191311e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff); 191411e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff); 191511e25f0dSDavid C Somayajulu 191611e25f0dSDavid C Somayajulu /* Flush the writes to IGU */ 191711e25f0dSDavid C Somayajulu OSAL_MMIOWB(p_hwfn->p_dev); 191811e25f0dSDavid C Somayajulu 191911e25f0dSDavid C Somayajulu /* Unmask AEU signals toward IGU */ 192011e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff); 192111e25f0dSDavid C Somayajulu } 192211e25f0dSDavid C Somayajulu 192311e25f0dSDavid C Somayajulu enum _ecore_status_t 192411e25f0dSDavid C Somayajulu ecore_int_igu_enable(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 192511e25f0dSDavid C Somayajulu enum ecore_int_mode int_mode) 192611e25f0dSDavid C Somayajulu { 192711e25f0dSDavid C Somayajulu enum _ecore_status_t rc = ECORE_SUCCESS; 192811e25f0dSDavid C Somayajulu u32 tmp; 192911e25f0dSDavid C Somayajulu 193011e25f0dSDavid C Somayajulu /* @@@tmp - Starting with MFW 8.2.1.0 we've started hitting AVS stop 193111e25f0dSDavid C Somayajulu * attentions. Since we're waiting for BRCM answer regarding this 193211e25f0dSDavid C Somayajulu * attention, in the meanwhile we simply mask it. 193311e25f0dSDavid C Somayajulu */ 193411e25f0dSDavid C Somayajulu tmp = ecore_rd(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0); 193511e25f0dSDavid C Somayajulu tmp &= ~0x800; 193611e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0, tmp); 193711e25f0dSDavid C Somayajulu 193811e25f0dSDavid C Somayajulu ecore_int_igu_enable_attn(p_hwfn, p_ptt); 193911e25f0dSDavid C Somayajulu 194011e25f0dSDavid C Somayajulu if ((int_mode != ECORE_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) { 194111e25f0dSDavid C Somayajulu rc = OSAL_SLOWPATH_IRQ_REQ(p_hwfn); 194211e25f0dSDavid C Somayajulu if (rc != ECORE_SUCCESS) { 194311e25f0dSDavid C Somayajulu DP_NOTICE(p_hwfn, true, "Slowpath IRQ request failed\n"); 194411e25f0dSDavid C Somayajulu return ECORE_NORESOURCES; 194511e25f0dSDavid C Somayajulu } 194611e25f0dSDavid C Somayajulu p_hwfn->b_int_requested = true; 194711e25f0dSDavid C Somayajulu } 194811e25f0dSDavid C Somayajulu 194911e25f0dSDavid C Somayajulu /* Enable interrupt Generation */ 195011e25f0dSDavid C Somayajulu ecore_int_igu_enable_int(p_hwfn, p_ptt, int_mode); 195111e25f0dSDavid C Somayajulu 195211e25f0dSDavid C Somayajulu p_hwfn->b_int_enabled = 1; 195311e25f0dSDavid C Somayajulu 195411e25f0dSDavid C Somayajulu return rc; 195511e25f0dSDavid C Somayajulu } 195611e25f0dSDavid C Somayajulu 195711e25f0dSDavid C Somayajulu void ecore_int_igu_disable_int(struct ecore_hwfn *p_hwfn, 195811e25f0dSDavid C Somayajulu struct ecore_ptt *p_ptt) 195911e25f0dSDavid C Somayajulu { 196011e25f0dSDavid C Somayajulu p_hwfn->b_int_enabled = 0; 196111e25f0dSDavid C Somayajulu 196211e25f0dSDavid C Somayajulu if (IS_VF(p_hwfn->p_dev)) 196311e25f0dSDavid C Somayajulu return; 196411e25f0dSDavid C Somayajulu 196511e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0); 196611e25f0dSDavid C Somayajulu } 196711e25f0dSDavid C Somayajulu 196811e25f0dSDavid C Somayajulu #define IGU_CLEANUP_SLEEP_LENGTH (1000) 196911e25f0dSDavid C Somayajulu static void ecore_int_igu_cleanup_sb(struct ecore_hwfn *p_hwfn, 197011e25f0dSDavid C Somayajulu struct ecore_ptt *p_ptt, 197111e25f0dSDavid C Somayajulu u16 igu_sb_id, 197211e25f0dSDavid C Somayajulu bool cleanup_set, 197311e25f0dSDavid C Somayajulu u16 opaque_fid) 197411e25f0dSDavid C Somayajulu { 197511e25f0dSDavid C Somayajulu u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0; 197611e25f0dSDavid C Somayajulu u32 pxp_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id; 197711e25f0dSDavid C Somayajulu u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH; 197811e25f0dSDavid C Somayajulu u8 type = 0; /* FIXME MichalS type??? */ 197911e25f0dSDavid C Somayajulu 198011e25f0dSDavid C Somayajulu OSAL_BUILD_BUG_ON((IGU_REG_CLEANUP_STATUS_4 - 198111e25f0dSDavid C Somayajulu IGU_REG_CLEANUP_STATUS_0) != 0x200); 198211e25f0dSDavid C Somayajulu 198311e25f0dSDavid C Somayajulu /* USE Control Command Register to perform cleanup. There is an 198411e25f0dSDavid C Somayajulu * option to do this using IGU bar, but then it can't be used for VFs. 198511e25f0dSDavid C Somayajulu */ 198611e25f0dSDavid C Somayajulu 198711e25f0dSDavid C Somayajulu /* Set the data field */ 198811e25f0dSDavid C Somayajulu SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0); 198911e25f0dSDavid C Somayajulu SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, type); 199011e25f0dSDavid C Somayajulu SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET); 199111e25f0dSDavid C Somayajulu 199211e25f0dSDavid C Somayajulu /* Set the control register */ 199311e25f0dSDavid C Somayajulu SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr); 199411e25f0dSDavid C Somayajulu SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid); 199511e25f0dSDavid C Somayajulu SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR); 199611e25f0dSDavid C Somayajulu 199711e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data); 199811e25f0dSDavid C Somayajulu 199911e25f0dSDavid C Somayajulu OSAL_BARRIER(p_hwfn->p_dev); 200011e25f0dSDavid C Somayajulu 200111e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl); 200211e25f0dSDavid C Somayajulu 200311e25f0dSDavid C Somayajulu /* Flush the write to IGU */ 200411e25f0dSDavid C Somayajulu OSAL_MMIOWB(p_hwfn->p_dev); 200511e25f0dSDavid C Somayajulu 200611e25f0dSDavid C Somayajulu /* calculate where to read the status bit from */ 200711e25f0dSDavid C Somayajulu sb_bit = 1 << (igu_sb_id % 32); 200811e25f0dSDavid C Somayajulu sb_bit_addr = igu_sb_id / 32 * sizeof(u32); 200911e25f0dSDavid C Somayajulu 201011e25f0dSDavid C Somayajulu sb_bit_addr += IGU_REG_CLEANUP_STATUS_0 + (0x80 * type); 201111e25f0dSDavid C Somayajulu 201211e25f0dSDavid C Somayajulu /* Now wait for the command to complete */ 201311e25f0dSDavid C Somayajulu while (--sleep_cnt) { 201411e25f0dSDavid C Somayajulu val = ecore_rd(p_hwfn, p_ptt, sb_bit_addr); 201511e25f0dSDavid C Somayajulu if ((val & sb_bit) == (cleanup_set ? sb_bit : 0)) 201611e25f0dSDavid C Somayajulu break; 201711e25f0dSDavid C Somayajulu OSAL_MSLEEP(5); 201811e25f0dSDavid C Somayajulu } 201911e25f0dSDavid C Somayajulu 202011e25f0dSDavid C Somayajulu if (!sleep_cnt) 202111e25f0dSDavid C Somayajulu DP_NOTICE(p_hwfn, true, 202211e25f0dSDavid C Somayajulu "Timeout waiting for clear status 0x%08x [for sb %d]\n", 202311e25f0dSDavid C Somayajulu val, igu_sb_id); 202411e25f0dSDavid C Somayajulu } 202511e25f0dSDavid C Somayajulu 202611e25f0dSDavid C Somayajulu void ecore_int_igu_init_pure_rt_single(struct ecore_hwfn *p_hwfn, 202711e25f0dSDavid C Somayajulu struct ecore_ptt *p_ptt, 202811e25f0dSDavid C Somayajulu u16 igu_sb_id, u16 opaque, bool b_set) 202911e25f0dSDavid C Somayajulu { 203011e25f0dSDavid C Somayajulu struct ecore_igu_block *p_block; 203111e25f0dSDavid C Somayajulu int pi, i; 203211e25f0dSDavid C Somayajulu 203311e25f0dSDavid C Somayajulu p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id]; 203411e25f0dSDavid C Somayajulu DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, 203511e25f0dSDavid C Somayajulu "Cleaning SB [%04x]: func_id= %d is_pf = %d vector_num = 0x%0x\n", 203611e25f0dSDavid C Somayajulu igu_sb_id, p_block->function_id, p_block->is_pf, 203711e25f0dSDavid C Somayajulu p_block->vector_number); 203811e25f0dSDavid C Somayajulu 203911e25f0dSDavid C Somayajulu /* Set */ 204011e25f0dSDavid C Somayajulu if (b_set) 204111e25f0dSDavid C Somayajulu ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque); 204211e25f0dSDavid C Somayajulu 204311e25f0dSDavid C Somayajulu /* Clear */ 204411e25f0dSDavid C Somayajulu ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque); 204511e25f0dSDavid C Somayajulu 204611e25f0dSDavid C Somayajulu /* Wait for the IGU SB to cleanup */ 204711e25f0dSDavid C Somayajulu for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) { 204811e25f0dSDavid C Somayajulu u32 val; 204911e25f0dSDavid C Somayajulu 205011e25f0dSDavid C Somayajulu val = ecore_rd(p_hwfn, p_ptt, 205111e25f0dSDavid C Somayajulu IGU_REG_WRITE_DONE_PENDING + 205211e25f0dSDavid C Somayajulu ((igu_sb_id / 32) * 4)); 205311e25f0dSDavid C Somayajulu if (val & (1 << (igu_sb_id % 32))) 205411e25f0dSDavid C Somayajulu OSAL_UDELAY(10); 205511e25f0dSDavid C Somayajulu else 205611e25f0dSDavid C Somayajulu break; 205711e25f0dSDavid C Somayajulu } 205811e25f0dSDavid C Somayajulu if (i == IGU_CLEANUP_SLEEP_LENGTH) 205911e25f0dSDavid C Somayajulu DP_NOTICE(p_hwfn, true, 206011e25f0dSDavid C Somayajulu "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n", 206111e25f0dSDavid C Somayajulu igu_sb_id); 206211e25f0dSDavid C Somayajulu 206311e25f0dSDavid C Somayajulu /* Clear the CAU for the SB */ 206411e25f0dSDavid C Somayajulu for (pi = 0; pi < 12; pi++) 206511e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_ptt, 206611e25f0dSDavid C Somayajulu CAU_REG_PI_MEMORY + (igu_sb_id * 12 + pi) * 4, 0); 206711e25f0dSDavid C Somayajulu } 206811e25f0dSDavid C Somayajulu 206911e25f0dSDavid C Somayajulu void ecore_int_igu_init_pure_rt(struct ecore_hwfn *p_hwfn, 207011e25f0dSDavid C Somayajulu struct ecore_ptt *p_ptt, 207111e25f0dSDavid C Somayajulu bool b_set, 207211e25f0dSDavid C Somayajulu bool b_slowpath) 207311e25f0dSDavid C Somayajulu { 207411e25f0dSDavid C Somayajulu struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 207511e25f0dSDavid C Somayajulu struct ecore_igu_block *p_block; 207611e25f0dSDavid C Somayajulu u16 igu_sb_id = 0; 207711e25f0dSDavid C Somayajulu u32 val = 0; 207811e25f0dSDavid C Somayajulu 207911e25f0dSDavid C Somayajulu /* @@@TBD MichalK temporary... should be moved to init-tool... */ 208011e25f0dSDavid C Somayajulu val = ecore_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION); 208111e25f0dSDavid C Somayajulu val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN; 208211e25f0dSDavid C Somayajulu val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN; 208311e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val); 208411e25f0dSDavid C Somayajulu /* end temporary */ 208511e25f0dSDavid C Somayajulu 208611e25f0dSDavid C Somayajulu for (igu_sb_id = 0; 208711e25f0dSDavid C Somayajulu igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev); 208811e25f0dSDavid C Somayajulu igu_sb_id++) { 208911e25f0dSDavid C Somayajulu p_block = &p_info->entry[igu_sb_id]; 209011e25f0dSDavid C Somayajulu 209111e25f0dSDavid C Somayajulu if (!(p_block->status & ECORE_IGU_STATUS_VALID) || 209211e25f0dSDavid C Somayajulu !p_block->is_pf || 209311e25f0dSDavid C Somayajulu (p_block->status & ECORE_IGU_STATUS_DSB)) 209411e25f0dSDavid C Somayajulu continue; 209511e25f0dSDavid C Somayajulu 209611e25f0dSDavid C Somayajulu ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id, 209711e25f0dSDavid C Somayajulu p_hwfn->hw_info.opaque_fid, 209811e25f0dSDavid C Somayajulu b_set); 209911e25f0dSDavid C Somayajulu } 210011e25f0dSDavid C Somayajulu 210111e25f0dSDavid C Somayajulu if (b_slowpath) 210211e25f0dSDavid C Somayajulu ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt, 210311e25f0dSDavid C Somayajulu p_info->igu_dsb_id, 210411e25f0dSDavid C Somayajulu p_hwfn->hw_info.opaque_fid, 210511e25f0dSDavid C Somayajulu b_set); 210611e25f0dSDavid C Somayajulu } 210711e25f0dSDavid C Somayajulu 210811e25f0dSDavid C Somayajulu int ecore_int_igu_reset_cam(struct ecore_hwfn *p_hwfn, 210911e25f0dSDavid C Somayajulu struct ecore_ptt *p_ptt) 211011e25f0dSDavid C Somayajulu { 211111e25f0dSDavid C Somayajulu struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 211211e25f0dSDavid C Somayajulu struct ecore_igu_block *p_block; 211311e25f0dSDavid C Somayajulu int pf_sbs, vf_sbs; 211411e25f0dSDavid C Somayajulu u16 igu_sb_id; 211511e25f0dSDavid C Somayajulu u32 val, rval; 211611e25f0dSDavid C Somayajulu 211711e25f0dSDavid C Somayajulu if (!RESC_NUM(p_hwfn, ECORE_SB)) { 211811e25f0dSDavid C Somayajulu /* We're using an old MFW - have to prevent any switching 211911e25f0dSDavid C Somayajulu * of SBs between PF and VFs as later driver wouldn't be 212011e25f0dSDavid C Somayajulu * able to tell which belongs to which. 212111e25f0dSDavid C Somayajulu */ 212211e25f0dSDavid C Somayajulu p_info->b_allow_pf_vf_change = false; 212311e25f0dSDavid C Somayajulu } else { 212411e25f0dSDavid C Somayajulu /* Use the numbers the MFW have provided - 212511e25f0dSDavid C Somayajulu * don't forget MFW accounts for the default SB as well. 212611e25f0dSDavid C Somayajulu */ 212711e25f0dSDavid C Somayajulu p_info->b_allow_pf_vf_change = true; 212811e25f0dSDavid C Somayajulu 212911e25f0dSDavid C Somayajulu if (p_info->usage.cnt != RESC_NUM(p_hwfn, ECORE_SB) - 1) { 213011e25f0dSDavid C Somayajulu DP_INFO(p_hwfn, 213111e25f0dSDavid C Somayajulu "MFW notifies of 0x%04x PF SBs; IGU indicates of only 0x%04x\n", 213211e25f0dSDavid C Somayajulu RESC_NUM(p_hwfn, ECORE_SB) - 1, 213311e25f0dSDavid C Somayajulu p_info->usage.cnt); 213411e25f0dSDavid C Somayajulu p_info->usage.cnt = RESC_NUM(p_hwfn, ECORE_SB) - 1; 213511e25f0dSDavid C Somayajulu } 213611e25f0dSDavid C Somayajulu 213711e25f0dSDavid C Somayajulu /* TODO - how do we learn about VF SBs from MFW? */ 213811e25f0dSDavid C Somayajulu if (IS_PF_SRIOV(p_hwfn)) { 213911e25f0dSDavid C Somayajulu u16 vfs = p_hwfn->p_dev->p_iov_info->total_vfs; 214011e25f0dSDavid C Somayajulu 214111e25f0dSDavid C Somayajulu if (vfs != p_info->usage.iov_cnt) 214211e25f0dSDavid C Somayajulu DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, 214311e25f0dSDavid C Somayajulu "0x%04x VF SBs in IGU CAM != PCI configuration 0x%04x\n", 214411e25f0dSDavid C Somayajulu p_info->usage.iov_cnt, vfs); 214511e25f0dSDavid C Somayajulu 214611e25f0dSDavid C Somayajulu /* At this point we know how many SBs we have totally 214711e25f0dSDavid C Somayajulu * in IGU + number of PF SBs. So we can validate that 214811e25f0dSDavid C Somayajulu * we'd have sufficient for VF. 214911e25f0dSDavid C Somayajulu */ 215011e25f0dSDavid C Somayajulu if (vfs > p_info->usage.free_cnt + 215111e25f0dSDavid C Somayajulu p_info->usage.free_cnt_iov - 215211e25f0dSDavid C Somayajulu p_info->usage.cnt) { 215311e25f0dSDavid C Somayajulu DP_NOTICE(p_hwfn, true, 215411e25f0dSDavid C Somayajulu "Not enough SBs for VFs - 0x%04x SBs, from which %04x PFs and %04x are required\n", 215511e25f0dSDavid C Somayajulu p_info->usage.free_cnt + 215611e25f0dSDavid C Somayajulu p_info->usage.free_cnt_iov, 215711e25f0dSDavid C Somayajulu p_info->usage.cnt, vfs); 215811e25f0dSDavid C Somayajulu return ECORE_INVAL; 215911e25f0dSDavid C Somayajulu } 216011e25f0dSDavid C Somayajulu 216111e25f0dSDavid C Somayajulu /* Currently cap the number of VFs SBs by the 216211e25f0dSDavid C Somayajulu * number of VFs. 216311e25f0dSDavid C Somayajulu */ 216411e25f0dSDavid C Somayajulu p_info->usage.iov_cnt = vfs; 216511e25f0dSDavid C Somayajulu } 216611e25f0dSDavid C Somayajulu } 216711e25f0dSDavid C Somayajulu 216811e25f0dSDavid C Somayajulu /* Mark all SBs as free, now in the right PF/VFs division */ 216911e25f0dSDavid C Somayajulu p_info->usage.free_cnt = p_info->usage.cnt; 217011e25f0dSDavid C Somayajulu p_info->usage.free_cnt_iov = p_info->usage.iov_cnt; 217111e25f0dSDavid C Somayajulu p_info->usage.orig = p_info->usage.cnt; 217211e25f0dSDavid C Somayajulu p_info->usage.iov_orig = p_info->usage.iov_cnt; 217311e25f0dSDavid C Somayajulu 217411e25f0dSDavid C Somayajulu /* We now proceed to re-configure the IGU cam to reflect the initial 217511e25f0dSDavid C Somayajulu * configuration. We can start with the Default SB. 217611e25f0dSDavid C Somayajulu */ 217711e25f0dSDavid C Somayajulu pf_sbs = p_info->usage.cnt; 217811e25f0dSDavid C Somayajulu vf_sbs = p_info->usage.iov_cnt; 217911e25f0dSDavid C Somayajulu 218011e25f0dSDavid C Somayajulu for (igu_sb_id = p_info->igu_dsb_id; 218111e25f0dSDavid C Somayajulu igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev); 218211e25f0dSDavid C Somayajulu igu_sb_id++) { 218311e25f0dSDavid C Somayajulu p_block = &p_info->entry[igu_sb_id]; 218411e25f0dSDavid C Somayajulu val = 0; 218511e25f0dSDavid C Somayajulu 218611e25f0dSDavid C Somayajulu if (!(p_block->status & ECORE_IGU_STATUS_VALID)) 218711e25f0dSDavid C Somayajulu continue; 218811e25f0dSDavid C Somayajulu 218911e25f0dSDavid C Somayajulu if (p_block->status & ECORE_IGU_STATUS_DSB) { 219011e25f0dSDavid C Somayajulu p_block->function_id = p_hwfn->rel_pf_id; 219111e25f0dSDavid C Somayajulu p_block->is_pf = 1; 219211e25f0dSDavid C Somayajulu p_block->vector_number = 0; 219311e25f0dSDavid C Somayajulu p_block->status = ECORE_IGU_STATUS_VALID | 219411e25f0dSDavid C Somayajulu ECORE_IGU_STATUS_PF | 219511e25f0dSDavid C Somayajulu ECORE_IGU_STATUS_DSB; 219611e25f0dSDavid C Somayajulu } else if (pf_sbs) { 219711e25f0dSDavid C Somayajulu pf_sbs--; 219811e25f0dSDavid C Somayajulu p_block->function_id = p_hwfn->rel_pf_id; 219911e25f0dSDavid C Somayajulu p_block->is_pf = 1; 220011e25f0dSDavid C Somayajulu p_block->vector_number = p_info->usage.cnt - pf_sbs; 220111e25f0dSDavid C Somayajulu p_block->status = ECORE_IGU_STATUS_VALID | 220211e25f0dSDavid C Somayajulu ECORE_IGU_STATUS_PF | 220311e25f0dSDavid C Somayajulu ECORE_IGU_STATUS_FREE; 220411e25f0dSDavid C Somayajulu } else if (vf_sbs) { 220511e25f0dSDavid C Somayajulu p_block->function_id = 220611e25f0dSDavid C Somayajulu p_hwfn->p_dev->p_iov_info->first_vf_in_pf + 220711e25f0dSDavid C Somayajulu p_info->usage.iov_cnt - vf_sbs; 220811e25f0dSDavid C Somayajulu p_block->is_pf = 0; 220911e25f0dSDavid C Somayajulu p_block->vector_number = 0; 221011e25f0dSDavid C Somayajulu p_block->status = ECORE_IGU_STATUS_VALID | 221111e25f0dSDavid C Somayajulu ECORE_IGU_STATUS_FREE; 221211e25f0dSDavid C Somayajulu vf_sbs--; 221311e25f0dSDavid C Somayajulu } else { 221411e25f0dSDavid C Somayajulu p_block->function_id = 0; 221511e25f0dSDavid C Somayajulu p_block->is_pf = 0; 221611e25f0dSDavid C Somayajulu p_block->vector_number = 0; 221711e25f0dSDavid C Somayajulu } 221811e25f0dSDavid C Somayajulu 221911e25f0dSDavid C Somayajulu SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER, 222011e25f0dSDavid C Somayajulu p_block->function_id); 222111e25f0dSDavid C Somayajulu SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf); 222211e25f0dSDavid C Somayajulu SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER, 222311e25f0dSDavid C Somayajulu p_block->vector_number); 222411e25f0dSDavid C Somayajulu 222511e25f0dSDavid C Somayajulu /* VF entries would be enabled when VF is initializaed */ 222611e25f0dSDavid C Somayajulu SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf); 222711e25f0dSDavid C Somayajulu 222811e25f0dSDavid C Somayajulu rval = ecore_rd(p_hwfn, p_ptt, 222911e25f0dSDavid C Somayajulu IGU_REG_MAPPING_MEMORY + 223011e25f0dSDavid C Somayajulu sizeof(u32) * igu_sb_id); 223111e25f0dSDavid C Somayajulu 223211e25f0dSDavid C Somayajulu if (rval != val) { 223311e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_ptt, 223411e25f0dSDavid C Somayajulu IGU_REG_MAPPING_MEMORY + 223511e25f0dSDavid C Somayajulu sizeof(u32) * igu_sb_id, 223611e25f0dSDavid C Somayajulu val); 223711e25f0dSDavid C Somayajulu 223811e25f0dSDavid C Somayajulu DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, 223911e25f0dSDavid C Somayajulu "IGU reset: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x [%08x -> %08x]\n", 224011e25f0dSDavid C Somayajulu igu_sb_id, p_block->function_id, 224111e25f0dSDavid C Somayajulu p_block->is_pf, p_block->vector_number, 224211e25f0dSDavid C Somayajulu rval, val); 224311e25f0dSDavid C Somayajulu } 224411e25f0dSDavid C Somayajulu } 224511e25f0dSDavid C Somayajulu 224611e25f0dSDavid C Somayajulu return 0; 224711e25f0dSDavid C Somayajulu } 224811e25f0dSDavid C Somayajulu 224911e25f0dSDavid C Somayajulu int ecore_int_igu_reset_cam_default(struct ecore_hwfn *p_hwfn, 225011e25f0dSDavid C Somayajulu struct ecore_ptt *p_ptt) 225111e25f0dSDavid C Somayajulu { 225211e25f0dSDavid C Somayajulu struct ecore_sb_cnt_info *p_cnt = &p_hwfn->hw_info.p_igu_info->usage; 225311e25f0dSDavid C Somayajulu 225411e25f0dSDavid C Somayajulu /* Return all the usage indications to default prior to the reset; 225511e25f0dSDavid C Somayajulu * The reset expects the !orig to reflect the initial status of the 225611e25f0dSDavid C Somayajulu * SBs, and would re-calculate the originals based on those. 225711e25f0dSDavid C Somayajulu */ 225811e25f0dSDavid C Somayajulu p_cnt->cnt = p_cnt->orig; 225911e25f0dSDavid C Somayajulu p_cnt->free_cnt = p_cnt->orig; 226011e25f0dSDavid C Somayajulu p_cnt->iov_cnt = p_cnt->iov_orig; 226111e25f0dSDavid C Somayajulu p_cnt->free_cnt_iov = p_cnt->iov_orig; 226211e25f0dSDavid C Somayajulu p_cnt->orig = 0; 226311e25f0dSDavid C Somayajulu p_cnt->iov_orig = 0; 226411e25f0dSDavid C Somayajulu 226511e25f0dSDavid C Somayajulu /* TODO - we probably need to re-configure the CAU as well... */ 226611e25f0dSDavid C Somayajulu return ecore_int_igu_reset_cam(p_hwfn, p_ptt); 226711e25f0dSDavid C Somayajulu } 226811e25f0dSDavid C Somayajulu 226911e25f0dSDavid C Somayajulu static void ecore_int_igu_read_cam_block(struct ecore_hwfn *p_hwfn, 227011e25f0dSDavid C Somayajulu struct ecore_ptt *p_ptt, 227111e25f0dSDavid C Somayajulu u16 igu_sb_id) 227211e25f0dSDavid C Somayajulu { 227311e25f0dSDavid C Somayajulu u32 val = ecore_rd(p_hwfn, p_ptt, 227411e25f0dSDavid C Somayajulu IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id); 227511e25f0dSDavid C Somayajulu struct ecore_igu_block *p_block; 227611e25f0dSDavid C Somayajulu 227711e25f0dSDavid C Somayajulu p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id]; 227811e25f0dSDavid C Somayajulu 227911e25f0dSDavid C Somayajulu /* Fill the block information */ 228011e25f0dSDavid C Somayajulu p_block->function_id = GET_FIELD(val, 228111e25f0dSDavid C Somayajulu IGU_MAPPING_LINE_FUNCTION_NUMBER); 228211e25f0dSDavid C Somayajulu p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID); 228311e25f0dSDavid C Somayajulu p_block->vector_number = GET_FIELD(val, 228411e25f0dSDavid C Somayajulu IGU_MAPPING_LINE_VECTOR_NUMBER); 228511e25f0dSDavid C Somayajulu p_block->igu_sb_id = igu_sb_id; 228611e25f0dSDavid C Somayajulu } 228711e25f0dSDavid C Somayajulu 228811e25f0dSDavid C Somayajulu enum _ecore_status_t ecore_int_igu_read_cam(struct ecore_hwfn *p_hwfn, 228911e25f0dSDavid C Somayajulu struct ecore_ptt *p_ptt) 229011e25f0dSDavid C Somayajulu { 229111e25f0dSDavid C Somayajulu struct ecore_igu_info *p_igu_info; 229211e25f0dSDavid C Somayajulu struct ecore_igu_block *p_block; 229311e25f0dSDavid C Somayajulu u32 min_vf = 0, max_vf = 0; 229411e25f0dSDavid C Somayajulu u16 igu_sb_id; 229511e25f0dSDavid C Somayajulu 229611e25f0dSDavid C Somayajulu p_hwfn->hw_info.p_igu_info = OSAL_ZALLOC(p_hwfn->p_dev, 229711e25f0dSDavid C Somayajulu GFP_KERNEL, 229811e25f0dSDavid C Somayajulu sizeof(*p_igu_info)); 229911e25f0dSDavid C Somayajulu if (!p_hwfn->hw_info.p_igu_info) 230011e25f0dSDavid C Somayajulu return ECORE_NOMEM; 230111e25f0dSDavid C Somayajulu p_igu_info = p_hwfn->hw_info.p_igu_info; 230211e25f0dSDavid C Somayajulu 230311e25f0dSDavid C Somayajulu /* Distinguish between existent and onn-existent default SB */ 230411e25f0dSDavid C Somayajulu p_igu_info->igu_dsb_id = ECORE_SB_INVALID_IDX; 230511e25f0dSDavid C Somayajulu 230611e25f0dSDavid C Somayajulu /* Find the range of VF ids whose SB belong to this PF */ 230711e25f0dSDavid C Somayajulu if (p_hwfn->p_dev->p_iov_info) { 230811e25f0dSDavid C Somayajulu struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info; 230911e25f0dSDavid C Somayajulu 231011e25f0dSDavid C Somayajulu min_vf = p_iov->first_vf_in_pf; 231111e25f0dSDavid C Somayajulu max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs; 231211e25f0dSDavid C Somayajulu } 231311e25f0dSDavid C Somayajulu 231411e25f0dSDavid C Somayajulu for (igu_sb_id = 0; 231511e25f0dSDavid C Somayajulu igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev); 231611e25f0dSDavid C Somayajulu igu_sb_id++) { 231711e25f0dSDavid C Somayajulu /* Read current entry; Notice it might not belong to this PF */ 231811e25f0dSDavid C Somayajulu ecore_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id); 231911e25f0dSDavid C Somayajulu p_block = &p_igu_info->entry[igu_sb_id]; 232011e25f0dSDavid C Somayajulu 232111e25f0dSDavid C Somayajulu if ((p_block->is_pf) && 232211e25f0dSDavid C Somayajulu (p_block->function_id == p_hwfn->rel_pf_id)) { 232311e25f0dSDavid C Somayajulu p_block->status = ECORE_IGU_STATUS_PF | 232411e25f0dSDavid C Somayajulu ECORE_IGU_STATUS_VALID | 232511e25f0dSDavid C Somayajulu ECORE_IGU_STATUS_FREE; 232611e25f0dSDavid C Somayajulu 232711e25f0dSDavid C Somayajulu if (p_igu_info->igu_dsb_id != ECORE_SB_INVALID_IDX) 232811e25f0dSDavid C Somayajulu p_igu_info->usage.cnt++; 232911e25f0dSDavid C Somayajulu } else if (!(p_block->is_pf) && 233011e25f0dSDavid C Somayajulu (p_block->function_id >= min_vf) && 233111e25f0dSDavid C Somayajulu (p_block->function_id < max_vf)) { 233211e25f0dSDavid C Somayajulu /* Available for VFs of this PF */ 233311e25f0dSDavid C Somayajulu p_block->status = ECORE_IGU_STATUS_VALID | 233411e25f0dSDavid C Somayajulu ECORE_IGU_STATUS_FREE; 233511e25f0dSDavid C Somayajulu 233611e25f0dSDavid C Somayajulu if (p_igu_info->igu_dsb_id != ECORE_SB_INVALID_IDX) 233711e25f0dSDavid C Somayajulu p_igu_info->usage.iov_cnt++; 233811e25f0dSDavid C Somayajulu } 233911e25f0dSDavid C Somayajulu 234011e25f0dSDavid C Somayajulu /* Mark the First entry belonging to the PF or its VFs 234111e25f0dSDavid C Somayajulu * as the default SB [we'll reset IGU prior to first usage]. 234211e25f0dSDavid C Somayajulu */ 234311e25f0dSDavid C Somayajulu if ((p_block->status & ECORE_IGU_STATUS_VALID) && 234411e25f0dSDavid C Somayajulu (p_igu_info->igu_dsb_id == ECORE_SB_INVALID_IDX)) { 234511e25f0dSDavid C Somayajulu p_igu_info->igu_dsb_id = igu_sb_id; 234611e25f0dSDavid C Somayajulu p_block->status |= ECORE_IGU_STATUS_DSB; 234711e25f0dSDavid C Somayajulu } 234811e25f0dSDavid C Somayajulu 234911e25f0dSDavid C Somayajulu /* While this isn't suitable for all clients, limit number 235011e25f0dSDavid C Somayajulu * of prints by having each PF print only its entries with the 235111e25f0dSDavid C Somayajulu * exception of PF0 which would print everything. 235211e25f0dSDavid C Somayajulu */ 235311e25f0dSDavid C Somayajulu if ((p_block->status & ECORE_IGU_STATUS_VALID) || 235411e25f0dSDavid C Somayajulu (p_hwfn->abs_pf_id == 0)) 235511e25f0dSDavid C Somayajulu DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, 235611e25f0dSDavid C Somayajulu "IGU_BLOCK: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n", 235711e25f0dSDavid C Somayajulu igu_sb_id, p_block->function_id, 235811e25f0dSDavid C Somayajulu p_block->is_pf, p_block->vector_number); 235911e25f0dSDavid C Somayajulu } 236011e25f0dSDavid C Somayajulu 236111e25f0dSDavid C Somayajulu if (p_igu_info->igu_dsb_id == ECORE_SB_INVALID_IDX) { 236211e25f0dSDavid C Somayajulu DP_NOTICE(p_hwfn, true, 236311e25f0dSDavid C Somayajulu "IGU CAM returned invalid values igu_dsb_id=0x%x\n", 236411e25f0dSDavid C Somayajulu p_igu_info->igu_dsb_id); 236511e25f0dSDavid C Somayajulu return ECORE_INVAL; 236611e25f0dSDavid C Somayajulu } 236711e25f0dSDavid C Somayajulu 236811e25f0dSDavid C Somayajulu /* All non default SB are considered free at this point */ 236911e25f0dSDavid C Somayajulu p_igu_info->usage.free_cnt = p_igu_info->usage.cnt; 237011e25f0dSDavid C Somayajulu p_igu_info->usage.free_cnt_iov = p_igu_info->usage.iov_cnt; 237111e25f0dSDavid C Somayajulu 237211e25f0dSDavid C Somayajulu DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, 237311e25f0dSDavid C Somayajulu "igu_dsb_id=0x%x, num Free SBs - PF: %04x VF: %04x [might change after resource allocation]\n", 237411e25f0dSDavid C Somayajulu p_igu_info->igu_dsb_id, p_igu_info->usage.cnt, 237511e25f0dSDavid C Somayajulu p_igu_info->usage.iov_cnt); 237611e25f0dSDavid C Somayajulu 237711e25f0dSDavid C Somayajulu return ECORE_SUCCESS; 237811e25f0dSDavid C Somayajulu } 237911e25f0dSDavid C Somayajulu 238011e25f0dSDavid C Somayajulu enum _ecore_status_t 238111e25f0dSDavid C Somayajulu ecore_int_igu_relocate_sb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 238211e25f0dSDavid C Somayajulu u16 sb_id, bool b_to_vf) 238311e25f0dSDavid C Somayajulu { 238411e25f0dSDavid C Somayajulu struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 238511e25f0dSDavid C Somayajulu struct ecore_igu_block *p_block = OSAL_NULL; 238611e25f0dSDavid C Somayajulu u16 igu_sb_id = 0, vf_num = 0; 238711e25f0dSDavid C Somayajulu u32 val = 0; 238811e25f0dSDavid C Somayajulu 238911e25f0dSDavid C Somayajulu if (IS_VF(p_hwfn->p_dev) || !IS_PF_SRIOV(p_hwfn)) 239011e25f0dSDavid C Somayajulu return ECORE_INVAL; 239111e25f0dSDavid C Somayajulu 239211e25f0dSDavid C Somayajulu if (sb_id == ECORE_SP_SB_ID) 239311e25f0dSDavid C Somayajulu return ECORE_INVAL; 239411e25f0dSDavid C Somayajulu 239511e25f0dSDavid C Somayajulu if (!p_info->b_allow_pf_vf_change) { 239611e25f0dSDavid C Somayajulu DP_INFO(p_hwfn, "Can't relocate SBs as MFW is too old.\n"); 239711e25f0dSDavid C Somayajulu return ECORE_INVAL; 239811e25f0dSDavid C Somayajulu } 239911e25f0dSDavid C Somayajulu 240011e25f0dSDavid C Somayajulu /* If we're moving a SB from PF to VF, the client had to specify 240111e25f0dSDavid C Somayajulu * which vector it wants to move. 240211e25f0dSDavid C Somayajulu */ 240311e25f0dSDavid C Somayajulu if (b_to_vf) { 240411e25f0dSDavid C Somayajulu igu_sb_id = ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1); 240511e25f0dSDavid C Somayajulu if (igu_sb_id == ECORE_SB_INVALID_IDX) 240611e25f0dSDavid C Somayajulu return ECORE_INVAL; 240711e25f0dSDavid C Somayajulu } 240811e25f0dSDavid C Somayajulu 240911e25f0dSDavid C Somayajulu /* If we're moving a SB from VF to PF, need to validate there isn't 241011e25f0dSDavid C Somayajulu * already a line configured for that vector. 241111e25f0dSDavid C Somayajulu */ 241211e25f0dSDavid C Somayajulu if (!b_to_vf) { 241311e25f0dSDavid C Somayajulu if (ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1) != 241411e25f0dSDavid C Somayajulu ECORE_SB_INVALID_IDX) 241511e25f0dSDavid C Somayajulu return ECORE_INVAL; 241611e25f0dSDavid C Somayajulu } 241711e25f0dSDavid C Somayajulu 241811e25f0dSDavid C Somayajulu /* We need to validate that the SB can actually be relocated. 241911e25f0dSDavid C Somayajulu * This would also handle the previous case where we've explicitly 242011e25f0dSDavid C Somayajulu * stated which IGU SB needs to move. 242111e25f0dSDavid C Somayajulu */ 242211e25f0dSDavid C Somayajulu for (; igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev); 242311e25f0dSDavid C Somayajulu igu_sb_id++) { 242411e25f0dSDavid C Somayajulu p_block = &p_info->entry[igu_sb_id]; 242511e25f0dSDavid C Somayajulu 242611e25f0dSDavid C Somayajulu if (!(p_block->status & ECORE_IGU_STATUS_VALID) || 242711e25f0dSDavid C Somayajulu !(p_block->status & ECORE_IGU_STATUS_FREE) || 242811e25f0dSDavid C Somayajulu (!!(p_block->status & ECORE_IGU_STATUS_PF) != b_to_vf)) { 242911e25f0dSDavid C Somayajulu if (b_to_vf) 243011e25f0dSDavid C Somayajulu return ECORE_INVAL; 243111e25f0dSDavid C Somayajulu else 243211e25f0dSDavid C Somayajulu continue; 243311e25f0dSDavid C Somayajulu } 243411e25f0dSDavid C Somayajulu 243511e25f0dSDavid C Somayajulu break; 243611e25f0dSDavid C Somayajulu } 243711e25f0dSDavid C Somayajulu 243811e25f0dSDavid C Somayajulu if (igu_sb_id == ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev)) { 243911e25f0dSDavid C Somayajulu DP_VERBOSE(p_hwfn, (ECORE_MSG_INTR | ECORE_MSG_IOV), 244011e25f0dSDavid C Somayajulu "Failed to find a free SB to move\n"); 244111e25f0dSDavid C Somayajulu return ECORE_INVAL; 244211e25f0dSDavid C Somayajulu } 244311e25f0dSDavid C Somayajulu 244411e25f0dSDavid C Somayajulu /* At this point, p_block points to the SB we want to relocate */ 244511e25f0dSDavid C Somayajulu if (b_to_vf) { 244611e25f0dSDavid C Somayajulu p_block->status &= ~ECORE_IGU_STATUS_PF; 244711e25f0dSDavid C Somayajulu 244811e25f0dSDavid C Somayajulu /* It doesn't matter which VF number we choose, since we're 244911e25f0dSDavid C Somayajulu * going to disable the line; But let's keep it in range. 245011e25f0dSDavid C Somayajulu */ 245111e25f0dSDavid C Somayajulu vf_num = (u16)p_hwfn->p_dev->p_iov_info->first_vf_in_pf; 245211e25f0dSDavid C Somayajulu 245311e25f0dSDavid C Somayajulu p_block->function_id = (u8)vf_num; 245411e25f0dSDavid C Somayajulu p_block->is_pf = 0; 245511e25f0dSDavid C Somayajulu p_block->vector_number = 0; 245611e25f0dSDavid C Somayajulu 245711e25f0dSDavid C Somayajulu p_info->usage.cnt--; 245811e25f0dSDavid C Somayajulu p_info->usage.free_cnt--; 245911e25f0dSDavid C Somayajulu p_info->usage.iov_cnt++; 246011e25f0dSDavid C Somayajulu p_info->usage.free_cnt_iov++; 246111e25f0dSDavid C Somayajulu 246211e25f0dSDavid C Somayajulu /* TODO - if SBs aren't really the limiting factor, 246311e25f0dSDavid C Somayajulu * then it might not be accurate [in the since that 246411e25f0dSDavid C Somayajulu * we might not need decrement the feature]. 246511e25f0dSDavid C Somayajulu */ 246611e25f0dSDavid C Somayajulu p_hwfn->hw_info.feat_num[ECORE_PF_L2_QUE]--; 246711e25f0dSDavid C Somayajulu p_hwfn->hw_info.feat_num[ECORE_VF_L2_QUE]++; 246811e25f0dSDavid C Somayajulu } else { 246911e25f0dSDavid C Somayajulu p_block->status |= ECORE_IGU_STATUS_PF; 247011e25f0dSDavid C Somayajulu p_block->function_id = p_hwfn->rel_pf_id; 247111e25f0dSDavid C Somayajulu p_block->is_pf = 1; 247211e25f0dSDavid C Somayajulu p_block->vector_number = sb_id + 1; 247311e25f0dSDavid C Somayajulu 247411e25f0dSDavid C Somayajulu p_info->usage.cnt++; 247511e25f0dSDavid C Somayajulu p_info->usage.free_cnt++; 247611e25f0dSDavid C Somayajulu p_info->usage.iov_cnt--; 247711e25f0dSDavid C Somayajulu p_info->usage.free_cnt_iov--; 247811e25f0dSDavid C Somayajulu 247911e25f0dSDavid C Somayajulu p_hwfn->hw_info.feat_num[ECORE_PF_L2_QUE]++; 248011e25f0dSDavid C Somayajulu p_hwfn->hw_info.feat_num[ECORE_VF_L2_QUE]--; 248111e25f0dSDavid C Somayajulu } 248211e25f0dSDavid C Somayajulu 248311e25f0dSDavid C Somayajulu /* Update the IGU and CAU with the new configuration */ 248411e25f0dSDavid C Somayajulu SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER, 248511e25f0dSDavid C Somayajulu p_block->function_id); 248611e25f0dSDavid C Somayajulu SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf); 248711e25f0dSDavid C Somayajulu SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf); 248811e25f0dSDavid C Somayajulu SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER, 248911e25f0dSDavid C Somayajulu p_block->vector_number); 249011e25f0dSDavid C Somayajulu 249111e25f0dSDavid C Somayajulu ecore_wr(p_hwfn, p_ptt, 249211e25f0dSDavid C Somayajulu IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id, 249311e25f0dSDavid C Somayajulu val); 249411e25f0dSDavid C Somayajulu 249511e25f0dSDavid C Somayajulu ecore_int_cau_conf_sb(p_hwfn, p_ptt, 0, 249611e25f0dSDavid C Somayajulu igu_sb_id, vf_num, 249711e25f0dSDavid C Somayajulu p_block->is_pf ? 0 : 1); 249811e25f0dSDavid C Somayajulu 249911e25f0dSDavid C Somayajulu DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, 250011e25f0dSDavid C Somayajulu "Relocation: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n", 250111e25f0dSDavid C Somayajulu igu_sb_id, p_block->function_id, 250211e25f0dSDavid C Somayajulu p_block->is_pf, p_block->vector_number); 250311e25f0dSDavid C Somayajulu 250411e25f0dSDavid C Somayajulu return ECORE_SUCCESS; 250511e25f0dSDavid C Somayajulu } 250611e25f0dSDavid C Somayajulu 250711e25f0dSDavid C Somayajulu /** 250811e25f0dSDavid C Somayajulu * @brief Initialize igu runtime registers 250911e25f0dSDavid C Somayajulu * 251011e25f0dSDavid C Somayajulu * @param p_hwfn 251111e25f0dSDavid C Somayajulu */ 251211e25f0dSDavid C Somayajulu void ecore_int_igu_init_rt(struct ecore_hwfn *p_hwfn) 251311e25f0dSDavid C Somayajulu { 251411e25f0dSDavid C Somayajulu u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN; 251511e25f0dSDavid C Somayajulu 251611e25f0dSDavid C Somayajulu STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf); 251711e25f0dSDavid C Somayajulu } 251811e25f0dSDavid C Somayajulu 251911e25f0dSDavid C Somayajulu #define LSB_IGU_CMD_ADDR (IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - \ 252011e25f0dSDavid C Somayajulu IGU_CMD_INT_ACK_BASE) 252111e25f0dSDavid C Somayajulu #define MSB_IGU_CMD_ADDR (IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - \ 252211e25f0dSDavid C Somayajulu IGU_CMD_INT_ACK_BASE) 252311e25f0dSDavid C Somayajulu u64 ecore_int_igu_read_sisr_reg(struct ecore_hwfn *p_hwfn) 252411e25f0dSDavid C Somayajulu { 252511e25f0dSDavid C Somayajulu u32 intr_status_hi = 0, intr_status_lo = 0; 252611e25f0dSDavid C Somayajulu u64 intr_status = 0; 252711e25f0dSDavid C Somayajulu 252811e25f0dSDavid C Somayajulu intr_status_lo = REG_RD(p_hwfn, 252911e25f0dSDavid C Somayajulu GTT_BAR0_MAP_REG_IGU_CMD + 253011e25f0dSDavid C Somayajulu LSB_IGU_CMD_ADDR * 8); 253111e25f0dSDavid C Somayajulu intr_status_hi = REG_RD(p_hwfn, 253211e25f0dSDavid C Somayajulu GTT_BAR0_MAP_REG_IGU_CMD + 253311e25f0dSDavid C Somayajulu MSB_IGU_CMD_ADDR * 8); 253411e25f0dSDavid C Somayajulu intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo; 253511e25f0dSDavid C Somayajulu 253611e25f0dSDavid C Somayajulu return intr_status; 253711e25f0dSDavid C Somayajulu } 253811e25f0dSDavid C Somayajulu 253911e25f0dSDavid C Somayajulu static void ecore_int_sp_dpc_setup(struct ecore_hwfn *p_hwfn) 254011e25f0dSDavid C Somayajulu { 254111e25f0dSDavid C Somayajulu OSAL_DPC_INIT(p_hwfn->sp_dpc, p_hwfn); 254211e25f0dSDavid C Somayajulu p_hwfn->b_sp_dpc_enabled = true; 254311e25f0dSDavid C Somayajulu } 254411e25f0dSDavid C Somayajulu 254511e25f0dSDavid C Somayajulu static enum _ecore_status_t ecore_int_sp_dpc_alloc(struct ecore_hwfn *p_hwfn) 254611e25f0dSDavid C Somayajulu { 254711e25f0dSDavid C Somayajulu p_hwfn->sp_dpc = OSAL_DPC_ALLOC(p_hwfn); 254811e25f0dSDavid C Somayajulu if (!p_hwfn->sp_dpc) 254911e25f0dSDavid C Somayajulu return ECORE_NOMEM; 255011e25f0dSDavid C Somayajulu 255111e25f0dSDavid C Somayajulu return ECORE_SUCCESS; 255211e25f0dSDavid C Somayajulu } 255311e25f0dSDavid C Somayajulu 255411e25f0dSDavid C Somayajulu static void ecore_int_sp_dpc_free(struct ecore_hwfn *p_hwfn) 255511e25f0dSDavid C Somayajulu { 255611e25f0dSDavid C Somayajulu OSAL_FREE(p_hwfn->p_dev, p_hwfn->sp_dpc); 255711e25f0dSDavid C Somayajulu p_hwfn->sp_dpc = OSAL_NULL; 255811e25f0dSDavid C Somayajulu } 255911e25f0dSDavid C Somayajulu 256011e25f0dSDavid C Somayajulu enum _ecore_status_t ecore_int_alloc(struct ecore_hwfn *p_hwfn, 256111e25f0dSDavid C Somayajulu struct ecore_ptt *p_ptt) 256211e25f0dSDavid C Somayajulu { 256311e25f0dSDavid C Somayajulu enum _ecore_status_t rc = ECORE_SUCCESS; 256411e25f0dSDavid C Somayajulu 256511e25f0dSDavid C Somayajulu rc = ecore_int_sp_dpc_alloc(p_hwfn); 256611e25f0dSDavid C Somayajulu if (rc != ECORE_SUCCESS) { 256711e25f0dSDavid C Somayajulu DP_ERR(p_hwfn->p_dev, "Failed to allocate sp dpc mem\n"); 256811e25f0dSDavid C Somayajulu return rc; 256911e25f0dSDavid C Somayajulu } 257011e25f0dSDavid C Somayajulu 257111e25f0dSDavid C Somayajulu rc = ecore_int_sp_sb_alloc(p_hwfn, p_ptt); 257211e25f0dSDavid C Somayajulu if (rc != ECORE_SUCCESS) { 257311e25f0dSDavid C Somayajulu DP_ERR(p_hwfn->p_dev, "Failed to allocate sp sb mem\n"); 257411e25f0dSDavid C Somayajulu return rc; 257511e25f0dSDavid C Somayajulu } 257611e25f0dSDavid C Somayajulu 257711e25f0dSDavid C Somayajulu rc = ecore_int_sb_attn_alloc(p_hwfn, p_ptt); 257811e25f0dSDavid C Somayajulu if (rc != ECORE_SUCCESS) 257911e25f0dSDavid C Somayajulu DP_ERR(p_hwfn->p_dev, "Failed to allocate sb attn mem\n"); 258011e25f0dSDavid C Somayajulu 258111e25f0dSDavid C Somayajulu return rc; 258211e25f0dSDavid C Somayajulu } 258311e25f0dSDavid C Somayajulu 258411e25f0dSDavid C Somayajulu void ecore_int_free(struct ecore_hwfn *p_hwfn) 258511e25f0dSDavid C Somayajulu { 258611e25f0dSDavid C Somayajulu ecore_int_sp_sb_free(p_hwfn); 258711e25f0dSDavid C Somayajulu ecore_int_sb_attn_free(p_hwfn); 258811e25f0dSDavid C Somayajulu ecore_int_sp_dpc_free(p_hwfn); 258911e25f0dSDavid C Somayajulu } 259011e25f0dSDavid C Somayajulu 259111e25f0dSDavid C Somayajulu void ecore_int_setup(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) 259211e25f0dSDavid C Somayajulu { 259311e25f0dSDavid C Somayajulu if (!p_hwfn || !p_hwfn->p_sp_sb || !p_hwfn->p_sb_attn) 259411e25f0dSDavid C Somayajulu return; 259511e25f0dSDavid C Somayajulu 259611e25f0dSDavid C Somayajulu ecore_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info); 259711e25f0dSDavid C Somayajulu ecore_int_sb_attn_setup(p_hwfn, p_ptt); 259811e25f0dSDavid C Somayajulu ecore_int_sp_dpc_setup(p_hwfn); 259911e25f0dSDavid C Somayajulu } 260011e25f0dSDavid C Somayajulu 260111e25f0dSDavid C Somayajulu void ecore_int_get_num_sbs(struct ecore_hwfn *p_hwfn, 260211e25f0dSDavid C Somayajulu struct ecore_sb_cnt_info *p_sb_cnt_info) 260311e25f0dSDavid C Somayajulu { 260411e25f0dSDavid C Somayajulu struct ecore_igu_info *p_igu_info = p_hwfn->hw_info.p_igu_info; 260511e25f0dSDavid C Somayajulu 260611e25f0dSDavid C Somayajulu if (!p_igu_info || !p_sb_cnt_info) 260711e25f0dSDavid C Somayajulu return; 260811e25f0dSDavid C Somayajulu 260911e25f0dSDavid C Somayajulu OSAL_MEMCPY(p_sb_cnt_info, &p_igu_info->usage, 261011e25f0dSDavid C Somayajulu sizeof(*p_sb_cnt_info)); 261111e25f0dSDavid C Somayajulu } 261211e25f0dSDavid C Somayajulu 261311e25f0dSDavid C Somayajulu void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev) 261411e25f0dSDavid C Somayajulu { 261511e25f0dSDavid C Somayajulu int i; 261611e25f0dSDavid C Somayajulu 261711e25f0dSDavid C Somayajulu for_each_hwfn(p_dev, i) 261811e25f0dSDavid C Somayajulu p_dev->hwfns[i].b_int_requested = false; 261911e25f0dSDavid C Somayajulu } 262011e25f0dSDavid C Somayajulu 262111e25f0dSDavid C Somayajulu void ecore_int_attn_clr_enable(struct ecore_dev *p_dev, bool clr_enable) 262211e25f0dSDavid C Somayajulu { 262311e25f0dSDavid C Somayajulu p_dev->attn_clr_en = clr_enable; 262411e25f0dSDavid C Somayajulu } 262511e25f0dSDavid C Somayajulu 262611e25f0dSDavid C Somayajulu enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn, 262711e25f0dSDavid C Somayajulu struct ecore_ptt *p_ptt, 262811e25f0dSDavid C Somayajulu u8 timer_res, u16 sb_id, bool tx) 262911e25f0dSDavid C Somayajulu { 263011e25f0dSDavid C Somayajulu struct cau_sb_entry sb_entry; 263111e25f0dSDavid C Somayajulu enum _ecore_status_t rc; 263211e25f0dSDavid C Somayajulu 263311e25f0dSDavid C Somayajulu if (!p_hwfn->hw_init_done) { 263411e25f0dSDavid C Somayajulu DP_ERR(p_hwfn, "hardware not initialized yet\n"); 263511e25f0dSDavid C Somayajulu return ECORE_INVAL; 263611e25f0dSDavid C Somayajulu } 263711e25f0dSDavid C Somayajulu 263811e25f0dSDavid C Somayajulu rc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY + 263911e25f0dSDavid C Somayajulu sb_id * sizeof(u64), 264011e25f0dSDavid C Somayajulu (u64)(osal_uintptr_t)&sb_entry, 2, 0); 264111e25f0dSDavid C Somayajulu if (rc != ECORE_SUCCESS) { 264211e25f0dSDavid C Somayajulu DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc); 264311e25f0dSDavid C Somayajulu return rc; 264411e25f0dSDavid C Somayajulu } 264511e25f0dSDavid C Somayajulu 264611e25f0dSDavid C Somayajulu if (tx) 264711e25f0dSDavid C Somayajulu SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 264811e25f0dSDavid C Somayajulu else 264911e25f0dSDavid C Somayajulu SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 265011e25f0dSDavid C Somayajulu 265111e25f0dSDavid C Somayajulu rc = ecore_dmae_host2grc(p_hwfn, p_ptt, 265211e25f0dSDavid C Somayajulu (u64)(osal_uintptr_t)&sb_entry, 265311e25f0dSDavid C Somayajulu CAU_REG_SB_VAR_MEMORY + 265411e25f0dSDavid C Somayajulu sb_id * sizeof(u64), 2, 0); 265511e25f0dSDavid C Somayajulu if (rc != ECORE_SUCCESS) { 265611e25f0dSDavid C Somayajulu DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc); 265711e25f0dSDavid C Somayajulu return rc; 265811e25f0dSDavid C Somayajulu } 265911e25f0dSDavid C Somayajulu 266011e25f0dSDavid C Somayajulu return rc; 266111e25f0dSDavid C Somayajulu } 266211e25f0dSDavid C Somayajulu 266311e25f0dSDavid C Somayajulu enum _ecore_status_t ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn, 266411e25f0dSDavid C Somayajulu struct ecore_ptt *p_ptt, 266511e25f0dSDavid C Somayajulu struct ecore_sb_info *p_sb, 266611e25f0dSDavid C Somayajulu struct ecore_sb_info_dbg *p_info) 266711e25f0dSDavid C Somayajulu { 266811e25f0dSDavid C Somayajulu u16 sbid = p_sb->igu_sb_id; 266911e25f0dSDavid C Somayajulu int i; 267011e25f0dSDavid C Somayajulu 267111e25f0dSDavid C Somayajulu if (IS_VF(p_hwfn->p_dev)) 267211e25f0dSDavid C Somayajulu return ECORE_INVAL; 267311e25f0dSDavid C Somayajulu 267411e25f0dSDavid C Somayajulu if (sbid > NUM_OF_SBS(p_hwfn->p_dev)) 267511e25f0dSDavid C Somayajulu return ECORE_INVAL; 267611e25f0dSDavid C Somayajulu 267711e25f0dSDavid C Somayajulu p_info->igu_prod = ecore_rd(p_hwfn, p_ptt, 267811e25f0dSDavid C Somayajulu IGU_REG_PRODUCER_MEMORY + sbid * 4); 267911e25f0dSDavid C Somayajulu p_info->igu_cons = ecore_rd(p_hwfn, p_ptt, 268011e25f0dSDavid C Somayajulu IGU_REG_CONSUMER_MEM + sbid * 4); 268111e25f0dSDavid C Somayajulu 26829efd0ba7SDavid C Somayajulu for (i = 0; i < PIS_PER_SB_E4; i++) 268311e25f0dSDavid C Somayajulu p_info->pi[i] = (u16)ecore_rd(p_hwfn, p_ptt, 268411e25f0dSDavid C Somayajulu CAU_REG_PI_MEMORY + 26859efd0ba7SDavid C Somayajulu sbid * 4 * PIS_PER_SB_E4 + i * 4); 268611e25f0dSDavid C Somayajulu 268711e25f0dSDavid C Somayajulu return ECORE_SUCCESS; 268811e25f0dSDavid C Somayajulu } 2689