1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __ECORE_MCP_API_H__ 32 #define __ECORE_MCP_API_H__ 33 34 #include "ecore_status.h" 35 36 struct ecore_mcp_link_speed_params { 37 bool autoneg; 38 u32 advertised_speeds; /* bitmask of DRV_SPEED_CAPABILITY */ 39 u32 forced_speed; /* In Mb/s */ 40 }; 41 42 struct ecore_mcp_link_pause_params { 43 bool autoneg; 44 bool forced_rx; 45 bool forced_tx; 46 }; 47 48 enum ecore_mcp_eee_mode { 49 ECORE_MCP_EEE_DISABLED, 50 ECORE_MCP_EEE_ENABLED, 51 ECORE_MCP_EEE_UNSUPPORTED 52 }; 53 54 #ifndef __EXTRACT__LINUX__ 55 struct ecore_link_eee_params { 56 u32 tx_lpi_timer; 57 #define ECORE_EEE_1G_ADV (1 << 0) 58 #define ECORE_EEE_10G_ADV (1 << 1) 59 /* Capabilities are represented using ECORE_EEE_*_ADV values */ 60 u8 adv_caps; 61 u8 lp_adv_caps; 62 bool enable; 63 bool tx_lpi_enable; 64 }; 65 #endif 66 67 struct ecore_mcp_link_params { 68 struct ecore_mcp_link_speed_params speed; 69 struct ecore_mcp_link_pause_params pause; 70 u32 loopback_mode; /* in PMM_LOOPBACK values */ 71 struct ecore_link_eee_params eee; 72 }; 73 74 struct ecore_mcp_link_capabilities { 75 u32 speed_capabilities; 76 bool default_speed_autoneg; /* In Mb/s */ 77 u32 default_speed; /* In Mb/s */ 78 enum ecore_mcp_eee_mode default_eee; 79 u32 eee_lpi_timer; 80 }; 81 82 struct ecore_mcp_link_state { 83 bool link_up; 84 85 u32 line_speed; /* In Mb/s */ 86 u32 min_pf_rate; /* In Mb/s */ 87 u32 speed; /* In Mb/s */ 88 bool full_duplex; 89 90 bool an; 91 bool an_complete; 92 bool parallel_detection; 93 bool pfc_enabled; 94 95 #define ECORE_LINK_PARTNER_SPEED_1G_HD (1 << 0) 96 #define ECORE_LINK_PARTNER_SPEED_1G_FD (1 << 1) 97 #define ECORE_LINK_PARTNER_SPEED_10G (1 << 2) 98 #define ECORE_LINK_PARTNER_SPEED_20G (1 << 3) 99 #define ECORE_LINK_PARTNER_SPEED_25G (1 << 4) 100 #define ECORE_LINK_PARTNER_SPEED_40G (1 << 5) 101 #define ECORE_LINK_PARTNER_SPEED_50G (1 << 6) 102 #define ECORE_LINK_PARTNER_SPEED_100G (1 << 7) 103 u32 partner_adv_speed; 104 105 bool partner_tx_flow_ctrl_en; 106 bool partner_rx_flow_ctrl_en; 107 108 #define ECORE_LINK_PARTNER_SYMMETRIC_PAUSE (1) 109 #define ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE (2) 110 #define ECORE_LINK_PARTNER_BOTH_PAUSE (3) 111 u8 partner_adv_pause; 112 113 bool sfp_tx_fault; 114 115 bool eee_active; 116 u8 eee_adv_caps; 117 u8 eee_lp_adv_caps; 118 }; 119 120 struct ecore_mcp_function_info { 121 u8 pause_on_host; 122 123 enum ecore_pci_personality protocol; 124 125 u8 bandwidth_min; 126 u8 bandwidth_max; 127 128 u8 mac[ETH_ALEN]; 129 130 u64 wwn_port; 131 u64 wwn_node; 132 133 #define ECORE_MCP_VLAN_UNSET (0xffff) 134 u16 ovlan; 135 136 u16 mtu; 137 }; 138 139 #ifndef __EXTRACT__LINUX__ 140 enum ecore_nvm_images { 141 ECORE_NVM_IMAGE_ISCSI_CFG, 142 ECORE_NVM_IMAGE_FCOE_CFG, 143 ECORE_NVM_IMAGE_MDUMP, 144 }; 145 #endif 146 147 struct ecore_mcp_drv_version { 148 u32 version; 149 u8 name[MCP_DRV_VER_STR_SIZE - 4]; 150 }; 151 152 struct ecore_mcp_lan_stats { 153 u64 ucast_rx_pkts; 154 u64 ucast_tx_pkts; 155 u32 fcs_err; 156 }; 157 158 #ifndef ECORE_PROTO_STATS 159 #define ECORE_PROTO_STATS 160 struct ecore_mcp_fcoe_stats { 161 u64 rx_pkts; 162 u64 tx_pkts; 163 u32 fcs_err; 164 u32 login_failure; 165 }; 166 167 struct ecore_mcp_iscsi_stats { 168 u64 rx_pdus; 169 u64 tx_pdus; 170 u64 rx_bytes; 171 u64 tx_bytes; 172 }; 173 174 struct ecore_mcp_rdma_stats { 175 u64 rx_pkts; 176 u64 tx_pkts; 177 u64 rx_bytes; 178 u64 tx_byts; 179 }; 180 181 enum ecore_mcp_protocol_type { 182 ECORE_MCP_LAN_STATS, 183 ECORE_MCP_FCOE_STATS, 184 ECORE_MCP_ISCSI_STATS, 185 ECORE_MCP_RDMA_STATS 186 }; 187 188 union ecore_mcp_protocol_stats { 189 struct ecore_mcp_lan_stats lan_stats; 190 struct ecore_mcp_fcoe_stats fcoe_stats; 191 struct ecore_mcp_iscsi_stats iscsi_stats; 192 struct ecore_mcp_rdma_stats rdma_stats; 193 }; 194 #endif 195 196 enum ecore_ov_client { 197 ECORE_OV_CLIENT_DRV, 198 ECORE_OV_CLIENT_USER, 199 ECORE_OV_CLIENT_VENDOR_SPEC 200 }; 201 202 enum ecore_ov_driver_state { 203 ECORE_OV_DRIVER_STATE_NOT_LOADED, 204 ECORE_OV_DRIVER_STATE_DISABLED, 205 ECORE_OV_DRIVER_STATE_ACTIVE 206 }; 207 208 enum ecore_ov_wol { 209 ECORE_OV_WOL_DEFAULT, 210 ECORE_OV_WOL_DISABLED, 211 ECORE_OV_WOL_ENABLED 212 }; 213 214 #ifndef __EXTRACT__LINUX__ 215 #define ECORE_MAX_NPIV_ENTRIES 128 216 #define ECORE_WWN_SIZE 8 217 struct ecore_fc_npiv_tbl { 218 u16 num_wwpn; 219 u16 num_wwnn; 220 u8 wwpn[ECORE_MAX_NPIV_ENTRIES][ECORE_WWN_SIZE]; 221 u8 wwnn[ECORE_MAX_NPIV_ENTRIES][ECORE_WWN_SIZE]; 222 }; 223 224 enum ecore_led_mode { 225 ECORE_LED_MODE_OFF, 226 ECORE_LED_MODE_ON, 227 ECORE_LED_MODE_RESTORE 228 }; 229 #endif 230 231 struct ecore_temperature_sensor { 232 u8 sensor_location; 233 u8 threshold_high; 234 u8 critical; 235 u8 current_temp; 236 }; 237 238 #define ECORE_MAX_NUM_OF_SENSORS 7 239 struct ecore_temperature_info { 240 u32 num_sensors; 241 struct ecore_temperature_sensor sensors[ECORE_MAX_NUM_OF_SENSORS]; 242 }; 243 244 enum ecore_mba_img_idx { 245 ECORE_MBA_LEGACY_IDX, 246 ECORE_MBA_PCI3CLP_IDX, 247 ECORE_MBA_PCI3_IDX, 248 ECORE_MBA_FCODE_IDX, 249 ECORE_EFI_X86_IDX, 250 ECORE_EFI_IPF_IDX, 251 ECORE_EFI_EBC_IDX, 252 ECORE_EFI_X64_IDX, 253 ECORE_MAX_NUM_OF_ROMIMG 254 }; 255 256 struct ecore_mba_vers { 257 u32 mba_vers[ECORE_MAX_NUM_OF_ROMIMG]; 258 }; 259 260 enum ecore_mfw_tlv_type { 261 ECORE_MFW_TLV_GENERIC = 0x1, /* Core driver TLVs */ 262 ECORE_MFW_TLV_ETH = 0x2, /* L2 driver TLVs */ 263 ECORE_MFW_TLV_FCOE = 0x4, /* FCoE protocol TLVs */ 264 ECORE_MFW_TLV_ISCSI = 0x8, /* SCSI protocol TLVs */ 265 ECORE_MFW_TLV_MAX = 0x16, 266 }; 267 268 struct ecore_mfw_tlv_generic { 269 struct { 270 u8 ipv4_csum_offload; 271 u8 lso_supported; 272 bool b_set; 273 } flags; 274 275 #define ECORE_MFW_TLV_MAC_COUNT 3 276 /* First entry for primary MAC, 2 secondary MACs possible */ 277 u8 mac[ECORE_MFW_TLV_MAC_COUNT][6]; 278 bool mac_set[ECORE_MFW_TLV_MAC_COUNT]; 279 280 u64 rx_frames; 281 bool rx_frames_set; 282 u64 rx_bytes; 283 bool rx_bytes_set; 284 u64 tx_frames; 285 bool tx_frames_set; 286 u64 tx_bytes; 287 bool tx_bytes_set; 288 }; 289 290 #ifndef __EXTRACT__LINUX__ 291 struct ecore_mfw_tlv_eth { 292 u16 lso_maxoff_size; 293 bool lso_maxoff_size_set; 294 u16 lso_minseg_size; 295 bool lso_minseg_size_set; 296 u8 prom_mode; 297 bool prom_mode_set; 298 u16 tx_descr_size; 299 bool tx_descr_size_set; 300 u16 rx_descr_size; 301 bool rx_descr_size_set; 302 u16 netq_count; 303 bool netq_count_set; 304 u32 tcp4_offloads; 305 bool tcp4_offloads_set; 306 u32 tcp6_offloads; 307 bool tcp6_offloads_set; 308 u16 tx_descr_qdepth; 309 bool tx_descr_qdepth_set; 310 u16 rx_descr_qdepth; 311 bool rx_descr_qdepth_set; 312 u8 iov_offload; 313 #define ECORE_MFW_TLV_IOV_OFFLOAD_NONE (0) 314 #define ECORE_MFW_TLV_IOV_OFFLOAD_MULTIQUEUE (1) 315 #define ECORE_MFW_TLV_IOV_OFFLOAD_VEB (2) 316 #define ECORE_MFW_TLV_IOV_OFFLOAD_VEPA (3) 317 bool iov_offload_set; 318 u8 txqs_empty; 319 bool txqs_empty_set; 320 u8 rxqs_empty; 321 bool rxqs_empty_set; 322 u8 num_txqs_full; 323 bool num_txqs_full_set; 324 u8 num_rxqs_full; 325 bool num_rxqs_full_set; 326 }; 327 328 struct ecore_mfw_tlv_time { 329 bool b_set; 330 u8 month; 331 u8 day; 332 u8 hour; 333 u8 min; 334 u16 msec; 335 u16 usec; 336 }; 337 338 struct ecore_mfw_tlv_fcoe { 339 u8 scsi_timeout; 340 bool scsi_timeout_set; 341 u32 rt_tov; 342 bool rt_tov_set; 343 u32 ra_tov; 344 bool ra_tov_set; 345 u32 ed_tov; 346 bool ed_tov_set; 347 u32 cr_tov; 348 bool cr_tov_set; 349 u8 boot_type; 350 bool boot_type_set; 351 u8 npiv_state; 352 bool npiv_state_set; 353 u32 num_npiv_ids; 354 bool num_npiv_ids_set; 355 u8 switch_name[8]; 356 bool switch_name_set; 357 u16 switch_portnum; 358 bool switch_portnum_set; 359 u8 switch_portid[3]; 360 bool switch_portid_set; 361 u8 vendor_name[8]; 362 bool vendor_name_set; 363 u8 switch_model[8]; 364 bool switch_model_set; 365 u8 switch_fw_version[8]; 366 bool switch_fw_version_set; 367 u8 qos_pri; 368 bool qos_pri_set; 369 u8 port_alias[3]; 370 bool port_alias_set; 371 u8 port_state; 372 #define ECORE_MFW_TLV_PORT_STATE_OFFLINE (0) 373 #define ECORE_MFW_TLV_PORT_STATE_LOOP (1) 374 #define ECORE_MFW_TLV_PORT_STATE_P2P (2) 375 #define ECORE_MFW_TLV_PORT_STATE_FABRIC (3) 376 bool port_state_set; 377 u16 fip_tx_descr_size; 378 bool fip_tx_descr_size_set; 379 u16 fip_rx_descr_size; 380 bool fip_rx_descr_size_set; 381 u16 link_failures; 382 bool link_failures_set; 383 u8 fcoe_boot_progress; 384 bool fcoe_boot_progress_set; 385 u64 rx_bcast; 386 bool rx_bcast_set; 387 u64 tx_bcast; 388 bool tx_bcast_set; 389 u16 fcoe_txq_depth; 390 bool fcoe_txq_depth_set; 391 u16 fcoe_rxq_depth; 392 bool fcoe_rxq_depth_set; 393 u64 fcoe_rx_frames; 394 bool fcoe_rx_frames_set; 395 u64 fcoe_rx_bytes; 396 bool fcoe_rx_bytes_set; 397 u64 fcoe_tx_frames; 398 bool fcoe_tx_frames_set; 399 u64 fcoe_tx_bytes; 400 bool fcoe_tx_bytes_set; 401 u16 crc_count; 402 bool crc_count_set; 403 u32 crc_err_src_fcid[5]; 404 bool crc_err_src_fcid_set[5]; 405 struct ecore_mfw_tlv_time crc_err[5]; 406 u16 losync_err; 407 bool losync_err_set; 408 u16 losig_err; 409 bool losig_err_set; 410 u16 primtive_err; 411 bool primtive_err_set; 412 u16 disparity_err; 413 bool disparity_err_set; 414 u16 code_violation_err; 415 bool code_violation_err_set; 416 u32 flogi_param[4]; 417 bool flogi_param_set[4]; 418 struct ecore_mfw_tlv_time flogi_tstamp; 419 u32 flogi_acc_param[4]; 420 bool flogi_acc_param_set[4]; 421 struct ecore_mfw_tlv_time flogi_acc_tstamp; 422 u32 flogi_rjt; 423 bool flogi_rjt_set; 424 struct ecore_mfw_tlv_time flogi_rjt_tstamp; 425 u32 fdiscs; 426 bool fdiscs_set; 427 u8 fdisc_acc; 428 bool fdisc_acc_set; 429 u8 fdisc_rjt; 430 bool fdisc_rjt_set; 431 u8 plogi; 432 bool plogi_set; 433 u8 plogi_acc; 434 bool plogi_acc_set; 435 u8 plogi_rjt; 436 bool plogi_rjt_set; 437 u32 plogi_dst_fcid[5]; 438 bool plogi_dst_fcid_set[5]; 439 struct ecore_mfw_tlv_time plogi_tstamp[5]; 440 u32 plogi_acc_src_fcid[5]; 441 bool plogi_acc_src_fcid_set[5]; 442 struct ecore_mfw_tlv_time plogi_acc_tstamp[5]; 443 u8 tx_plogos; 444 bool tx_plogos_set; 445 u8 plogo_acc; 446 bool plogo_acc_set; 447 u8 plogo_rjt; 448 bool plogo_rjt_set; 449 u32 plogo_src_fcid[5]; 450 bool plogo_src_fcid_set[5]; 451 struct ecore_mfw_tlv_time plogo_tstamp[5]; 452 u8 rx_logos; 453 bool rx_logos_set; 454 u8 tx_accs; 455 bool tx_accs_set; 456 u8 tx_prlis; 457 bool tx_prlis_set; 458 u8 rx_accs; 459 bool rx_accs_set; 460 u8 tx_abts; 461 bool tx_abts_set; 462 u8 rx_abts_acc; 463 bool rx_abts_acc_set; 464 u8 rx_abts_rjt; 465 bool rx_abts_rjt_set; 466 u32 abts_dst_fcid[5]; 467 bool abts_dst_fcid_set[5]; 468 struct ecore_mfw_tlv_time abts_tstamp[5]; 469 u8 rx_rscn; 470 bool rx_rscn_set; 471 u32 rx_rscn_nport[4]; 472 bool rx_rscn_nport_set[4]; 473 u8 tx_lun_rst; 474 bool tx_lun_rst_set; 475 u8 abort_task_sets; 476 bool abort_task_sets_set; 477 u8 tx_tprlos; 478 bool tx_tprlos_set; 479 u8 tx_nos; 480 bool tx_nos_set; 481 u8 rx_nos; 482 bool rx_nos_set; 483 u8 ols; 484 bool ols_set; 485 u8 lr; 486 bool lr_set; 487 u8 lrr; 488 bool lrr_set; 489 u8 tx_lip; 490 bool tx_lip_set; 491 u8 rx_lip; 492 bool rx_lip_set; 493 u8 eofa; 494 bool eofa_set; 495 u8 eofni; 496 bool eofni_set; 497 u8 scsi_chks; 498 bool scsi_chks_set; 499 u8 scsi_cond_met; 500 bool scsi_cond_met_set; 501 u8 scsi_busy; 502 bool scsi_busy_set; 503 u8 scsi_inter; 504 bool scsi_inter_set; 505 u8 scsi_inter_cond_met; 506 bool scsi_inter_cond_met_set; 507 u8 scsi_rsv_conflicts; 508 bool scsi_rsv_conflicts_set; 509 u8 scsi_tsk_full; 510 bool scsi_tsk_full_set; 511 u8 scsi_aca_active; 512 bool scsi_aca_active_set; 513 u8 scsi_tsk_abort; 514 bool scsi_tsk_abort_set; 515 u32 scsi_rx_chk[5]; 516 bool scsi_rx_chk_set[5]; 517 struct ecore_mfw_tlv_time scsi_chk_tstamp[5]; 518 }; 519 520 struct ecore_mfw_tlv_iscsi { 521 u8 target_llmnr; 522 bool target_llmnr_set; 523 u8 header_digest; 524 bool header_digest_set; 525 u8 data_digest; 526 bool data_digest_set; 527 u8 auth_method; 528 #define ECORE_MFW_TLV_AUTH_METHOD_NONE (1) 529 #define ECORE_MFW_TLV_AUTH_METHOD_CHAP (2) 530 #define ECORE_MFW_TLV_AUTH_METHOD_MUTUAL_CHAP (3) 531 bool auth_method_set; 532 u16 boot_taget_portal; 533 bool boot_taget_portal_set; 534 u16 frame_size; 535 bool frame_size_set; 536 u16 tx_desc_size; 537 bool tx_desc_size_set; 538 u16 rx_desc_size; 539 bool rx_desc_size_set; 540 u8 boot_progress; 541 bool boot_progress_set; 542 u16 tx_desc_qdepth; 543 bool tx_desc_qdepth_set; 544 u16 rx_desc_qdepth; 545 bool rx_desc_qdepth_set; 546 u64 rx_frames; 547 bool rx_frames_set; 548 u64 rx_bytes; 549 bool rx_bytes_set; 550 u64 tx_frames; 551 bool tx_frames_set; 552 u64 tx_bytes; 553 bool tx_bytes_set; 554 }; 555 #endif 556 557 union ecore_mfw_tlv_data { 558 struct ecore_mfw_tlv_generic generic; 559 struct ecore_mfw_tlv_eth eth; 560 struct ecore_mfw_tlv_fcoe fcoe; 561 struct ecore_mfw_tlv_iscsi iscsi; 562 }; 563 564 enum ecore_hw_info_change { 565 ECORE_HW_INFO_CHANGE_OVLAN, 566 }; 567 568 /** 569 * @brief - returns the link params of the hw function 570 * 571 * @param p_hwfn 572 * 573 * @returns pointer to link params 574 */ 575 struct ecore_mcp_link_params *ecore_mcp_get_link_params(struct ecore_hwfn*); 576 577 /** 578 * @brief - return the link state of the hw function 579 * 580 * @param p_hwfn 581 * 582 * @returns pointer to link state 583 */ 584 struct ecore_mcp_link_state *ecore_mcp_get_link_state(struct ecore_hwfn*); 585 586 /** 587 * @brief - return the link capabilities of the hw function 588 * 589 * @param p_hwfn 590 * 591 * @returns pointer to link capabilities 592 */ 593 struct ecore_mcp_link_capabilities 594 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn); 595 596 /** 597 * @brief Request the MFW to set the the link according to 'link_input'. 598 * 599 * @param p_hwfn 600 * @param p_ptt 601 * @param b_up - raise link if `true'. Reset link if `false'. 602 * 603 * @return enum _ecore_status_t 604 */ 605 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn, 606 struct ecore_ptt *p_ptt, 607 bool b_up); 608 609 /** 610 * @brief Get the management firmware version value 611 * 612 * @param p_hwfn 613 * @param p_ptt 614 * @param p_mfw_ver - mfw version value 615 * @param p_running_bundle_id - image id in nvram; Optional. 616 * 617 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 618 */ 619 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn, 620 struct ecore_ptt *p_ptt, 621 u32 *p_mfw_ver, 622 u32 *p_running_bundle_id); 623 624 /** 625 * @brief Get the MBI version value 626 * 627 * @param p_hwfn 628 * @param p_ptt 629 * @param p_mbi_ver - A pointer to a variable to be filled with the MBI version. 630 * 631 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 632 */ 633 enum _ecore_status_t ecore_mcp_get_mbi_ver(struct ecore_hwfn *p_hwfn, 634 struct ecore_ptt *p_ptt, 635 u32 *p_mbi_ver); 636 637 /** 638 * @brief Get media type value of the port. 639 * 640 * @param p_dev - ecore dev pointer 641 * @param mfw_ver - media type value 642 * 643 * @return enum _ecore_status_t - 644 * ECORE_SUCCESS - Operation was successful. 645 * ECORE_BUSY - Operation failed 646 */ 647 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_dev *p_dev, 648 u32 *media_type); 649 650 /** 651 * @brief - Sends a command to the MCP mailbox. 652 * 653 * @param p_hwfn - hw function 654 * @param p_ptt - PTT required for register access 655 * @param cmd - command to be sent to the MCP 656 * @param param - optional param 657 * @param o_mcp_resp - the MCP response code (exclude sequence) 658 * @param o_mcp_param - optional parameter provided by the MCP response 659 * 660 * @return enum _ecore_status_t - 661 * ECORE_SUCCESS - operation was successful 662 * ECORE_BUSY - operation failed 663 */ 664 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn, 665 struct ecore_ptt *p_ptt, u32 cmd, u32 param, 666 u32 *o_mcp_resp, u32 *o_mcp_param); 667 668 /** 669 * @brief - drains the nig, allowing completion to pass in case of pauses. 670 * (Should be called only from sleepable context) 671 * 672 * @param p_hwfn 673 * @param p_ptt 674 */ 675 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn, 676 struct ecore_ptt *p_ptt); 677 678 #ifndef LINUX_REMOVE 679 /** 680 * @brief - return the mcp function info of the hw function 681 * 682 * @param p_hwfn 683 * 684 * @returns pointer to mcp function info 685 */ 686 const struct ecore_mcp_function_info 687 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn); 688 #endif 689 690 #ifndef LINUX_REMOVE 691 /** 692 * @brief - count number of function with a matching personality on engine. 693 * 694 * @param p_hwfn 695 * @param p_ptt 696 * @param personalities - a bitmask of ecore_pci_personality values 697 * 698 * @returns the count of all devices on engine whose personality match one of 699 * the bitsmasks. 700 */ 701 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn, 702 struct ecore_ptt *p_ptt, 703 u32 personalities); 704 #endif 705 706 /** 707 * @brief Get the flash size value 708 * 709 * @param p_hwfn 710 * @param p_ptt 711 * @param p_flash_size - flash size in bytes to be filled. 712 * 713 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 714 */ 715 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn, 716 struct ecore_ptt *p_ptt, 717 u32 *p_flash_size); 718 719 /** 720 * @brief Send driver version to MFW 721 * 722 * @param p_hwfn 723 * @param p_ptt 724 * @param version - Version value 725 * @param name - Protocol driver name 726 * 727 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 728 */ 729 enum _ecore_status_t 730 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 731 struct ecore_mcp_drv_version *p_ver); 732 733 /** 734 * @brief Read the MFW process kill counter 735 * 736 * @param p_hwfn 737 * @param p_ptt 738 * 739 * @return u32 740 */ 741 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn, 742 struct ecore_ptt *p_ptt); 743 744 /** 745 * @brief Trigger a recovery process 746 * 747 * @param p_hwfn 748 * @param p_ptt 749 * 750 * @return enum _ecore_status_t 751 */ 752 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn, 753 struct ecore_ptt *p_ptt); 754 755 /** 756 * @brief Notify MFW about the change in base device properties 757 * 758 * @param p_hwfn 759 * @param p_ptt 760 * @param client - ecore client type 761 * 762 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 763 */ 764 enum _ecore_status_t 765 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn, 766 struct ecore_ptt *p_ptt, 767 enum ecore_ov_client client); 768 769 /** 770 * @brief Notify MFW about the driver state 771 * 772 * @param p_hwfn 773 * @param p_ptt 774 * @param drv_state - Driver state 775 * 776 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 777 */ 778 enum _ecore_status_t 779 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn, 780 struct ecore_ptt *p_ptt, 781 enum ecore_ov_driver_state drv_state); 782 783 /** 784 * @brief Read NPIV settings form the MFW 785 * 786 * @param p_hwfn 787 * @param p_ptt 788 * @param p_table - Array to hold the FC NPIV data. Client need allocate the 789 * required buffer. The field 'count' specifies number of NPIV 790 * entries. A value of 0 means the table was not populated. 791 * 792 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 793 */ 794 enum _ecore_status_t 795 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 796 struct ecore_fc_npiv_tbl *p_table); 797 798 /** 799 * @brief Send MTU size to MFW 800 * 801 * @param p_hwfn 802 * @param p_ptt 803 * @param mtu - MTU size 804 * 805 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 806 */ 807 enum _ecore_status_t ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn, 808 struct ecore_ptt *p_ptt, u16 mtu); 809 810 /** 811 * @brief Send MAC address to MFW 812 * 813 * @param p_hwfn 814 * @param p_ptt 815 * @param mac - MAC address 816 * 817 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 818 */ 819 enum _ecore_status_t 820 ecore_mcp_ov_update_mac(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 821 u8 *mac); 822 823 /** 824 * @brief Send WOL mode to MFW 825 * 826 * @param p_hwfn 827 * @param p_ptt 828 * @param wol - WOL mode 829 * 830 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 831 */ 832 enum _ecore_status_t 833 ecore_mcp_ov_update_wol(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 834 enum ecore_ov_wol wol); 835 836 /** 837 * @brief Set LED status 838 * 839 * @param p_hwfn 840 * @param p_ptt 841 * @param mode - LED mode 842 * 843 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 844 */ 845 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn, 846 struct ecore_ptt *p_ptt, 847 enum ecore_led_mode mode); 848 849 /** 850 * @brief Set secure mode 851 * 852 * @param p_dev 853 * @param addr - nvm offset 854 * 855 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 856 */ 857 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev, 858 u32 addr); 859 860 /** 861 * @brief Write to phy 862 * 863 * @param p_dev 864 * @param addr - nvm offset 865 * @param cmd - nvm command 866 * @param p_buf - nvm write buffer 867 * @param len - buffer len 868 * 869 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 870 */ 871 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd, 872 u32 addr, u8 *p_buf, u32 len); 873 874 /** 875 * @brief Write to nvm 876 * 877 * @param p_dev 878 * @param addr - nvm offset 879 * @param cmd - nvm command 880 * @param p_buf - nvm write buffer 881 * @param len - buffer len 882 * 883 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 884 */ 885 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd, 886 u32 addr, u8 *p_buf, u32 len); 887 888 /** 889 * @brief Put file begin 890 * 891 * @param p_dev 892 * @param addr - nvm offset 893 * 894 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 895 */ 896 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev, 897 u32 addr); 898 899 /** 900 * @brief Delete file 901 * 902 * @param p_dev 903 * @param addr - nvm offset 904 * 905 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 906 */ 907 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, 908 u32 addr); 909 910 /** 911 * @brief Check latest response 912 * 913 * @param p_dev 914 * @param p_buf - nvm write buffer 915 * 916 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 917 */ 918 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf); 919 920 /** 921 * @brief Read from phy 922 * 923 * @param p_dev 924 * @param addr - nvm offset 925 * @param cmd - nvm command 926 * @param p_buf - nvm write buffer 927 * @param len - buffer len 928 * 929 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 930 */ 931 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd, 932 u32 addr, u8 *p_buf, u32 len); 933 934 /** 935 * @brief Read from nvm 936 * 937 * @param p_dev 938 * @param addr - nvm offset 939 * @param p_buf - nvm write buffer 940 * @param len - buffer len 941 * 942 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 943 */ 944 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr, 945 u8 *p_buf, u32 len); 946 947 struct ecore_nvm_image_att { 948 u32 start_addr; 949 u32 length; 950 }; 951 952 /** 953 * @brief Allows reading a whole nvram image 954 * 955 * @param p_hwfn 956 * @param p_ptt 957 * @param image_id - image to get attributes for 958 * @param p_image_att - image attributes structure into which to fill data 959 * 960 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 961 */ 962 enum _ecore_status_t 963 ecore_mcp_get_nvm_image_att(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 964 enum ecore_nvm_images image_id, 965 struct ecore_nvm_image_att *p_image_att); 966 967 /** 968 * @brief Allows reading a whole nvram image 969 * 970 * @param p_hwfn 971 * @param p_ptt 972 * @param image_id - image requested for reading 973 * @param p_buffer - allocated buffer into which to fill data 974 * @param buffer_len - length of the allocated buffer. 975 * 976 * @return ECORE_SUCCESS iff p_buffer now contains the nvram image. 977 */ 978 enum _ecore_status_t ecore_mcp_get_nvm_image(struct ecore_hwfn *p_hwfn, 979 struct ecore_ptt *p_ptt, 980 enum ecore_nvm_images image_id, 981 u8 *p_buffer, u32 buffer_len); 982 983 /** 984 * @brief - Sends an NVM write command request to the MFW with 985 * payload. 986 * 987 * @param p_hwfn 988 * @param p_ptt 989 * @param cmd - Command: Either DRV_MSG_CODE_NVM_WRITE_NVRAM or 990 * DRV_MSG_CODE_NVM_PUT_FILE_DATA 991 * @param param - [0:23] - Offset [24:31] - Size 992 * @param o_mcp_resp - MCP response 993 * @param o_mcp_param - MCP response param 994 * @param i_txn_size - Buffer size 995 * @param i_buf - Pointer to the buffer 996 * 997 * @param return ECORE_SUCCESS upon success. 998 */ 999 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn, 1000 struct ecore_ptt *p_ptt, 1001 u32 cmd, 1002 u32 param, 1003 u32 *o_mcp_resp, 1004 u32 *o_mcp_param, 1005 u32 i_txn_size, 1006 u32 *i_buf); 1007 1008 /** 1009 * @brief - Sends an NVM read command request to the MFW to get 1010 * a buffer. 1011 * 1012 * @param p_hwfn 1013 * @param p_ptt 1014 * @param cmd - Command: DRV_MSG_CODE_NVM_GET_FILE_DATA or 1015 * DRV_MSG_CODE_NVM_READ_NVRAM commands 1016 * @param param - [0:23] - Offset [24:31] - Size 1017 * @param o_mcp_resp - MCP response 1018 * @param o_mcp_param - MCP response param 1019 * @param o_txn_size - Buffer size output 1020 * @param o_buf - Pointer to the buffer returned by the MFW. 1021 * 1022 * @param return ECORE_SUCCESS upon success. 1023 */ 1024 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn, 1025 struct ecore_ptt *p_ptt, 1026 u32 cmd, 1027 u32 param, 1028 u32 *o_mcp_resp, 1029 u32 *o_mcp_param, 1030 u32 *o_txn_size, 1031 u32 *o_buf); 1032 1033 /** 1034 * @brief Read from sfp 1035 * 1036 * @param p_hwfn - hw function 1037 * @param p_ptt - PTT required for register access 1038 * @param port - transceiver port 1039 * @param addr - I2C address 1040 * @param offset - offset in sfp 1041 * @param len - buffer length 1042 * @param p_buf - buffer to read into 1043 * 1044 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1045 */ 1046 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn, 1047 struct ecore_ptt *p_ptt, 1048 u32 port, u32 addr, u32 offset, 1049 u32 len, u8 *p_buf); 1050 1051 /** 1052 * @brief Write to sfp 1053 * 1054 * @param p_hwfn - hw function 1055 * @param p_ptt - PTT required for register access 1056 * @param port - transceiver port 1057 * @param addr - I2C address 1058 * @param offset - offset in sfp 1059 * @param len - buffer length 1060 * @param p_buf - buffer to write from 1061 * 1062 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1063 */ 1064 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn, 1065 struct ecore_ptt *p_ptt, 1066 u32 port, u32 addr, u32 offset, 1067 u32 len, u8 *p_buf); 1068 1069 /** 1070 * @brief Gpio read 1071 * 1072 * @param p_hwfn - hw function 1073 * @param p_ptt - PTT required for register access 1074 * @param gpio - gpio number 1075 * @param gpio_val - value read from gpio 1076 * 1077 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1078 */ 1079 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn, 1080 struct ecore_ptt *p_ptt, 1081 u16 gpio, u32 *gpio_val); 1082 1083 /** 1084 * @brief Gpio write 1085 * 1086 * @param p_hwfn - hw function 1087 * @param p_ptt - PTT required for register access 1088 * @param gpio - gpio number 1089 * @param gpio_val - value to write to gpio 1090 * 1091 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1092 */ 1093 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn, 1094 struct ecore_ptt *p_ptt, 1095 u16 gpio, u16 gpio_val); 1096 1097 /** 1098 * @brief Gpio get information 1099 * 1100 * @param p_hwfn - hw function 1101 * @param p_ptt - PTT required for register access 1102 * @param gpio - gpio number 1103 * @param gpio_direction - gpio is output (0) or input (1) 1104 * @param gpio_ctrl - gpio control is uninitialized (0), 1105 * path 0 (1), path 1 (2) or shared(3) 1106 * 1107 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1108 */ 1109 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn, 1110 struct ecore_ptt *p_ptt, 1111 u16 gpio, u32 *gpio_direction, 1112 u32 *gpio_ctrl); 1113 1114 /** 1115 * @brief Bist register test 1116 * 1117 * @param p_hwfn - hw function 1118 * @param p_ptt - PTT required for register access 1119 * 1120 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1121 */ 1122 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn, 1123 struct ecore_ptt *p_ptt); 1124 1125 /** 1126 * @brief Bist clock test 1127 * 1128 * @param p_hwfn - hw function 1129 * @param p_ptt - PTT required for register access 1130 * 1131 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1132 */ 1133 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn, 1134 struct ecore_ptt *p_ptt); 1135 1136 /** 1137 * @brief Bist nvm test - get number of images 1138 * 1139 * @param p_hwfn - hw function 1140 * @param p_ptt - PTT required for register access 1141 * @param num_images - number of images if operation was 1142 * successful. 0 if not. 1143 * 1144 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1145 */ 1146 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(struct ecore_hwfn *p_hwfn, 1147 struct ecore_ptt *p_ptt, 1148 u32 *num_images); 1149 1150 /** 1151 * @brief Bist nvm test - get image attributes by index 1152 * 1153 * @param p_hwfn - hw function 1154 * @param p_ptt - PTT required for register access 1155 * @param p_image_att - Attributes of image 1156 * @param image_index - Index of image to get information for 1157 * 1158 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1159 */ 1160 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(struct ecore_hwfn *p_hwfn, 1161 struct ecore_ptt *p_ptt, 1162 struct bist_nvm_image_att *p_image_att, 1163 u32 image_index); 1164 1165 /** 1166 * @brief ecore_mcp_get_temperature_info - get the status of the temperature 1167 * sensors 1168 * 1169 * @param p_hwfn - hw function 1170 * @param p_ptt - PTT required for register access 1171 * @param p_temp_status - A pointer to an ecore_temperature_info structure to 1172 * be filled with the temperature data 1173 * 1174 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1175 */ 1176 enum _ecore_status_t 1177 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn, 1178 struct ecore_ptt *p_ptt, 1179 struct ecore_temperature_info *p_temp_info); 1180 1181 /** 1182 * @brief Get MBA versions - get MBA sub images versions 1183 * 1184 * @param p_hwfn - hw function 1185 * @param p_ptt - PTT required for register access 1186 * @param p_mba_vers - MBA versions array to fill 1187 * 1188 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1189 */ 1190 enum _ecore_status_t ecore_mcp_get_mba_versions( 1191 struct ecore_hwfn *p_hwfn, 1192 struct ecore_ptt *p_ptt, 1193 struct ecore_mba_vers *p_mba_vers); 1194 1195 /** 1196 * @brief Count memory ecc events 1197 * 1198 * @param p_hwfn - hw function 1199 * @param p_ptt - PTT required for register access 1200 * @param num_events - number of memory ecc events 1201 * 1202 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1203 */ 1204 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn, 1205 struct ecore_ptt *p_ptt, 1206 u64 *num_events); 1207 1208 struct ecore_mdump_info { 1209 u32 reason; 1210 u32 version; 1211 u32 config; 1212 u32 epoch; 1213 u32 num_of_logs; 1214 u32 valid_logs; 1215 }; 1216 1217 /** 1218 * @brief - Gets the MFW crash dump configuration and logs info. 1219 * 1220 * @param p_hwfn 1221 * @param p_ptt 1222 * @param p_mdump_info 1223 * 1224 * @param return ECORE_SUCCESS upon success. 1225 */ 1226 enum _ecore_status_t 1227 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 1228 struct ecore_mdump_info *p_mdump_info); 1229 1230 /** 1231 * @brief - Clears the MFW crash dump logs. 1232 * 1233 * @param p_hwfn 1234 * @param p_ptt 1235 * 1236 * @param return ECORE_SUCCESS upon success. 1237 */ 1238 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn, 1239 struct ecore_ptt *p_ptt); 1240 1241 /** 1242 * @brief - Clear the mdump retained data. 1243 * 1244 * @param p_hwfn 1245 * @param p_ptt 1246 * 1247 * @param return ECORE_SUCCESS upon success. 1248 */ 1249 enum _ecore_status_t ecore_mcp_mdump_clr_retain(struct ecore_hwfn *p_hwfn, 1250 struct ecore_ptt *p_ptt); 1251 1252 /** 1253 * @brief - Gets the LLDP MAC address. 1254 * 1255 * @param p_hwfn 1256 * @param p_ptt 1257 * @param lldp_mac_addr - a buffer to be filled with the read LLDP MAC address. 1258 * 1259 * @param return ECORE_SUCCESS upon success. 1260 */ 1261 enum _ecore_status_t ecore_mcp_get_lldp_mac(struct ecore_hwfn *p_hwfn, 1262 struct ecore_ptt *p_ptt, 1263 u8 lldp_mac_addr[ETH_ALEN]); 1264 1265 /** 1266 * @brief - Sets the LLDP MAC address. 1267 * 1268 * @param p_hwfn 1269 * @param p_ptt 1270 * @param lldp_mac_addr - a buffer with the LLDP MAC address to be written. 1271 * 1272 * @param return ECORE_SUCCESS upon success. 1273 */ 1274 enum _ecore_status_t ecore_mcp_set_lldp_mac(struct ecore_hwfn *p_hwfn, 1275 struct ecore_ptt *p_ptt, 1276 u8 lldp_mac_addr[ETH_ALEN]); 1277 1278 /** 1279 * @brief - Processes the TLV request from MFW i.e., get the required TLV info 1280 * from the ecore client and send it to the MFW. 1281 * 1282 * @param p_hwfn 1283 * @param p_ptt 1284 * 1285 * @param return ECORE_SUCCESS upon success. 1286 */ 1287 enum _ecore_status_t ecore_mfw_process_tlv_req(struct ecore_hwfn *p_hwfn, 1288 struct ecore_ptt *p_ptt); 1289 1290 /** 1291 * @brief - Update fcoe vlan id value to the MFW. 1292 * 1293 * @param p_hwfn 1294 * @param p_ptt 1295 * @param vlan - fcoe vlan 1296 * 1297 * @param return ECORE_SUCCESS upon success. 1298 */ 1299 enum _ecore_status_t 1300 ecore_mcp_update_fcoe_cvid(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 1301 u16 vlan); 1302 1303 /** 1304 * @brief - Update fabric name (wwn) value to the MFW. 1305 * 1306 * @param p_hwfn 1307 * @param p_ptt 1308 * @param wwn - world wide name 1309 * 1310 * @param return ECORE_SUCCESS upon success. 1311 */ 1312 enum _ecore_status_t 1313 ecore_mcp_update_fcoe_fabric_name(struct ecore_hwfn *p_hwfn, 1314 struct ecore_ptt *p_ptt, u8 *wwn); 1315 #endif 1316