1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 32 #ifndef __RT_DEFS_H__ 33 #define __RT_DEFS_H__ 34 35 /* Runtime array offsets */ 36 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0 37 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1 38 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2 39 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3 40 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4 41 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5 42 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6 43 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7 44 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8 45 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9 46 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10 47 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11 48 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12 49 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13 50 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14 51 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15 52 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16 53 #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17 54 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET 18 55 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET 19 56 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 20 57 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 21 58 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 22 59 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 23 60 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 24 61 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 1049 62 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 1024 63 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 1049 64 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 1024 65 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 2073 66 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 1024 67 #define CAU_REG_PI_MEMORY_RT_OFFSET 3097 68 #define CAU_REG_PI_MEMORY_RT_SIZE 4416 69 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 7513 70 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 7514 71 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 7515 72 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 7516 73 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 7517 74 #define PRS_REG_SEARCH_TCP_RT_OFFSET 7518 75 #define PRS_REG_SEARCH_FCOE_RT_OFFSET 7519 76 #define PRS_REG_SEARCH_ROCE_RT_OFFSET 7520 77 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 7521 78 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 7522 79 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 7523 80 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 7524 81 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 7525 82 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 7526 83 #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 7527 84 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 7528 85 #define SRC_REG_FIRSTFREE_RT_OFFSET 7529 86 #define SRC_REG_FIRSTFREE_RT_SIZE 2 87 #define SRC_REG_LASTFREE_RT_OFFSET 7531 88 #define SRC_REG_LASTFREE_RT_SIZE 2 89 #define SRC_REG_COUNTFREE_RT_OFFSET 7533 90 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 7534 91 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 7535 92 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 7536 93 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 7537 94 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 7538 95 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 7539 96 #define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 7540 97 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 7541 98 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 7542 99 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 7543 100 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 7544 101 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 7545 102 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 7546 103 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 7547 104 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 7548 105 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 7549 106 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 7550 107 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 7551 108 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 7552 109 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 7553 110 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 7554 111 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 7555 112 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 7556 113 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 7557 114 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 7558 115 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 7559 116 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 7560 117 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 7561 118 #define PSWRQ2_REG_VF_BASE_RT_OFFSET 7562 119 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 7563 120 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 7564 121 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 7565 122 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 7566 123 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000 124 #define PGLUE_REG_B_VF_BASE_RT_OFFSET 29566 125 #define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 29567 126 #define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 29568 127 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 29569 128 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 29570 129 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 29571 130 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 29572 131 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET 29573 132 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET 29574 133 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET 29575 134 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 29576 135 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 29577 136 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 29578 137 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416 138 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29994 139 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE 608 140 #define QM_REG_MAXPQSIZE_0_RT_OFFSET 30602 141 #define QM_REG_MAXPQSIZE_1_RT_OFFSET 30603 142 #define QM_REG_MAXPQSIZE_2_RT_OFFSET 30604 143 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 30605 144 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 30606 145 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 30607 146 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 30608 147 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 30609 148 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 30610 149 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 30611 150 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 30612 151 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 30613 152 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 30614 153 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 30615 154 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 30616 155 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 30617 156 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 30618 157 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 30619 158 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 30620 159 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 30621 160 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 30622 161 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 30623 162 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 30624 163 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 30625 164 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 30626 165 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 30627 166 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 30628 167 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 30629 168 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 30630 169 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 30631 170 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 30632 171 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 30633 172 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 30634 173 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 30635 174 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 30636 175 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 30637 176 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 30638 177 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 30639 178 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 30640 179 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 30641 180 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 30642 181 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 30643 182 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 30644 183 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 30645 184 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 30646 185 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 30647 186 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 30648 187 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 30649 188 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 30650 189 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 30651 190 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 30652 191 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 30653 192 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 30654 193 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 30655 194 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 30656 195 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 30657 196 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 30658 197 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 30659 198 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 30660 199 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 30661 200 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 30662 201 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 30663 202 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 30664 203 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 30665 204 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 30666 205 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 30667 206 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 30668 207 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET 30669 208 #define QM_REG_BASEADDROTHERPQ_RT_SIZE 128 209 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 30797 210 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 30798 211 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 30799 212 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 30800 213 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 30801 214 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 30802 215 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 30803 216 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 30804 217 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 30805 218 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 30806 219 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 30807 220 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 30808 221 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 30809 222 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 30810 223 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 30811 224 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 30812 225 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 30813 226 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 30814 227 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 30815 228 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 30816 229 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 30817 230 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 30818 231 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 30819 232 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 30820 233 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 30821 234 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 30822 235 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 30823 236 #define QM_REG_PQTX2PF_0_RT_OFFSET 30824 237 #define QM_REG_PQTX2PF_1_RT_OFFSET 30825 238 #define QM_REG_PQTX2PF_2_RT_OFFSET 30826 239 #define QM_REG_PQTX2PF_3_RT_OFFSET 30827 240 #define QM_REG_PQTX2PF_4_RT_OFFSET 30828 241 #define QM_REG_PQTX2PF_5_RT_OFFSET 30829 242 #define QM_REG_PQTX2PF_6_RT_OFFSET 30830 243 #define QM_REG_PQTX2PF_7_RT_OFFSET 30831 244 #define QM_REG_PQTX2PF_8_RT_OFFSET 30832 245 #define QM_REG_PQTX2PF_9_RT_OFFSET 30833 246 #define QM_REG_PQTX2PF_10_RT_OFFSET 30834 247 #define QM_REG_PQTX2PF_11_RT_OFFSET 30835 248 #define QM_REG_PQTX2PF_12_RT_OFFSET 30836 249 #define QM_REG_PQTX2PF_13_RT_OFFSET 30837 250 #define QM_REG_PQTX2PF_14_RT_OFFSET 30838 251 #define QM_REG_PQTX2PF_15_RT_OFFSET 30839 252 #define QM_REG_PQTX2PF_16_RT_OFFSET 30840 253 #define QM_REG_PQTX2PF_17_RT_OFFSET 30841 254 #define QM_REG_PQTX2PF_18_RT_OFFSET 30842 255 #define QM_REG_PQTX2PF_19_RT_OFFSET 30843 256 #define QM_REG_PQTX2PF_20_RT_OFFSET 30844 257 #define QM_REG_PQTX2PF_21_RT_OFFSET 30845 258 #define QM_REG_PQTX2PF_22_RT_OFFSET 30846 259 #define QM_REG_PQTX2PF_23_RT_OFFSET 30847 260 #define QM_REG_PQTX2PF_24_RT_OFFSET 30848 261 #define QM_REG_PQTX2PF_25_RT_OFFSET 30849 262 #define QM_REG_PQTX2PF_26_RT_OFFSET 30850 263 #define QM_REG_PQTX2PF_27_RT_OFFSET 30851 264 #define QM_REG_PQTX2PF_28_RT_OFFSET 30852 265 #define QM_REG_PQTX2PF_29_RT_OFFSET 30853 266 #define QM_REG_PQTX2PF_30_RT_OFFSET 30854 267 #define QM_REG_PQTX2PF_31_RT_OFFSET 30855 268 #define QM_REG_PQTX2PF_32_RT_OFFSET 30856 269 #define QM_REG_PQTX2PF_33_RT_OFFSET 30857 270 #define QM_REG_PQTX2PF_34_RT_OFFSET 30858 271 #define QM_REG_PQTX2PF_35_RT_OFFSET 30859 272 #define QM_REG_PQTX2PF_36_RT_OFFSET 30860 273 #define QM_REG_PQTX2PF_37_RT_OFFSET 30861 274 #define QM_REG_PQTX2PF_38_RT_OFFSET 30862 275 #define QM_REG_PQTX2PF_39_RT_OFFSET 30863 276 #define QM_REG_PQTX2PF_40_RT_OFFSET 30864 277 #define QM_REG_PQTX2PF_41_RT_OFFSET 30865 278 #define QM_REG_PQTX2PF_42_RT_OFFSET 30866 279 #define QM_REG_PQTX2PF_43_RT_OFFSET 30867 280 #define QM_REG_PQTX2PF_44_RT_OFFSET 30868 281 #define QM_REG_PQTX2PF_45_RT_OFFSET 30869 282 #define QM_REG_PQTX2PF_46_RT_OFFSET 30870 283 #define QM_REG_PQTX2PF_47_RT_OFFSET 30871 284 #define QM_REG_PQTX2PF_48_RT_OFFSET 30872 285 #define QM_REG_PQTX2PF_49_RT_OFFSET 30873 286 #define QM_REG_PQTX2PF_50_RT_OFFSET 30874 287 #define QM_REG_PQTX2PF_51_RT_OFFSET 30875 288 #define QM_REG_PQTX2PF_52_RT_OFFSET 30876 289 #define QM_REG_PQTX2PF_53_RT_OFFSET 30877 290 #define QM_REG_PQTX2PF_54_RT_OFFSET 30878 291 #define QM_REG_PQTX2PF_55_RT_OFFSET 30879 292 #define QM_REG_PQTX2PF_56_RT_OFFSET 30880 293 #define QM_REG_PQTX2PF_57_RT_OFFSET 30881 294 #define QM_REG_PQTX2PF_58_RT_OFFSET 30882 295 #define QM_REG_PQTX2PF_59_RT_OFFSET 30883 296 #define QM_REG_PQTX2PF_60_RT_OFFSET 30884 297 #define QM_REG_PQTX2PF_61_RT_OFFSET 30885 298 #define QM_REG_PQTX2PF_62_RT_OFFSET 30886 299 #define QM_REG_PQTX2PF_63_RT_OFFSET 30887 300 #define QM_REG_PQOTHER2PF_0_RT_OFFSET 30888 301 #define QM_REG_PQOTHER2PF_1_RT_OFFSET 30889 302 #define QM_REG_PQOTHER2PF_2_RT_OFFSET 30890 303 #define QM_REG_PQOTHER2PF_3_RT_OFFSET 30891 304 #define QM_REG_PQOTHER2PF_4_RT_OFFSET 30892 305 #define QM_REG_PQOTHER2PF_5_RT_OFFSET 30893 306 #define QM_REG_PQOTHER2PF_6_RT_OFFSET 30894 307 #define QM_REG_PQOTHER2PF_7_RT_OFFSET 30895 308 #define QM_REG_PQOTHER2PF_8_RT_OFFSET 30896 309 #define QM_REG_PQOTHER2PF_9_RT_OFFSET 30897 310 #define QM_REG_PQOTHER2PF_10_RT_OFFSET 30898 311 #define QM_REG_PQOTHER2PF_11_RT_OFFSET 30899 312 #define QM_REG_PQOTHER2PF_12_RT_OFFSET 30900 313 #define QM_REG_PQOTHER2PF_13_RT_OFFSET 30901 314 #define QM_REG_PQOTHER2PF_14_RT_OFFSET 30902 315 #define QM_REG_PQOTHER2PF_15_RT_OFFSET 30903 316 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 30904 317 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 30905 318 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 30906 319 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 30907 320 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 30908 321 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 30909 322 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 30910 323 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 30911 324 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 30912 325 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 30913 326 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 30914 327 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 30915 328 #define QM_REG_RLGLBLINCVAL_RT_OFFSET 30916 329 #define QM_REG_RLGLBLINCVAL_RT_SIZE 256 330 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 31172 331 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256 332 #define QM_REG_RLGLBLCRD_RT_OFFSET 31428 333 #define QM_REG_RLGLBLCRD_RT_SIZE 256 334 #define QM_REG_RLGLBLENABLE_RT_OFFSET 31684 335 #define QM_REG_RLPFPERIOD_RT_OFFSET 31685 336 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET 31686 337 #define QM_REG_RLPFINCVAL_RT_OFFSET 31687 338 #define QM_REG_RLPFINCVAL_RT_SIZE 16 339 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET 31703 340 #define QM_REG_RLPFUPPERBOUND_RT_SIZE 16 341 #define QM_REG_RLPFCRD_RT_OFFSET 31719 342 #define QM_REG_RLPFCRD_RT_SIZE 16 343 #define QM_REG_RLPFENABLE_RT_OFFSET 31735 344 #define QM_REG_RLPFVOQENABLE_RT_OFFSET 31736 345 #define QM_REG_WFQPFWEIGHT_RT_OFFSET 31737 346 #define QM_REG_WFQPFWEIGHT_RT_SIZE 16 347 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 31753 348 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16 349 #define QM_REG_WFQPFCRD_RT_OFFSET 31769 350 #define QM_REG_WFQPFCRD_RT_SIZE 256 351 #define QM_REG_WFQPFENABLE_RT_OFFSET 32025 352 #define QM_REG_WFQVPENABLE_RT_OFFSET 32026 353 #define QM_REG_BASEADDRTXPQ_RT_OFFSET 32027 354 #define QM_REG_BASEADDRTXPQ_RT_SIZE 512 355 #define QM_REG_TXPQMAP_RT_OFFSET 32539 356 #define QM_REG_TXPQMAP_RT_SIZE 512 357 #define QM_REG_WFQVPWEIGHT_RT_OFFSET 33051 358 #define QM_REG_WFQVPWEIGHT_RT_SIZE 512 359 #define QM_REG_WFQVPCRD_RT_OFFSET 33563 360 #define QM_REG_WFQVPCRD_RT_SIZE 512 361 #define QM_REG_WFQVPMAP_RT_OFFSET 34075 362 #define QM_REG_WFQVPMAP_RT_SIZE 512 363 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET 34587 364 #define QM_REG_WFQPFCRD_MSB_RT_SIZE 320 365 #define QM_REG_VOQCRDLINE_RT_OFFSET 34907 366 #define QM_REG_VOQCRDLINE_RT_SIZE 36 367 #define QM_REG_VOQINITCRDLINE_RT_OFFSET 34943 368 #define QM_REG_VOQINITCRDLINE_RT_SIZE 36 369 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 34979 370 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 34980 371 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 34981 372 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 34982 373 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 34983 374 #define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 34984 375 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 34985 376 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 34986 377 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4 378 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 34990 379 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE 4 380 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 34994 381 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4 382 #define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 34998 383 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 34999 384 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32 385 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 35031 386 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16 387 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 35047 388 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16 389 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 35063 390 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16 391 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 35079 392 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16 393 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 35095 394 #define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 35096 395 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 35097 396 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 35098 397 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 35099 398 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 35100 399 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 35101 400 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 35102 401 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 35103 402 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 35104 403 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 35105 404 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 35106 405 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 35107 406 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 35108 407 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 35109 408 #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 35110 409 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 35111 410 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 35112 411 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 35113 412 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 35114 413 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 35115 414 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 35116 415 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 35117 416 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 35118 417 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 35119 418 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 35120 419 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 35121 420 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 35122 421 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 35123 422 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 35124 423 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 35125 424 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 35126 425 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 35127 426 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 35128 427 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 35129 428 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 35130 429 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 35131 430 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 35132 431 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 35133 432 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 35134 433 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 35135 434 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 35136 435 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 35137 436 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 35138 437 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 35139 438 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 35140 439 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 35141 440 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 35142 441 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 35143 442 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 35144 443 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 35145 444 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 35146 445 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 35147 446 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 35148 447 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 35149 448 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 35150 449 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 35151 450 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 35152 451 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 35153 452 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 35154 453 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 35155 454 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 35156 455 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 35157 456 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 35158 457 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 35159 458 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 35160 459 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 35161 460 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 35162 461 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 35163 462 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 35164 463 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 35165 464 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 35166 465 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 35167 466 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 35168 467 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 35169 468 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 35170 469 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 35171 470 #define XCM_REG_CON_PHY_Q3_RT_OFFSET 35172 471 472 #define RUNTIME_ARRAY_SIZE 35173 473 474 #endif /* __RT_DEFS_H__ */ 475