1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * File : ecore_sp_commands.c 30 */ 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "bcm_osal.h" 35 36 #include "ecore.h" 37 #include "ecore_status.h" 38 #include "ecore_chain.h" 39 #include "ecore_spq.h" 40 #include "ecore_init_fw_funcs.h" 41 #include "ecore_cxt.h" 42 #include "ecore_sp_commands.h" 43 #include "ecore_gtt_reg_addr.h" 44 #include "ecore_iro.h" 45 #include "reg_addr.h" 46 #include "ecore_int.h" 47 #include "ecore_hw.h" 48 #include "ecore_dcbx.h" 49 #include "ecore_sriov.h" 50 #include "ecore_vf.h" 51 52 enum _ecore_status_t ecore_sp_init_request(struct ecore_hwfn *p_hwfn, 53 struct ecore_spq_entry **pp_ent, 54 u8 cmd, 55 u8 protocol, 56 struct ecore_sp_init_data *p_data) 57 { 58 u32 opaque_cid = p_data->opaque_fid << 16 | p_data->cid; 59 struct ecore_spq_entry *p_ent = OSAL_NULL; 60 enum _ecore_status_t rc; 61 62 if (!pp_ent) 63 return ECORE_INVAL; 64 65 /* Get an SPQ entry */ 66 rc = ecore_spq_get_entry(p_hwfn, pp_ent); 67 if (rc != ECORE_SUCCESS) 68 return rc; 69 70 /* Fill the SPQ entry */ 71 p_ent = *pp_ent; 72 p_ent->elem.hdr.cid = OSAL_CPU_TO_LE32(opaque_cid); 73 p_ent->elem.hdr.cmd_id = cmd; 74 p_ent->elem.hdr.protocol_id = protocol; 75 p_ent->priority = ECORE_SPQ_PRIORITY_NORMAL; 76 p_ent->comp_mode = p_data->comp_mode; 77 p_ent->comp_done.done = 0; 78 79 switch (p_ent->comp_mode) { 80 case ECORE_SPQ_MODE_EBLOCK: 81 p_ent->comp_cb.cookie = &p_ent->comp_done; 82 break; 83 84 case ECORE_SPQ_MODE_BLOCK: 85 if (!p_data->p_comp_data) 86 return ECORE_INVAL; 87 88 p_ent->comp_cb.cookie = p_data->p_comp_data->cookie; 89 break; 90 91 case ECORE_SPQ_MODE_CB: 92 if (!p_data->p_comp_data) 93 p_ent->comp_cb.function = OSAL_NULL; 94 else 95 p_ent->comp_cb = *p_data->p_comp_data; 96 break; 97 98 default: 99 DP_NOTICE(p_hwfn, true, "Unknown SPQE completion mode %d\n", 100 p_ent->comp_mode); 101 return ECORE_INVAL; 102 } 103 104 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, 105 "Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n", 106 opaque_cid, cmd, protocol, 107 (unsigned long)&p_ent->ramrod, 108 D_TRINE(p_ent->comp_mode, ECORE_SPQ_MODE_EBLOCK, 109 ECORE_SPQ_MODE_BLOCK, "MODE_EBLOCK", "MODE_BLOCK", 110 "MODE_CB")); 111 112 OSAL_MEMSET(&p_ent->ramrod, 0, sizeof(p_ent->ramrod)); 113 114 return ECORE_SUCCESS; 115 } 116 117 static enum tunnel_clss ecore_tunn_clss_to_fw_clss(u8 type) 118 { 119 switch (type) { 120 case ECORE_TUNN_CLSS_MAC_VLAN: 121 return TUNNEL_CLSS_MAC_VLAN; 122 case ECORE_TUNN_CLSS_MAC_VNI: 123 return TUNNEL_CLSS_MAC_VNI; 124 case ECORE_TUNN_CLSS_INNER_MAC_VLAN: 125 return TUNNEL_CLSS_INNER_MAC_VLAN; 126 case ECORE_TUNN_CLSS_INNER_MAC_VNI: 127 return TUNNEL_CLSS_INNER_MAC_VNI; 128 case ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE: 129 return TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE; 130 default: 131 return TUNNEL_CLSS_MAC_VLAN; 132 } 133 } 134 135 static void 136 ecore_set_pf_update_tunn_mode(struct ecore_tunnel_info *p_tun, 137 struct ecore_tunnel_info *p_src, 138 bool b_pf_start) 139 { 140 if (p_src->vxlan.b_update_mode || b_pf_start) 141 p_tun->vxlan.b_mode_enabled = p_src->vxlan.b_mode_enabled; 142 143 if (p_src->l2_gre.b_update_mode || b_pf_start) 144 p_tun->l2_gre.b_mode_enabled = p_src->l2_gre.b_mode_enabled; 145 146 if (p_src->ip_gre.b_update_mode || b_pf_start) 147 p_tun->ip_gre.b_mode_enabled = p_src->ip_gre.b_mode_enabled; 148 149 if (p_src->l2_geneve.b_update_mode || b_pf_start) 150 p_tun->l2_geneve.b_mode_enabled = 151 p_src->l2_geneve.b_mode_enabled; 152 153 if (p_src->ip_geneve.b_update_mode || b_pf_start) 154 p_tun->ip_geneve.b_mode_enabled = 155 p_src->ip_geneve.b_mode_enabled; 156 } 157 158 static void ecore_set_tunn_cls_info(struct ecore_tunnel_info *p_tun, 159 struct ecore_tunnel_info *p_src) 160 { 161 enum tunnel_clss type; 162 163 p_tun->b_update_rx_cls = p_src->b_update_rx_cls; 164 p_tun->b_update_tx_cls = p_src->b_update_tx_cls; 165 166 type = ecore_tunn_clss_to_fw_clss(p_src->vxlan.tun_cls); 167 p_tun->vxlan.tun_cls = (enum ecore_tunn_clss)type; 168 type = ecore_tunn_clss_to_fw_clss(p_src->l2_gre.tun_cls); 169 p_tun->l2_gre.tun_cls = (enum ecore_tunn_clss)type; 170 type = ecore_tunn_clss_to_fw_clss(p_src->ip_gre.tun_cls); 171 p_tun->ip_gre.tun_cls = (enum ecore_tunn_clss)type; 172 type = ecore_tunn_clss_to_fw_clss(p_src->l2_geneve.tun_cls); 173 p_tun->l2_geneve.tun_cls = (enum ecore_tunn_clss)type; 174 type = ecore_tunn_clss_to_fw_clss(p_src->ip_geneve.tun_cls); 175 p_tun->ip_geneve.tun_cls = (enum ecore_tunn_clss)type; 176 } 177 178 static void ecore_set_tunn_ports(struct ecore_tunnel_info *p_tun, 179 struct ecore_tunnel_info *p_src) 180 { 181 p_tun->geneve_port.b_update_port = p_src->geneve_port.b_update_port; 182 p_tun->vxlan_port.b_update_port = p_src->vxlan_port.b_update_port; 183 184 if (p_src->geneve_port.b_update_port) 185 p_tun->geneve_port.port = p_src->geneve_port.port; 186 187 if (p_src->vxlan_port.b_update_port) 188 p_tun->vxlan_port.port = p_src->vxlan_port.port; 189 } 190 191 static void 192 __ecore_set_ramrod_tunnel_param(u8 *p_tunn_cls, 193 struct ecore_tunn_update_type *tun_type) 194 { 195 *p_tunn_cls = tun_type->tun_cls; 196 } 197 198 static void 199 ecore_set_ramrod_tunnel_param(u8 *p_tunn_cls, 200 struct ecore_tunn_update_type *tun_type, 201 u8 *p_update_port, __le16 *p_port, 202 struct ecore_tunn_update_udp_port *p_udp_port) 203 { 204 __ecore_set_ramrod_tunnel_param(p_tunn_cls, tun_type); 205 if (p_udp_port->b_update_port) { 206 *p_update_port = 1; 207 *p_port = OSAL_CPU_TO_LE16(p_udp_port->port); 208 } 209 } 210 211 static void 212 ecore_tunn_set_pf_update_params(struct ecore_hwfn *p_hwfn, 213 struct ecore_tunnel_info *p_src, 214 struct pf_update_tunnel_config *p_tunn_cfg) 215 { 216 struct ecore_tunnel_info *p_tun = &p_hwfn->p_dev->tunnel; 217 218 ecore_set_pf_update_tunn_mode(p_tun, p_src, false); 219 ecore_set_tunn_cls_info(p_tun, p_src); 220 ecore_set_tunn_ports(p_tun, p_src); 221 222 ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan, 223 &p_tun->vxlan, 224 &p_tunn_cfg->set_vxlan_udp_port_flg, 225 &p_tunn_cfg->vxlan_udp_port, 226 &p_tun->vxlan_port); 227 228 ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve, 229 &p_tun->l2_geneve, 230 &p_tunn_cfg->set_geneve_udp_port_flg, 231 &p_tunn_cfg->geneve_udp_port, 232 &p_tun->geneve_port); 233 234 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve, 235 &p_tun->ip_geneve); 236 237 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre, 238 &p_tun->l2_gre); 239 240 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre, 241 &p_tun->ip_gre); 242 243 p_tunn_cfg->update_rx_pf_clss = p_tun->b_update_rx_cls; 244 } 245 246 static void ecore_set_hw_tunn_mode(struct ecore_hwfn *p_hwfn, 247 struct ecore_ptt *p_ptt, 248 struct ecore_tunnel_info *p_tun) 249 { 250 ecore_set_gre_enable(p_hwfn, p_ptt, p_tun->l2_gre.b_mode_enabled, 251 p_tun->ip_gre.b_mode_enabled); 252 ecore_set_vxlan_enable(p_hwfn, p_ptt, p_tun->vxlan.b_mode_enabled); 253 254 ecore_set_geneve_enable(p_hwfn, p_ptt, p_tun->l2_geneve.b_mode_enabled, 255 p_tun->ip_geneve.b_mode_enabled); 256 } 257 258 static void ecore_set_hw_tunn_mode_port(struct ecore_hwfn *p_hwfn, 259 struct ecore_ptt *p_ptt, 260 struct ecore_tunnel_info *p_tunn) 261 { 262 if (ECORE_IS_BB_A0(p_hwfn->p_dev)) { 263 DP_NOTICE(p_hwfn, true, 264 "A0 chip: tunnel hw config is not supported\n"); 265 return; 266 } 267 268 if (p_tunn->vxlan_port.b_update_port) 269 ecore_set_vxlan_dest_port(p_hwfn, p_ptt, 270 p_tunn->vxlan_port.port); 271 272 if (p_tunn->geneve_port.b_update_port) 273 ecore_set_geneve_dest_port(p_hwfn, p_ptt, 274 p_tunn->geneve_port.port); 275 276 ecore_set_hw_tunn_mode(p_hwfn, p_ptt, p_tunn); 277 } 278 279 static void 280 ecore_tunn_set_pf_start_params(struct ecore_hwfn *p_hwfn, 281 struct ecore_tunnel_info *p_src, 282 struct pf_start_tunnel_config *p_tunn_cfg) 283 { 284 struct ecore_tunnel_info *p_tun = &p_hwfn->p_dev->tunnel; 285 286 if (ECORE_IS_BB_A0(p_hwfn->p_dev)) { 287 DP_NOTICE(p_hwfn, true, 288 "A0 chip: tunnel pf start config is not supported\n"); 289 return; 290 } 291 292 if (!p_src) 293 return; 294 295 ecore_set_pf_update_tunn_mode(p_tun, p_src, true); 296 ecore_set_tunn_cls_info(p_tun, p_src); 297 ecore_set_tunn_ports(p_tun, p_src); 298 299 ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan, 300 &p_tun->vxlan, 301 &p_tunn_cfg->set_vxlan_udp_port_flg, 302 &p_tunn_cfg->vxlan_udp_port, 303 &p_tun->vxlan_port); 304 305 ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve, 306 &p_tun->l2_geneve, 307 &p_tunn_cfg->set_geneve_udp_port_flg, 308 &p_tunn_cfg->geneve_udp_port, 309 &p_tun->geneve_port); 310 311 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve, 312 &p_tun->ip_geneve); 313 314 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre, 315 &p_tun->l2_gre); 316 317 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre, 318 &p_tun->ip_gre); 319 } 320 321 enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn, 322 struct ecore_ptt *p_ptt, 323 struct ecore_tunnel_info *p_tunn, 324 enum ecore_mf_mode mode, 325 bool allow_npar_tx_switch) 326 { 327 struct pf_start_ramrod_data *p_ramrod = OSAL_NULL; 328 u16 sb = ecore_int_get_sp_sb_id(p_hwfn); 329 u8 sb_index = p_hwfn->p_eq->eq_sb_index; 330 struct ecore_spq_entry *p_ent = OSAL_NULL; 331 struct ecore_sp_init_data init_data; 332 enum _ecore_status_t rc = ECORE_NOTIMPL; 333 u8 page_cnt; 334 335 /* update initial eq producer */ 336 ecore_eq_prod_update(p_hwfn, 337 ecore_chain_get_prod_idx(&p_hwfn->p_eq->chain)); 338 339 /* Initialize the SPQ entry for the ramrod */ 340 OSAL_MEMSET(&init_data, 0, sizeof(init_data)); 341 init_data.cid = ecore_spq_get_cid(p_hwfn); 342 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 343 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK; 344 345 rc = ecore_sp_init_request(p_hwfn, &p_ent, 346 COMMON_RAMROD_PF_START, 347 PROTOCOLID_COMMON, 348 &init_data); 349 if (rc != ECORE_SUCCESS) 350 return rc; 351 352 /* Fill the ramrod data */ 353 p_ramrod = &p_ent->ramrod.pf_start; 354 p_ramrod->event_ring_sb_id = OSAL_CPU_TO_LE16(sb); 355 p_ramrod->event_ring_sb_index = sb_index; 356 p_ramrod->path_id = ECORE_PATH_ID(p_hwfn); 357 358 /* For easier debugging */ 359 p_ramrod->dont_log_ramrods = 0; 360 p_ramrod->log_type_mask = OSAL_CPU_TO_LE16(0x8f); 361 362 switch (mode) { 363 case ECORE_MF_DEFAULT: 364 case ECORE_MF_NPAR: 365 p_ramrod->mf_mode = MF_NPAR; 366 break; 367 case ECORE_MF_OVLAN: 368 p_ramrod->mf_mode = MF_OVLAN; 369 break; 370 default: 371 DP_NOTICE(p_hwfn, true, "Unsupported MF mode, init as DEFAULT\n"); 372 p_ramrod->mf_mode = MF_NPAR; 373 } 374 p_ramrod->outer_tag = p_hwfn->hw_info.ovlan; 375 376 /* Place EQ address in RAMROD */ 377 DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr, 378 p_hwfn->p_eq->chain.pbl_sp.p_phys_table); 379 page_cnt = (u8)ecore_chain_get_page_cnt(&p_hwfn->p_eq->chain); 380 p_ramrod->event_ring_num_pages = page_cnt; 381 DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr, 382 p_hwfn->p_consq->chain.pbl_sp.p_phys_table); 383 384 ecore_tunn_set_pf_start_params(p_hwfn, p_tunn, 385 &p_ramrod->tunnel_config); 386 387 if (IS_MF_SI(p_hwfn)) 388 p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch; 389 390 switch (p_hwfn->hw_info.personality) { 391 case ECORE_PCI_ETH: 392 p_ramrod->personality = PERSONALITY_ETH; 393 break; 394 case ECORE_PCI_FCOE: 395 p_ramrod->personality = PERSONALITY_FCOE; 396 break; 397 case ECORE_PCI_ISCSI: 398 p_ramrod->personality = PERSONALITY_ISCSI; 399 break; 400 case ECORE_PCI_ETH_IWARP: 401 case ECORE_PCI_ETH_ROCE: 402 case ECORE_PCI_ETH_RDMA: 403 p_ramrod->personality = PERSONALITY_RDMA_AND_ETH; 404 break; 405 default: 406 DP_NOTICE(p_hwfn, true, "Unknown personality %d\n", 407 p_hwfn->hw_info.personality); 408 p_ramrod->personality = PERSONALITY_ETH; 409 } 410 411 if (p_hwfn->p_dev->p_iov_info) { 412 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info; 413 414 p_ramrod->base_vf_id = (u8)p_iov->first_vf_in_pf; 415 p_ramrod->num_vfs = (u8)p_iov->total_vfs; 416 } 417 /* @@@TBD - update also the "ROCE_VER_KEY" entries when the FW RoCE HSI 418 * version is available. 419 */ 420 p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR; 421 p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR; 422 423 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, 424 "Setting event_ring_sb [id %04x index %02x], outer_tag [%d]\n", 425 sb, sb_index, p_ramrod->outer_tag); 426 427 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL); 428 429 if (p_tunn) 430 ecore_set_hw_tunn_mode_port(p_hwfn, p_ptt, 431 &p_hwfn->p_dev->tunnel); 432 433 return rc; 434 } 435 436 enum _ecore_status_t ecore_sp_pf_update_dcbx(struct ecore_hwfn *p_hwfn) 437 { 438 struct ecore_spq_entry *p_ent = OSAL_NULL; 439 struct ecore_sp_init_data init_data; 440 enum _ecore_status_t rc = ECORE_NOTIMPL; 441 442 /* Get SPQ entry */ 443 OSAL_MEMSET(&init_data, 0, sizeof(init_data)); 444 init_data.cid = ecore_spq_get_cid(p_hwfn); 445 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 446 init_data.comp_mode = ECORE_SPQ_MODE_CB; 447 448 rc = ecore_sp_init_request(p_hwfn, &p_ent, 449 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON, 450 &init_data); 451 if (rc != ECORE_SUCCESS) 452 return rc; 453 454 ecore_dcbx_set_pf_update_params(&p_hwfn->p_dcbx_info->results, 455 &p_ent->ramrod.pf_update); 456 457 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL); 458 } 459 460 enum _ecore_status_t ecore_sp_rl_update(struct ecore_hwfn *p_hwfn, 461 struct ecore_rl_update_params *params) 462 { 463 struct ecore_spq_entry *p_ent = OSAL_NULL; 464 enum _ecore_status_t rc = ECORE_NOTIMPL; 465 struct rl_update_ramrod_data *rl_update; 466 struct ecore_sp_init_data init_data; 467 468 /* Get SPQ entry */ 469 OSAL_MEMSET(&init_data, 0, sizeof(init_data)); 470 init_data.cid = ecore_spq_get_cid(p_hwfn); 471 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 472 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK; 473 474 rc = ecore_sp_init_request(p_hwfn, &p_ent, 475 COMMON_RAMROD_RL_UPDATE, PROTOCOLID_COMMON, 476 &init_data); 477 if (rc != ECORE_SUCCESS) 478 return rc; 479 480 rl_update = &p_ent->ramrod.rl_update; 481 482 rl_update->qcn_update_param_flg = params->qcn_update_param_flg; 483 rl_update->dcqcn_update_param_flg = params->dcqcn_update_param_flg; 484 rl_update->rl_init_flg = params->rl_init_flg; 485 rl_update->rl_start_flg = params->rl_start_flg; 486 rl_update->rl_stop_flg = params->rl_stop_flg; 487 rl_update->rl_id_first = params->rl_id_first; 488 rl_update->rl_id_last = params->rl_id_last; 489 rl_update->rl_dc_qcn_flg = params->rl_dc_qcn_flg; 490 rl_update->rl_bc_rate = OSAL_CPU_TO_LE32(params->rl_bc_rate); 491 rl_update->rl_max_rate = OSAL_CPU_TO_LE16(params->rl_max_rate); 492 rl_update->rl_r_ai = OSAL_CPU_TO_LE16(params->rl_r_ai); 493 rl_update->rl_r_hai = OSAL_CPU_TO_LE16(params->rl_r_hai); 494 rl_update->dcqcn_g = OSAL_CPU_TO_LE16(params->dcqcn_g); 495 rl_update->dcqcn_k_us = OSAL_CPU_TO_LE32(params->dcqcn_k_us); 496 rl_update->dcqcn_timeuot_us = OSAL_CPU_TO_LE32( 497 params->dcqcn_timeuot_us); 498 rl_update->qcn_timeuot_us = OSAL_CPU_TO_LE32(params->qcn_timeuot_us); 499 500 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL); 501 } 502 503 /* Set pf update ramrod command params */ 504 enum _ecore_status_t 505 ecore_sp_pf_update_tunn_cfg(struct ecore_hwfn *p_hwfn, 506 struct ecore_ptt *p_ptt, 507 struct ecore_tunnel_info *p_tunn, 508 enum spq_mode comp_mode, 509 struct ecore_spq_comp_cb *p_comp_data) 510 { 511 struct ecore_spq_entry *p_ent = OSAL_NULL; 512 struct ecore_sp_init_data init_data; 513 enum _ecore_status_t rc = ECORE_NOTIMPL; 514 515 if (IS_VF(p_hwfn->p_dev)) 516 return ecore_vf_pf_tunnel_param_update(p_hwfn, p_tunn); 517 518 if (ECORE_IS_BB_A0(p_hwfn->p_dev)) { 519 DP_NOTICE(p_hwfn, true, 520 "A0 chip: tunnel pf update config is not supported\n"); 521 return rc; 522 } 523 524 if (!p_tunn) 525 return ECORE_INVAL; 526 527 /* Get SPQ entry */ 528 OSAL_MEMSET(&init_data, 0, sizeof(init_data)); 529 init_data.cid = ecore_spq_get_cid(p_hwfn); 530 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 531 init_data.comp_mode = comp_mode; 532 init_data.p_comp_data = p_comp_data; 533 534 rc = ecore_sp_init_request(p_hwfn, &p_ent, 535 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON, 536 &init_data); 537 if (rc != ECORE_SUCCESS) 538 return rc; 539 540 ecore_tunn_set_pf_update_params(p_hwfn, p_tunn, 541 &p_ent->ramrod.pf_update.tunnel_config); 542 543 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL); 544 if (rc != ECORE_SUCCESS) 545 return rc; 546 547 ecore_set_hw_tunn_mode_port(p_hwfn, p_ptt, &p_hwfn->p_dev->tunnel); 548 549 return rc; 550 } 551 552 enum _ecore_status_t ecore_sp_pf_stop(struct ecore_hwfn *p_hwfn) 553 { 554 struct ecore_spq_entry *p_ent = OSAL_NULL; 555 struct ecore_sp_init_data init_data; 556 enum _ecore_status_t rc = ECORE_NOTIMPL; 557 558 /* Get SPQ entry */ 559 OSAL_MEMSET(&init_data, 0, sizeof(init_data)); 560 init_data.cid = ecore_spq_get_cid(p_hwfn); 561 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 562 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK; 563 564 rc = ecore_sp_init_request(p_hwfn, &p_ent, 565 COMMON_RAMROD_PF_STOP, PROTOCOLID_COMMON, 566 &init_data); 567 if (rc != ECORE_SUCCESS) 568 return rc; 569 570 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL); 571 } 572 573 enum _ecore_status_t ecore_sp_heartbeat_ramrod(struct ecore_hwfn *p_hwfn) 574 { 575 struct ecore_spq_entry *p_ent = OSAL_NULL; 576 struct ecore_sp_init_data init_data; 577 enum _ecore_status_t rc; 578 579 /* Get SPQ entry */ 580 OSAL_MEMSET(&init_data, 0, sizeof(init_data)); 581 init_data.cid = ecore_spq_get_cid(p_hwfn); 582 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 583 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK; 584 585 rc = ecore_sp_init_request(p_hwfn, &p_ent, 586 COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON, 587 &init_data); 588 if (rc != ECORE_SUCCESS) 589 return rc; 590 591 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL); 592 } 593 594 enum _ecore_status_t ecore_sp_pf_update_stag(struct ecore_hwfn *p_hwfn) 595 { 596 struct ecore_spq_entry *p_ent = OSAL_NULL; 597 struct ecore_sp_init_data init_data; 598 enum _ecore_status_t rc = ECORE_NOTIMPL; 599 600 /* Get SPQ entry */ 601 OSAL_MEMSET(&init_data, 0, sizeof(init_data)); 602 init_data.cid = ecore_spq_get_cid(p_hwfn); 603 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 604 init_data.comp_mode = ECORE_SPQ_MODE_CB; 605 606 rc = ecore_sp_init_request(p_hwfn, &p_ent, 607 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON, 608 &init_data); 609 if (rc != ECORE_SUCCESS) 610 return rc; 611 612 p_ent->ramrod.pf_update.update_mf_vlan_flag = true; 613 p_ent->ramrod.pf_update.mf_vlan = OSAL_CPU_TO_LE16(p_hwfn->hw_info.ovlan); 614 615 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL); 616 } 617