1 /* 2 * Copyright (c) 2018-2019 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * File: qlnxr_os.c 30 */ 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "qlnxr_def.h" 35 36 SYSCTL_NODE(_dev, OID_AUTO, qnxr, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 37 "Qlogic RDMA module"); 38 39 uint32_t delayed_ack = 0; 40 SYSCTL_UINT(_dev_qnxr, OID_AUTO, delayed_ack, CTLFLAG_RW, &delayed_ack, 1, 41 "iWARP: Delayed Ack: 0 - Disabled 1 - Enabled. Default: Disabled"); 42 43 uint32_t timestamp = 1; 44 SYSCTL_UINT(_dev_qnxr, OID_AUTO, timestamp, CTLFLAG_RW, ×tamp, 1, 45 "iWARP: Timestamp: 0 - Disabled 1 - Enabled. Default:Enabled"); 46 47 uint32_t rcv_wnd_size = 0; 48 SYSCTL_UINT(_dev_qnxr, OID_AUTO, rcv_wnd_size, CTLFLAG_RW, &rcv_wnd_size, 1, 49 "iWARP: Receive Window Size in K. Default 1M"); 50 51 uint32_t crc_needed = 1; 52 SYSCTL_UINT(_dev_qnxr, OID_AUTO, crc_needed, CTLFLAG_RW, &crc_needed, 1, 53 "iWARP: CRC needed 0 - Disabled 1 - Enabled. Default:Enabled"); 54 55 uint32_t peer2peer = 1; 56 SYSCTL_UINT(_dev_qnxr, OID_AUTO, peer2peer, CTLFLAG_RW, &peer2peer, 1, 57 "iWARP: Support peer2peer ULPs 0 - Disabled 1 - Enabled. Default:Enabled"); 58 59 uint32_t mpa_enhanced = 1; 60 SYSCTL_UINT(_dev_qnxr, OID_AUTO, mpa_enhanced, CTLFLAG_RW, &mpa_enhanced, 1, 61 "iWARP: MPA Enhanced mode. Default:1"); 62 63 uint32_t rtr_type = 7; 64 SYSCTL_UINT(_dev_qnxr, OID_AUTO, rtr_type, CTLFLAG_RW, &rtr_type, 1, 65 "iWARP: RDMAP opcode to use for the RTR message: BITMAP 1: RDMA_SEND 2: RDMA_WRITE 4: RDMA_READ. Default: 7"); 66 67 #define QNXR_WQ_MULTIPLIER_MIN (1) 68 #define QNXR_WQ_MULTIPLIER_MAX (7) 69 #define QNXR_WQ_MULTIPLIER_DFT (3) 70 71 uint32_t wq_multiplier= QNXR_WQ_MULTIPLIER_DFT; 72 SYSCTL_UINT(_dev_qnxr, OID_AUTO, wq_multiplier, CTLFLAG_RW, &wq_multiplier, 1, 73 " When creating a WQ the actual number of WQE created will" 74 " be multiplied by this number (default is 3)."); 75 static ssize_t 76 show_rev(struct device *device, struct device_attribute *attr, 77 char *buf) 78 { 79 struct qlnxr_dev *dev = dev_get_drvdata(device); 80 81 return sprintf(buf, "0x%x\n", dev->cdev->vendor_id); 82 } 83 84 static ssize_t 85 show_hca_type(struct device *device, 86 struct device_attribute *attr, char *buf) 87 { 88 struct qlnxr_dev *dev = dev_get_drvdata(device); 89 return sprintf(buf, "QLogic0x%x\n", dev->cdev->device_id); 90 } 91 92 static ssize_t 93 show_fw_ver(struct device *device, 94 struct device_attribute *attr, char *buf) 95 { 96 struct qlnxr_dev *dev = dev_get_drvdata(device); 97 uint32_t fw_ver = (uint32_t) dev->attr.fw_ver; 98 99 return sprintf(buf, "%d.%d.%d\n", 100 (fw_ver >> 24) & 0xff, (fw_ver >> 16) & 0xff, 101 (fw_ver >> 8) & 0xff); 102 } 103 static ssize_t 104 show_board(struct device *device, 105 struct device_attribute *attr, char *buf) 106 { 107 struct qlnxr_dev *dev = dev_get_drvdata(device); 108 return sprintf(buf, "%x\n", dev->cdev->device_id); 109 } 110 111 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 112 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca_type, NULL); 113 static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL); 114 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 115 116 static struct device_attribute *qlnxr_class_attributes[] = { 117 &dev_attr_hw_rev, 118 &dev_attr_hca_type, 119 &dev_attr_fw_ver, 120 &dev_attr_board_id 121 }; 122 123 static void 124 qlnxr_ib_dispatch_event(qlnxr_dev_t *dev, uint8_t port_num, 125 enum ib_event_type type) 126 { 127 struct ib_event ibev; 128 129 QL_DPRINT12(dev->ha, "enter\n"); 130 131 ibev.device = &dev->ibdev; 132 ibev.element.port_num = port_num; 133 ibev.event = type; 134 135 ib_dispatch_event(&ibev); 136 137 QL_DPRINT12(dev->ha, "exit\n"); 138 } 139 140 static int 141 __qlnxr_iw_destroy_listen(struct iw_cm_id *cm_id) 142 { 143 qlnxr_iw_destroy_listen(cm_id); 144 145 return (0); 146 } 147 148 static int 149 qlnxr_register_device(qlnxr_dev_t *dev) 150 { 151 struct ib_device *ibdev; 152 struct iw_cm_verbs *iwcm; 153 int ret; 154 155 QL_DPRINT12(dev->ha, "enter\n"); 156 157 ibdev = &dev->ibdev; 158 159 #define qlnxr_ib_ah qlnxr_ah 160 #define qlnxr_ib_cq qlnxr_cq 161 #define qlnxr_ib_pd qlnxr_pd 162 #define qlnxr_ib_qp qlnxr_qp 163 #define qlnxr_ib_srq qlnxr_srq 164 #define qlnxr_ib_ucontext qlnxr_ucontext 165 INIT_IB_DEVICE_OPS(&ibdev->ops, qlnxr, QLNXR); 166 strlcpy(ibdev->name, "qlnxr%d", IB_DEVICE_NAME_MAX); 167 168 memset(&ibdev->node_guid, 0, sizeof(ibdev->node_guid)); 169 memcpy(&ibdev->node_guid, dev->ha->primary_mac, ETHER_ADDR_LEN); 170 171 memcpy(ibdev->node_desc, QLNXR_NODE_DESC, sizeof(QLNXR_NODE_DESC)); 172 173 ibdev->owner = THIS_MODULE; 174 ibdev->uverbs_abi_ver = 7; 175 ibdev->local_dma_lkey = 0; 176 177 ibdev->uverbs_cmd_mask = 178 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 179 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 180 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 181 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 182 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 183 (1ull << IB_USER_VERBS_CMD_REG_MR) | 184 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 185 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 186 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 187 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 188 (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) | 189 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 190 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 191 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 192 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 193 (1ull << IB_USER_VERBS_CMD_POLL_CQ) | 194 (1ull << IB_USER_VERBS_CMD_POST_SEND) | 195 (1ull << IB_USER_VERBS_CMD_POST_RECV); 196 197 if (QLNX_IS_IWARP(dev)) { 198 ibdev->node_type = RDMA_NODE_RNIC; 199 ibdev->query_gid = qlnxr_iw_query_gid; 200 } else { 201 ibdev->node_type = RDMA_NODE_IB_CA; 202 ibdev->query_gid = qlnxr_query_gid; 203 ibdev->uverbs_cmd_mask |= 204 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 205 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 206 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 207 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 208 (1ull << IB_USER_VERBS_CMD_POST_SRQ_RECV); 209 ibdev->create_srq = qlnxr_create_srq; 210 ibdev->destroy_srq = qlnxr_destroy_srq; 211 ibdev->modify_srq = qlnxr_modify_srq; 212 ibdev->query_srq = qlnxr_query_srq; 213 ibdev->post_srq_recv = qlnxr_post_srq_recv; 214 } 215 216 ibdev->phys_port_cnt = 1; 217 ibdev->num_comp_vectors = dev->num_cnq; 218 219 /* mandatory verbs. */ 220 ibdev->query_device = qlnxr_query_device; 221 ibdev->query_port = qlnxr_query_port; 222 ibdev->modify_port = qlnxr_modify_port; 223 224 ibdev->alloc_ucontext = qlnxr_alloc_ucontext; 225 ibdev->dealloc_ucontext = qlnxr_dealloc_ucontext; 226 /* mandatory to support user space verbs consumer. */ 227 ibdev->mmap = qlnxr_mmap; 228 229 ibdev->alloc_pd = qlnxr_alloc_pd; 230 ibdev->dealloc_pd = qlnxr_dealloc_pd; 231 232 ibdev->create_cq = qlnxr_create_cq; 233 ibdev->destroy_cq = qlnxr_destroy_cq; 234 ibdev->resize_cq = qlnxr_resize_cq; 235 ibdev->req_notify_cq = qlnxr_arm_cq; 236 237 ibdev->create_qp = qlnxr_create_qp; 238 ibdev->modify_qp = qlnxr_modify_qp; 239 ibdev->query_qp = qlnxr_query_qp; 240 ibdev->destroy_qp = qlnxr_destroy_qp; 241 242 ibdev->query_pkey = qlnxr_query_pkey; 243 ibdev->create_ah = qlnxr_create_ah; 244 ibdev->destroy_ah = qlnxr_destroy_ah; 245 ibdev->query_ah = qlnxr_query_ah; 246 ibdev->modify_ah = qlnxr_modify_ah; 247 ibdev->get_dma_mr = qlnxr_get_dma_mr; 248 ibdev->dereg_mr = qlnxr_dereg_mr; 249 ibdev->reg_user_mr = qlnxr_reg_user_mr; 250 251 ibdev->alloc_mr = qlnxr_alloc_mr; 252 ibdev->map_mr_sg = qlnxr_map_mr_sg; 253 ibdev->get_port_immutable = qlnxr_get_port_immutable; 254 255 ibdev->poll_cq = qlnxr_poll_cq; 256 ibdev->post_send = qlnxr_post_send; 257 ibdev->post_recv = qlnxr_post_recv; 258 ibdev->process_mad = qlnxr_process_mad; 259 260 ibdev->dma_device = &dev->pdev.dev; 261 262 ibdev->get_link_layer = qlnxr_link_layer; 263 264 if (QLNX_IS_IWARP(dev)) { 265 iwcm = kmalloc(sizeof(*iwcm), GFP_KERNEL); 266 267 device_printf(dev->ha->pci_dev, "device is IWARP\n"); 268 if (iwcm == NULL) 269 return (-ENOMEM); 270 271 ibdev->iwcm = iwcm; 272 273 iwcm->connect = qlnxr_iw_connect; 274 iwcm->accept = qlnxr_iw_accept; 275 iwcm->reject = qlnxr_iw_reject; 276 277 iwcm->create_listen = qlnxr_iw_create_listen; 278 iwcm->destroy_listen = __qlnxr_iw_destroy_listen; 279 280 iwcm->add_ref = qlnxr_iw_qp_add_ref; 281 iwcm->rem_ref = qlnxr_iw_qp_rem_ref; 282 iwcm->get_qp = qlnxr_iw_get_qp; 283 } 284 285 ret = ib_register_device(ibdev, NULL); 286 if (ret) { 287 kfree(iwcm); 288 } 289 290 QL_DPRINT12(dev->ha, "exit\n"); 291 return ret; 292 } 293 294 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 295 296 static void 297 qlnxr_intr(void *handle) 298 { 299 struct qlnxr_cnq *cnq = handle; 300 struct qlnxr_cq *cq; 301 struct regpair *cq_handle; 302 u16 hw_comp_cons, sw_comp_cons; 303 qlnx_host_t *ha; 304 305 ha = cnq->dev->ha; 306 307 QL_DPRINT12(ha, "enter cnq = %p\n", handle); 308 309 ecore_sb_ack(cnq->sb, IGU_INT_DISABLE, 0 /*do not update*/); 310 311 ecore_sb_update_sb_idx(cnq->sb); 312 313 hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr); 314 sw_comp_cons = ecore_chain_get_cons_idx(&cnq->pbl); 315 316 rmb(); 317 318 QL_DPRINT12(ha, "enter cnq = %p hw_comp_cons = 0x%x sw_comp_cons = 0x%x\n", 319 handle, hw_comp_cons, sw_comp_cons); 320 321 while (sw_comp_cons != hw_comp_cons) { 322 cq_handle = (struct regpair *)ecore_chain_consume(&cnq->pbl); 323 cq = (struct qlnxr_cq *)(uintptr_t)HILO_U64(cq_handle->hi, 324 cq_handle->lo); 325 326 if (cq == NULL) { 327 QL_DPRINT11(ha, "cq == NULL\n"); 328 break; 329 } 330 331 if (cq->sig != QLNXR_CQ_MAGIC_NUMBER) { 332 QL_DPRINT11(ha, 333 "cq->sig = 0x%x QLNXR_CQ_MAGIC_NUMBER = 0x%x\n", 334 cq->sig, QLNXR_CQ_MAGIC_NUMBER); 335 break; 336 } 337 cq->arm_flags = 0; 338 339 if (!cq->destroyed && cq->ibcq.comp_handler) { 340 QL_DPRINT11(ha, "calling comp_handler = %p " 341 "ibcq = %p cq_context = 0x%x\n", 342 &cq->ibcq, cq->ibcq.cq_context); 343 344 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context); 345 } 346 cq->cnq_notif++; 347 348 sw_comp_cons = ecore_chain_get_cons_idx(&cnq->pbl); 349 350 cnq->n_comp++; 351 } 352 353 ecore_rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index, sw_comp_cons); 354 355 ecore_sb_ack(cnq->sb, IGU_INT_ENABLE, 1 /*update*/); 356 357 QL_DPRINT12(ha, "exit cnq = %p\n", handle); 358 return; 359 } 360 361 static void 362 qlnxr_release_irqs(struct qlnxr_dev *dev) 363 { 364 int i; 365 qlnx_host_t *ha; 366 367 ha = dev->ha; 368 369 QL_DPRINT12(ha, "enter\n"); 370 371 for (i = 0; i < dev->num_cnq; i++) { 372 if (dev->cnq_array[i].irq_handle) 373 (void)bus_teardown_intr(dev->ha->pci_dev, 374 dev->cnq_array[i].irq, 375 dev->cnq_array[i].irq_handle); 376 377 if (dev->cnq_array[i].irq) 378 (void) bus_release_resource(dev->ha->pci_dev, 379 SYS_RES_IRQ, 380 dev->cnq_array[i].irq_rid, 381 dev->cnq_array[i].irq); 382 } 383 QL_DPRINT12(ha, "exit\n"); 384 return; 385 } 386 387 static int 388 qlnxr_setup_irqs(struct qlnxr_dev *dev) 389 { 390 int start_irq_rid; 391 int i; 392 qlnx_host_t *ha; 393 394 ha = dev->ha; 395 396 start_irq_rid = dev->sb_start + 2; 397 398 QL_DPRINT12(ha, "enter start_irq_rid = %d num_rss = %d\n", 399 start_irq_rid, dev->ha->num_rss); 400 401 for (i = 0; i < dev->num_cnq; i++) { 402 dev->cnq_array[i].irq_rid = start_irq_rid + i; 403 404 dev->cnq_array[i].irq = bus_alloc_resource_any(dev->ha->pci_dev, 405 SYS_RES_IRQ, 406 &dev->cnq_array[i].irq_rid, 407 (RF_ACTIVE | RF_SHAREABLE)); 408 409 if (dev->cnq_array[i].irq == NULL) { 410 QL_DPRINT11(ha, 411 "bus_alloc_resource_any failed irq_rid = %d\n", 412 dev->cnq_array[i].irq_rid); 413 414 goto qlnxr_setup_irqs_err; 415 } 416 417 if (bus_setup_intr(dev->ha->pci_dev, 418 dev->cnq_array[i].irq, 419 (INTR_TYPE_NET | INTR_MPSAFE), 420 NULL, qlnxr_intr, &dev->cnq_array[i], 421 &dev->cnq_array[i].irq_handle)) { 422 QL_DPRINT11(ha, "bus_setup_intr failed\n"); 423 goto qlnxr_setup_irqs_err; 424 } 425 QL_DPRINT12(ha, "irq_rid = %d irq = %p irq_handle = %p\n", 426 dev->cnq_array[i].irq_rid, dev->cnq_array[i].irq, 427 dev->cnq_array[i].irq_handle); 428 } 429 430 QL_DPRINT12(ha, "exit\n"); 431 return (0); 432 433 qlnxr_setup_irqs_err: 434 qlnxr_release_irqs(dev); 435 436 QL_DPRINT12(ha, "exit -1\n"); 437 return (-1); 438 } 439 440 static void 441 qlnxr_free_resources(struct qlnxr_dev *dev) 442 { 443 int i; 444 qlnx_host_t *ha; 445 446 ha = dev->ha; 447 448 QL_DPRINT12(ha, "enter dev->num_cnq = %d\n", dev->num_cnq); 449 450 if (QLNX_IS_IWARP(dev)) { 451 if (dev->iwarp_wq != NULL) 452 destroy_workqueue(dev->iwarp_wq); 453 } 454 455 for (i = 0; i < dev->num_cnq; i++) { 456 qlnx_free_mem_sb(dev->ha, &dev->sb_array[i]); 457 ecore_chain_free(&dev->ha->cdev, &dev->cnq_array[i].pbl); 458 } 459 460 bzero(dev->cnq_array, (sizeof(struct qlnxr_cnq) * QLNXR_MAX_MSIX)); 461 bzero(dev->sb_array, (sizeof(struct ecore_sb_info) * QLNXR_MAX_MSIX)); 462 bzero(dev->sgid_tbl, (sizeof(union ib_gid) * QLNXR_MAX_SGID)); 463 464 if (mtx_initialized(&dev->idr_lock)) 465 mtx_destroy(&dev->idr_lock); 466 467 if (mtx_initialized(&dev->sgid_lock)) 468 mtx_destroy(&dev->sgid_lock); 469 470 QL_DPRINT12(ha, "exit\n"); 471 return; 472 } 473 474 static int 475 qlnxr_alloc_resources(struct qlnxr_dev *dev) 476 { 477 uint16_t n_entries; 478 int i, rc; 479 qlnx_host_t *ha; 480 481 ha = dev->ha; 482 483 QL_DPRINT12(ha, "enter\n"); 484 485 bzero(dev->sgid_tbl, (sizeof (union ib_gid) * QLNXR_MAX_SGID)); 486 487 mtx_init(&dev->idr_lock, "idr_lock", NULL, MTX_DEF); 488 mtx_init(&dev->sgid_lock, "sgid_lock", NULL, MTX_DEF); 489 490 idr_init(&dev->qpidr); 491 492 bzero(dev->sb_array, (sizeof (struct ecore_sb_info) * QLNXR_MAX_MSIX)); 493 bzero(dev->cnq_array, (sizeof (struct qlnxr_cnq) * QLNXR_MAX_MSIX)); 494 495 dev->sb_start = ecore_rdma_get_sb_id(dev->rdma_ctx, 0); 496 497 QL_DPRINT12(ha, "dev->sb_start = 0x%x\n", dev->sb_start); 498 499 /* Allocate CNQ PBLs */ 500 501 n_entries = min_t(u32, ECORE_RDMA_MAX_CNQ_SIZE, QLNXR_ROCE_MAX_CNQ_SIZE); 502 503 for (i = 0; i < dev->num_cnq; i++) { 504 rc = qlnx_alloc_mem_sb(dev->ha, &dev->sb_array[i], 505 dev->sb_start + i); 506 if (rc) 507 goto qlnxr_alloc_resources_exit; 508 509 rc = ecore_chain_alloc(&dev->ha->cdev, 510 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE, 511 ECORE_CHAIN_MODE_PBL, 512 ECORE_CHAIN_CNT_TYPE_U16, 513 n_entries, 514 sizeof(struct regpair *), 515 &dev->cnq_array[i].pbl, 516 NULL); 517 518 /* configure cnq, except name since ibdev.name is still NULL */ 519 dev->cnq_array[i].dev = dev; 520 dev->cnq_array[i].sb = &dev->sb_array[i]; 521 dev->cnq_array[i].hw_cons_ptr = 522 &(dev->sb_array[i].sb_virt->pi_array[ECORE_ROCE_PROTOCOL_INDEX]); 523 dev->cnq_array[i].index = i; 524 sprintf(dev->cnq_array[i].name, "qlnxr%d@pci:%d", 525 i, (dev->ha->pci_func)); 526 } 527 528 QL_DPRINT12(ha, "exit\n"); 529 return 0; 530 531 qlnxr_alloc_resources_exit: 532 533 qlnxr_free_resources(dev); 534 535 QL_DPRINT12(ha, "exit -ENOMEM\n"); 536 return -ENOMEM; 537 } 538 539 void 540 qlnxr_affiliated_event(void *context, u8 e_code, void *fw_handle) 541 { 542 #define EVENT_TYPE_NOT_DEFINED 0 543 #define EVENT_TYPE_CQ 1 544 #define EVENT_TYPE_QP 2 545 #define EVENT_TYPE_GENERAL 3 546 547 struct qlnxr_dev *dev = (struct qlnxr_dev *)context; 548 struct regpair *async_handle = (struct regpair *)fw_handle; 549 u64 roceHandle64 = ((u64)async_handle->hi << 32) + async_handle->lo; 550 struct qlnxr_cq *cq = (struct qlnxr_cq *)(uintptr_t)roceHandle64; 551 struct qlnxr_qp *qp = (struct qlnxr_qp *)(uintptr_t)roceHandle64; 552 u8 event_type = EVENT_TYPE_NOT_DEFINED; 553 struct ib_event event; 554 qlnx_host_t *ha; 555 556 ha = dev->ha; 557 558 QL_DPRINT12(ha, "enter context = %p e_code = 0x%x fw_handle = %p\n", 559 context, e_code, fw_handle); 560 561 if (QLNX_IS_IWARP(dev)) { 562 switch (e_code) { 563 case ECORE_IWARP_EVENT_CQ_OVERFLOW: 564 event.event = IB_EVENT_CQ_ERR; 565 event_type = EVENT_TYPE_CQ; 566 break; 567 568 default: 569 QL_DPRINT12(ha, 570 "unsupported event %d on handle=%llx\n", 571 e_code, roceHandle64); 572 break; 573 } 574 } else { 575 switch (e_code) { 576 case ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR: 577 event.event = IB_EVENT_CQ_ERR; 578 event_type = EVENT_TYPE_CQ; 579 break; 580 581 case ROCE_ASYNC_EVENT_SQ_DRAINED: 582 event.event = IB_EVENT_SQ_DRAINED; 583 event_type = EVENT_TYPE_QP; 584 break; 585 586 case ROCE_ASYNC_EVENT_QP_CATASTROPHIC_ERR: 587 event.event = IB_EVENT_QP_FATAL; 588 event_type = EVENT_TYPE_QP; 589 break; 590 591 case ROCE_ASYNC_EVENT_LOCAL_INVALID_REQUEST_ERR: 592 event.event = IB_EVENT_QP_REQ_ERR; 593 event_type = EVENT_TYPE_QP; 594 break; 595 596 case ROCE_ASYNC_EVENT_LOCAL_ACCESS_ERR: 597 event.event = IB_EVENT_QP_ACCESS_ERR; 598 event_type = EVENT_TYPE_QP; 599 break; 600 601 /* NOTE the following are not implemented in FW 602 * ROCE_ASYNC_EVENT_CQ_ERR 603 * ROCE_ASYNC_EVENT_COMM_EST 604 */ 605 /* TODO associate the following events - 606 * ROCE_ASYNC_EVENT_SRQ_LIMIT 607 * ROCE_ASYNC_EVENT_LAST_WQE_REACHED 608 * ROCE_ASYNC_EVENT_LOCAL_CATASTROPHIC_ERR (un-affiliated) 609 */ 610 default: 611 QL_DPRINT12(ha, 612 "unsupported event 0x%x on fw_handle = %p\n", 613 e_code, fw_handle); 614 break; 615 } 616 } 617 618 switch (event_type) { 619 case EVENT_TYPE_CQ: 620 if (cq && cq->sig == QLNXR_CQ_MAGIC_NUMBER) { 621 struct ib_cq *ibcq = &cq->ibcq; 622 623 if (ibcq->event_handler) { 624 event.device = ibcq->device; 625 event.element.cq = ibcq; 626 ibcq->event_handler(&event, ibcq->cq_context); 627 } 628 } else { 629 QL_DPRINT11(ha, 630 "CQ event with invalid CQ pointer" 631 " Handle = %llx\n", roceHandle64); 632 } 633 QL_DPRINT12(ha, 634 "CQ event 0x%x on handle = %p\n", e_code, cq); 635 break; 636 637 case EVENT_TYPE_QP: 638 if (qp && qp->sig == QLNXR_QP_MAGIC_NUMBER) { 639 struct ib_qp *ibqp = &qp->ibqp; 640 641 if (ibqp->event_handler) { 642 event.device = ibqp->device; 643 event.element.qp = ibqp; 644 ibqp->event_handler(&event, ibqp->qp_context); 645 } 646 } else { 647 QL_DPRINT11(ha, 648 "QP event 0x%x with invalid QP pointer" 649 " qp handle = %p\n", 650 e_code, roceHandle64); 651 } 652 QL_DPRINT12(ha, "QP event 0x%x on qp handle = %p\n", 653 e_code, qp); 654 break; 655 656 case EVENT_TYPE_GENERAL: 657 break; 658 659 default: 660 break; 661 } 662 663 QL_DPRINT12(ha, "exit\n"); 664 665 return; 666 } 667 668 void 669 qlnxr_unaffiliated_event(void *context, u8 e_code) 670 { 671 struct qlnxr_dev *dev = (struct qlnxr_dev *)context; 672 qlnx_host_t *ha; 673 674 ha = dev->ha; 675 676 QL_DPRINT12(ha, "enter/exit \n"); 677 return; 678 } 679 680 static int 681 qlnxr_set_device_attr(struct qlnxr_dev *dev) 682 { 683 struct ecore_rdma_device *ecore_attr; 684 struct qlnxr_device_attr *attr; 685 u32 page_size; 686 687 ecore_attr = ecore_rdma_query_device(dev->rdma_ctx); 688 689 page_size = ~dev->attr.page_size_caps + 1; 690 if(page_size > PAGE_SIZE) { 691 QL_DPRINT12(dev->ha, "Kernel page size : %ld is smaller than" 692 " minimum page size : %ld required by qlnxr\n", 693 PAGE_SIZE, page_size); 694 return -ENODEV; 695 } 696 attr = &dev->attr; 697 attr->vendor_id = ecore_attr->vendor_id; 698 attr->vendor_part_id = ecore_attr->vendor_part_id; 699 700 QL_DPRINT12(dev->ha, "in qlnxr_set_device_attr, vendor : %x device : %x\n", 701 attr->vendor_id, attr->vendor_part_id); 702 703 attr->hw_ver = ecore_attr->hw_ver; 704 attr->fw_ver = ecore_attr->fw_ver; 705 attr->node_guid = ecore_attr->node_guid; 706 attr->sys_image_guid = ecore_attr->sys_image_guid; 707 attr->max_cnq = ecore_attr->max_cnq; 708 attr->max_sge = ecore_attr->max_sge; 709 attr->max_inline = ecore_attr->max_inline; 710 attr->max_sqe = min_t(u32, ecore_attr->max_wqe, QLNXR_MAX_SQE); 711 attr->max_rqe = min_t(u32, ecore_attr->max_wqe, QLNXR_MAX_RQE); 712 attr->max_qp_resp_rd_atomic_resc = ecore_attr->max_qp_resp_rd_atomic_resc; 713 attr->max_qp_req_rd_atomic_resc = ecore_attr->max_qp_req_rd_atomic_resc; 714 attr->max_dev_resp_rd_atomic_resc = 715 ecore_attr->max_dev_resp_rd_atomic_resc; 716 attr->max_cq = ecore_attr->max_cq; 717 attr->max_qp = ecore_attr->max_qp; 718 attr->max_mr = ecore_attr->max_mr; 719 attr->max_mr_size = ecore_attr->max_mr_size; 720 attr->max_cqe = min_t(u64, ecore_attr->max_cqe, QLNXR_MAX_CQES); 721 attr->max_mw = ecore_attr->max_mw; 722 attr->max_fmr = ecore_attr->max_fmr; 723 attr->max_mr_mw_fmr_pbl = ecore_attr->max_mr_mw_fmr_pbl; 724 attr->max_mr_mw_fmr_size = ecore_attr->max_mr_mw_fmr_size; 725 attr->max_pd = ecore_attr->max_pd; 726 attr->max_ah = ecore_attr->max_ah; 727 attr->max_pkey = ecore_attr->max_pkey; 728 attr->max_srq = ecore_attr->max_srq; 729 attr->max_srq_wr = ecore_attr->max_srq_wr; 730 //attr->dev_caps = ecore_attr->dev_caps; 731 attr->page_size_caps = ecore_attr->page_size_caps; 732 attr->dev_ack_delay = ecore_attr->dev_ack_delay; 733 attr->reserved_lkey = ecore_attr->reserved_lkey; 734 attr->bad_pkey_counter = ecore_attr->bad_pkey_counter; 735 attr->max_stats_queues = ecore_attr->max_stats_queues; 736 737 return 0; 738 } 739 740 static int 741 qlnxr_init_hw(struct qlnxr_dev *dev) 742 { 743 struct ecore_rdma_events events; 744 struct ecore_rdma_add_user_out_params out_params; 745 struct ecore_rdma_cnq_params *cur_pbl; 746 struct ecore_rdma_start_in_params *in_params; 747 dma_addr_t p_phys_table; 748 u32 page_cnt; 749 int rc = 0; 750 int i; 751 qlnx_host_t *ha; 752 753 ha = dev->ha; 754 755 QL_DPRINT12(ha, "enter\n"); 756 757 in_params = kzalloc(sizeof(*in_params), GFP_KERNEL); 758 if (!in_params) { 759 rc = -ENOMEM; 760 goto out; 761 } 762 763 bzero(&out_params, sizeof(struct ecore_rdma_add_user_out_params)); 764 bzero(&events, sizeof(struct ecore_rdma_events)); 765 766 in_params->desired_cnq = dev->num_cnq; 767 768 for (i = 0; i < dev->num_cnq; i++) { 769 cur_pbl = &in_params->cnq_pbl_list[i]; 770 771 page_cnt = ecore_chain_get_page_cnt(&dev->cnq_array[i].pbl); 772 cur_pbl->num_pbl_pages = page_cnt; 773 774 p_phys_table = ecore_chain_get_pbl_phys(&dev->cnq_array[i].pbl); 775 cur_pbl->pbl_ptr = (u64)p_phys_table; 776 } 777 778 events.affiliated_event = qlnxr_affiliated_event; 779 events.unaffiliated_event = qlnxr_unaffiliated_event; 780 events.context = dev; 781 782 in_params->events = &events; 783 in_params->roce.cq_mode = ECORE_RDMA_CQ_MODE_32_BITS; 784 in_params->max_mtu = dev->ha->max_frame_size; 785 786 if (QLNX_IS_IWARP(dev)) { 787 if (delayed_ack) 788 in_params->iwarp.flags |= ECORE_IWARP_DA_EN; 789 790 if (timestamp) 791 in_params->iwarp.flags |= ECORE_IWARP_TS_EN; 792 793 in_params->iwarp.rcv_wnd_size = rcv_wnd_size*1024; 794 in_params->iwarp.crc_needed = crc_needed; 795 in_params->iwarp.ooo_num_rx_bufs = 796 (MAX_RXMIT_CONNS * in_params->iwarp.rcv_wnd_size) / 797 in_params->max_mtu; 798 799 in_params->iwarp.mpa_peer2peer = peer2peer; 800 in_params->iwarp.mpa_rev = 801 mpa_enhanced ? ECORE_MPA_REV2 : ECORE_MPA_REV1; 802 in_params->iwarp.mpa_rtr = rtr_type; 803 } 804 805 memcpy(&in_params->mac_addr[0], dev->ha->primary_mac, ETH_ALEN); 806 807 rc = ecore_rdma_start(dev->rdma_ctx, in_params); 808 if (rc) 809 goto out; 810 811 rc = ecore_rdma_add_user(dev->rdma_ctx, &out_params); 812 if (rc) 813 goto out; 814 815 dev->db_addr = (void *)(uintptr_t)out_params.dpi_addr; 816 dev->db_phys_addr = out_params.dpi_phys_addr; 817 dev->db_size = out_params.dpi_size; 818 dev->dpi = out_params.dpi; 819 820 qlnxr_set_device_attr(dev); 821 822 QL_DPRINT12(ha, 823 "cdev->doorbells = %p, db_phys_addr = %p db_size = 0x%x\n", 824 (void *)ha->cdev.doorbells, 825 (void *)ha->cdev.db_phys_addr, ha->cdev.db_size); 826 827 QL_DPRINT12(ha, 828 "db_addr = %p db_phys_addr = %p db_size = 0x%x dpi = 0x%x\n", 829 (void *)dev->db_addr, (void *)dev->db_phys_addr, 830 dev->db_size, dev->dpi); 831 out: 832 kfree(in_params); 833 834 QL_DPRINT12(ha, "exit\n"); 835 return rc; 836 } 837 838 static void 839 qlnxr_build_sgid_mac(union ib_gid *sgid, unsigned char *mac_addr, 840 bool is_vlan, u16 vlan_id) 841 { 842 sgid->global.subnet_prefix = OSAL_CPU_TO_BE64(0xfe80000000000000LL); 843 sgid->raw[8] = mac_addr[0] ^ 2; 844 sgid->raw[9] = mac_addr[1]; 845 sgid->raw[10] = mac_addr[2]; 846 if (is_vlan) { 847 sgid->raw[11] = vlan_id >> 8; 848 sgid->raw[12] = vlan_id & 0xff; 849 } else { 850 sgid->raw[11] = 0xff; 851 sgid->raw[12] = 0xfe; 852 } 853 sgid->raw[13] = mac_addr[3]; 854 sgid->raw[14] = mac_addr[4]; 855 sgid->raw[15] = mac_addr[5]; 856 } 857 static bool 858 qlnxr_add_sgid(struct qlnxr_dev *dev, union ib_gid *new_sgid); 859 860 static void 861 qlnxr_add_ip_based_gid(struct qlnxr_dev *dev, struct ifnet *ifp) 862 { 863 struct ifaddr *ifa; 864 union ib_gid gid; 865 866 CK_STAILQ_FOREACH(ifa, &ifp->if_addrhead, ifa_link) { 867 if (ifa->ifa_addr && ifa->ifa_addr->sa_family == AF_INET) { 868 QL_DPRINT12(dev->ha, "IP address : %x\n", ((struct sockaddr_in *) ifa->ifa_addr)->sin_addr.s_addr); 869 ipv6_addr_set_v4mapped( 870 ((struct sockaddr_in *) ifa->ifa_addr)->sin_addr.s_addr, 871 (struct in6_addr *)&gid); 872 QL_DPRINT12(dev->ha, "gid generated : %llx\n", gid); 873 874 qlnxr_add_sgid(dev, &gid); 875 } 876 } 877 for (int i = 0; i < 16; i++) { 878 QL_DPRINT12(dev->ha, "gid generated : %x\n", gid.raw[i]); 879 } 880 } 881 882 static bool 883 qlnxr_add_sgid(struct qlnxr_dev *dev, union ib_gid *new_sgid) 884 { 885 union ib_gid zero_sgid = { { 0 } }; 886 int i; 887 //unsigned long flags; 888 mtx_lock(&dev->sgid_lock); 889 for (i = 0; i < QLNXR_MAX_SGID; i++) { 890 if (!memcmp(&dev->sgid_tbl[i], &zero_sgid, 891 sizeof(union ib_gid))) { 892 /* found free entry */ 893 memcpy(&dev->sgid_tbl[i], new_sgid, 894 sizeof(union ib_gid)); 895 QL_DPRINT12(dev->ha, "copying sgid : %llx\n", 896 *new_sgid); 897 mtx_unlock(&dev->sgid_lock); 898 //TODO ib_dispatch event here? 899 return true; 900 } else if (!memcmp(&dev->sgid_tbl[i], new_sgid, 901 sizeof(union ib_gid))) { 902 /* entry already present, no addition required */ 903 mtx_unlock(&dev->sgid_lock); 904 QL_DPRINT12(dev->ha, "sgid present : %llx\n", 905 *new_sgid); 906 return false; 907 } 908 } 909 if (i == QLNXR_MAX_SGID) { 910 QL_DPRINT12(dev->ha, "didn't find an empty entry in sgid_tbl\n"); 911 } 912 mtx_unlock(&dev->sgid_lock); 913 return false; 914 } 915 916 static bool qlnxr_del_sgid(struct qlnxr_dev *dev, union ib_gid *gid) 917 { 918 int found = false; 919 int i; 920 //unsigned long flags; 921 922 QL_DPRINT12(dev->ha, "removing gid %llx %llx\n", 923 gid->global.interface_id, 924 gid->global.subnet_prefix); 925 mtx_lock(&dev->sgid_lock); 926 /* first is the default sgid which cannot be deleted */ 927 for (i = 1; i < QLNXR_MAX_SGID; i++) { 928 if (!memcmp(&dev->sgid_tbl[i], gid, sizeof(union ib_gid))) { 929 /* found matching entry */ 930 memset(&dev->sgid_tbl[i], 0, sizeof(union ib_gid)); 931 found = true; 932 break; 933 } 934 } 935 mtx_unlock(&dev->sgid_lock); 936 937 return found; 938 } 939 940 static void 941 qlnxr_add_sgids(struct qlnxr_dev *dev) 942 { 943 qlnx_host_t *ha = dev->ha; 944 u16 vlan_id; 945 bool is_vlan; 946 union ib_gid vgid; 947 948 qlnxr_add_ip_based_gid(dev, ha->ifp); 949 /* MAC/VLAN base GIDs */ 950 is_vlan = is_vlan_dev(ha->ifp); 951 vlan_id = (is_vlan) ? vlan_dev_vlan_id(ha->ifp) : 0; 952 qlnxr_build_sgid_mac(&vgid, ha->primary_mac, is_vlan, vlan_id); 953 qlnxr_add_sgid(dev, &vgid); 954 } 955 956 static int 957 qlnxr_add_default_sgid(struct qlnxr_dev *dev) 958 { 959 /* GID Index 0 - Invariant manufacturer-assigned EUI-64 */ 960 union ib_gid *sgid = &dev->sgid_tbl[0]; 961 struct ecore_rdma_device *qattr; 962 qlnx_host_t *ha; 963 ha = dev->ha; 964 965 qattr = ecore_rdma_query_device(dev->rdma_ctx); 966 if(sgid == NULL) 967 QL_DPRINT12(ha, "sgid = NULL?\n"); 968 969 sgid->global.subnet_prefix = OSAL_CPU_TO_BE64(0xfe80000000000000LL); 970 QL_DPRINT12(ha, "node_guid = %llx", dev->attr.node_guid); 971 memcpy(&sgid->raw[8], &qattr->node_guid, 972 sizeof(qattr->node_guid)); 973 //memcpy(&sgid->raw[8], &dev->attr.node_guid, 974 // sizeof(dev->attr.node_guid)); 975 QL_DPRINT12(ha, "DEFAULT sgid=[%x][%x][%x][%x][%x][%x][%x][%x][%x][%x][%x][%x][%x][%x][%x][%x]\n", 976 sgid->raw[0], sgid->raw[1], sgid->raw[2], sgid->raw[3], sgid->raw[4], sgid->raw[5], 977 sgid->raw[6], sgid->raw[7], sgid->raw[8], sgid->raw[9], sgid->raw[10], sgid->raw[11], 978 sgid->raw[12], sgid->raw[13], sgid->raw[14], sgid->raw[15]); 979 return 0; 980 } 981 982 static int qlnxr_addr_event (struct qlnxr_dev *dev, 983 unsigned long event, 984 struct ifnet *ifp, 985 union ib_gid *gid) 986 { 987 bool is_vlan = false; 988 union ib_gid vgid; 989 u16 vlan_id = 0xffff; 990 991 QL_DPRINT12(dev->ha, "Link event occured\n"); 992 is_vlan = is_vlan_dev(dev->ha->ifp); 993 vlan_id = (is_vlan) ? vlan_dev_vlan_id(dev->ha->ifp) : 0; 994 995 switch (event) { 996 case NETDEV_UP : 997 qlnxr_add_sgid(dev, gid); 998 if (is_vlan) { 999 qlnxr_build_sgid_mac(&vgid, dev->ha->primary_mac, is_vlan, vlan_id); 1000 qlnxr_add_sgid(dev, &vgid); 1001 } 1002 break; 1003 case NETDEV_DOWN : 1004 qlnxr_del_sgid(dev, gid); 1005 if (is_vlan) { 1006 qlnxr_build_sgid_mac(&vgid, dev->ha->primary_mac, is_vlan, vlan_id); 1007 qlnxr_del_sgid(dev, &vgid); 1008 } 1009 break; 1010 default : 1011 break; 1012 } 1013 return 1; 1014 } 1015 1016 static int qlnxr_inetaddr_event(struct notifier_block *notifier, 1017 unsigned long event, void *ptr) 1018 { 1019 struct ifaddr *ifa = ptr; 1020 union ib_gid gid; 1021 struct qlnxr_dev *dev = container_of(notifier, struct qlnxr_dev, nb_inet); 1022 qlnx_host_t *ha = dev->ha; 1023 1024 ipv6_addr_set_v4mapped( 1025 ((struct sockaddr_in *) ifa->ifa_addr)->sin_addr.s_addr, 1026 (struct in6_addr *)&gid); 1027 return qlnxr_addr_event(dev, event, ha->ifp, &gid); 1028 } 1029 1030 static int 1031 qlnxr_register_inet(struct qlnxr_dev *dev) 1032 { 1033 int ret; 1034 dev->nb_inet.notifier_call = qlnxr_inetaddr_event; 1035 ret = register_inetaddr_notifier(&dev->nb_inet); 1036 if (ret) { 1037 QL_DPRINT12(dev->ha, "Failed to register inetaddr\n"); 1038 return ret; 1039 } 1040 /* TODO : add for CONFIG_IPV6) */ 1041 return 0; 1042 } 1043 1044 static int 1045 qlnxr_build_sgid_tbl(struct qlnxr_dev *dev) 1046 { 1047 qlnxr_add_default_sgid(dev); 1048 qlnxr_add_sgids(dev); 1049 return 0; 1050 } 1051 1052 static struct qlnx_rdma_if qlnxr_drv; 1053 1054 static void * 1055 qlnxr_add(void *eth_dev) 1056 { 1057 struct qlnxr_dev *dev; 1058 int ret; 1059 //device_t pci_dev; 1060 qlnx_host_t *ha; 1061 1062 ha = eth_dev; 1063 1064 QL_DPRINT12(ha, "enter [ha = %p]\n", ha); 1065 1066 dev = (struct qlnxr_dev *)ib_alloc_device(sizeof(struct qlnxr_dev)); 1067 1068 if (dev == NULL) 1069 return (NULL); 1070 1071 dev->ha = eth_dev; 1072 dev->cdev = &ha->cdev; 1073 /* Added to extend Application support */ 1074 linux_pci_attach_device(dev->ha->pci_dev, NULL, NULL, &dev->pdev); 1075 1076 dev->rdma_ctx = &ha->cdev.hwfns[0]; 1077 dev->wq_multiplier = wq_multiplier; 1078 dev->num_cnq = QLNX_NUM_CNQ; 1079 1080 QL_DPRINT12(ha, 1081 "ha = %p dev = %p ha->cdev = %p\n", 1082 ha, dev, &ha->cdev); 1083 QL_DPRINT12(ha, 1084 "dev->cdev = %p dev->rdma_ctx = %p\n", 1085 dev->cdev, dev->rdma_ctx); 1086 1087 ret = qlnxr_alloc_resources(dev); 1088 1089 if (ret) 1090 goto qlnxr_add_err; 1091 1092 ret = qlnxr_setup_irqs(dev); 1093 1094 if (ret) { 1095 qlnxr_free_resources(dev); 1096 goto qlnxr_add_err; 1097 } 1098 1099 ret = qlnxr_init_hw(dev); 1100 1101 if (ret) { 1102 qlnxr_release_irqs(dev); 1103 qlnxr_free_resources(dev); 1104 goto qlnxr_add_err; 1105 } 1106 1107 qlnxr_register_device(dev); 1108 for (int i = 0; i < ARRAY_SIZE(qlnxr_class_attributes); ++i) { 1109 if (device_create_file(&dev->ibdev.dev, qlnxr_class_attributes[i])) 1110 goto sysfs_err; 1111 } 1112 qlnxr_build_sgid_tbl(dev); 1113 //ret = qlnxr_register_inet(dev); 1114 QL_DPRINT12(ha, "exit\n"); 1115 if (!test_and_set_bit(QLNXR_ENET_STATE_BIT, &dev->enet_state)) { 1116 QL_DPRINT12(ha, "dispatching IB_PORT_ACITVE event\n"); 1117 qlnxr_ib_dispatch_event(dev, QLNXR_PORT, 1118 IB_EVENT_PORT_ACTIVE); 1119 } 1120 1121 return (dev); 1122 sysfs_err: 1123 for (int i = 0; i < ARRAY_SIZE(qlnxr_class_attributes); ++i) { 1124 device_remove_file(&dev->ibdev.dev, qlnxr_class_attributes[i]); 1125 } 1126 ib_unregister_device(&dev->ibdev); 1127 1128 qlnxr_add_err: 1129 ib_dealloc_device(&dev->ibdev); 1130 1131 QL_DPRINT12(ha, "exit failed\n"); 1132 return (NULL); 1133 } 1134 1135 static void 1136 qlnxr_remove_sysfiles(struct qlnxr_dev *dev) 1137 { 1138 int i; 1139 for (i = 0; i < ARRAY_SIZE(qlnxr_class_attributes); ++i) 1140 device_remove_file(&dev->ibdev.dev, qlnxr_class_attributes[i]); 1141 } 1142 1143 static int 1144 qlnxr_remove(void *eth_dev, void *qlnx_rdma_dev) 1145 { 1146 struct qlnxr_dev *dev; 1147 qlnx_host_t *ha; 1148 1149 dev = qlnx_rdma_dev; 1150 ha = eth_dev; 1151 1152 if ((ha == NULL) || (dev == NULL)) 1153 return (0); 1154 1155 QL_DPRINT12(ha, "enter ha = %p qlnx_rdma_dev = %p pd_count = %d\n", 1156 ha, qlnx_rdma_dev, dev->pd_count); 1157 1158 qlnxr_ib_dispatch_event(dev, QLNXR_PORT, 1159 IB_EVENT_PORT_ERR); 1160 1161 if (QLNX_IS_IWARP(dev)) { 1162 if (dev->pd_count) 1163 return (EBUSY); 1164 } 1165 1166 ib_unregister_device(&dev->ibdev); 1167 1168 if (QLNX_IS_ROCE(dev)) { 1169 if (dev->pd_count) 1170 return (EBUSY); 1171 } 1172 1173 ecore_rdma_remove_user(dev->rdma_ctx, dev->dpi); 1174 ecore_rdma_stop(dev->rdma_ctx); 1175 1176 qlnxr_release_irqs(dev); 1177 1178 qlnxr_free_resources(dev); 1179 1180 qlnxr_remove_sysfiles(dev); 1181 ib_dealloc_device(&dev->ibdev); 1182 1183 linux_pci_detach_device(&dev->pdev); 1184 1185 QL_DPRINT12(ha, "exit ha = %p qlnx_rdma_dev = %p\n", ha, qlnx_rdma_dev); 1186 return (0); 1187 } 1188 1189 int 1190 qlnx_rdma_ll2_set_mac_filter(void *rdma_ctx, uint8_t *old_mac_address, 1191 uint8_t *new_mac_address) 1192 { 1193 struct ecore_hwfn *p_hwfn = rdma_ctx; 1194 struct qlnx_host *ha; 1195 int ret = 0; 1196 1197 ha = (struct qlnx_host *)(p_hwfn->p_dev); 1198 QL_DPRINT2(ha, "enter rdma_ctx (%p)\n", rdma_ctx); 1199 1200 if (old_mac_address) 1201 ecore_llh_remove_mac_filter(p_hwfn->p_dev, 0, old_mac_address); 1202 1203 if (new_mac_address) 1204 ret = ecore_llh_add_mac_filter(p_hwfn->p_dev, 0, new_mac_address); 1205 1206 QL_DPRINT2(ha, "exit rdma_ctx (%p)\n", rdma_ctx); 1207 return (ret); 1208 } 1209 1210 static void 1211 qlnxr_mac_address_change(struct qlnxr_dev *dev) 1212 { 1213 qlnx_host_t *ha; 1214 1215 ha = dev->ha; 1216 1217 QL_DPRINT12(ha, "enter/exit\n"); 1218 1219 return; 1220 } 1221 1222 static void 1223 qlnxr_notify(void *eth_dev, void *qlnx_rdma_dev, enum qlnx_rdma_event event) 1224 { 1225 struct qlnxr_dev *dev; 1226 qlnx_host_t *ha; 1227 1228 dev = qlnx_rdma_dev; 1229 1230 if (dev == NULL) 1231 return; 1232 1233 ha = dev->ha; 1234 1235 QL_DPRINT12(ha, "enter (%p, %d)\n", qlnx_rdma_dev, event); 1236 1237 switch (event) { 1238 case QLNX_ETHDEV_UP: 1239 if (!test_and_set_bit(QLNXR_ENET_STATE_BIT, &dev->enet_state)) 1240 qlnxr_ib_dispatch_event(dev, QLNXR_PORT, 1241 IB_EVENT_PORT_ACTIVE); 1242 break; 1243 1244 case QLNX_ETHDEV_CHANGE_ADDR: 1245 qlnxr_mac_address_change(dev); 1246 break; 1247 1248 case QLNX_ETHDEV_DOWN: 1249 if (test_and_set_bit(QLNXR_ENET_STATE_BIT, &dev->enet_state)) 1250 qlnxr_ib_dispatch_event(dev, QLNXR_PORT, 1251 IB_EVENT_PORT_ERR); 1252 break; 1253 } 1254 1255 QL_DPRINT12(ha, "exit (%p, %d)\n", qlnx_rdma_dev, event); 1256 return; 1257 } 1258 1259 static int 1260 qlnxr_mod_load(void) 1261 { 1262 int ret; 1263 1264 qlnxr_drv.add = qlnxr_add; 1265 qlnxr_drv.remove = qlnxr_remove; 1266 qlnxr_drv.notify = qlnxr_notify; 1267 1268 ret = qlnx_rdma_register_if(&qlnxr_drv); 1269 1270 return (ret); 1271 } 1272 1273 static int 1274 qlnxr_mod_unload(void) 1275 { 1276 int ret; 1277 1278 ret = qlnx_rdma_deregister_if(&qlnxr_drv); 1279 return (ret); 1280 } 1281 1282 static int 1283 qlnxr_event_handler(module_t mod, int event, void *arg) 1284 { 1285 1286 int ret = 0; 1287 1288 switch (event) { 1289 case MOD_LOAD: 1290 ret = qlnxr_mod_load(); 1291 break; 1292 1293 case MOD_UNLOAD: 1294 ret = qlnxr_mod_unload(); 1295 break; 1296 1297 default: 1298 break; 1299 } 1300 1301 return (ret); 1302 } 1303 1304 static moduledata_t qlnxr_mod_info = { 1305 .name = "qlnxr", 1306 .evhand = qlnxr_event_handler, 1307 }; 1308 1309 MODULE_VERSION(qlnxr, 1); 1310 MODULE_DEPEND(qlnxr, if_qlnxe, 1, 1, 1); 1311 MODULE_DEPEND(qlnxr, ibcore, 1, 1, 1); 1312 MODULE_DEPEND(qlnxr, linuxkpi, 1, 1, 1); 1313 1314 DECLARE_MODULE(qlnxr, qlnxr_mod_info, SI_SUB_LAST, SI_ORDER_ANY); 1315