1b2d3d26fSGleb Smirnoff /*- 2b2d3d26fSGleb Smirnoff * Copyright (c) 1997, 1998-2003 3b2d3d26fSGleb Smirnoff * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4b2d3d26fSGleb Smirnoff * 5b2d3d26fSGleb Smirnoff * Redistribution and use in source and binary forms, with or without 6b2d3d26fSGleb Smirnoff * modification, are permitted provided that the following conditions 7b2d3d26fSGleb Smirnoff * are met: 8b2d3d26fSGleb Smirnoff * 1. Redistributions of source code must retain the above copyright 9b2d3d26fSGleb Smirnoff * notice, this list of conditions and the following disclaimer. 10b2d3d26fSGleb Smirnoff * 2. Redistributions in binary form must reproduce the above copyright 11b2d3d26fSGleb Smirnoff * notice, this list of conditions and the following disclaimer in the 12b2d3d26fSGleb Smirnoff * documentation and/or other materials provided with the distribution. 13b2d3d26fSGleb Smirnoff * 3. All advertising materials mentioning features or use of this software 14b2d3d26fSGleb Smirnoff * must display the following acknowledgement: 15b2d3d26fSGleb Smirnoff * This product includes software developed by Bill Paul. 16b2d3d26fSGleb Smirnoff * 4. Neither the name of the author nor the names of any co-contributors 17b2d3d26fSGleb Smirnoff * may be used to endorse or promote products derived from this software 18b2d3d26fSGleb Smirnoff * without specific prior written permission. 19b2d3d26fSGleb Smirnoff * 20b2d3d26fSGleb Smirnoff * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21b2d3d26fSGleb Smirnoff * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22b2d3d26fSGleb Smirnoff * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23b2d3d26fSGleb Smirnoff * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24b2d3d26fSGleb Smirnoff * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25b2d3d26fSGleb Smirnoff * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26b2d3d26fSGleb Smirnoff * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27b2d3d26fSGleb Smirnoff * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28b2d3d26fSGleb Smirnoff * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29b2d3d26fSGleb Smirnoff * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30b2d3d26fSGleb Smirnoff * THE POSSIBILITY OF SUCH DAMAGE. 31b2d3d26fSGleb Smirnoff */ 32b2d3d26fSGleb Smirnoff 33b2d3d26fSGleb Smirnoff /* 34b2d3d26fSGleb Smirnoff * RealTek 8129/8139 register offsets 35b2d3d26fSGleb Smirnoff */ 36b2d3d26fSGleb Smirnoff #define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 37b2d3d26fSGleb Smirnoff #define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 38b2d3d26fSGleb Smirnoff #define RL_IDR2 0x0002 39b2d3d26fSGleb Smirnoff #define RL_IDR3 0x0003 40b2d3d26fSGleb Smirnoff #define RL_IDR4 0x0004 41b2d3d26fSGleb Smirnoff #define RL_IDR5 0x0005 42b2d3d26fSGleb Smirnoff /* 0006-0007 reserved */ 43b2d3d26fSGleb Smirnoff #define RL_MAR0 0x0008 /* Multicast hash table */ 44b2d3d26fSGleb Smirnoff #define RL_MAR1 0x0009 45b2d3d26fSGleb Smirnoff #define RL_MAR2 0x000A 46b2d3d26fSGleb Smirnoff #define RL_MAR3 0x000B 47b2d3d26fSGleb Smirnoff #define RL_MAR4 0x000C 48b2d3d26fSGleb Smirnoff #define RL_MAR5 0x000D 49b2d3d26fSGleb Smirnoff #define RL_MAR6 0x000E 50b2d3d26fSGleb Smirnoff #define RL_MAR7 0x000F 51b2d3d26fSGleb Smirnoff 52b2d3d26fSGleb Smirnoff #define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 53b2d3d26fSGleb Smirnoff #define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 54b2d3d26fSGleb Smirnoff #define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 55b2d3d26fSGleb Smirnoff #define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 56b2d3d26fSGleb Smirnoff 57b2d3d26fSGleb Smirnoff #define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 58b2d3d26fSGleb Smirnoff #define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 59b2d3d26fSGleb Smirnoff #define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 60b2d3d26fSGleb Smirnoff #define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 61b2d3d26fSGleb Smirnoff 62b2d3d26fSGleb Smirnoff #define RL_RXADDR 0x0030 /* RX ring start address */ 63b2d3d26fSGleb Smirnoff #define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 64b2d3d26fSGleb Smirnoff #define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 65b2d3d26fSGleb Smirnoff #define RL_COMMAND 0x0037 /* command register */ 66b2d3d26fSGleb Smirnoff #define RL_CURRXADDR 0x0038 /* current address of packet read */ 67b2d3d26fSGleb Smirnoff #define RL_CURRXBUF 0x003A /* current RX buffer address */ 68b2d3d26fSGleb Smirnoff #define RL_IMR 0x003C /* interrupt mask register */ 69b2d3d26fSGleb Smirnoff #define RL_ISR 0x003E /* interrupt status register */ 70b2d3d26fSGleb Smirnoff #define RL_TXCFG 0x0040 /* transmit config */ 71b2d3d26fSGleb Smirnoff #define RL_RXCFG 0x0044 /* receive config */ 72b2d3d26fSGleb Smirnoff #define RL_TIMERCNT 0x0048 /* timer count register */ 73b2d3d26fSGleb Smirnoff #define RL_MISSEDPKT 0x004C /* missed packet counter */ 74b2d3d26fSGleb Smirnoff #define RL_EECMD 0x0050 /* EEPROM command register */ 75b2d3d26fSGleb Smirnoff 76b2d3d26fSGleb Smirnoff /* RTL8139/RTL8139C+ only */ 77b2d3d26fSGleb Smirnoff #define RL_8139_CFG0 0x0051 /* config register #0 */ 78b2d3d26fSGleb Smirnoff #define RL_8139_CFG1 0x0052 /* config register #1 */ 79b2d3d26fSGleb Smirnoff #define RL_8139_CFG3 0x0059 /* config register #3 */ 80b2d3d26fSGleb Smirnoff #define RL_8139_CFG4 0x005A /* config register #4 */ 81b2d3d26fSGleb Smirnoff #define RL_8139_CFG5 0x00D8 /* config register #5 */ 82b2d3d26fSGleb Smirnoff 83b2d3d26fSGleb Smirnoff #define RL_CFG0 0x0051 /* config register #0 */ 84b2d3d26fSGleb Smirnoff #define RL_CFG1 0x0052 /* config register #1 */ 85b2d3d26fSGleb Smirnoff #define RL_CFG2 0x0053 /* config register #2 */ 86b2d3d26fSGleb Smirnoff #define RL_CFG3 0x0054 /* config register #3 */ 87b2d3d26fSGleb Smirnoff #define RL_CFG4 0x0055 /* config register #4 */ 88b2d3d26fSGleb Smirnoff #define RL_CFG5 0x0056 /* config register #5 */ 89b2d3d26fSGleb Smirnoff /* 0057 reserved */ 90b2d3d26fSGleb Smirnoff #define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 91b2d3d26fSGleb Smirnoff /* 0059-005A reserved */ 92b2d3d26fSGleb Smirnoff #define RL_MII 0x005A /* 8129 chip only */ 93b2d3d26fSGleb Smirnoff #define RL_HALTCLK 0x005B 94b2d3d26fSGleb Smirnoff #define RL_MULTIINTR 0x005C /* multiple interrupt */ 95b2d3d26fSGleb Smirnoff #define RL_PCIREV 0x005E /* PCI revision value */ 96b2d3d26fSGleb Smirnoff /* 005F reserved */ 97b2d3d26fSGleb Smirnoff #define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 98b2d3d26fSGleb Smirnoff 99b2d3d26fSGleb Smirnoff /* Direct PHY access registers only available on 8139 */ 100b2d3d26fSGleb Smirnoff #define RL_BMCR 0x0062 /* PHY basic mode control */ 101b2d3d26fSGleb Smirnoff #define RL_BMSR 0x0064 /* PHY basic mode status */ 102b2d3d26fSGleb Smirnoff #define RL_ANAR 0x0066 /* PHY autoneg advert */ 103b2d3d26fSGleb Smirnoff #define RL_LPAR 0x0068 /* PHY link partner ability */ 104b2d3d26fSGleb Smirnoff #define RL_ANER 0x006A /* PHY autoneg expansion */ 105b2d3d26fSGleb Smirnoff 106b2d3d26fSGleb Smirnoff #define RL_DISCCNT 0x006C /* disconnect counter */ 107b2d3d26fSGleb Smirnoff #define RL_FALSECAR 0x006E /* false carrier counter */ 108b2d3d26fSGleb Smirnoff #define RL_NWAYTST 0x0070 /* NWAY test register */ 109b2d3d26fSGleb Smirnoff #define RL_RX_ER 0x0072 /* RX_ER counter */ 110b2d3d26fSGleb Smirnoff #define RL_CSCFG 0x0074 /* CS configuration register */ 111b2d3d26fSGleb Smirnoff 112b2d3d26fSGleb Smirnoff /* 113b2d3d26fSGleb Smirnoff * When operating in special C+ mode, some of the registers in an 114b2d3d26fSGleb Smirnoff * 8139C+ chip have different definitions. These are also used for 115b2d3d26fSGleb Smirnoff * the 8169 gigE chip. 116b2d3d26fSGleb Smirnoff */ 117b2d3d26fSGleb Smirnoff #define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 118b2d3d26fSGleb Smirnoff #define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 119b2d3d26fSGleb Smirnoff #define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 120b2d3d26fSGleb Smirnoff #define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 121b2d3d26fSGleb Smirnoff #define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 122b2d3d26fSGleb Smirnoff #define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 123b2d3d26fSGleb Smirnoff #define RL_CFG2 0x0053 124b2d3d26fSGleb Smirnoff #define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 125b2d3d26fSGleb Smirnoff #define RL_TXSTART 0x00D9 /* 8 bits */ 126b2d3d26fSGleb Smirnoff #define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 127b2d3d26fSGleb Smirnoff #define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 128b2d3d26fSGleb Smirnoff #define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 129b2d3d26fSGleb Smirnoff #define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 130b2d3d26fSGleb Smirnoff 131b2d3d26fSGleb Smirnoff /* 132b2d3d26fSGleb Smirnoff * Registers specific to the 8169 gigE chip 133b2d3d26fSGleb Smirnoff */ 134b2d3d26fSGleb Smirnoff #define RL_GTXSTART 0x0038 /* 8 bits */ 135b2d3d26fSGleb Smirnoff #define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 136b2d3d26fSGleb Smirnoff #define RL_PHYAR 0x0060 137b2d3d26fSGleb Smirnoff #define RL_TBICSR 0x0064 138b2d3d26fSGleb Smirnoff #define RL_TBI_ANAR 0x0068 139b2d3d26fSGleb Smirnoff #define RL_TBI_LPAR 0x006A 140b2d3d26fSGleb Smirnoff #define RL_GMEDIASTAT 0x006C /* 8 bits */ 141b2d3d26fSGleb Smirnoff #define RL_MACDBG 0x006D /* 8 bits, 8168C SPIN2 only */ 142b2d3d26fSGleb Smirnoff #define RL_GPIO 0x006E /* 8 bits, 8168C SPIN2 only */ 143b2d3d26fSGleb Smirnoff #define RL_PMCH 0x006F /* 8 bits */ 144b2d3d26fSGleb Smirnoff #define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 145b2d3d26fSGleb Smirnoff #define RL_INTRMOD 0x00E2 /* 16 bits */ 146b2d3d26fSGleb Smirnoff #define RL_MISC 0x00F0 147b2d3d26fSGleb Smirnoff 148b2d3d26fSGleb Smirnoff /* 149b2d3d26fSGleb Smirnoff * TX config register bits 150b2d3d26fSGleb Smirnoff */ 151b2d3d26fSGleb Smirnoff #define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 152b2d3d26fSGleb Smirnoff #define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 153b2d3d26fSGleb Smirnoff #define RL_TXCFG_QUEUE_EMPTY 0x00000800 /* 8168E-VL or higher */ 154b2d3d26fSGleb Smirnoff #define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 155b2d3d26fSGleb Smirnoff #define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 156b2d3d26fSGleb Smirnoff #define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 157b2d3d26fSGleb Smirnoff #define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 158b2d3d26fSGleb Smirnoff #define RL_TXCFG_HWREV 0x7CC00000 159b2d3d26fSGleb Smirnoff 160b2d3d26fSGleb Smirnoff #define RL_LOOPTEST_OFF 0x00000000 161b2d3d26fSGleb Smirnoff #define RL_LOOPTEST_ON 0x00020000 162b2d3d26fSGleb Smirnoff #define RL_LOOPTEST_ON_CPLUS 0x00060000 163b2d3d26fSGleb Smirnoff 164b2d3d26fSGleb Smirnoff /* Known revision codes. */ 165b2d3d26fSGleb Smirnoff #define RL_HWREV_8169 0x00000000 166b2d3d26fSGleb Smirnoff #define RL_HWREV_8169S 0x00800000 167b2d3d26fSGleb Smirnoff #define RL_HWREV_8110S 0x04000000 168b2d3d26fSGleb Smirnoff #define RL_HWREV_8169_8110SB 0x10000000 169b2d3d26fSGleb Smirnoff #define RL_HWREV_8169_8110SC 0x18000000 170b2d3d26fSGleb Smirnoff #define RL_HWREV_8401E 0x24000000 171b2d3d26fSGleb Smirnoff #define RL_HWREV_8102EL 0x24800000 172b2d3d26fSGleb Smirnoff #define RL_HWREV_8102EL_SPIN1 0x24C00000 173b2d3d26fSGleb Smirnoff #define RL_HWREV_8168D 0x28000000 174b2d3d26fSGleb Smirnoff #define RL_HWREV_8168DP 0x28800000 175b2d3d26fSGleb Smirnoff #define RL_HWREV_8168E 0x2C000000 176b2d3d26fSGleb Smirnoff #define RL_HWREV_8168E_VL 0x2C800000 177b2d3d26fSGleb Smirnoff #define RL_HWREV_8168B_SPIN1 0x30000000 178b2d3d26fSGleb Smirnoff #define RL_HWREV_8100E 0x30800000 179b2d3d26fSGleb Smirnoff #define RL_HWREV_8101E 0x34000000 180b2d3d26fSGleb Smirnoff #define RL_HWREV_8102E 0x34800000 181b2d3d26fSGleb Smirnoff #define RL_HWREV_8103E 0x34C00000 182b2d3d26fSGleb Smirnoff #define RL_HWREV_8168B_SPIN2 0x38000000 183b2d3d26fSGleb Smirnoff #define RL_HWREV_8168B_SPIN3 0x38400000 184b2d3d26fSGleb Smirnoff #define RL_HWREV_8168C 0x3C000000 185b2d3d26fSGleb Smirnoff #define RL_HWREV_8168C_SPIN2 0x3C400000 186b2d3d26fSGleb Smirnoff #define RL_HWREV_8168CP 0x3C800000 187b2d3d26fSGleb Smirnoff #define RL_HWREV_8105E 0x40800000 188b2d3d26fSGleb Smirnoff #define RL_HWREV_8105E_SPIN1 0x40C00000 189b2d3d26fSGleb Smirnoff #define RL_HWREV_8402 0x44000000 190b2d3d26fSGleb Smirnoff #define RL_HWREV_8106E 0x44800000 191b2d3d26fSGleb Smirnoff #define RL_HWREV_8168F 0x48000000 192b2d3d26fSGleb Smirnoff #define RL_HWREV_8411 0x48800000 193b2d3d26fSGleb Smirnoff #define RL_HWREV_8168G 0x4C000000 194b2d3d26fSGleb Smirnoff #define RL_HWREV_8168EP 0x50000000 195b2d3d26fSGleb Smirnoff #define RL_HWREV_8168GU 0x50800000 19696b2c26aSMarius Strobl #define RL_HWREV_8168H 0x54000000 19788d2b69cSBrad Smith #define RL_HWREV_8168FP 0x54800000 198b2d3d26fSGleb Smirnoff #define RL_HWREV_8411B 0x5C800000 199b2d3d26fSGleb Smirnoff #define RL_HWREV_8139 0x60000000 200b2d3d26fSGleb Smirnoff #define RL_HWREV_8139A 0x70000000 201b2d3d26fSGleb Smirnoff #define RL_HWREV_8139AG 0x70800000 202b2d3d26fSGleb Smirnoff #define RL_HWREV_8139B 0x78000000 203b2d3d26fSGleb Smirnoff #define RL_HWREV_8130 0x7C000000 204b2d3d26fSGleb Smirnoff #define RL_HWREV_8139C 0x74000000 205b2d3d26fSGleb Smirnoff #define RL_HWREV_8139D 0x74400000 206b2d3d26fSGleb Smirnoff #define RL_HWREV_8139CPLUS 0x74800000 207b2d3d26fSGleb Smirnoff #define RL_HWREV_8101 0x74C00000 208b2d3d26fSGleb Smirnoff #define RL_HWREV_8100 0x78800000 209b2d3d26fSGleb Smirnoff #define RL_HWREV_8169_8110SBL 0x7CC00000 210b2d3d26fSGleb Smirnoff #define RL_HWREV_8169_8110SCE 0x98000000 211b2d3d26fSGleb Smirnoff 212b2d3d26fSGleb Smirnoff #define RL_TXDMA_16BYTES 0x00000000 213b2d3d26fSGleb Smirnoff #define RL_TXDMA_32BYTES 0x00000100 214b2d3d26fSGleb Smirnoff #define RL_TXDMA_64BYTES 0x00000200 215b2d3d26fSGleb Smirnoff #define RL_TXDMA_128BYTES 0x00000300 216b2d3d26fSGleb Smirnoff #define RL_TXDMA_256BYTES 0x00000400 217b2d3d26fSGleb Smirnoff #define RL_TXDMA_512BYTES 0x00000500 218b2d3d26fSGleb Smirnoff #define RL_TXDMA_1024BYTES 0x00000600 219b2d3d26fSGleb Smirnoff #define RL_TXDMA_2048BYTES 0x00000700 220b2d3d26fSGleb Smirnoff 221b2d3d26fSGleb Smirnoff /* 222b2d3d26fSGleb Smirnoff * Transmit descriptor status register bits. 223b2d3d26fSGleb Smirnoff */ 224b2d3d26fSGleb Smirnoff #define RL_TXSTAT_LENMASK 0x00001FFF 225b2d3d26fSGleb Smirnoff #define RL_TXSTAT_OWN 0x00002000 226b2d3d26fSGleb Smirnoff #define RL_TXSTAT_TX_UNDERRUN 0x00004000 227b2d3d26fSGleb Smirnoff #define RL_TXSTAT_TX_OK 0x00008000 228b2d3d26fSGleb Smirnoff #define RL_TXSTAT_EARLY_THRESH 0x003F0000 229b2d3d26fSGleb Smirnoff #define RL_TXSTAT_COLLCNT 0x0F000000 230b2d3d26fSGleb Smirnoff #define RL_TXSTAT_CARR_HBEAT 0x10000000 231b2d3d26fSGleb Smirnoff #define RL_TXSTAT_OUTOFWIN 0x20000000 232b2d3d26fSGleb Smirnoff #define RL_TXSTAT_TXABRT 0x40000000 233b2d3d26fSGleb Smirnoff #define RL_TXSTAT_CARRLOSS 0x80000000 234b2d3d26fSGleb Smirnoff 235b2d3d26fSGleb Smirnoff /* 236b2d3d26fSGleb Smirnoff * Interrupt status register bits. 237b2d3d26fSGleb Smirnoff */ 238b2d3d26fSGleb Smirnoff #define RL_ISR_RX_OK 0x0001 239b2d3d26fSGleb Smirnoff #define RL_ISR_RX_ERR 0x0002 240b2d3d26fSGleb Smirnoff #define RL_ISR_TX_OK 0x0004 241b2d3d26fSGleb Smirnoff #define RL_ISR_TX_ERR 0x0008 242b2d3d26fSGleb Smirnoff #define RL_ISR_RX_OVERRUN 0x0010 243b2d3d26fSGleb Smirnoff #define RL_ISR_PKT_UNDERRUN 0x0020 244b2d3d26fSGleb Smirnoff #define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 245b2d3d26fSGleb Smirnoff #define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 246b2d3d26fSGleb Smirnoff #define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 247b2d3d26fSGleb Smirnoff #define RL_ISR_SWI 0x0100 /* C+ only */ 248b2d3d26fSGleb Smirnoff #define RL_ISR_CABLE_LEN_CHGD 0x2000 249b2d3d26fSGleb Smirnoff #define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 250b2d3d26fSGleb Smirnoff #define RL_ISR_TIMEOUT_EXPIRED 0x4000 251b2d3d26fSGleb Smirnoff #define RL_ISR_SYSTEM_ERR 0x8000 252b2d3d26fSGleb Smirnoff 253b2d3d26fSGleb Smirnoff #define RL_INTRS \ 254b2d3d26fSGleb Smirnoff (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 255b2d3d26fSGleb Smirnoff RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 256b2d3d26fSGleb Smirnoff RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 257b2d3d26fSGleb Smirnoff 258b2d3d26fSGleb Smirnoff #ifdef RE_TX_MODERATION 259b2d3d26fSGleb Smirnoff #define RL_INTRS_CPLUS \ 260b2d3d26fSGleb Smirnoff (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 261b2d3d26fSGleb Smirnoff RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 262b2d3d26fSGleb Smirnoff RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 263b2d3d26fSGleb Smirnoff #else 264b2d3d26fSGleb Smirnoff #define RL_INTRS_CPLUS \ 265b2d3d26fSGleb Smirnoff (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 266b2d3d26fSGleb Smirnoff RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 267b2d3d26fSGleb Smirnoff RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 268b2d3d26fSGleb Smirnoff #endif 269b2d3d26fSGleb Smirnoff 270b2d3d26fSGleb Smirnoff /* 271b2d3d26fSGleb Smirnoff * Media status register. (8139 only) 272b2d3d26fSGleb Smirnoff */ 273b2d3d26fSGleb Smirnoff #define RL_MEDIASTAT_RXPAUSE 0x01 274b2d3d26fSGleb Smirnoff #define RL_MEDIASTAT_TXPAUSE 0x02 275b2d3d26fSGleb Smirnoff #define RL_MEDIASTAT_LINK 0x04 276b2d3d26fSGleb Smirnoff #define RL_MEDIASTAT_SPEED10 0x08 277b2d3d26fSGleb Smirnoff #define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 278b2d3d26fSGleb Smirnoff #define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 279b2d3d26fSGleb Smirnoff 280b2d3d26fSGleb Smirnoff /* 281b2d3d26fSGleb Smirnoff * Receive config register. 282b2d3d26fSGleb Smirnoff */ 283b2d3d26fSGleb Smirnoff #define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 284b2d3d26fSGleb Smirnoff #define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 285b2d3d26fSGleb Smirnoff #define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 286b2d3d26fSGleb Smirnoff #define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 287b2d3d26fSGleb Smirnoff #define RL_RXCFG_RX_RUNT 0x00000010 288b2d3d26fSGleb Smirnoff #define RL_RXCFG_RX_ERRPKT 0x00000020 289b2d3d26fSGleb Smirnoff #define RL_RXCFG_WRAP 0x00000080 290b2d3d26fSGleb Smirnoff #define RL_RXCFG_EARLYOFFV2 0x00000800 291b2d3d26fSGleb Smirnoff #define RL_RXCFG_MAXDMA 0x00000700 292b2d3d26fSGleb Smirnoff #define RL_RXCFG_BUFSZ 0x00001800 293b2d3d26fSGleb Smirnoff #define RL_RXCFG_EARLYOFF 0x00003800 294b2d3d26fSGleb Smirnoff #define RL_RXCFG_FIFOTHRESH 0x0000E000 295b2d3d26fSGleb Smirnoff #define RL_RXCFG_EARLYTHRESH 0x07000000 296b2d3d26fSGleb Smirnoff 297b2d3d26fSGleb Smirnoff #define RL_RXDMA_16BYTES 0x00000000 298b2d3d26fSGleb Smirnoff #define RL_RXDMA_32BYTES 0x00000100 299b2d3d26fSGleb Smirnoff #define RL_RXDMA_64BYTES 0x00000200 300b2d3d26fSGleb Smirnoff #define RL_RXDMA_128BYTES 0x00000300 301b2d3d26fSGleb Smirnoff #define RL_RXDMA_256BYTES 0x00000400 302b2d3d26fSGleb Smirnoff #define RL_RXDMA_512BYTES 0x00000500 303b2d3d26fSGleb Smirnoff #define RL_RXDMA_1024BYTES 0x00000600 304b2d3d26fSGleb Smirnoff #define RL_RXDMA_UNLIMITED 0x00000700 305b2d3d26fSGleb Smirnoff 306b2d3d26fSGleb Smirnoff #define RL_RXBUF_8 0x00000000 307b2d3d26fSGleb Smirnoff #define RL_RXBUF_16 0x00000800 308b2d3d26fSGleb Smirnoff #define RL_RXBUF_32 0x00001000 309b2d3d26fSGleb Smirnoff #define RL_RXBUF_64 0x00001800 310b2d3d26fSGleb Smirnoff 311b2d3d26fSGleb Smirnoff #define RL_RXFIFO_16BYTES 0x00000000 312b2d3d26fSGleb Smirnoff #define RL_RXFIFO_32BYTES 0x00002000 313b2d3d26fSGleb Smirnoff #define RL_RXFIFO_64BYTES 0x00004000 314b2d3d26fSGleb Smirnoff #define RL_RXFIFO_128BYTES 0x00006000 315b2d3d26fSGleb Smirnoff #define RL_RXFIFO_256BYTES 0x00008000 316b2d3d26fSGleb Smirnoff #define RL_RXFIFO_512BYTES 0x0000A000 317b2d3d26fSGleb Smirnoff #define RL_RXFIFO_1024BYTES 0x0000C000 318b2d3d26fSGleb Smirnoff #define RL_RXFIFO_NOTHRESH 0x0000E000 319b2d3d26fSGleb Smirnoff 320b2d3d26fSGleb Smirnoff /* 321b2d3d26fSGleb Smirnoff * Bits in RX status header (included with RX'ed packet 322b2d3d26fSGleb Smirnoff * in ring buffer). 323b2d3d26fSGleb Smirnoff */ 324b2d3d26fSGleb Smirnoff #define RL_RXSTAT_RXOK 0x00000001 325b2d3d26fSGleb Smirnoff #define RL_RXSTAT_ALIGNERR 0x00000002 326b2d3d26fSGleb Smirnoff #define RL_RXSTAT_CRCERR 0x00000004 327b2d3d26fSGleb Smirnoff #define RL_RXSTAT_GIANT 0x00000008 328b2d3d26fSGleb Smirnoff #define RL_RXSTAT_RUNT 0x00000010 329b2d3d26fSGleb Smirnoff #define RL_RXSTAT_BADSYM 0x00000020 330b2d3d26fSGleb Smirnoff #define RL_RXSTAT_BROAD 0x00002000 331b2d3d26fSGleb Smirnoff #define RL_RXSTAT_INDIV 0x00004000 332b2d3d26fSGleb Smirnoff #define RL_RXSTAT_MULTI 0x00008000 333b2d3d26fSGleb Smirnoff #define RL_RXSTAT_LENMASK 0xFFFF0000 334b2d3d26fSGleb Smirnoff #define RL_RXSTAT_UNFINISHED 0x0000FFF0 /* DMA still in progress */ 335b2d3d26fSGleb Smirnoff 336b2d3d26fSGleb Smirnoff /* 337b2d3d26fSGleb Smirnoff * Command register. 338b2d3d26fSGleb Smirnoff */ 339b2d3d26fSGleb Smirnoff #define RL_CMD_EMPTY_RXBUF 0x0001 340b2d3d26fSGleb Smirnoff #define RL_CMD_TX_ENB 0x0004 341b2d3d26fSGleb Smirnoff #define RL_CMD_RX_ENB 0x0008 342b2d3d26fSGleb Smirnoff #define RL_CMD_RESET 0x0010 343b2d3d26fSGleb Smirnoff #define RL_CMD_STOPREQ 0x0080 344b2d3d26fSGleb Smirnoff 345b2d3d26fSGleb Smirnoff /* 346b2d3d26fSGleb Smirnoff * Twister register values. These are completely undocumented and derived 347b2d3d26fSGleb Smirnoff * from public sources. 348b2d3d26fSGleb Smirnoff */ 349b2d3d26fSGleb Smirnoff #define RL_CSCFG_LINK_OK 0x0400 350b2d3d26fSGleb Smirnoff #define RL_CSCFG_CHANGE 0x0800 351b2d3d26fSGleb Smirnoff #define RL_CSCFG_STATUS 0xf000 352b2d3d26fSGleb Smirnoff #define RL_CSCFG_ROW3 0x7000 353b2d3d26fSGleb Smirnoff #define RL_CSCFG_ROW2 0x3000 354b2d3d26fSGleb Smirnoff #define RL_CSCFG_ROW1 0x1000 355b2d3d26fSGleb Smirnoff #define RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0 356b2d3d26fSGleb Smirnoff #define RL_CSCFG_LINK_DOWN_CMD 0xf3c0 357b2d3d26fSGleb Smirnoff 358b2d3d26fSGleb Smirnoff #define RL_NWAYTST_RESET 0 359b2d3d26fSGleb Smirnoff #define RL_NWAYTST_CBL_TEST 0x20 360b2d3d26fSGleb Smirnoff 361b2d3d26fSGleb Smirnoff #define RL_PARA78 0x78 362b2d3d26fSGleb Smirnoff #define RL_PARA78_DEF 0x78fa8388 363b2d3d26fSGleb Smirnoff #define RL_PARA7C 0x7C 364b2d3d26fSGleb Smirnoff #define RL_PARA7C_DEF 0xcb38de43 365b2d3d26fSGleb Smirnoff #define RL_PARA7C_RETUNE 0xfb38de03 366b2d3d26fSGleb Smirnoff 367b2d3d26fSGleb Smirnoff /* 368b2d3d26fSGleb Smirnoff * EEPROM control register 369b2d3d26fSGleb Smirnoff */ 370b2d3d26fSGleb Smirnoff #define RL_EE_DATAOUT 0x01 /* Data out */ 371b2d3d26fSGleb Smirnoff #define RL_EE_DATAIN 0x02 /* Data in */ 372b2d3d26fSGleb Smirnoff #define RL_EE_CLK 0x04 /* clock */ 373b2d3d26fSGleb Smirnoff #define RL_EE_SEL 0x08 /* chip select */ 374b2d3d26fSGleb Smirnoff #define RL_EE_MODE (0x40|0x80) 375b2d3d26fSGleb Smirnoff 376b2d3d26fSGleb Smirnoff #define RL_EEMODE_OFF 0x00 377b2d3d26fSGleb Smirnoff #define RL_EEMODE_AUTOLOAD 0x40 378b2d3d26fSGleb Smirnoff #define RL_EEMODE_PROGRAM 0x80 379b2d3d26fSGleb Smirnoff #define RL_EEMODE_WRITECFG (0x80|0x40) 380b2d3d26fSGleb Smirnoff 381b2d3d26fSGleb Smirnoff /* 9346 EEPROM commands */ 382b2d3d26fSGleb Smirnoff #define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 383b2d3d26fSGleb Smirnoff #define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 384b2d3d26fSGleb Smirnoff 385b2d3d26fSGleb Smirnoff #define RL_9346_WRITE 0x5 386b2d3d26fSGleb Smirnoff #define RL_9346_READ 0x6 387b2d3d26fSGleb Smirnoff #define RL_9346_ERASE 0x7 388b2d3d26fSGleb Smirnoff #define RL_9346_EWEN 0x4 389b2d3d26fSGleb Smirnoff #define RL_9346_EWEN_ADDR 0x30 390b2d3d26fSGleb Smirnoff #define RL_9456_EWDS 0x4 391b2d3d26fSGleb Smirnoff #define RL_9346_EWDS_ADDR 0x00 392b2d3d26fSGleb Smirnoff 393b2d3d26fSGleb Smirnoff #define RL_EECMD_WRITE 0x140 394b2d3d26fSGleb Smirnoff #define RL_EECMD_READ_6BIT 0x180 395b2d3d26fSGleb Smirnoff #define RL_EECMD_READ_8BIT 0x600 396b2d3d26fSGleb Smirnoff #define RL_EECMD_ERASE 0x1c0 397b2d3d26fSGleb Smirnoff 398b2d3d26fSGleb Smirnoff #define RL_EE_ID 0x00 399b2d3d26fSGleb Smirnoff #define RL_EE_PCI_VID 0x01 400b2d3d26fSGleb Smirnoff #define RL_EE_PCI_DID 0x02 401b2d3d26fSGleb Smirnoff /* Location of station address inside EEPROM */ 402b2d3d26fSGleb Smirnoff #define RL_EE_EADDR 0x07 403b2d3d26fSGleb Smirnoff 404b2d3d26fSGleb Smirnoff /* 405b2d3d26fSGleb Smirnoff * MII register (8129 only) 406b2d3d26fSGleb Smirnoff */ 407b2d3d26fSGleb Smirnoff #define RL_MII_CLK 0x01 408b2d3d26fSGleb Smirnoff #define RL_MII_DATAIN 0x02 409b2d3d26fSGleb Smirnoff #define RL_MII_DATAOUT 0x04 410b2d3d26fSGleb Smirnoff #define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 411b2d3d26fSGleb Smirnoff 412b2d3d26fSGleb Smirnoff /* 413b2d3d26fSGleb Smirnoff * Config 0 register 414b2d3d26fSGleb Smirnoff */ 415b2d3d26fSGleb Smirnoff #define RL_CFG0_ROM0 0x01 416b2d3d26fSGleb Smirnoff #define RL_CFG0_ROM1 0x02 417b2d3d26fSGleb Smirnoff #define RL_CFG0_ROM2 0x04 418b2d3d26fSGleb Smirnoff #define RL_CFG0_PL0 0x08 419b2d3d26fSGleb Smirnoff #define RL_CFG0_PL1 0x10 420b2d3d26fSGleb Smirnoff #define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 421b2d3d26fSGleb Smirnoff #define RL_CFG0_PCS 0x40 422b2d3d26fSGleb Smirnoff #define RL_CFG0_SCR 0x80 423b2d3d26fSGleb Smirnoff 424b2d3d26fSGleb Smirnoff /* 425b2d3d26fSGleb Smirnoff * Config 1 register 426b2d3d26fSGleb Smirnoff */ 427b2d3d26fSGleb Smirnoff #define RL_CFG1_PWRDWN 0x01 428b2d3d26fSGleb Smirnoff #define RL_CFG1_PME 0x01 429b2d3d26fSGleb Smirnoff #define RL_CFG1_SLEEP 0x02 430b2d3d26fSGleb Smirnoff #define RL_CFG1_VPDEN 0x02 431b2d3d26fSGleb Smirnoff #define RL_CFG1_IOMAP 0x04 432b2d3d26fSGleb Smirnoff #define RL_CFG1_MEMMAP 0x08 433b2d3d26fSGleb Smirnoff #define RL_CFG1_RSVD 0x10 434b2d3d26fSGleb Smirnoff #define RL_CFG1_LWACT 0x10 435b2d3d26fSGleb Smirnoff #define RL_CFG1_DRVLOAD 0x20 436b2d3d26fSGleb Smirnoff #define RL_CFG1_LED0 0x40 437b2d3d26fSGleb Smirnoff #define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 438b2d3d26fSGleb Smirnoff #define RL_CFG1_LED1 0x80 439b2d3d26fSGleb Smirnoff 440b2d3d26fSGleb Smirnoff /* 441b2d3d26fSGleb Smirnoff * Config 2 register 442b2d3d26fSGleb Smirnoff */ 443b2d3d26fSGleb Smirnoff #define RL_CFG2_PCI33MHZ 0x00 444b2d3d26fSGleb Smirnoff #define RL_CFG2_PCI66MHZ 0x01 445b2d3d26fSGleb Smirnoff #define RL_CFG2_PCI64BIT 0x08 446b2d3d26fSGleb Smirnoff #define RL_CFG2_AUXPWR 0x10 447b2d3d26fSGleb Smirnoff #define RL_CFG2_MSI 0x20 448b2d3d26fSGleb Smirnoff 449b2d3d26fSGleb Smirnoff /* 450b2d3d26fSGleb Smirnoff * Config 3 register 451b2d3d26fSGleb Smirnoff */ 452b2d3d26fSGleb Smirnoff #define RL_CFG3_GRANTSEL 0x80 453b2d3d26fSGleb Smirnoff #define RL_CFG3_WOL_MAGIC 0x20 454b2d3d26fSGleb Smirnoff #define RL_CFG3_WOL_LINK 0x10 455b2d3d26fSGleb Smirnoff #define RL_CFG3_JUMBO_EN0 0x04 /* RTL8168C or later. */ 456b2d3d26fSGleb Smirnoff #define RL_CFG3_FAST_B2B 0x01 457b2d3d26fSGleb Smirnoff 458b2d3d26fSGleb Smirnoff /* 459b2d3d26fSGleb Smirnoff * Config 4 register 460b2d3d26fSGleb Smirnoff */ 461b2d3d26fSGleb Smirnoff #define RL_CFG4_LWPTN 0x04 462b2d3d26fSGleb Smirnoff #define RL_CFG4_LWPME 0x10 463b2d3d26fSGleb Smirnoff #define RL_CFG4_JUMBO_EN1 0x02 /* RTL8168C or later. */ 464b2d3d26fSGleb Smirnoff 465b2d3d26fSGleb Smirnoff /* 466b2d3d26fSGleb Smirnoff * Config 5 register 467b2d3d26fSGleb Smirnoff */ 468b2d3d26fSGleb Smirnoff #define RL_CFG5_WOL_BCAST 0x40 469b2d3d26fSGleb Smirnoff #define RL_CFG5_WOL_MCAST 0x20 470b2d3d26fSGleb Smirnoff #define RL_CFG5_WOL_UCAST 0x10 471b2d3d26fSGleb Smirnoff #define RL_CFG5_WOL_LANWAKE 0x02 472b2d3d26fSGleb Smirnoff #define RL_CFG5_PME_STS 0x01 473b2d3d26fSGleb Smirnoff 474b2d3d26fSGleb Smirnoff /* 475b2d3d26fSGleb Smirnoff * 8139C+ register definitions 476b2d3d26fSGleb Smirnoff */ 477b2d3d26fSGleb Smirnoff 478b2d3d26fSGleb Smirnoff /* RL_DUMPSTATS_LO register */ 479b2d3d26fSGleb Smirnoff #define RL_DUMPSTATS_START 0x00000008 480b2d3d26fSGleb Smirnoff 481b2d3d26fSGleb Smirnoff /* Transmit start register */ 482b2d3d26fSGleb Smirnoff #define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 483b2d3d26fSGleb Smirnoff #define RL_TXSTART_START 0x40 /* start normal queue transmit */ 484b2d3d26fSGleb Smirnoff #define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 485b2d3d26fSGleb Smirnoff 486b2d3d26fSGleb Smirnoff /* 487b2d3d26fSGleb Smirnoff * Config 2 register, 8139C+/8169/8169S/8110S only 488b2d3d26fSGleb Smirnoff */ 489b2d3d26fSGleb Smirnoff #define RL_CFG2_BUSFREQ 0x07 490b2d3d26fSGleb Smirnoff #define RL_CFG2_BUSWIDTH 0x08 491b2d3d26fSGleb Smirnoff #define RL_CFG2_AUXPWRSTS 0x10 492b2d3d26fSGleb Smirnoff 493b2d3d26fSGleb Smirnoff #define RL_BUSFREQ_33MHZ 0x00 494b2d3d26fSGleb Smirnoff #define RL_BUSFREQ_66MHZ 0x01 495b2d3d26fSGleb Smirnoff 496b2d3d26fSGleb Smirnoff #define RL_BUSWIDTH_32BITS 0x00 497b2d3d26fSGleb Smirnoff #define RL_BUSWIDTH_64BITS 0x08 498b2d3d26fSGleb Smirnoff 499b2d3d26fSGleb Smirnoff /* C+ mode command register */ 500b2d3d26fSGleb Smirnoff #define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 501b2d3d26fSGleb Smirnoff #define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 502b2d3d26fSGleb Smirnoff #define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 503b2d3d26fSGleb Smirnoff #define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 504b2d3d26fSGleb Smirnoff #define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 505b2d3d26fSGleb Smirnoff #define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 506b2d3d26fSGleb Smirnoff #define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ 507b2d3d26fSGleb Smirnoff #define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ 508b2d3d26fSGleb Smirnoff #define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ 509b2d3d26fSGleb Smirnoff #define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ 510b2d3d26fSGleb Smirnoff #define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 511b2d3d26fSGleb Smirnoff #define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 512b2d3d26fSGleb Smirnoff #define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 513b2d3d26fSGleb Smirnoff #define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 514b2d3d26fSGleb Smirnoff #define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 515b2d3d26fSGleb Smirnoff 516b2d3d26fSGleb Smirnoff /* C+ early transmit threshold */ 517b2d3d26fSGleb Smirnoff #define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 518b2d3d26fSGleb Smirnoff 519b2d3d26fSGleb Smirnoff /* Timer interrupt register */ 520b2d3d26fSGleb Smirnoff #define RL_TIMERINT_8169_VAL 0x00001FFF 521b2d3d26fSGleb Smirnoff #define RL_TIMER_MIN 0 522b2d3d26fSGleb Smirnoff #define RL_TIMER_MAX 65 /* 65.528us */ 523b2d3d26fSGleb Smirnoff #define RL_TIMER_DEFAULT RL_TIMER_MAX 524b2d3d26fSGleb Smirnoff #define RL_TIMER_PCIE_CLK 125 /* 125MHZ */ 525b2d3d26fSGleb Smirnoff #define RL_USECS(x) ((x) * RL_TIMER_PCIE_CLK) 526b2d3d26fSGleb Smirnoff 527b2d3d26fSGleb Smirnoff /* 528b2d3d26fSGleb Smirnoff * Gigabit PHY access register (8169 only) 529b2d3d26fSGleb Smirnoff */ 530b2d3d26fSGleb Smirnoff #define RL_PHYAR_PHYDATA 0x0000FFFF 531b2d3d26fSGleb Smirnoff #define RL_PHYAR_PHYREG 0x001F0000 532b2d3d26fSGleb Smirnoff #define RL_PHYAR_BUSY 0x80000000 533b2d3d26fSGleb Smirnoff 534b2d3d26fSGleb Smirnoff /* 535b2d3d26fSGleb Smirnoff * Gigabit media status (8169 only) 536b2d3d26fSGleb Smirnoff */ 537b2d3d26fSGleb Smirnoff #define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 538b2d3d26fSGleb Smirnoff #define RL_GMEDIASTAT_LINK 0x02 /* link up */ 539b2d3d26fSGleb Smirnoff #define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 540b2d3d26fSGleb Smirnoff #define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 541b2d3d26fSGleb Smirnoff #define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 542b2d3d26fSGleb Smirnoff #define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 543b2d3d26fSGleb Smirnoff #define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 544b2d3d26fSGleb Smirnoff #define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 545b2d3d26fSGleb Smirnoff 546b2d3d26fSGleb Smirnoff /* 547b2d3d26fSGleb Smirnoff * The RealTek doesn't use a fragment-based descriptor mechanism. 548486ee364SWarner Losh * Instead, there are only four register sets, each of which represents 549b2d3d26fSGleb Smirnoff * one 'descriptor.' Basically, each TX descriptor is just a contiguous 550b2d3d26fSGleb Smirnoff * packet buffer (32-bit aligned!) and we place the buffer addresses in 551b2d3d26fSGleb Smirnoff * the registers so the chip knows where they are. 552b2d3d26fSGleb Smirnoff * 553b2d3d26fSGleb Smirnoff * We can sort of kludge together the same kind of buffer management 554b2d3d26fSGleb Smirnoff * used in previous drivers, but we have to do buffer copies almost all 555b2d3d26fSGleb Smirnoff * the time, so it doesn't really buy us much. 556b2d3d26fSGleb Smirnoff * 557b2d3d26fSGleb Smirnoff * For reception, there's just one large buffer where the chip stores 558b2d3d26fSGleb Smirnoff * all received packets. 559b2d3d26fSGleb Smirnoff */ 560b2d3d26fSGleb Smirnoff #define RL_RX_BUF_SZ RL_RXBUF_64 561b2d3d26fSGleb Smirnoff #define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 562b2d3d26fSGleb Smirnoff #define RL_TX_LIST_CNT 4 563b2d3d26fSGleb Smirnoff #define RL_MIN_FRAMELEN 60 564b2d3d26fSGleb Smirnoff #define RL_TX_8139_BUF_ALIGN 4 565b2d3d26fSGleb Smirnoff #define RL_RX_8139_BUF_ALIGN 8 566b2d3d26fSGleb Smirnoff #define RL_RX_8139_BUF_RESERVE sizeof(int64_t) 567b2d3d26fSGleb Smirnoff #define RL_RX_8139_BUF_GUARD_SZ \ 568b2d3d26fSGleb Smirnoff (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE) 569b2d3d26fSGleb Smirnoff #define RL_TXTHRESH(x) ((x) << 11) 570b2d3d26fSGleb Smirnoff #define RL_TX_THRESH_INIT 96 571b2d3d26fSGleb Smirnoff #define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 572b2d3d26fSGleb Smirnoff #define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 573b2d3d26fSGleb Smirnoff #define RL_TX_MAXDMA RL_TXDMA_2048BYTES 574b2d3d26fSGleb Smirnoff 575b2d3d26fSGleb Smirnoff #define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 576b2d3d26fSGleb Smirnoff #define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 577b2d3d26fSGleb Smirnoff 578b2d3d26fSGleb Smirnoff #define RL_ETHER_ALIGN 2 579b2d3d26fSGleb Smirnoff 580b2d3d26fSGleb Smirnoff /* 581b2d3d26fSGleb Smirnoff * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets. 582b2d3d26fSGleb Smirnoff */ 583b2d3d26fSGleb Smirnoff #define RL_IP4CSUMTX_MINLEN 28 584b2d3d26fSGleb Smirnoff #define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) 585b2d3d26fSGleb Smirnoff 586b2d3d26fSGleb Smirnoff struct rl_chain_data { 587b2d3d26fSGleb Smirnoff uint16_t cur_rx; 588b2d3d26fSGleb Smirnoff uint8_t *rl_rx_buf; 589b2d3d26fSGleb Smirnoff uint8_t *rl_rx_buf_ptr; 590b2d3d26fSGleb Smirnoff 591b2d3d26fSGleb Smirnoff struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 592b2d3d26fSGleb Smirnoff bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 593b2d3d26fSGleb Smirnoff bus_dma_tag_t rl_tx_tag; 594b2d3d26fSGleb Smirnoff bus_dma_tag_t rl_rx_tag; 595b2d3d26fSGleb Smirnoff bus_dmamap_t rl_rx_dmamap; 596b2d3d26fSGleb Smirnoff bus_addr_t rl_rx_buf_paddr; 597b2d3d26fSGleb Smirnoff uint8_t last_tx; 598b2d3d26fSGleb Smirnoff uint8_t cur_tx; 599b2d3d26fSGleb Smirnoff }; 600b2d3d26fSGleb Smirnoff 601b2d3d26fSGleb Smirnoff #define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 602b2d3d26fSGleb Smirnoff #define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 603b2d3d26fSGleb Smirnoff #define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 604b2d3d26fSGleb Smirnoff #define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 605b2d3d26fSGleb Smirnoff #define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 606b2d3d26fSGleb Smirnoff #define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 607b2d3d26fSGleb Smirnoff #define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 608b2d3d26fSGleb Smirnoff #define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 609b2d3d26fSGleb Smirnoff #define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 610b2d3d26fSGleb Smirnoff 611b2d3d26fSGleb Smirnoff struct rl_type { 612b2d3d26fSGleb Smirnoff uint16_t rl_vid; 613b2d3d26fSGleb Smirnoff uint16_t rl_did; 614b2d3d26fSGleb Smirnoff int rl_basetype; 615b2d3d26fSGleb Smirnoff const char *rl_name; 616b2d3d26fSGleb Smirnoff }; 617b2d3d26fSGleb Smirnoff 618b2d3d26fSGleb Smirnoff struct rl_hwrev { 619b2d3d26fSGleb Smirnoff uint32_t rl_rev; 620b2d3d26fSGleb Smirnoff int rl_type; 621b2d3d26fSGleb Smirnoff const char *rl_desc; 622b2d3d26fSGleb Smirnoff int rl_max_mtu; 623b2d3d26fSGleb Smirnoff }; 624b2d3d26fSGleb Smirnoff 625b2d3d26fSGleb Smirnoff #define RL_8129 1 626b2d3d26fSGleb Smirnoff #define RL_8139 2 627b2d3d26fSGleb Smirnoff #define RL_8139CPLUS 3 628b2d3d26fSGleb Smirnoff #define RL_8169 4 629b2d3d26fSGleb Smirnoff 630b2d3d26fSGleb Smirnoff #define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 631b2d3d26fSGleb Smirnoff (x)->rl_type == RL_8169) 632b2d3d26fSGleb Smirnoff 633b2d3d26fSGleb Smirnoff /* 634b2d3d26fSGleb Smirnoff * The 8139C+ and 8160 gigE chips support descriptor-based TX 635b2d3d26fSGleb Smirnoff * and RX. In fact, they even support TCP large send. Descriptors 636b2d3d26fSGleb Smirnoff * must be allocated in contiguous blocks that are aligned on a 637b2d3d26fSGleb Smirnoff * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 638b2d3d26fSGleb Smirnoff */ 639b2d3d26fSGleb Smirnoff 640b2d3d26fSGleb Smirnoff /* 641b2d3d26fSGleb Smirnoff * RX/TX descriptor definition. When large send mode is enabled, the 642b2d3d26fSGleb Smirnoff * lower 11 bits of the TX rl_cmdstat word are used to hold the MSS, and 643b2d3d26fSGleb Smirnoff * the checksum offload bits are disabled. The structure layout is 644b2d3d26fSGleb Smirnoff * the same for RX and TX descriptors 645b2d3d26fSGleb Smirnoff */ 646b2d3d26fSGleb Smirnoff struct rl_desc { 647b2d3d26fSGleb Smirnoff uint32_t rl_cmdstat; 648b2d3d26fSGleb Smirnoff uint32_t rl_vlanctl; 649b2d3d26fSGleb Smirnoff uint32_t rl_bufaddr_lo; 650b2d3d26fSGleb Smirnoff uint32_t rl_bufaddr_hi; 651b2d3d26fSGleb Smirnoff }; 652b2d3d26fSGleb Smirnoff 653b2d3d26fSGleb Smirnoff #define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 654b2d3d26fSGleb Smirnoff #define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 655b2d3d26fSGleb Smirnoff #define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 656b2d3d26fSGleb Smirnoff #define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 657b2d3d26fSGleb Smirnoff #define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 658b2d3d26fSGleb Smirnoff #define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 659b2d3d26fSGleb Smirnoff #define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 660b2d3d26fSGleb Smirnoff #define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 661b2d3d26fSGleb Smirnoff #define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 662b2d3d26fSGleb Smirnoff #define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 663b2d3d26fSGleb Smirnoff #define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 664b2d3d26fSGleb Smirnoff 665b2d3d26fSGleb Smirnoff #define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 666b2d3d26fSGleb Smirnoff #define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 667b2d3d26fSGleb Smirnoff /* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 668b2d3d26fSGleb Smirnoff #define RL_TDESC_CMD_UDPCSUMV2 0x80000000 669b2d3d26fSGleb Smirnoff #define RL_TDESC_CMD_TCPCSUMV2 0x40000000 670b2d3d26fSGleb Smirnoff #define RL_TDESC_CMD_IPCSUMV2 0x20000000 671b2d3d26fSGleb Smirnoff #define RL_TDESC_CMD_MSSVALV2 0x1FFC0000 672b2d3d26fSGleb Smirnoff #define RL_TDESC_CMD_MSSVALV2_SHIFT 18 673b2d3d26fSGleb Smirnoff 674b2d3d26fSGleb Smirnoff /* 675b2d3d26fSGleb Smirnoff * Error bits are valid only on the last descriptor of a frame 676b2d3d26fSGleb Smirnoff * (i.e. RL_TDESC_CMD_EOF == 1) 677b2d3d26fSGleb Smirnoff */ 678b2d3d26fSGleb Smirnoff #define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 679b2d3d26fSGleb Smirnoff #define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 680b2d3d26fSGleb Smirnoff #define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 681b2d3d26fSGleb Smirnoff #define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 682b2d3d26fSGleb Smirnoff #define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 683453130d9SPedro F. Giffuni #define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occurred */ 684b2d3d26fSGleb Smirnoff #define RL_TDESC_STAT_OWN 0x80000000 685b2d3d26fSGleb Smirnoff 686b2d3d26fSGleb Smirnoff /* 687b2d3d26fSGleb Smirnoff * RX descriptor cmd/vlan definitions 688b2d3d26fSGleb Smirnoff */ 689b2d3d26fSGleb Smirnoff #define RL_RDESC_CMD_EOR 0x40000000 690b2d3d26fSGleb Smirnoff #define RL_RDESC_CMD_OWN 0x80000000 691b2d3d26fSGleb Smirnoff #define RL_RDESC_CMD_BUFLEN 0x00001FFF 692b2d3d26fSGleb Smirnoff 693b2d3d26fSGleb Smirnoff #define RL_RDESC_STAT_OWN 0x80000000 694b2d3d26fSGleb Smirnoff #define RL_RDESC_STAT_EOR 0x40000000 695b2d3d26fSGleb Smirnoff #define RL_RDESC_STAT_SOF 0x20000000 696b2d3d26fSGleb Smirnoff #define RL_RDESC_STAT_EOF 0x10000000 697b2d3d26fSGleb Smirnoff #define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 698b2d3d26fSGleb Smirnoff #define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 699b2d3d26fSGleb Smirnoff #define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 700b2d3d26fSGleb Smirnoff #define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 701b2d3d26fSGleb Smirnoff #define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 702b2d3d26fSGleb Smirnoff #define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 703b2d3d26fSGleb Smirnoff #define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 704b2d3d26fSGleb Smirnoff #define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 705b2d3d26fSGleb Smirnoff #define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 706b2d3d26fSGleb Smirnoff #define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 707b2d3d26fSGleb Smirnoff #define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 708b2d3d26fSGleb Smirnoff #define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */ 709b2d3d26fSGleb Smirnoff #define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */ 710b2d3d26fSGleb Smirnoff #define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 711b2d3d26fSGleb Smirnoff #define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 712b2d3d26fSGleb Smirnoff #define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 713b2d3d26fSGleb Smirnoff #define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 714b2d3d26fSGleb Smirnoff #define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 715b2d3d26fSGleb Smirnoff #define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 716b2d3d26fSGleb Smirnoff RL_RDESC_STAT_CRCERR) 717b2d3d26fSGleb Smirnoff 718b2d3d26fSGleb Smirnoff #define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 719b2d3d26fSGleb Smirnoff (rl_vlandata valid)*/ 720b2d3d26fSGleb Smirnoff #define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 721b2d3d26fSGleb Smirnoff /* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 722b2d3d26fSGleb Smirnoff #define RL_RDESC_IPV6 0x80000000 723b2d3d26fSGleb Smirnoff #define RL_RDESC_IPV4 0x40000000 724b2d3d26fSGleb Smirnoff 725b2d3d26fSGleb Smirnoff #define RL_PROTOID_NONIP 0x00000000 726b2d3d26fSGleb Smirnoff #define RL_PROTOID_TCPIP 0x00010000 727b2d3d26fSGleb Smirnoff #define RL_PROTOID_UDPIP 0x00020000 728b2d3d26fSGleb Smirnoff #define RL_PROTOID_IP 0x00030000 729b2d3d26fSGleb Smirnoff #define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 730b2d3d26fSGleb Smirnoff RL_PROTOID_TCPIP) 731b2d3d26fSGleb Smirnoff #define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 732b2d3d26fSGleb Smirnoff RL_PROTOID_UDPIP) 733b2d3d26fSGleb Smirnoff 734b2d3d26fSGleb Smirnoff /* 735b2d3d26fSGleb Smirnoff * Statistics counter structure (8139C+ and 8169 only) 736b2d3d26fSGleb Smirnoff */ 737b2d3d26fSGleb Smirnoff struct rl_stats { 738b2d3d26fSGleb Smirnoff uint64_t rl_tx_pkts; 739b2d3d26fSGleb Smirnoff uint64_t rl_rx_pkts; 740b2d3d26fSGleb Smirnoff uint64_t rl_tx_errs; 741b2d3d26fSGleb Smirnoff uint32_t rl_rx_errs; 742b2d3d26fSGleb Smirnoff uint16_t rl_missed_pkts; 743b2d3d26fSGleb Smirnoff uint16_t rl_rx_framealign_errs; 744b2d3d26fSGleb Smirnoff uint32_t rl_tx_onecoll; 745b2d3d26fSGleb Smirnoff uint32_t rl_tx_multicolls; 746b2d3d26fSGleb Smirnoff uint64_t rl_rx_ucasts; 747b2d3d26fSGleb Smirnoff uint64_t rl_rx_bcasts; 748b2d3d26fSGleb Smirnoff uint32_t rl_rx_mcasts; 749b2d3d26fSGleb Smirnoff uint16_t rl_tx_aborts; 750b2d3d26fSGleb Smirnoff uint16_t rl_rx_underruns; 751b2d3d26fSGleb Smirnoff }; 752b2d3d26fSGleb Smirnoff 753b2d3d26fSGleb Smirnoff /* 754b2d3d26fSGleb Smirnoff * Rx/Tx descriptor parameters (8139C+ and 8169 only) 755b2d3d26fSGleb Smirnoff * 756b2d3d26fSGleb Smirnoff * 8139C+ 757b2d3d26fSGleb Smirnoff * Number of descriptors supported : up to 64 758b2d3d26fSGleb Smirnoff * Descriptor alignment : 256 bytes 759b2d3d26fSGleb Smirnoff * Tx buffer : At least 4 bytes in length. 760b2d3d26fSGleb Smirnoff * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 761b2d3d26fSGleb Smirnoff * 762b2d3d26fSGleb Smirnoff * 8169 763b2d3d26fSGleb Smirnoff * Number of descriptors supported : up to 1024 764b2d3d26fSGleb Smirnoff * Descriptor alignment : 256 bytes 765b2d3d26fSGleb Smirnoff * Tx buffer : At least 4 bytes in length. 766b2d3d26fSGleb Smirnoff * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 767b2d3d26fSGleb Smirnoff */ 768b2d3d26fSGleb Smirnoff #ifndef __NO_STRICT_ALIGNMENT 769b2d3d26fSGleb Smirnoff #define RE_FIXUP_RX 1 770b2d3d26fSGleb Smirnoff #endif 771b2d3d26fSGleb Smirnoff 772b2d3d26fSGleb Smirnoff #define RL_8169_TX_DESC_CNT 256 773b2d3d26fSGleb Smirnoff #define RL_8169_RX_DESC_CNT 256 774b2d3d26fSGleb Smirnoff #define RL_8139_TX_DESC_CNT 64 775b2d3d26fSGleb Smirnoff #define RL_8139_RX_DESC_CNT 64 776b2d3d26fSGleb Smirnoff #define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT 777b2d3d26fSGleb Smirnoff #define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT 778b2d3d26fSGleb Smirnoff #define RL_RX_JUMBO_DESC_CNT RL_RX_DESC_CNT 779b2d3d26fSGleb Smirnoff #define RL_NTXSEGS 35 780b2d3d26fSGleb Smirnoff 781b2d3d26fSGleb Smirnoff #define RL_RING_ALIGN 256 782b2d3d26fSGleb Smirnoff #define RL_DUMP_ALIGN 64 783b2d3d26fSGleb Smirnoff #define RL_IFQ_MAXLEN 512 784b2d3d26fSGleb Smirnoff #define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 785b2d3d26fSGleb Smirnoff #define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 786b2d3d26fSGleb Smirnoff #define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1)) 787b2d3d26fSGleb Smirnoff #define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 788b2d3d26fSGleb Smirnoff #define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 789b2d3d26fSGleb Smirnoff #define RL_PKTSZ(x) ((x)/* >> 3*/) 790b2d3d26fSGleb Smirnoff #ifdef RE_FIXUP_RX 791b2d3d26fSGleb Smirnoff #define RE_ETHER_ALIGN sizeof(uint64_t) 792b2d3d26fSGleb Smirnoff #define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 793b2d3d26fSGleb Smirnoff #else 794b2d3d26fSGleb Smirnoff #define RE_ETHER_ALIGN 0 795b2d3d26fSGleb Smirnoff #define RE_RX_DESC_BUFLEN MCLBYTES 796b2d3d26fSGleb Smirnoff #endif 797b2d3d26fSGleb Smirnoff 798b2d3d26fSGleb Smirnoff #define RL_MSI_MESSAGES 1 799b2d3d26fSGleb Smirnoff 800b2d3d26fSGleb Smirnoff #define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 801b2d3d26fSGleb Smirnoff #define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 802b2d3d26fSGleb Smirnoff 803b2d3d26fSGleb Smirnoff /* 804b2d3d26fSGleb Smirnoff * The number of bits reserved for MSS in RealTek controllers is 805b2d3d26fSGleb Smirnoff * 11bits. This limits the maximum interface MTU size in TSO case 806b2d3d26fSGleb Smirnoff * as upper stack should not generate TCP segments with MSS greater 807b2d3d26fSGleb Smirnoff * than the limit. 808b2d3d26fSGleb Smirnoff */ 809b2d3d26fSGleb Smirnoff #define RL_TSO_MTU (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN) 810b2d3d26fSGleb Smirnoff 811b2d3d26fSGleb Smirnoff /* see comment in dev/re/if_re.c */ 812b2d3d26fSGleb Smirnoff #define RL_JUMBO_FRAMELEN 7440 813b2d3d26fSGleb Smirnoff #define RL_JUMBO_MTU \ 814b2d3d26fSGleb Smirnoff (RL_JUMBO_FRAMELEN-ETHER_VLAN_ENCAP_LEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 815b2d3d26fSGleb Smirnoff #define RL_JUMBO_MTU_6K \ 816b2d3d26fSGleb Smirnoff ((6 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 817b2d3d26fSGleb Smirnoff #define RL_JUMBO_MTU_9K \ 818b2d3d26fSGleb Smirnoff ((9 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 819b2d3d26fSGleb Smirnoff #define RL_MTU \ 820b2d3d26fSGleb Smirnoff (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 821b2d3d26fSGleb Smirnoff 822b2d3d26fSGleb Smirnoff struct rl_txdesc { 823b2d3d26fSGleb Smirnoff struct mbuf *tx_m; 824b2d3d26fSGleb Smirnoff bus_dmamap_t tx_dmamap; 825b2d3d26fSGleb Smirnoff }; 826b2d3d26fSGleb Smirnoff 827b2d3d26fSGleb Smirnoff struct rl_rxdesc { 828b2d3d26fSGleb Smirnoff struct mbuf *rx_m; 829b2d3d26fSGleb Smirnoff bus_dmamap_t rx_dmamap; 830b2d3d26fSGleb Smirnoff bus_size_t rx_size; 831b2d3d26fSGleb Smirnoff }; 832b2d3d26fSGleb Smirnoff 833b2d3d26fSGleb Smirnoff struct rl_list_data { 834b2d3d26fSGleb Smirnoff struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT]; 835b2d3d26fSGleb Smirnoff struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT]; 836b2d3d26fSGleb Smirnoff struct rl_rxdesc rl_jrx_desc[RL_RX_JUMBO_DESC_CNT]; 837b2d3d26fSGleb Smirnoff int rl_tx_desc_cnt; 838b2d3d26fSGleb Smirnoff int rl_rx_desc_cnt; 839b2d3d26fSGleb Smirnoff int rl_tx_prodidx; 840b2d3d26fSGleb Smirnoff int rl_rx_prodidx; 841b2d3d26fSGleb Smirnoff int rl_tx_considx; 842b2d3d26fSGleb Smirnoff int rl_tx_free; 843b2d3d26fSGleb Smirnoff bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */ 844b2d3d26fSGleb Smirnoff bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */ 845b2d3d26fSGleb Smirnoff bus_dma_tag_t rl_jrx_mtag; /* mbuf RX mapping tag */ 846b2d3d26fSGleb Smirnoff bus_dmamap_t rl_rx_sparemap; 847b2d3d26fSGleb Smirnoff bus_dmamap_t rl_jrx_sparemap; 848b2d3d26fSGleb Smirnoff bus_dma_tag_t rl_stag; /* stats mapping tag */ 849b2d3d26fSGleb Smirnoff bus_dmamap_t rl_smap; /* stats map */ 850b2d3d26fSGleb Smirnoff struct rl_stats *rl_stats; 851b2d3d26fSGleb Smirnoff bus_addr_t rl_stats_addr; 852b2d3d26fSGleb Smirnoff bus_dma_tag_t rl_rx_list_tag; 853b2d3d26fSGleb Smirnoff bus_dmamap_t rl_rx_list_map; 854b2d3d26fSGleb Smirnoff struct rl_desc *rl_rx_list; 855b2d3d26fSGleb Smirnoff bus_addr_t rl_rx_list_addr; 856b2d3d26fSGleb Smirnoff bus_dma_tag_t rl_tx_list_tag; 857b2d3d26fSGleb Smirnoff bus_dmamap_t rl_tx_list_map; 858b2d3d26fSGleb Smirnoff struct rl_desc *rl_tx_list; 859b2d3d26fSGleb Smirnoff bus_addr_t rl_tx_list_addr; 860b2d3d26fSGleb Smirnoff }; 861b2d3d26fSGleb Smirnoff 862b2d3d26fSGleb Smirnoff enum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE }; 863b2d3d26fSGleb Smirnoff 864b2d3d26fSGleb Smirnoff struct rl_softc { 865ac8e2243SJustin Hibbits if_t rl_ifp; /* interface info */ 866b2d3d26fSGleb Smirnoff bus_space_handle_t rl_bhandle; /* bus space handle */ 867b2d3d26fSGleb Smirnoff bus_space_tag_t rl_btag; /* bus space tag */ 868b2d3d26fSGleb Smirnoff device_t rl_dev; 869b2d3d26fSGleb Smirnoff struct resource *rl_res; 870b2d3d26fSGleb Smirnoff int rl_res_id; 871b2d3d26fSGleb Smirnoff int rl_res_type; 872b2d3d26fSGleb Smirnoff struct resource *rl_res_pba; 873b2d3d26fSGleb Smirnoff struct resource *rl_irq[RL_MSI_MESSAGES]; 874b2d3d26fSGleb Smirnoff void *rl_intrhand[RL_MSI_MESSAGES]; 875b2d3d26fSGleb Smirnoff device_t rl_miibus; 876b2d3d26fSGleb Smirnoff bus_dma_tag_t rl_parent_tag; 877b2d3d26fSGleb Smirnoff uint8_t rl_type; 878b2d3d26fSGleb Smirnoff const struct rl_hwrev *rl_hwrev; 879b2d3d26fSGleb Smirnoff uint32_t rl_macrev; 880b2d3d26fSGleb Smirnoff int rl_eecmd_read; 881b2d3d26fSGleb Smirnoff int rl_eewidth; 882b2d3d26fSGleb Smirnoff int rl_expcap; 883b2d3d26fSGleb Smirnoff int rl_txthresh; 884b2d3d26fSGleb Smirnoff bus_size_t rl_cfg0; 885b2d3d26fSGleb Smirnoff bus_size_t rl_cfg1; 886b2d3d26fSGleb Smirnoff bus_size_t rl_cfg2; 887b2d3d26fSGleb Smirnoff bus_size_t rl_cfg3; 888b2d3d26fSGleb Smirnoff bus_size_t rl_cfg4; 889b2d3d26fSGleb Smirnoff bus_size_t rl_cfg5; 890b2d3d26fSGleb Smirnoff struct rl_chain_data rl_cdata; 891b2d3d26fSGleb Smirnoff struct rl_list_data rl_ldata; 892b2d3d26fSGleb Smirnoff struct callout rl_stat_callout; 893b2d3d26fSGleb Smirnoff int rl_watchdog_timer; 894b2d3d26fSGleb Smirnoff struct mtx rl_mtx; 895b2d3d26fSGleb Smirnoff struct mbuf *rl_head; 896b2d3d26fSGleb Smirnoff struct mbuf *rl_tail; 897b2d3d26fSGleb Smirnoff uint32_t rl_rxlenmask; 898b2d3d26fSGleb Smirnoff int rl_testmode; 899b2d3d26fSGleb Smirnoff int rl_if_flags; 900b2d3d26fSGleb Smirnoff int rl_twister_enable; 901b2d3d26fSGleb Smirnoff enum rl_twist rl_twister; 902b2d3d26fSGleb Smirnoff int rl_twist_row; 903b2d3d26fSGleb Smirnoff int rl_twist_col; 904b2d3d26fSGleb Smirnoff int suspended; /* 0 = normal 1 = suspended */ 905b2d3d26fSGleb Smirnoff #ifdef DEVICE_POLLING 906b2d3d26fSGleb Smirnoff int rxcycles; 907b2d3d26fSGleb Smirnoff #endif 908b2d3d26fSGleb Smirnoff 909b2d3d26fSGleb Smirnoff struct task rl_inttask; 910b2d3d26fSGleb Smirnoff 911b2d3d26fSGleb Smirnoff int rl_txstart; 912b2d3d26fSGleb Smirnoff int rl_int_rx_act; 913b2d3d26fSGleb Smirnoff int rl_int_rx_mod; 914b2d3d26fSGleb Smirnoff uint32_t rl_flags; 915b2d3d26fSGleb Smirnoff #define RL_FLAG_MSI 0x00000001 916b2d3d26fSGleb Smirnoff #define RL_FLAG_AUTOPAD 0x00000002 917b2d3d26fSGleb Smirnoff #define RL_FLAG_PHYWAKE_PM 0x00000004 918b2d3d26fSGleb Smirnoff #define RL_FLAG_PHYWAKE 0x00000008 919b2d3d26fSGleb Smirnoff #define RL_FLAG_JUMBOV2 0x00000010 920b2d3d26fSGleb Smirnoff #define RL_FLAG_PAR 0x00000020 921b2d3d26fSGleb Smirnoff #define RL_FLAG_DESCV2 0x00000040 922b2d3d26fSGleb Smirnoff #define RL_FLAG_MACSTAT 0x00000080 923b2d3d26fSGleb Smirnoff #define RL_FLAG_FASTETHER 0x00000100 924b2d3d26fSGleb Smirnoff #define RL_FLAG_CMDSTOP 0x00000200 925b2d3d26fSGleb Smirnoff #define RL_FLAG_MACRESET 0x00000400 926b2d3d26fSGleb Smirnoff #define RL_FLAG_MSIX 0x00000800 927b2d3d26fSGleb Smirnoff #define RL_FLAG_WOLRXENB 0x00001000 928b2d3d26fSGleb Smirnoff #define RL_FLAG_MACSLEEP 0x00002000 929b2d3d26fSGleb Smirnoff #define RL_FLAG_WAIT_TXPOLL 0x00004000 930b2d3d26fSGleb Smirnoff #define RL_FLAG_CMDSTOP_WAIT_TXQ 0x00008000 931b2d3d26fSGleb Smirnoff #define RL_FLAG_WOL_MANLINK 0x00010000 932b2d3d26fSGleb Smirnoff #define RL_FLAG_EARLYOFF 0x00020000 93314013280SMarius Strobl #define RL_FLAG_8168G_PLUS 0x00040000 934b2d3d26fSGleb Smirnoff #define RL_FLAG_PCIE 0x40000000 935b2d3d26fSGleb Smirnoff #define RL_FLAG_LINK 0x80000000 936b2d3d26fSGleb Smirnoff }; 937b2d3d26fSGleb Smirnoff 938b2d3d26fSGleb Smirnoff #define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 939b2d3d26fSGleb Smirnoff #define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 940b2d3d26fSGleb Smirnoff #define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 941b2d3d26fSGleb Smirnoff 942b2d3d26fSGleb Smirnoff /* 943b2d3d26fSGleb Smirnoff * register space access macros 944b2d3d26fSGleb Smirnoff */ 945b2d3d26fSGleb Smirnoff #define CSR_WRITE_STREAM_4(sc, reg, val) \ 946b2d3d26fSGleb Smirnoff bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 947b2d3d26fSGleb Smirnoff #define CSR_WRITE_4(sc, reg, val) \ 948b2d3d26fSGleb Smirnoff bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 949b2d3d26fSGleb Smirnoff #define CSR_WRITE_2(sc, reg, val) \ 950b2d3d26fSGleb Smirnoff bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 951b2d3d26fSGleb Smirnoff #define CSR_WRITE_1(sc, reg, val) \ 952b2d3d26fSGleb Smirnoff bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 953b2d3d26fSGleb Smirnoff 954b2d3d26fSGleb Smirnoff #define CSR_READ_4(sc, reg) \ 955b2d3d26fSGleb Smirnoff bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 956b2d3d26fSGleb Smirnoff #define CSR_READ_2(sc, reg) \ 957b2d3d26fSGleb Smirnoff bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 958b2d3d26fSGleb Smirnoff #define CSR_READ_1(sc, reg) \ 959b2d3d26fSGleb Smirnoff bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 960b2d3d26fSGleb Smirnoff 961b2d3d26fSGleb Smirnoff #define CSR_BARRIER(sc, reg, length, flags) \ 962b2d3d26fSGleb Smirnoff bus_space_barrier(sc->rl_btag, sc->rl_bhandle, reg, length, flags) 963b2d3d26fSGleb Smirnoff 964b2d3d26fSGleb Smirnoff #define CSR_SETBIT_1(sc, offset, val) \ 965b2d3d26fSGleb Smirnoff CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 966b2d3d26fSGleb Smirnoff 967b2d3d26fSGleb Smirnoff #define CSR_CLRBIT_1(sc, offset, val) \ 968b2d3d26fSGleb Smirnoff CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 969b2d3d26fSGleb Smirnoff 970b2d3d26fSGleb Smirnoff #define CSR_SETBIT_2(sc, offset, val) \ 971b2d3d26fSGleb Smirnoff CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 972b2d3d26fSGleb Smirnoff 973b2d3d26fSGleb Smirnoff #define CSR_CLRBIT_2(sc, offset, val) \ 974b2d3d26fSGleb Smirnoff CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 975b2d3d26fSGleb Smirnoff 976b2d3d26fSGleb Smirnoff #define CSR_SETBIT_4(sc, offset, val) \ 977b2d3d26fSGleb Smirnoff CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 978b2d3d26fSGleb Smirnoff 979b2d3d26fSGleb Smirnoff #define CSR_CLRBIT_4(sc, offset, val) \ 980b2d3d26fSGleb Smirnoff CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 981b2d3d26fSGleb Smirnoff 982b2d3d26fSGleb Smirnoff #define RL_TIMEOUT 1000 983b2d3d26fSGleb Smirnoff #define RL_PHY_TIMEOUT 2000 984b2d3d26fSGleb Smirnoff 985b2d3d26fSGleb Smirnoff /* 986b2d3d26fSGleb Smirnoff * General constants that are fun to know. 987b2d3d26fSGleb Smirnoff * 988b2d3d26fSGleb Smirnoff * RealTek PCI vendor ID 989b2d3d26fSGleb Smirnoff */ 990b2d3d26fSGleb Smirnoff #define RT_VENDORID 0x10EC 991b2d3d26fSGleb Smirnoff 992b2d3d26fSGleb Smirnoff /* 993b2d3d26fSGleb Smirnoff * RealTek chip device IDs. 994b2d3d26fSGleb Smirnoff */ 9953c871489SSk Razee #define RT_DEVICEID_2600 0x2600 996b2d3d26fSGleb Smirnoff #define RT_DEVICEID_8139D 0x8039 997b2d3d26fSGleb Smirnoff #define RT_DEVICEID_8129 0x8129 998b2d3d26fSGleb Smirnoff #define RT_DEVICEID_8101E 0x8136 999b2d3d26fSGleb Smirnoff #define RT_DEVICEID_8138 0x8138 1000b2d3d26fSGleb Smirnoff #define RT_DEVICEID_8139 0x8139 1001b2d3d26fSGleb Smirnoff #define RT_DEVICEID_8169SC 0x8167 1002ce3e137cSMark Johnston #define RT_DEVICEID_8161 0x8161 1003b2d3d26fSGleb Smirnoff #define RT_DEVICEID_8168 0x8168 1004b2d3d26fSGleb Smirnoff #define RT_DEVICEID_8169 0x8169 1005b2d3d26fSGleb Smirnoff #define RT_DEVICEID_8100 0x8100 1006b2d3d26fSGleb Smirnoff 1007b2d3d26fSGleb Smirnoff #define RT_REVID_8139CPLUS 0x20 1008b2d3d26fSGleb Smirnoff 1009b2d3d26fSGleb Smirnoff /* 1010b2d3d26fSGleb Smirnoff * Accton PCI vendor ID 1011b2d3d26fSGleb Smirnoff */ 1012b2d3d26fSGleb Smirnoff #define ACCTON_VENDORID 0x1113 1013b2d3d26fSGleb Smirnoff 1014b2d3d26fSGleb Smirnoff /* 1015b2d3d26fSGleb Smirnoff * Accton MPX 5030/5038 device ID. 1016b2d3d26fSGleb Smirnoff */ 1017b2d3d26fSGleb Smirnoff #define ACCTON_DEVICEID_5030 0x1211 1018b2d3d26fSGleb Smirnoff 1019b2d3d26fSGleb Smirnoff /* 1020b2d3d26fSGleb Smirnoff * Nortel PCI vendor ID 1021b2d3d26fSGleb Smirnoff */ 1022b2d3d26fSGleb Smirnoff #define NORTEL_VENDORID 0x126C 1023b2d3d26fSGleb Smirnoff 1024b2d3d26fSGleb Smirnoff /* 1025b2d3d26fSGleb Smirnoff * Delta Electronics Vendor ID. 1026b2d3d26fSGleb Smirnoff */ 1027b2d3d26fSGleb Smirnoff #define DELTA_VENDORID 0x1500 1028b2d3d26fSGleb Smirnoff 1029b2d3d26fSGleb Smirnoff /* 1030b2d3d26fSGleb Smirnoff * Delta device IDs. 1031b2d3d26fSGleb Smirnoff */ 1032b2d3d26fSGleb Smirnoff #define DELTA_DEVICEID_8139 0x1360 1033b2d3d26fSGleb Smirnoff 1034b2d3d26fSGleb Smirnoff /* 1035b2d3d26fSGleb Smirnoff * Addtron vendor ID. 1036b2d3d26fSGleb Smirnoff */ 1037b2d3d26fSGleb Smirnoff #define ADDTRON_VENDORID 0x4033 1038b2d3d26fSGleb Smirnoff 1039b2d3d26fSGleb Smirnoff /* 1040b2d3d26fSGleb Smirnoff * Addtron device IDs. 1041b2d3d26fSGleb Smirnoff */ 1042b2d3d26fSGleb Smirnoff #define ADDTRON_DEVICEID_8139 0x1360 1043b2d3d26fSGleb Smirnoff 1044b2d3d26fSGleb Smirnoff /* 1045b2d3d26fSGleb Smirnoff * D-Link vendor ID. 1046b2d3d26fSGleb Smirnoff */ 1047b2d3d26fSGleb Smirnoff #define DLINK_VENDORID 0x1186 1048b2d3d26fSGleb Smirnoff 1049b2d3d26fSGleb Smirnoff /* 1050b2d3d26fSGleb Smirnoff * D-Link DFE-530TX+ device ID 1051b2d3d26fSGleb Smirnoff */ 1052b2d3d26fSGleb Smirnoff #define DLINK_DEVICEID_530TXPLUS 0x1300 1053b2d3d26fSGleb Smirnoff 1054b2d3d26fSGleb Smirnoff /* 1055b2d3d26fSGleb Smirnoff * D-Link DFE-520TX rev. C1 device ID 1056b2d3d26fSGleb Smirnoff */ 1057b2d3d26fSGleb Smirnoff #define DLINK_DEVICEID_520TX_REVC1 0x4200 1058b2d3d26fSGleb Smirnoff 1059b2d3d26fSGleb Smirnoff /* 1060b2d3d26fSGleb Smirnoff * D-Link DFE-5280T device ID 1061b2d3d26fSGleb Smirnoff */ 1062b2d3d26fSGleb Smirnoff #define DLINK_DEVICEID_528T 0x4300 1063b2d3d26fSGleb Smirnoff #define DLINK_DEVICEID_530T_REVC 0x4302 1064b2d3d26fSGleb Smirnoff 1065b2d3d26fSGleb Smirnoff /* 1066b2d3d26fSGleb Smirnoff * D-Link DFE-690TXD device ID 1067b2d3d26fSGleb Smirnoff */ 1068b2d3d26fSGleb Smirnoff #define DLINK_DEVICEID_690TXD 0x1340 1069b2d3d26fSGleb Smirnoff 1070b2d3d26fSGleb Smirnoff /* 1071b2d3d26fSGleb Smirnoff * Corega K.K vendor ID 1072b2d3d26fSGleb Smirnoff */ 1073b2d3d26fSGleb Smirnoff #define COREGA_VENDORID 0x1259 1074b2d3d26fSGleb Smirnoff 1075b2d3d26fSGleb Smirnoff /* 1076b2d3d26fSGleb Smirnoff * Corega FEther CB-TXD device ID 1077b2d3d26fSGleb Smirnoff */ 1078b2d3d26fSGleb Smirnoff #define COREGA_DEVICEID_FETHERCBTXD 0xa117 1079b2d3d26fSGleb Smirnoff 1080b2d3d26fSGleb Smirnoff /* 1081b2d3d26fSGleb Smirnoff * Corega FEtherII CB-TXD device ID 1082b2d3d26fSGleb Smirnoff */ 1083b2d3d26fSGleb Smirnoff #define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 1084b2d3d26fSGleb Smirnoff 1085b2d3d26fSGleb Smirnoff /* 1086b2d3d26fSGleb Smirnoff * Corega CG-LAPCIGT device ID 1087b2d3d26fSGleb Smirnoff */ 1088b2d3d26fSGleb Smirnoff #define COREGA_DEVICEID_CGLAPCIGT 0xc107 1089b2d3d26fSGleb Smirnoff 1090b2d3d26fSGleb Smirnoff /* 1091b2d3d26fSGleb Smirnoff * Linksys vendor ID 1092b2d3d26fSGleb Smirnoff */ 1093b2d3d26fSGleb Smirnoff #define LINKSYS_VENDORID 0x1737 1094b2d3d26fSGleb Smirnoff 1095b2d3d26fSGleb Smirnoff /* 1096b2d3d26fSGleb Smirnoff * Linksys EG1032 device ID 1097b2d3d26fSGleb Smirnoff */ 1098b2d3d26fSGleb Smirnoff #define LINKSYS_DEVICEID_EG1032 0x1032 1099b2d3d26fSGleb Smirnoff 1100b2d3d26fSGleb Smirnoff /* 1101b2d3d26fSGleb Smirnoff * Linksys EG1032 rev 3 sub-device ID 1102b2d3d26fSGleb Smirnoff */ 1103b2d3d26fSGleb Smirnoff #define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 1104b2d3d26fSGleb Smirnoff 1105b2d3d26fSGleb Smirnoff /* 1106b2d3d26fSGleb Smirnoff * Peppercon vendor ID 1107b2d3d26fSGleb Smirnoff */ 1108b2d3d26fSGleb Smirnoff #define PEPPERCON_VENDORID 0x1743 1109b2d3d26fSGleb Smirnoff 1110b2d3d26fSGleb Smirnoff /* 1111b2d3d26fSGleb Smirnoff * Peppercon ROL-F device ID 1112b2d3d26fSGleb Smirnoff */ 1113b2d3d26fSGleb Smirnoff #define PEPPERCON_DEVICEID_ROLF 0x8139 1114b2d3d26fSGleb Smirnoff 1115b2d3d26fSGleb Smirnoff /* 1116b2d3d26fSGleb Smirnoff * Planex Communications, Inc. vendor ID 1117b2d3d26fSGleb Smirnoff */ 1118b2d3d26fSGleb Smirnoff #define PLANEX_VENDORID 0x14ea 1119b2d3d26fSGleb Smirnoff 1120b2d3d26fSGleb Smirnoff /* 1121b2d3d26fSGleb Smirnoff * Planex FNW-3603-TX device ID 1122b2d3d26fSGleb Smirnoff */ 1123b2d3d26fSGleb Smirnoff #define PLANEX_DEVICEID_FNW3603TX 0xab06 1124b2d3d26fSGleb Smirnoff 1125b2d3d26fSGleb Smirnoff /* 1126b2d3d26fSGleb Smirnoff * Planex FNW-3800-TX device ID 1127b2d3d26fSGleb Smirnoff */ 1128b2d3d26fSGleb Smirnoff #define PLANEX_DEVICEID_FNW3800TX 0xab07 1129b2d3d26fSGleb Smirnoff 1130b2d3d26fSGleb Smirnoff /* 1131b2d3d26fSGleb Smirnoff * LevelOne vendor ID 1132b2d3d26fSGleb Smirnoff */ 1133b2d3d26fSGleb Smirnoff #define LEVEL1_VENDORID 0x018A 1134b2d3d26fSGleb Smirnoff 1135b2d3d26fSGleb Smirnoff /* 1136b2d3d26fSGleb Smirnoff * LevelOne FPC-0106TX devide ID 1137b2d3d26fSGleb Smirnoff */ 1138b2d3d26fSGleb Smirnoff #define LEVEL1_DEVICEID_FPC0106TX 0x0106 1139b2d3d26fSGleb Smirnoff 1140b2d3d26fSGleb Smirnoff /* 1141b2d3d26fSGleb Smirnoff * Compaq vendor ID 1142b2d3d26fSGleb Smirnoff */ 1143b2d3d26fSGleb Smirnoff #define CP_VENDORID 0x021B 1144b2d3d26fSGleb Smirnoff 1145b2d3d26fSGleb Smirnoff /* 1146b2d3d26fSGleb Smirnoff * Edimax vendor ID 1147b2d3d26fSGleb Smirnoff */ 1148b2d3d26fSGleb Smirnoff #define EDIMAX_VENDORID 0x13D1 1149b2d3d26fSGleb Smirnoff 1150b2d3d26fSGleb Smirnoff /* 1151b2d3d26fSGleb Smirnoff * Edimax EP-4103DL cardbus device ID 1152b2d3d26fSGleb Smirnoff */ 1153b2d3d26fSGleb Smirnoff #define EDIMAX_DEVICEID_EP4103DL 0xAB06 1154b2d3d26fSGleb Smirnoff 1155b2d3d26fSGleb Smirnoff /* US Robotics vendor ID */ 1156b2d3d26fSGleb Smirnoff 1157b2d3d26fSGleb Smirnoff #define USR_VENDORID 0x16EC 1158b2d3d26fSGleb Smirnoff 1159b2d3d26fSGleb Smirnoff /* US Robotics 997902 device ID */ 1160b2d3d26fSGleb Smirnoff 1161b2d3d26fSGleb Smirnoff #define USR_DEVICEID_997902 0x0116 1162938e9a89SKevin Lo 1163938e9a89SKevin Lo /* 1164938e9a89SKevin Lo * NCube vendor ID 1165938e9a89SKevin Lo */ 1166938e9a89SKevin Lo #define NCUBE_VENDORID 0x10FF 1167