1 /* $OpenBSD: if_rtwn.c,v 1.6 2015/08/28 00:03:53 deraadt Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org> 6 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/cdefs.h> 22 __FBSDID("$FreeBSD$"); 23 24 #include "opt_wlan.h" 25 26 #include <sys/param.h> 27 #include <sys/lock.h> 28 #include <sys/mutex.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/queue.h> 35 #include <sys/taskqueue.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/linker.h> 39 40 #include <machine/bus.h> 41 #include <machine/resource.h> 42 #include <sys/rman.h> 43 44 #include <net/if.h> 45 #include <net/ethernet.h> 46 #include <net/if_media.h> 47 48 #include <net80211/ieee80211_var.h> 49 #include <net80211/ieee80211_radiotap.h> 50 51 #include <dev/rtwn/if_rtwnreg.h> 52 #include <dev/rtwn/if_rtwnvar.h> 53 #include <dev/rtwn/if_rtwn_debug.h> 54 55 #include <dev/rtwn/pci/rtwn_pci_var.h> 56 57 #include <dev/rtwn/rtl8192c/pci/r92ce.h> 58 #include <dev/rtwn/rtl8192c/pci/r92ce_reg.h> 59 60 61 /* Registers to save and restore during IQ calibration. */ 62 struct r92ce_iq_cal_reg_vals { 63 uint32_t adda[16]; 64 uint8_t txpause; 65 uint8_t bcn_ctrl[2]; 66 uint32_t gpio_muxcfg; 67 uint32_t ofdm0_trxpathena; 68 uint32_t ofdm0_trmuxpar; 69 uint32_t fpga0_rfifacesw1; 70 }; 71 72 /* XXX 92CU? */ 73 static int 74 r92ce_iq_calib_chain(struct rtwn_softc *sc, int chain, uint16_t tx[2], 75 uint16_t rx[2]) 76 { 77 uint32_t status; 78 79 if (chain == 0) { /* IQ calibration for chain 0. */ 80 /* IQ calibration settings for chain 0. */ 81 rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x10008c1f); 82 rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x10008c1f); 83 rtwn_bb_write(sc, R92C_TX_IQK_PI(0), 0x82140102); 84 85 if (sc->ntxchains > 1) { 86 rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160202); 87 /* IQ calibration settings for chain 1. */ 88 rtwn_bb_write(sc, R92C_TX_IQK_TONE(1), 0x10008c22); 89 rtwn_bb_write(sc, R92C_RX_IQK_TONE(1), 0x10008c22); 90 rtwn_bb_write(sc, R92C_TX_IQK_PI(1), 0x82140102); 91 rtwn_bb_write(sc, R92C_RX_IQK_PI(1), 0x28160202); 92 } else 93 rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160502); 94 95 /* LO calibration settings. */ 96 rtwn_bb_write(sc, R92C_IQK_AGC_RSP, 0x001028d1); 97 /* We're doing LO and IQ calibration in one shot. */ 98 rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf9000000); 99 rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf8000000); 100 101 } else { /* IQ calibration for chain 1. */ 102 /* We're doing LO and IQ calibration in one shot. */ 103 rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 2); 104 rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 0); 105 } 106 107 /* Give LO and IQ calibrations the time to complete. */ 108 rtwn_delay(sc, 1000); 109 110 /* Read IQ calibration status. */ 111 status = rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(0)); 112 113 if (status & (1 << (28 + chain * 3))) 114 return (0); /* Tx failed. */ 115 /* Read Tx IQ calibration results. */ 116 tx[0] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_BEFORE(chain)), 117 R92C_POWER_IQK_RESULT); 118 tx[1] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_AFTER(chain)), 119 R92C_POWER_IQK_RESULT); 120 if (tx[0] == 0x142 || tx[1] == 0x042) 121 return (0); /* Tx failed. */ 122 123 if (status & (1 << (27 + chain * 3))) 124 return (1); /* Rx failed. */ 125 /* Read Rx IQ calibration results. */ 126 rx[0] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_BEFORE(chain)), 127 R92C_POWER_IQK_RESULT); 128 rx[1] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(chain)), 129 R92C_POWER_IQK_RESULT); 130 if (rx[0] == 0x132 || rx[1] == 0x036) 131 return (1); /* Rx failed. */ 132 133 return (3); /* Both Tx and Rx succeeded. */ 134 } 135 136 static void 137 r92ce_iq_calib_run(struct rtwn_softc *sc, int n, uint16_t tx[2][2], 138 uint16_t rx[2][2], struct r92ce_iq_cal_reg_vals *vals) 139 { 140 /* Registers to save and restore during IQ calibration. */ 141 static const uint16_t reg_adda[16] = { 142 0x85c, 0xe6c, 0xe70, 0xe74, 143 0xe78, 0xe7c, 0xe80, 0xe84, 144 0xe88, 0xe8c, 0xed0, 0xed4, 145 0xed8, 0xedc, 0xee0, 0xeec 146 }; 147 int i, chain; 148 uint32_t hssi_param1; 149 150 if (n == 0) { 151 for (i = 0; i < nitems(reg_adda); i++) 152 vals->adda[i] = rtwn_bb_read(sc, reg_adda[i]); 153 154 vals->txpause = rtwn_read_1(sc, R92C_TXPAUSE); 155 vals->bcn_ctrl[0] = rtwn_read_1(sc, R92C_BCN_CTRL(0)); 156 vals->bcn_ctrl[1] = rtwn_read_1(sc, R92C_BCN_CTRL(1)); 157 vals->gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG); 158 } 159 160 if (sc->ntxchains == 1) { 161 rtwn_bb_write(sc, reg_adda[0], 0x0b1b25a0); 162 for (i = 1; i < nitems(reg_adda); i++) 163 rtwn_bb_write(sc, reg_adda[i], 0x0bdb25a0); 164 } else { 165 for (i = 0; i < nitems(reg_adda); i++) 166 rtwn_bb_write(sc, reg_adda[i], 0x04db25a4); 167 } 168 169 hssi_param1 = rtwn_bb_read(sc, R92C_HSSI_PARAM1(0)); 170 if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) { 171 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 172 hssi_param1 | R92C_HSSI_PARAM1_PI); 173 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 174 hssi_param1 | R92C_HSSI_PARAM1_PI); 175 } 176 177 if (n == 0) { 178 vals->ofdm0_trxpathena = 179 rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 180 vals->ofdm0_trmuxpar = rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 181 vals->fpga0_rfifacesw1 = 182 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 183 } 184 185 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 0x03a05600); 186 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 0x000800e4); 187 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000); 188 if (sc->ntxchains > 1) { 189 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); 190 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00010000); 191 } 192 193 rtwn_write_1(sc, R92C_TXPAUSE, 194 R92C_TX_QUEUE_AC | R92C_TX_QUEUE_MGT | R92C_TX_QUEUE_HIGH); 195 rtwn_write_1(sc, R92C_BCN_CTRL(0), 196 vals->bcn_ctrl[0] & ~R92C_BCN_CTRL_EN_BCN); 197 rtwn_write_1(sc, R92C_BCN_CTRL(1), 198 vals->bcn_ctrl[1] & ~R92C_BCN_CTRL_EN_BCN); 199 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 200 vals->gpio_muxcfg & ~R92C_GPIO_MUXCFG_ENBT); 201 202 rtwn_bb_write(sc, 0x0b68, 0x00080000); 203 if (sc->ntxchains > 1) 204 rtwn_bb_write(sc, 0x0b6c, 0x00080000); 205 206 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000); 207 rtwn_bb_write(sc, R92C_TX_IQK, 0x01007c00); 208 rtwn_bb_write(sc, R92C_RX_IQK, 0x01004800); 209 210 rtwn_bb_write(sc, 0x0b68, 0x00080000); 211 212 for (chain = 0; chain < sc->ntxchains; chain++) { 213 if (chain > 0) { 214 /* Put chain 0 on standby. */ 215 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0); 216 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); 217 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000); 218 219 /* Enable chain 1. */ 220 for (i = 0; i < nitems(reg_adda); i++) 221 rtwn_bb_write(sc, reg_adda[i], 0x0b1b25a4); 222 } 223 224 /* Run IQ calibration twice. */ 225 for (i = 0; i < 2; i++) { 226 int ret; 227 228 ret = r92ce_iq_calib_chain(sc, chain, 229 tx[chain], rx[chain]); 230 if (ret == 0) { 231 RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB, 232 "%s: chain %d: Tx failed.\n", 233 __func__, chain); 234 tx[chain][0] = 0xff; 235 tx[chain][1] = 0xff; 236 rx[chain][0] = 0xff; 237 rx[chain][1] = 0xff; 238 } else if (ret == 1) { 239 RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB, 240 "%s: chain %d: Rx failed.\n", 241 __func__, chain); 242 rx[chain][0] = 0xff; 243 rx[chain][1] = 0xff; 244 } else if (ret == 3) { 245 RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB, 246 "%s: chain %d: Both Tx and Rx " 247 "succeeded.\n", __func__, chain); 248 } 249 } 250 251 RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB, 252 "%s: results for run %d chain %d: tx[0] 0x%x, " 253 "tx[1] 0x%x, rx[0] 0x%x, rx[1] 0x%x\n", __func__, n, chain, 254 tx[chain][0], tx[chain][1], rx[chain][0], rx[chain][1]); 255 } 256 257 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 258 vals->ofdm0_trxpathena); 259 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 260 vals->fpga0_rfifacesw1); 261 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, vals->ofdm0_trmuxpar); 262 263 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0); 264 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00032ed3); 265 if (sc->ntxchains > 1) 266 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00032ed3); 267 268 if (n != 0) { 269 if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) { 270 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), hssi_param1); 271 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), hssi_param1); 272 } 273 274 for (i = 0; i < nitems(reg_adda); i++) 275 rtwn_bb_write(sc, reg_adda[i], vals->adda[i]); 276 277 rtwn_write_1(sc, R92C_TXPAUSE, vals->txpause); 278 rtwn_write_1(sc, R92C_BCN_CTRL(0), vals->bcn_ctrl[0]); 279 rtwn_write_1(sc, R92C_BCN_CTRL(1), vals->bcn_ctrl[1]); 280 rtwn_write_4(sc, R92C_GPIO_MUXCFG, vals->gpio_muxcfg); 281 } 282 } 283 284 #define RTWN_IQ_CAL_MAX_TOLERANCE 5 285 static int 286 r92ce_iq_calib_compare_results(struct rtwn_softc *sc, uint16_t tx1[2][2], 287 uint16_t rx1[2][2], uint16_t tx2[2][2], uint16_t rx2[2][2]) 288 { 289 int chain, i, tx_ok[2], rx_ok[2]; 290 291 tx_ok[0] = tx_ok[1] = rx_ok[0] = rx_ok[1] = 0; 292 for (chain = 0; chain < sc->ntxchains; chain++) { 293 for (i = 0; i < 2; i++) { 294 if (tx1[chain][i] == 0xff || tx2[chain][i] == 0xff || 295 rx1[chain][i] == 0xff || rx2[chain][i] == 0xff) 296 continue; 297 298 tx_ok[chain] = (abs(tx1[chain][i] - tx2[chain][i]) <= 299 RTWN_IQ_CAL_MAX_TOLERANCE); 300 301 rx_ok[chain] = (abs(rx1[chain][i] - rx2[chain][i]) <= 302 RTWN_IQ_CAL_MAX_TOLERANCE); 303 } 304 } 305 306 if (sc->ntxchains > 1) 307 return (tx_ok[0] && tx_ok[1] && rx_ok[0] && rx_ok[1]); 308 else 309 return (tx_ok[0] && rx_ok[0]); 310 } 311 #undef RTWN_IQ_CAL_MAX_TOLERANCE 312 313 static void 314 r92ce_iq_calib_write_results(struct rtwn_softc *sc, uint16_t tx[2], 315 uint16_t rx[2], int chain) 316 { 317 uint32_t reg, val, x; 318 long y, tx_c; 319 320 if (tx[0] == 0xff || tx[1] == 0xff) 321 return; 322 323 reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain)); 324 val = ((reg >> 22) & 0x3ff); 325 x = tx[0]; 326 if (x & 0x00000200) 327 x |= 0xfffffc00; 328 reg = (((x * val) >> 8) & 0x3ff); 329 rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(chain), 0x3ff, reg); 330 rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x80000000, 331 ((x * val) & 0x80) << 24); 332 333 y = tx[1]; 334 if (y & 0x00000200) 335 y |= 0xfffffc00; 336 tx_c = (y * val) >> 8; 337 rtwn_bb_setbits(sc, R92C_OFDM0_TXAFE(chain), 0xf0000000, 338 (tx_c & 0x3c0) << 22); 339 rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(chain), 0x003f0000, 340 (tx_c & 0x3f) << 16); 341 rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x20000000, 342 ((y * val) & 0x80) << 22); 343 344 if (rx[0] == 0xff || rx[1] == 0xff) 345 return; 346 347 rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(chain), 0x3ff, 348 rx[0] & 0x3ff); 349 rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(chain), 0xfc00, 350 (rx[1] & 0x3f) << 10); 351 352 if (chain == 0) { 353 rtwn_bb_setbits(sc, R92C_OFDM0_RXIQEXTANTA, 0xf0000000, 354 (rx[1] & 0x3c0) << 22); 355 } else { 356 rtwn_bb_setbits(sc, R92C_OFDM0_AGCRSSITABLE, 0xf000, 357 (rx[1] & 0x3c0) << 6); 358 } 359 } 360 361 #define RTWN_IQ_CAL_NRUN 3 362 void 363 r92ce_iq_calib(struct rtwn_softc *sc) 364 { 365 struct r92ce_iq_cal_reg_vals vals; 366 uint16_t tx[RTWN_IQ_CAL_NRUN][2][2], rx[RTWN_IQ_CAL_NRUN][2][2]; 367 int n, valid; 368 369 valid = 0; 370 for (n = 0; n < RTWN_IQ_CAL_NRUN; n++) { 371 r92ce_iq_calib_run(sc, n, tx[n], rx[n], &vals); 372 373 if (n == 0) 374 continue; 375 376 /* Valid results remain stable after consecutive runs. */ 377 valid = r92ce_iq_calib_compare_results(sc, tx[n - 1], 378 rx[n - 1], tx[n], rx[n]); 379 if (valid) 380 break; 381 } 382 383 if (valid) { 384 r92ce_iq_calib_write_results(sc, tx[n][0], rx[n][0], 0); 385 if (sc->ntxchains > 1) 386 r92ce_iq_calib_write_results(sc, tx[n][1], rx[n][1], 1); 387 } 388 } 389 #undef RTWN_IQ_CAL_NRUN 390