1 /*- 2 * Copyright (c) 2017 Kevin Lo <kevlo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #include "opt_wlan.h" 29 30 #include <sys/param.h> 31 #include <sys/lock.h> 32 #include <sys/mutex.h> 33 #include <sys/mbuf.h> 34 #include <sys/kernel.h> 35 #include <sys/socket.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/queue.h> 39 #include <sys/taskqueue.h> 40 #include <sys/bus.h> 41 #include <sys/endian.h> 42 #include <sys/linker.h> 43 44 #include <net/if.h> 45 #include <net/ethernet.h> 46 #include <net/if_media.h> 47 48 #include <net80211/ieee80211_var.h> 49 #include <net80211/ieee80211_radiotap.h> 50 51 #include <dev/rtwn/if_rtwnreg.h> 52 #include <dev/rtwn/if_rtwnvar.h> 53 54 #include <dev/rtwn/if_rtwn_debug.h> 55 56 #include <dev/rtwn/rtl8192c/r92c.h> 57 58 #include <dev/rtwn/rtl8192e/r92e.h> 59 #include <dev/rtwn/rtl8192e/r92e_reg.h> 60 #include <dev/rtwn/rtl8192e/r92e_priv.h> 61 #include <dev/rtwn/rtl8192e/r92e_var.h> 62 63 int 64 r92e_llt_init(struct rtwn_softc *sc) 65 { 66 int ntries, error; 67 68 error = rtwn_setbits_4(sc, R92C_AUTO_LLT, 0, R92C_AUTO_LLT_INIT); 69 if (error != 0) 70 return (error); 71 for (ntries = 0; ntries < 1000; ntries++) { 72 if (!(rtwn_read_4(sc, R92C_AUTO_LLT) & R92C_AUTO_LLT_INIT)) 73 return (0); 74 rtwn_delay(sc, 1); 75 } 76 return (ETIMEDOUT); 77 } 78 79 static void 80 r92e_crystalcap_write(struct rtwn_softc *sc) 81 { 82 struct r92e_softc *rs = sc->sc_priv; 83 uint32_t reg; 84 uint8_t val; 85 86 val = rs->crystalcap & 0x3f; 87 reg = rtwn_bb_read(sc, R92E_AFE_XTAL_CTRL); 88 rtwn_bb_write(sc, R92E_AFE_XTAL_CTRL, 89 RW(reg, R92E_AFE_XTAL_CTRL_ADDR, val | val << 6)); 90 rtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 0x000f81fb); 91 } 92 93 void 94 r92e_init_bb(struct rtwn_softc *sc) 95 { 96 int i, j; 97 98 rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0, 99 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD); 100 101 /* Enable BB and RF. */ 102 rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0, 103 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 104 R92C_SYS_FUNC_EN_DIO_RF); 105 106 /* PathA RF Power On. */ 107 rtwn_write_1(sc, R92C_RF_CTRL, 108 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 109 110 /* Write BB initialization values. */ 111 for (i = 0; i < sc->bb_size; i++) { 112 const struct rtwn_bb_prog *bb_prog = &sc->bb_prog[i]; 113 114 while (!rtwn_check_condition(sc, bb_prog->cond)) { 115 KASSERT(bb_prog->next != NULL, 116 ("%s: wrong condition value (i %d)\n", 117 __func__, i)); 118 bb_prog = bb_prog->next; 119 } 120 121 for (j = 0; j < bb_prog->count; j++) { 122 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 123 "BB: reg 0x%03x, val 0x%08x\n", 124 bb_prog->reg[j], bb_prog->val[j]); 125 126 rtwn_bb_write(sc, bb_prog->reg[j], bb_prog->val[j]); 127 rtwn_delay(sc, 1); 128 } 129 } 130 131 /* Write AGC values. */ 132 for (i = 0; i < sc->agc_size; i++) { 133 const struct rtwn_agc_prog *agc_prog = &sc->agc_prog[i]; 134 135 while (!rtwn_check_condition(sc, agc_prog->cond)) { 136 KASSERT(agc_prog->next != NULL, 137 ("%s: wrong condition value (2) (i %d)\n", 138 __func__, i)); 139 agc_prog = agc_prog->next; 140 } 141 142 for (j = 0; j < agc_prog->count; j++) { 143 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 144 "AGC: val 0x%08x\n", agc_prog->val[j]); 145 146 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 147 agc_prog->val[j]); 148 rtwn_delay(sc, 1); 149 } 150 } 151 152 if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & R92C_HSSI_PARAM2_CCK_HIPWR) 153 sc->sc_flags |= RTWN_FLAG_CCK_HIPWR; 154 155 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040022); 156 rtwn_delay(sc, 1); 157 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040020); 158 rtwn_delay(sc, 1); 159 160 r92e_crystalcap_write(sc); 161 } 162 163 void 164 r92e_init_rf(struct rtwn_softc *sc) 165 { 166 struct r92e_softc *rs = sc->sc_priv; 167 uint32_t reg, type; 168 int i, chain, idx, off; 169 170 for (chain = 0, i = 0; chain < sc->nrxchains; chain++, i++) { 171 /* Save RF_ENV control type. */ 172 idx = chain / 2; 173 off = (chain % 2) * 16; 174 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 175 type = (reg >> off) & 0x10; 176 177 /* Set RF_ENV enable. */ 178 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain), 179 0, 0x100000); 180 rtwn_delay(sc, 1); 181 /* Set RF_ENV output high. */ 182 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain), 183 0, 0x10); 184 rtwn_delay(sc, 1); 185 /* Set address and data lengths of RF registers. */ 186 rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(chain), 187 R92C_HSSI_PARAM2_ADDR_LENGTH, 0); 188 rtwn_delay(sc, 1); 189 rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(chain), 190 R92C_HSSI_PARAM2_DATA_LENGTH, 0); 191 rtwn_delay(sc, 1); 192 193 /* Write RF initialization values for this chain. */ 194 i += r92c_init_rf_chain(sc, &sc->rf_prog[i], chain); 195 196 /* Restore RF_ENV control type. */ 197 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 198 reg &= ~(0x10 << off) | (type << off); 199 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 200 201 /* Cache RF register CHNLBW. */ 202 rs->rf_chnlbw[chain] = rtwn_rf_read(sc, chain, R92C_RF_CHNLBW); 203 } 204 205 /* Turn CCK and OFDM blocks on. */ 206 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_CCK_EN); 207 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_OFDM_EN); 208 } 209 210 static void 211 r92e_adj_crystal(struct rtwn_softc *sc) 212 { 213 214 rtwn_setbits_1(sc, R92C_AFE_PLL_CTRL, R92C_AFE_PLL_CTRL_FREF_SEL, 0); 215 rtwn_setbits_4(sc, R92E_APE_PLL_CTRL_EXT, 0x00000380, 0); 216 rtwn_setbits_1(sc, R92C_AFE_PLL_CTRL, 0x40, 0); 217 rtwn_setbits_4(sc, R92E_APE_PLL_CTRL_EXT, 0x00200000, 0); 218 } 219 220 int 221 r92e_power_on(struct rtwn_softc *sc) 222 { 223 #define RTWN_CHK(res) do { \ 224 if (res != 0) \ 225 return (EIO); \ 226 } while(0) 227 int ntries; 228 229 if (rtwn_read_4(sc, R92C_SYS_CFG) & R92C_SYS_CFG_TRP_BT_EN) 230 RTWN_CHK(rtwn_write_1(sc, R92C_LDO_SWR_CTRL, 0xc3)); 231 else { 232 RTWN_CHK(rtwn_setbits_4(sc, R92E_LDOV12_CTRL, 0x00100000, 233 0x00500000)); 234 RTWN_CHK(rtwn_write_1(sc, R92C_LDO_SWR_CTRL, 0x83)); 235 } 236 237 r92e_adj_crystal(sc); 238 239 /* Enable WL suspend. */ 240 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 241 R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE, 0, 1)); 242 243 /* Disable HWPDN, SW LPS and WL suspend. */ 244 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 245 R92C_APS_FSMCO_APFM_RSM | R92C_APS_FSMCO_AFSM_HSUS | 246 R92C_APS_FSMCO_AFSM_PCIE | R92C_APS_FSMCO_APDM_HPDN, 0, 1)); 247 248 /* Wait for power ready bit. */ 249 for (ntries = 0; ntries < 5000; ntries++) { 250 if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 251 break; 252 rtwn_delay(sc, 10); 253 } 254 if (ntries == 5000) { 255 device_printf(sc->sc_dev, 256 "timeout waiting for chip power up\n"); 257 return (ETIMEDOUT); 258 } 259 260 /* Release WLON reset. */ 261 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, 262 R92C_APS_FSMCO_RDY_MACON, 2)); 263 264 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, 265 R92C_APS_FSMCO_APFM_ONMAC, 1)); 266 for (ntries = 0; ntries < 5000; ntries++) { 267 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) & 268 R92C_APS_FSMCO_APFM_ONMAC)) 269 break; 270 rtwn_delay(sc, 10); 271 } 272 if (ntries == 5000) 273 return (ETIMEDOUT); 274 275 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 276 RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0)); 277 RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0, 278 R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN | 279 R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN | 280 R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN | 281 ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) | 282 R92C_CR_CALTMR_EN)); 283 284 return (0); 285 } 286 287 void 288 r92e_power_off(struct rtwn_softc *sc) 289 { 290 int error, ntries; 291 292 /* Stop Rx. */ 293 error = rtwn_write_1(sc, R92C_CR, 0); 294 if (error == ENXIO) /* hardware gone */ 295 return; 296 297 /* Move card to Low Power state. */ 298 /* Block all Tx queues. */ 299 rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 300 301 for (ntries = 0; ntries < 5000; ntries++) { 302 /* Should be zero if no packet is transmitting. */ 303 if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0) 304 break; 305 306 rtwn_delay(sc, 10); 307 } 308 if (ntries == 5000) { 309 device_printf(sc->sc_dev, "%s: failed to block Tx queues\n", 310 __func__); 311 return; 312 } 313 314 /* CCK and OFDM are disabled, and clock are gated. */ 315 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0); 316 317 rtwn_delay(sc, 1); 318 319 /* Reset whole BB. */ 320 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0); 321 322 /* Reset MAC TRX. */ 323 rtwn_write_1(sc, R92C_CR, 324 R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN); 325 326 /* Check if removed later. */ 327 rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1); 328 329 /* Respond TxOK to scheduler */ 330 rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, R92C_DUAL_TSF_RST_TXOK); 331 332 /* Reset MCU. */ 333 rtwn_write_1(sc, R92C_MCUFWDL, 0); 334 335 #ifndef RTWN_WITHOUT_UCODE 336 /* Reset MCU IO wrapper. */ 337 rtwn_setbits_1(sc, R92C_RSV_CTRL + 1, 0x01, 0); 338 339 rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, 340 R92C_SYS_FUNC_EN_CPUEN, 0, 1); 341 342 /* Enable MCU IO wrapper. */ 343 rtwn_setbits_1(sc, R92C_RSV_CTRL + 1, 0, 0x01); 344 #endif 345 346 /* Move card to Disabled state. */ 347 /* Turn off RF. */ 348 rtwn_write_1(sc, R92C_RF_CTRL, 0); 349 350 /* Switch DPDT_SEL_P output. */ 351 rtwn_setbits_1(sc, R92C_LEDCFG2, 0x80, 0); 352 353 /* Turn off MAC by HW state machine */ 354 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_OFF, 355 1); 356 357 for (ntries = 0; ntries < 5000; ntries++) { 358 /* Wait until it will be disabled. */ 359 if ((rtwn_read_2(sc, R92C_APS_FSMCO) & 360 R92C_APS_FSMCO_APFM_OFF) == 0) 361 break; 362 363 rtwn_delay(sc, 10); 364 } 365 if (ntries == 5000) { 366 device_printf(sc->sc_dev, "%s: could not turn off MAC\n", 367 __func__); 368 return; 369 } 370 371 /* SOP option to disable BG/MB. */ 372 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff, 373 R92C_APS_FSMCO_SOP_RCK, 3); 374 375 /* Unlock small LDO Register. */ 376 rtwn_setbits_1(sc, 0xcc, 0, 0x4); 377 378 /* Disable small LDO. */ 379 rtwn_setbits_1(sc, R92C_SPS0_CTRL, 0x1, 0); 380 381 /* Enable WL suspend. */ 382 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_AFSM_PCIE, 383 R92C_APS_FSMCO_AFSM_HSUS, 1); 384 385 /* Enable SW LPS. */ 386 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, 387 R92C_APS_FSMCO_APFM_RSM, 1); 388 } 389