1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/callout.h> 33 #include <sys/conf.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/resource.h> 39 #include <sys/rman.h> 40 #include <sys/sysctl.h> 41 #include <sys/taskqueue.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <machine/stdarg.h> 46 47 #include <dev/mmc/bridge.h> 48 #include <dev/mmc/mmcreg.h> 49 #include <dev/mmc/mmcbrvar.h> 50 51 #include <cam/cam.h> 52 #include <cam/cam_ccb.h> 53 #include <cam/cam_debug.h> 54 #include <cam/cam_sim.h> 55 #include <cam/cam_xpt_sim.h> 56 57 #include "mmcbr_if.h" 58 #include "sdhci.h" 59 #include "sdhci_if.h" 60 61 #include "opt_mmccam.h" 62 63 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 64 65 static int sdhci_debug = 0; 66 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, 67 "Debug level"); 68 u_int sdhci_quirk_clear = 0; 69 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_clear, CTLFLAG_RWTUN, &sdhci_quirk_clear, 70 0, "Mask of quirks to clear"); 71 u_int sdhci_quirk_set = 0; 72 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_set, CTLFLAG_RWTUN, &sdhci_quirk_set, 0, 73 "Mask of quirks to set"); 74 75 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 76 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 77 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 78 #define RD_MULTI_4(slot, off, ptr, count) \ 79 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 80 81 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 82 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 83 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 84 #define WR_MULTI_4(slot, off, ptr, count) \ 85 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 86 87 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 88 static void sdhci_start(struct sdhci_slot *slot); 89 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 90 91 static void sdhci_card_poll(void *); 92 static void sdhci_card_task(void *, int); 93 94 #ifdef MMCCAM 95 /* CAM-related */ 96 int sdhci_cam_get_possible_host_clock(struct sdhci_slot *slot, int proposed_clock); 97 static int sdhci_cam_update_ios(struct sdhci_slot *slot); 98 static int sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb); 99 static void sdhci_cam_action(struct cam_sim *sim, union ccb *ccb); 100 static void sdhci_cam_poll(struct cam_sim *sim); 101 static int sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb); 102 #endif 103 104 /* helper routines */ 105 static void sdhci_dumpregs(struct sdhci_slot *slot); 106 static int slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 107 __printflike(2, 3); 108 109 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 110 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 111 #define SDHCI_LOCK_INIT(_slot) \ 112 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 113 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 114 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 115 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 116 117 #define SDHCI_DEFAULT_MAX_FREQ 50 118 119 #define SDHCI_200_MAX_DIVIDER 256 120 #define SDHCI_300_MAX_DIVIDER 2046 121 122 #define SDHCI_CARD_PRESENT_TICKS (hz / 5) 123 #define SDHCI_INSERT_DELAY_TICKS (hz / 2) 124 125 /* 126 * Broadcom BCM577xx Controller Constants 127 */ 128 /* Maximum divider supported by the default clock source. */ 129 #define BCM577XX_DEFAULT_MAX_DIVIDER 256 130 /* Alternative clock's base frequency. */ 131 #define BCM577XX_ALT_CLOCK_BASE 63000000 132 133 #define BCM577XX_HOST_CONTROL 0x198 134 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF 135 #define BCM577XX_CTRL_CLKSEL_SHIFT 12 136 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0 137 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3 138 139 static void 140 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 141 { 142 143 if (error != 0) { 144 printf("getaddr: error %d\n", error); 145 return; 146 } 147 *(bus_addr_t *)arg = segs[0].ds_addr; 148 } 149 150 static int 151 slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 152 { 153 va_list ap; 154 int retval; 155 156 retval = printf("%s-slot%d: ", 157 device_get_nameunit(slot->bus), slot->num); 158 159 va_start(ap, fmt); 160 retval += vprintf(fmt, ap); 161 va_end(ap); 162 return (retval); 163 } 164 165 static void 166 sdhci_dumpregs(struct sdhci_slot *slot) 167 { 168 169 slot_printf(slot, 170 "============== REGISTER DUMP ==============\n"); 171 172 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 173 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 174 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 175 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 176 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 177 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 178 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 179 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 180 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 181 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 182 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 183 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 184 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 185 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 186 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 187 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 188 slot_printf(slot, "AC12 err: 0x%08x | Host ctl2: 0x%08x\n", 189 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2)); 190 slot_printf(slot, "Caps: 0x%08x | Caps2: 0x%08x\n", 191 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2)); 192 slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n", 193 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR)); 194 slot_printf(slot, "ADMA addr: 0x%08x | Slot int: 0x%08x\n", 195 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS)); 196 197 slot_printf(slot, 198 "===========================================\n"); 199 } 200 201 static void 202 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 203 { 204 int timeout; 205 uint32_t clock; 206 207 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 208 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot)) 209 return; 210 } 211 212 /* Some controllers need this kick or reset won't work. */ 213 if ((mask & SDHCI_RESET_ALL) == 0 && 214 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 215 /* This is to force an update */ 216 clock = slot->clock; 217 slot->clock = 0; 218 sdhci_set_clock(slot, clock); 219 } 220 221 if (mask & SDHCI_RESET_ALL) { 222 slot->clock = 0; 223 slot->power = 0; 224 } 225 226 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 227 228 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) { 229 /* 230 * Resets on TI OMAPs and AM335x are incompatible with SDHCI 231 * specification. The reset bit has internal propagation delay, 232 * so a fast read after write returns 0 even if reset process is 233 * in progress. The workaround is to poll for 1 before polling 234 * for 0. In the worst case, if we miss seeing it asserted the 235 * time we spent waiting is enough to ensure the reset finishes. 236 */ 237 timeout = 10000; 238 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) { 239 if (timeout <= 0) 240 break; 241 timeout--; 242 DELAY(1); 243 } 244 } 245 246 /* Wait max 100 ms */ 247 timeout = 10000; 248 /* Controller clears the bits when it's done */ 249 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) { 250 if (timeout <= 0) { 251 slot_printf(slot, "Reset 0x%x never completed.\n", 252 mask); 253 sdhci_dumpregs(slot); 254 return; 255 } 256 timeout--; 257 DELAY(10); 258 } 259 } 260 261 static void 262 sdhci_init(struct sdhci_slot *slot) 263 { 264 265 sdhci_reset(slot, SDHCI_RESET_ALL); 266 267 /* Enable interrupts. */ 268 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 269 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 270 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 271 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 272 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 273 SDHCI_INT_ACMD12ERR; 274 275 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 276 !(slot->opt & SDHCI_NON_REMOVABLE)) { 277 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; 278 } 279 280 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 281 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 282 } 283 284 static void 285 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 286 { 287 uint32_t clk_base; 288 uint32_t clk_sel; 289 uint32_t res; 290 uint16_t clk; 291 uint16_t div; 292 int timeout; 293 294 if (clock == slot->clock) 295 return; 296 slot->clock = clock; 297 298 /* Turn off the clock. */ 299 clk = RD2(slot, SDHCI_CLOCK_CONTROL); 300 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); 301 /* If no clock requested - leave it so. */ 302 if (clock == 0) 303 return; 304 305 /* Determine the clock base frequency */ 306 clk_base = slot->max_clk; 307 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) { 308 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & 309 BCM577XX_CTRL_CLKSEL_MASK; 310 311 /* 312 * Select clock source appropriate for the requested frequency. 313 */ 314 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) { 315 clk_base = BCM577XX_ALT_CLOCK_BASE; 316 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << 317 BCM577XX_CTRL_CLKSEL_SHIFT); 318 } else { 319 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << 320 BCM577XX_CTRL_CLKSEL_SHIFT); 321 } 322 323 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); 324 } 325 326 /* Recalculate timeout clock frequency based on the new sd clock. */ 327 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 328 slot->timeout_clk = slot->clock / 1000; 329 330 if (slot->version < SDHCI_SPEC_300) { 331 /* Looking for highest freq <= clock. */ 332 res = clk_base; 333 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 334 if (res <= clock) 335 break; 336 res >>= 1; 337 } 338 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 339 div >>= 1; 340 } else { 341 /* Version 3.0 divisors are multiples of two up to 1023 * 2 */ 342 if (clock >= clk_base) 343 div = 0; 344 else { 345 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 346 if ((clk_base / div) <= clock) 347 break; 348 } 349 } 350 div >>= 1; 351 } 352 353 if (bootverbose || sdhci_debug) 354 slot_printf(slot, "Divider %d for freq %d (base %d)\n", 355 div, clock, clk_base); 356 357 /* Now we have got divider, set it. */ 358 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 359 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 360 << SDHCI_DIVIDER_HI_SHIFT; 361 362 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 363 /* Enable clock. */ 364 clk |= SDHCI_CLOCK_INT_EN; 365 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 366 /* Wait up to 10 ms until it stabilize. */ 367 timeout = 10; 368 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 369 & SDHCI_CLOCK_INT_STABLE)) { 370 if (timeout == 0) { 371 slot_printf(slot, 372 "Internal clock never stabilised.\n"); 373 sdhci_dumpregs(slot); 374 return; 375 } 376 timeout--; 377 DELAY(1000); 378 } 379 /* Pass clock signal to the bus. */ 380 clk |= SDHCI_CLOCK_CARD_EN; 381 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 382 } 383 384 static void 385 sdhci_set_power(struct sdhci_slot *slot, u_char power) 386 { 387 int i; 388 uint8_t pwr; 389 390 if (slot->power == power) 391 return; 392 393 slot->power = power; 394 395 /* Turn off the power. */ 396 pwr = 0; 397 WR1(slot, SDHCI_POWER_CONTROL, pwr); 398 /* If power down requested - leave it so. */ 399 if (power == 0) 400 return; 401 /* Set voltage. */ 402 switch (1 << power) { 403 case MMC_OCR_LOW_VOLTAGE: 404 pwr |= SDHCI_POWER_180; 405 break; 406 case MMC_OCR_290_300: 407 case MMC_OCR_300_310: 408 pwr |= SDHCI_POWER_300; 409 break; 410 case MMC_OCR_320_330: 411 case MMC_OCR_330_340: 412 pwr |= SDHCI_POWER_330; 413 break; 414 } 415 WR1(slot, SDHCI_POWER_CONTROL, pwr); 416 /* 417 * Turn on VDD1 power. Note that at least some Intel controllers can 418 * fail to enable bus power on the first try after transiting from D3 419 * to D0, so we give them up to 2 ms. 420 */ 421 pwr |= SDHCI_POWER_ON; 422 for (i = 0; i < 20; i++) { 423 WR1(slot, SDHCI_POWER_CONTROL, pwr); 424 if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON) 425 break; 426 DELAY(100); 427 } 428 if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)) 429 slot_printf(slot, "Bus power failed to enable"); 430 431 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) { 432 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10); 433 DELAY(10); 434 WR1(slot, SDHCI_POWER_CONTROL, pwr); 435 DELAY(300); 436 } 437 } 438 439 static void 440 sdhci_read_block_pio(struct sdhci_slot *slot) 441 { 442 uint32_t data; 443 char *buffer; 444 size_t left; 445 446 buffer = slot->curcmd->data->data; 447 buffer += slot->offset; 448 /* Transfer one block at a time. */ 449 left = min(512, slot->curcmd->data->len - slot->offset); 450 slot->offset += left; 451 452 /* If we are too fast, broken controllers return zeroes. */ 453 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 454 DELAY(10); 455 /* Handle unaligned and aligned buffer cases. */ 456 if ((intptr_t)buffer & 3) { 457 while (left > 3) { 458 data = RD4(slot, SDHCI_BUFFER); 459 buffer[0] = data; 460 buffer[1] = (data >> 8); 461 buffer[2] = (data >> 16); 462 buffer[3] = (data >> 24); 463 buffer += 4; 464 left -= 4; 465 } 466 } else { 467 RD_MULTI_4(slot, SDHCI_BUFFER, 468 (uint32_t *)buffer, left >> 2); 469 left &= 3; 470 } 471 /* Handle uneven size case. */ 472 if (left > 0) { 473 data = RD4(slot, SDHCI_BUFFER); 474 while (left > 0) { 475 *(buffer++) = data; 476 data >>= 8; 477 left--; 478 } 479 } 480 } 481 482 static void 483 sdhci_write_block_pio(struct sdhci_slot *slot) 484 { 485 uint32_t data = 0; 486 char *buffer; 487 size_t left; 488 489 buffer = slot->curcmd->data->data; 490 buffer += slot->offset; 491 /* Transfer one block at a time. */ 492 left = min(512, slot->curcmd->data->len - slot->offset); 493 slot->offset += left; 494 495 /* Handle unaligned and aligned buffer cases. */ 496 if ((intptr_t)buffer & 3) { 497 while (left > 3) { 498 data = buffer[0] + 499 (buffer[1] << 8) + 500 (buffer[2] << 16) + 501 (buffer[3] << 24); 502 left -= 4; 503 buffer += 4; 504 WR4(slot, SDHCI_BUFFER, data); 505 } 506 } else { 507 WR_MULTI_4(slot, SDHCI_BUFFER, 508 (uint32_t *)buffer, left >> 2); 509 left &= 3; 510 } 511 /* Handle uneven size case. */ 512 if (left > 0) { 513 while (left > 0) { 514 data <<= 8; 515 data += *(buffer++); 516 left--; 517 } 518 WR4(slot, SDHCI_BUFFER, data); 519 } 520 } 521 522 static void 523 sdhci_transfer_pio(struct sdhci_slot *slot) 524 { 525 526 /* Read as many blocks as possible. */ 527 if (slot->curcmd->data->flags & MMC_DATA_READ) { 528 while (RD4(slot, SDHCI_PRESENT_STATE) & 529 SDHCI_DATA_AVAILABLE) { 530 sdhci_read_block_pio(slot); 531 if (slot->offset >= slot->curcmd->data->len) 532 break; 533 } 534 } else { 535 while (RD4(slot, SDHCI_PRESENT_STATE) & 536 SDHCI_SPACE_AVAILABLE) { 537 sdhci_write_block_pio(slot); 538 if (slot->offset >= slot->curcmd->data->len) 539 break; 540 } 541 } 542 } 543 544 static void 545 sdhci_card_task(void *arg, int pending __unused) 546 { 547 struct sdhci_slot *slot = arg; 548 device_t d; 549 550 SDHCI_LOCK(slot); 551 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) { 552 #ifdef MMCCAM 553 if (slot->card_present == 0) { 554 #else 555 if (slot->dev == NULL) { 556 #endif 557 /* If card is present - attach mmc bus. */ 558 if (bootverbose || sdhci_debug) 559 slot_printf(slot, "Card inserted\n"); 560 #ifdef MMCCAM 561 slot->card_present = 1; 562 union ccb *ccb; 563 uint32_t pathid; 564 pathid = cam_sim_path(slot->sim); 565 ccb = xpt_alloc_ccb_nowait(); 566 if (ccb == NULL) { 567 slot_printf(slot, "Unable to alloc CCB for rescan\n"); 568 SDHCI_UNLOCK(slot); 569 return; 570 } 571 572 /* 573 * We create a rescan request for BUS:0:0, since the card 574 * will be at lun 0. 575 */ 576 if (xpt_create_path(&ccb->ccb_h.path, NULL, pathid, 577 /* target */ 0, /* lun */ 0) != CAM_REQ_CMP) { 578 slot_printf(slot, "Unable to create path for rescan\n"); 579 SDHCI_UNLOCK(slot); 580 xpt_free_ccb(ccb); 581 return; 582 } 583 SDHCI_UNLOCK(slot); 584 xpt_rescan(ccb); 585 #else 586 slot->dev = device_add_child(slot->bus, "mmc", -1); 587 device_set_ivars(slot->dev, slot); 588 SDHCI_UNLOCK(slot); 589 device_probe_and_attach(slot->dev); 590 #endif 591 } else 592 SDHCI_UNLOCK(slot); 593 } else { 594 #ifdef MMCCAM 595 if (slot->card_present == 1) { 596 #else 597 if (slot->dev != NULL) { 598 #endif 599 /* If no card present - detach mmc bus. */ 600 if (bootverbose || sdhci_debug) 601 slot_printf(slot, "Card removed\n"); 602 d = slot->dev; 603 slot->dev = NULL; 604 #ifdef MMCCAM 605 slot->card_present = 0; 606 union ccb *ccb; 607 uint32_t pathid; 608 pathid = cam_sim_path(slot->sim); 609 ccb = xpt_alloc_ccb_nowait(); 610 if (ccb == NULL) { 611 slot_printf(slot, "Unable to alloc CCB for rescan\n"); 612 SDHCI_UNLOCK(slot); 613 return; 614 } 615 616 /* 617 * We create a rescan request for BUS:0:0, since the card 618 * will be at lun 0. 619 */ 620 if (xpt_create_path(&ccb->ccb_h.path, NULL, pathid, 621 /* target */ 0, /* lun */ 0) != CAM_REQ_CMP) { 622 slot_printf(slot, "Unable to create path for rescan\n"); 623 SDHCI_UNLOCK(slot); 624 xpt_free_ccb(ccb); 625 return; 626 } 627 SDHCI_UNLOCK(slot); 628 xpt_rescan(ccb); 629 #else 630 SDHCI_UNLOCK(slot); 631 device_delete_child(slot->bus, d); 632 #endif 633 } else 634 SDHCI_UNLOCK(slot); 635 } 636 } 637 638 static void 639 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present) 640 { 641 bool was_present; 642 643 /* 644 * If there was no card and now there is one, schedule the task to 645 * create the child device after a short delay. The delay is to 646 * debounce the card insert (sometimes the card detect pin stabilizes 647 * before the other pins have made good contact). 648 * 649 * If there was a card present and now it's gone, immediately schedule 650 * the task to delete the child device. No debouncing -- gone is gone, 651 * because once power is removed, a full card re-init is needed, and 652 * that happens by deleting and recreating the child device. 653 */ 654 #ifdef MMCCAM 655 was_present = slot->card_present; 656 #else 657 was_present = slot->dev != NULL; 658 #endif 659 if (!was_present && is_present) { 660 taskqueue_enqueue_timeout(taskqueue_swi_giant, 661 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS); 662 } else if (was_present && !is_present) { 663 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 664 } 665 } 666 667 void 668 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present) 669 { 670 671 SDHCI_LOCK(slot); 672 sdhci_handle_card_present_locked(slot, is_present); 673 SDHCI_UNLOCK(slot); 674 } 675 676 static void 677 sdhci_card_poll(void *arg) 678 { 679 struct sdhci_slot *slot = arg; 680 681 sdhci_handle_card_present(slot, 682 SDHCI_GET_CARD_PRESENT(slot->bus, slot)); 683 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS, 684 sdhci_card_poll, slot); 685 } 686 687 int 688 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 689 { 690 uint32_t caps, caps2, freq, host_caps; 691 int err; 692 693 SDHCI_LOCK_INIT(slot); 694 695 slot->num = num; 696 slot->bus = dev; 697 698 /* Allocate DMA tag. */ 699 err = bus_dma_tag_create(bus_get_dma_tag(dev), 700 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 701 BUS_SPACE_MAXADDR, NULL, NULL, 702 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 703 BUS_DMA_ALLOCNOW, NULL, NULL, 704 &slot->dmatag); 705 if (err != 0) { 706 device_printf(dev, "Can't create DMA tag\n"); 707 SDHCI_LOCK_DESTROY(slot); 708 return (err); 709 } 710 /* Allocate DMA memory. */ 711 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 712 BUS_DMA_NOWAIT, &slot->dmamap); 713 if (err != 0) { 714 device_printf(dev, "Can't alloc DMA memory\n"); 715 SDHCI_LOCK_DESTROY(slot); 716 return (err); 717 } 718 /* Map the memory. */ 719 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 720 (void *)slot->dmamem, DMA_BLOCK_SIZE, 721 sdhci_getaddr, &slot->paddr, 0); 722 if (err != 0 || slot->paddr == 0) { 723 device_printf(dev, "Can't load DMA memory\n"); 724 SDHCI_LOCK_DESTROY(slot); 725 if (err) 726 return (err); 727 else 728 return (EFAULT); 729 } 730 731 /* Initialize slot. */ 732 sdhci_init(slot); 733 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 734 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 735 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) { 736 caps = slot->caps; 737 caps2 = slot->caps2; 738 } else { 739 caps = RD4(slot, SDHCI_CAPABILITIES); 740 if (slot->version >= SDHCI_SPEC_300) 741 caps2 = RD4(slot, SDHCI_CAPABILITIES2); 742 else 743 caps2 = 0; 744 } 745 /* Calculate base clock frequency. */ 746 if (slot->version >= SDHCI_SPEC_300) 747 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 748 SDHCI_CLOCK_BASE_SHIFT; 749 else 750 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> 751 SDHCI_CLOCK_BASE_SHIFT; 752 if (freq != 0) 753 slot->max_clk = freq * 1000000; 754 /* 755 * If the frequency wasn't in the capabilities and the hardware driver 756 * hasn't already set max_clk we're probably not going to work right 757 * with an assumption, so complain about it. 758 */ 759 if (slot->max_clk == 0) { 760 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; 761 device_printf(dev, "Hardware doesn't specify base clock " 762 "frequency, using %dMHz as default.\n", 763 SDHCI_DEFAULT_MAX_FREQ); 764 } 765 /* Calculate/set timeout clock frequency. */ 766 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 767 slot->timeout_clk = slot->max_clk / 1000; 768 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) { 769 slot->timeout_clk = 1000; 770 } else { 771 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >> 772 SDHCI_TIMEOUT_CLK_SHIFT; 773 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 774 slot->timeout_clk *= 1000; 775 } 776 /* 777 * If the frequency wasn't in the capabilities and the hardware driver 778 * hasn't already set timeout_clk we'll probably work okay using the 779 * max timeout, but still mention it. 780 */ 781 if (slot->timeout_clk == 0) { 782 device_printf(dev, "Hardware doesn't specify timeout clock " 783 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 784 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 785 } 786 787 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 788 slot->host.f_max = slot->max_clk; 789 slot->host.host_ocr = 0; 790 if (caps & SDHCI_CAN_VDD_330) 791 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 792 if (caps & SDHCI_CAN_VDD_300) 793 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 794 if (caps & SDHCI_CAN_VDD_180) 795 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 796 if (slot->host.host_ocr == 0) { 797 device_printf(dev, "Hardware doesn't report any " 798 "support voltages.\n"); 799 } 800 host_caps = MMC_CAP_4_BIT_DATA; 801 if (caps & SDHCI_CAN_DO_8BITBUS) 802 host_caps |= MMC_CAP_8_BIT_DATA; 803 if (caps & SDHCI_CAN_DO_HISPD) 804 host_caps |= MMC_CAP_HSPEED; 805 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC) 806 host_caps |= MMC_CAP_BOOT_NOACC; 807 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY) 808 host_caps |= MMC_CAP_WAIT_WHILE_BUSY; 809 if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50)) 810 host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 811 if (caps2 & SDHCI_CAN_SDR104) { 812 host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 813 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200)) 814 host_caps |= MMC_CAP_MMC_HS200; 815 } else if (caps2 & SDHCI_CAN_SDR50) 816 host_caps |= MMC_CAP_UHS_SDR50; 817 if (caps2 & SDHCI_CAN_DDR50 && 818 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50)) 819 host_caps |= MMC_CAP_UHS_DDR50; 820 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52) 821 host_caps |= MMC_CAP_MMC_DDR52; 822 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 && 823 caps2 & SDHCI_CAN_MMC_HS400) 824 host_caps |= MMC_CAP_MMC_HS400; 825 host_caps |= MMC_CAP_SIGNALING_330; 826 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 827 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_DDR50 | 828 MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 | 829 MMC_CAP_MMC_HS400_180)) 830 host_caps |= MMC_CAP_SIGNALING_180; 831 if (caps2 & SDHCI_CAN_DRIVE_TYPE_A) 832 host_caps |= MMC_CAP_DRIVER_TYPE_A; 833 if (caps2 & SDHCI_CAN_DRIVE_TYPE_C) 834 host_caps |= MMC_CAP_DRIVER_TYPE_C; 835 if (caps2 & SDHCI_CAN_DRIVE_TYPE_D) 836 host_caps |= MMC_CAP_DRIVER_TYPE_D; 837 slot->host.caps = host_caps; 838 839 /* Decide if we have usable DMA. */ 840 if (caps & SDHCI_CAN_DO_DMA) 841 slot->opt |= SDHCI_HAVE_DMA; 842 843 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 844 slot->opt &= ~SDHCI_HAVE_DMA; 845 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 846 slot->opt |= SDHCI_HAVE_DMA; 847 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE) 848 slot->opt |= SDHCI_NON_REMOVABLE; 849 850 /* 851 * Use platform-provided transfer backend 852 * with PIO as a fallback mechanism 853 */ 854 if (slot->opt & SDHCI_PLATFORM_TRANSFER) 855 slot->opt &= ~SDHCI_HAVE_DMA; 856 857 if (bootverbose || sdhci_debug) { 858 slot_printf(slot, 859 "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s\n", 860 slot->max_clk / 1000000, 861 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 862 (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" : 863 ((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"), 864 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 865 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 866 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 867 (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "", 868 (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "", 869 (caps2 & SDHCI_CAN_DRIVE_TYPE_A) ? "A" : "", 870 (caps2 & SDHCI_CAN_DRIVE_TYPE_C) ? "C" : "", 871 (caps2 & SDHCI_CAN_DRIVE_TYPE_D) ? "D" : "", 872 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 873 if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | 874 MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) 875 slot_printf(slot, "eMMC:%s%s%s%s\n", 876 (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "", 877 (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "", 878 (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "", 879 ((host_caps & 880 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) == 881 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ? 882 " HS400ES" : ""); 883 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 884 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104)) 885 slot_printf(slot, "UHS-I:%s%s%s%s%s\n", 886 (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "", 887 (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "", 888 (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "", 889 (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "", 890 (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : ""); 891 sdhci_dumpregs(slot); 892 } 893 894 slot->timeout = 10; 895 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus), 896 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO, 897 "timeout", CTLFLAG_RW, &slot->timeout, 0, 898 "Maximum timeout for SDHCI transfers (in secs)"); 899 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 900 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0, 901 sdhci_card_task, slot); 902 callout_init(&slot->card_poll_callout, 1); 903 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0); 904 905 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 906 !(slot->opt & SDHCI_NON_REMOVABLE)) { 907 callout_reset(&slot->card_poll_callout, 908 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot); 909 } 910 911 return (0); 912 } 913 914 void 915 sdhci_start_slot(struct sdhci_slot *slot) 916 { 917 918 sdhci_card_task(slot, 0); 919 } 920 921 int 922 sdhci_cleanup_slot(struct sdhci_slot *slot) 923 { 924 device_t d; 925 926 callout_drain(&slot->timeout_callout); 927 callout_drain(&slot->card_poll_callout); 928 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 929 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task); 930 931 SDHCI_LOCK(slot); 932 d = slot->dev; 933 slot->dev = NULL; 934 SDHCI_UNLOCK(slot); 935 if (d != NULL) 936 device_delete_child(slot->bus, d); 937 938 SDHCI_LOCK(slot); 939 sdhci_reset(slot, SDHCI_RESET_ALL); 940 SDHCI_UNLOCK(slot); 941 bus_dmamap_unload(slot->dmatag, slot->dmamap); 942 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 943 bus_dma_tag_destroy(slot->dmatag); 944 945 SDHCI_LOCK_DESTROY(slot); 946 947 return (0); 948 } 949 950 int 951 sdhci_generic_suspend(struct sdhci_slot *slot) 952 { 953 954 sdhci_reset(slot, SDHCI_RESET_ALL); 955 956 return (0); 957 } 958 959 int 960 sdhci_generic_resume(struct sdhci_slot *slot) 961 { 962 963 sdhci_init(slot); 964 965 return (0); 966 } 967 968 uint32_t 969 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot) 970 { 971 972 if (slot->version >= SDHCI_SPEC_300) 973 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 974 else 975 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 976 } 977 978 bool 979 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot) 980 { 981 982 if (slot->opt & SDHCI_NON_REMOVABLE) 983 return true; 984 985 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 986 } 987 988 void 989 sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot) 990 { 991 struct mmc_ios *ios; 992 uint16_t hostctrl2; 993 994 if (slot->version < SDHCI_SPEC_300) 995 return; 996 997 ios = &slot->host.ios; 998 sdhci_set_clock(slot, 0); 999 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1000 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK; 1001 if (ios->timing == bus_timing_mmc_hs400 || 1002 ios->timing == bus_timing_mmc_hs400es) 1003 hostctrl2 |= SDHCI_CTRL2_MMC_HS400; 1004 else if (ios->clock > SD_SDR50_MAX) 1005 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104; 1006 else if (ios->clock > SD_SDR25_MAX) 1007 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50; 1008 else if (ios->clock > SD_SDR12_MAX) { 1009 if (ios->timing == bus_timing_uhs_ddr50 || 1010 ios->timing == bus_timing_mmc_ddr52) 1011 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50; 1012 else 1013 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25; 1014 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) 1015 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12; 1016 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1017 sdhci_set_clock(slot, ios->clock); 1018 } 1019 1020 int 1021 sdhci_generic_update_ios(device_t brdev, device_t reqdev) 1022 { 1023 struct sdhci_slot *slot = device_get_ivars(reqdev); 1024 struct mmc_ios *ios = &slot->host.ios; 1025 1026 SDHCI_LOCK(slot); 1027 /* Do full reset on bus power down to clear from any state. */ 1028 if (ios->power_mode == power_off) { 1029 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 1030 sdhci_init(slot); 1031 } 1032 /* Configure the bus. */ 1033 sdhci_set_clock(slot, ios->clock); 1034 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 1035 if (ios->bus_width == bus_width_8) { 1036 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 1037 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 1038 } else if (ios->bus_width == bus_width_4) { 1039 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 1040 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 1041 } else if (ios->bus_width == bus_width_1) { 1042 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 1043 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 1044 } else { 1045 panic("Invalid bus width: %d", ios->bus_width); 1046 } 1047 if (ios->clock > SD_SDR12_MAX && 1048 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 1049 slot->hostctrl |= SDHCI_CTRL_HISPD; 1050 else 1051 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 1052 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 1053 SDHCI_SET_UHS_TIMING(brdev, slot); 1054 /* Some controllers like reset after bus changes. */ 1055 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 1056 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1057 1058 SDHCI_UNLOCK(slot); 1059 return (0); 1060 } 1061 1062 int 1063 sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev) 1064 { 1065 struct sdhci_slot *slot = device_get_ivars(reqdev); 1066 enum mmc_vccq vccq; 1067 int err; 1068 uint16_t hostctrl2; 1069 1070 if (slot->version < SDHCI_SPEC_300) 1071 return (0); 1072 1073 err = 0; 1074 vccq = slot->host.ios.vccq; 1075 SDHCI_LOCK(slot); 1076 sdhci_set_clock(slot, 0); 1077 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1078 switch (vccq) { 1079 case vccq_330: 1080 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 1081 goto done; 1082 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE; 1083 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1084 DELAY(5000); 1085 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1086 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 1087 goto done; 1088 err = EAGAIN; 1089 break; 1090 case vccq_180: 1091 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) { 1092 err = EINVAL; 1093 goto done; 1094 } 1095 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 1096 goto done; 1097 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE; 1098 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1099 DELAY(5000); 1100 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1101 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 1102 goto done; 1103 err = EAGAIN; 1104 break; 1105 default: 1106 slot_printf(slot, 1107 "Attempt to set unsupported signaling voltage\n"); 1108 err = EINVAL; 1109 break; 1110 } 1111 done: 1112 sdhci_set_clock(slot, slot->host.ios.clock); 1113 SDHCI_UNLOCK(slot); 1114 return (err); 1115 } 1116 1117 #ifdef MMCCAM 1118 static void 1119 sdhci_req_done(struct sdhci_slot *slot) 1120 { 1121 union ccb *ccb; 1122 1123 if (sdhci_debug > 1) 1124 slot_printf(slot, "%s\n", __func__); 1125 if (slot->ccb != NULL && slot->curcmd != NULL) { 1126 callout_stop(&slot->timeout_callout); 1127 ccb = slot->ccb; 1128 slot->ccb = NULL; 1129 slot->curcmd = NULL; 1130 1131 /* Tell CAM the request is finished */ 1132 struct ccb_mmcio *mmcio; 1133 mmcio = &ccb->mmcio; 1134 1135 ccb->ccb_h.status = 1136 (mmcio->cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 1137 xpt_done(ccb); 1138 } 1139 } 1140 #else 1141 static void 1142 sdhci_req_done(struct sdhci_slot *slot) 1143 { 1144 struct mmc_request *req; 1145 1146 if (slot->req != NULL && slot->curcmd != NULL) { 1147 callout_stop(&slot->timeout_callout); 1148 req = slot->req; 1149 slot->req = NULL; 1150 slot->curcmd = NULL; 1151 req->done(req); 1152 } 1153 } 1154 #endif 1155 1156 static void 1157 sdhci_timeout(void *arg) 1158 { 1159 struct sdhci_slot *slot = arg; 1160 1161 if (slot->curcmd != NULL) { 1162 slot_printf(slot, " Controller timeout\n"); 1163 sdhci_dumpregs(slot); 1164 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1165 slot->curcmd->error = MMC_ERR_TIMEOUT; 1166 sdhci_req_done(slot); 1167 } else { 1168 slot_printf(slot, " Spurious timeout - no active command\n"); 1169 } 1170 } 1171 1172 static void 1173 sdhci_set_transfer_mode(struct sdhci_slot *slot, struct mmc_data *data) 1174 { 1175 uint16_t mode; 1176 1177 if (data == NULL) 1178 return; 1179 1180 mode = SDHCI_TRNS_BLK_CNT_EN; 1181 if (data->len > 512) 1182 mode |= SDHCI_TRNS_MULTI; 1183 if (data->flags & MMC_DATA_READ) 1184 mode |= SDHCI_TRNS_READ; 1185 #ifdef MMCCAM 1186 struct ccb_mmcio *mmcio; 1187 mmcio = &slot->ccb->mmcio; 1188 if (mmcio->stop.opcode == MMC_STOP_TRANSMISSION 1189 && !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) 1190 mode |= SDHCI_TRNS_ACMD12; 1191 #else 1192 if (slot->req->stop && !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) 1193 mode |= SDHCI_TRNS_ACMD12; 1194 #endif 1195 if (slot->flags & SDHCI_USE_DMA) 1196 mode |= SDHCI_TRNS_DMA; 1197 1198 WR2(slot, SDHCI_TRANSFER_MODE, mode); 1199 } 1200 1201 static void 1202 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 1203 { 1204 int flags, timeout; 1205 uint32_t mask; 1206 1207 slot->curcmd = cmd; 1208 slot->cmd_done = 0; 1209 1210 cmd->error = MMC_ERR_NONE; 1211 1212 /* This flags combination is not supported by controller. */ 1213 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1214 slot_printf(slot, "Unsupported response type!\n"); 1215 cmd->error = MMC_ERR_FAILED; 1216 sdhci_req_done(slot); 1217 return; 1218 } 1219 1220 /* 1221 * Do not issue command if there is no card, clock or power. 1222 * Controller will not detect timeout without clock active. 1223 */ 1224 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) || 1225 slot->power == 0 || 1226 slot->clock == 0) { 1227 slot_printf(slot, 1228 "Cannot issue a command (power=%d clock=%d)", 1229 slot->power, slot->clock); 1230 cmd->error = MMC_ERR_FAILED; 1231 sdhci_req_done(slot); 1232 return; 1233 } 1234 /* Always wait for free CMD bus. */ 1235 mask = SDHCI_CMD_INHIBIT; 1236 /* Wait for free DAT if we have data or busy signal. */ 1237 if (cmd->data != NULL || (cmd->flags & MMC_RSP_BUSY)) 1238 mask |= SDHCI_DAT_INHIBIT; 1239 /* We shouldn't wait for DAT for stop commands. */ 1240 #ifdef MMCCAM 1241 struct ccb_mmcio *mmcio = &slot->ccb->mmcio; 1242 if (cmd == &mmcio->stop) 1243 mask &= ~SDHCI_DAT_INHIBIT; 1244 #else 1245 if (cmd == slot->req->stop) 1246 mask &= ~SDHCI_DAT_INHIBIT; 1247 #endif 1248 /* 1249 * Wait for bus no more then 250 ms. Typically there will be no wait 1250 * here at all, but when writing a crash dump we may be bypassing the 1251 * host platform's interrupt handler, and in some cases that handler 1252 * may be working around hardware quirks such as not respecting r1b 1253 * busy indications. In those cases, this wait-loop serves the purpose 1254 * of waiting for the prior command and data transfers to be done, and 1255 * SD cards are allowed to take up to 250ms for write and erase ops. 1256 * (It's usually more like 20-30ms in the real world.) 1257 */ 1258 timeout = 250; 1259 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) { 1260 if (timeout == 0) { 1261 slot_printf(slot, "Controller never released " 1262 "inhibit bit(s).\n"); 1263 sdhci_dumpregs(slot); 1264 cmd->error = MMC_ERR_FAILED; 1265 sdhci_req_done(slot); 1266 return; 1267 } 1268 timeout--; 1269 DELAY(1000); 1270 } 1271 1272 /* Prepare command flags. */ 1273 if (!(cmd->flags & MMC_RSP_PRESENT)) 1274 flags = SDHCI_CMD_RESP_NONE; 1275 else if (cmd->flags & MMC_RSP_136) 1276 flags = SDHCI_CMD_RESP_LONG; 1277 else if (cmd->flags & MMC_RSP_BUSY) 1278 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1279 else 1280 flags = SDHCI_CMD_RESP_SHORT; 1281 if (cmd->flags & MMC_RSP_CRC) 1282 flags |= SDHCI_CMD_CRC; 1283 if (cmd->flags & MMC_RSP_OPCODE) 1284 flags |= SDHCI_CMD_INDEX; 1285 if (cmd->data != NULL) 1286 flags |= SDHCI_CMD_DATA; 1287 if (cmd->opcode == MMC_STOP_TRANSMISSION) 1288 flags |= SDHCI_CMD_TYPE_ABORT; 1289 /* Prepare data. */ 1290 sdhci_start_data(slot, cmd->data); 1291 /* 1292 * Interrupt aggregation: To reduce total number of interrupts 1293 * group response interrupt with data interrupt when possible. 1294 * If there going to be data interrupt, mask response one. 1295 */ 1296 if (slot->data_done == 0) { 1297 WR4(slot, SDHCI_SIGNAL_ENABLE, 1298 slot->intmask &= ~SDHCI_INT_RESPONSE); 1299 } 1300 /* Set command argument. */ 1301 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 1302 /* Set data transfer mode. */ 1303 sdhci_set_transfer_mode(slot, cmd->data); 1304 if (sdhci_debug > 1) 1305 slot_printf(slot, "Starting command!\n"); 1306 /* Start command. */ 1307 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 1308 /* Start timeout callout. */ 1309 callout_reset(&slot->timeout_callout, slot->timeout * hz, 1310 sdhci_timeout, slot); 1311 } 1312 1313 static void 1314 sdhci_finish_command(struct sdhci_slot *slot) 1315 { 1316 int i; 1317 uint32_t val; 1318 uint8_t extra; 1319 1320 if (sdhci_debug > 1) 1321 slot_printf(slot, "%s: called, err %d flags %d\n", 1322 __func__, slot->curcmd->error, slot->curcmd->flags); 1323 slot->cmd_done = 1; 1324 /* 1325 * Interrupt aggregation: Restore command interrupt. 1326 * Main restore point for the case when command interrupt 1327 * happened first. 1328 */ 1329 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 1330 /* In case of error - reset host and return. */ 1331 if (slot->curcmd->error) { 1332 sdhci_reset(slot, SDHCI_RESET_CMD); 1333 sdhci_reset(slot, SDHCI_RESET_DATA); 1334 sdhci_start(slot); 1335 return; 1336 } 1337 /* If command has response - fetch it. */ 1338 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 1339 if (slot->curcmd->flags & MMC_RSP_136) { 1340 /* CRC is stripped so we need one byte shift. */ 1341 extra = 0; 1342 for (i = 0; i < 4; i++) { 1343 val = RD4(slot, SDHCI_RESPONSE + i * 4); 1344 if (slot->quirks & 1345 SDHCI_QUIRK_DONT_SHIFT_RESPONSE) 1346 slot->curcmd->resp[3 - i] = val; 1347 else { 1348 slot->curcmd->resp[3 - i] = 1349 (val << 8) | extra; 1350 extra = val >> 24; 1351 } 1352 } 1353 } else 1354 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 1355 } 1356 if (sdhci_debug > 1) 1357 printf("Resp: %02x %02x %02x %02x\n", 1358 slot->curcmd->resp[0], slot->curcmd->resp[1], 1359 slot->curcmd->resp[2], slot->curcmd->resp[3]); 1360 1361 /* If data ready - finish. */ 1362 if (slot->data_done) 1363 sdhci_start(slot); 1364 } 1365 1366 static void 1367 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 1368 { 1369 uint32_t target_timeout, current_timeout; 1370 uint8_t div; 1371 1372 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1373 slot->data_done = 1; 1374 return; 1375 } 1376 1377 slot->data_done = 0; 1378 1379 /* Calculate and set data timeout.*/ 1380 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 1381 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 1382 div = 0xE; 1383 } else { 1384 target_timeout = 1000000; 1385 div = 0; 1386 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 1387 while (current_timeout < target_timeout && div < 0xE) { 1388 ++div; 1389 current_timeout <<= 1; 1390 } 1391 /* Compensate for an off-by-one error in the CaFe chip.*/ 1392 if (div < 0xE && 1393 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 1394 ++div; 1395 } 1396 } 1397 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 1398 1399 if (data == NULL) 1400 return; 1401 1402 /* Use DMA if possible. */ 1403 if ((slot->opt & SDHCI_HAVE_DMA)) 1404 slot->flags |= SDHCI_USE_DMA; 1405 /* If data is small, broken DMA may return zeroes instead of data, */ 1406 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 1407 (data->len <= 512)) 1408 slot->flags &= ~SDHCI_USE_DMA; 1409 /* Some controllers require even block sizes. */ 1410 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 1411 ((data->len) & 0x3)) 1412 slot->flags &= ~SDHCI_USE_DMA; 1413 /* Load DMA buffer. */ 1414 if (slot->flags & SDHCI_USE_DMA) { 1415 if (data->flags & MMC_DATA_READ) 1416 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1417 BUS_DMASYNC_PREREAD); 1418 else { 1419 memcpy(slot->dmamem, data->data, 1420 (data->len < DMA_BLOCK_SIZE) ? 1421 data->len : DMA_BLOCK_SIZE); 1422 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1423 BUS_DMASYNC_PREWRITE); 1424 } 1425 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1426 /* Interrupt aggregation: Mask border interrupt 1427 * for the last page and unmask else. */ 1428 if (data->len == DMA_BLOCK_SIZE) 1429 slot->intmask &= ~SDHCI_INT_DMA_END; 1430 else 1431 slot->intmask |= SDHCI_INT_DMA_END; 1432 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1433 } 1434 /* Current data offset for both PIO and DMA. */ 1435 slot->offset = 0; 1436 /* Set block size and request IRQ on 4K border. */ 1437 WR2(slot, SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, 1438 (data->len < 512) ? data->len : 512)); 1439 /* Set block count. */ 1440 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 1441 1442 if (sdhci_debug > 1) 1443 slot_printf(slot, "Block size: %02x, count %lu\n", 1444 (unsigned int)SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512) ? data->len : 512), 1445 (unsigned long)(data->len + 511) / 512); 1446 } 1447 1448 void 1449 sdhci_finish_data(struct sdhci_slot *slot) 1450 { 1451 struct mmc_data *data = slot->curcmd->data; 1452 size_t left; 1453 1454 /* Interrupt aggregation: Restore command interrupt. 1455 * Auxiliary restore point for the case when data interrupt 1456 * happened first. */ 1457 if (!slot->cmd_done) { 1458 WR4(slot, SDHCI_SIGNAL_ENABLE, 1459 slot->intmask |= SDHCI_INT_RESPONSE); 1460 } 1461 /* Unload rest of data from DMA buffer. */ 1462 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA) && 1463 slot->curcmd->data != NULL) { 1464 if (data->flags & MMC_DATA_READ) { 1465 left = data->len - slot->offset; 1466 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1467 BUS_DMASYNC_POSTREAD); 1468 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1469 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE); 1470 } else 1471 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1472 BUS_DMASYNC_POSTWRITE); 1473 } 1474 slot->data_done = 1; 1475 /* If there was error - reset the host. */ 1476 if (slot->curcmd->error) { 1477 sdhci_reset(slot, SDHCI_RESET_CMD); 1478 sdhci_reset(slot, SDHCI_RESET_DATA); 1479 sdhci_start(slot); 1480 return; 1481 } 1482 /* If we already have command response - finish. */ 1483 if (slot->cmd_done) 1484 sdhci_start(slot); 1485 } 1486 1487 #ifdef MMCCAM 1488 static void 1489 sdhci_start(struct sdhci_slot *slot) 1490 { 1491 union ccb *ccb; 1492 1493 ccb = slot->ccb; 1494 if (ccb == NULL) 1495 return; 1496 1497 struct ccb_mmcio *mmcio; 1498 mmcio = &ccb->mmcio; 1499 1500 if (!(slot->flags & CMD_STARTED)) { 1501 slot->flags |= CMD_STARTED; 1502 sdhci_start_command(slot, &mmcio->cmd); 1503 return; 1504 } 1505 1506 /* 1507 * Old stack doesn't use this! 1508 * Enabling this code causes significant performance degradation 1509 * and IRQ storms on BBB, Wandboard behaves fine. 1510 * Not using this code does no harm... 1511 if (!(slot->flags & STOP_STARTED) && mmcio->stop.opcode != 0) { 1512 slot->flags |= STOP_STARTED; 1513 sdhci_start_command(slot, &mmcio->stop); 1514 return; 1515 } 1516 */ 1517 if (sdhci_debug > 1) 1518 slot_printf(slot, "result: %d\n", mmcio->cmd.error); 1519 if (mmcio->cmd.error == 0 && 1520 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 1521 sdhci_reset(slot, SDHCI_RESET_CMD); 1522 sdhci_reset(slot, SDHCI_RESET_DATA); 1523 } 1524 1525 sdhci_req_done(slot); 1526 } 1527 #else 1528 static void 1529 sdhci_start(struct sdhci_slot *slot) 1530 { 1531 struct mmc_request *req; 1532 1533 req = slot->req; 1534 if (req == NULL) 1535 return; 1536 1537 if (!(slot->flags & CMD_STARTED)) { 1538 slot->flags |= CMD_STARTED; 1539 sdhci_start_command(slot, req->cmd); 1540 return; 1541 } 1542 if ((slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP) && 1543 !(slot->flags & STOP_STARTED) && req->stop) { 1544 slot->flags |= STOP_STARTED; 1545 sdhci_start_command(slot, req->stop); 1546 return; 1547 } 1548 if (sdhci_debug > 1) 1549 slot_printf(slot, "result: %d\n", req->cmd->error); 1550 if (!req->cmd->error && 1551 ((slot->curcmd == req->stop && 1552 (slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) || 1553 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 1554 sdhci_reset(slot, SDHCI_RESET_CMD); 1555 sdhci_reset(slot, SDHCI_RESET_DATA); 1556 } 1557 1558 sdhci_req_done(slot); 1559 } 1560 #endif 1561 1562 int 1563 sdhci_generic_request(device_t brdev __unused, device_t reqdev, 1564 struct mmc_request *req) 1565 { 1566 struct sdhci_slot *slot = device_get_ivars(reqdev); 1567 1568 SDHCI_LOCK(slot); 1569 if (slot->req != NULL) { 1570 SDHCI_UNLOCK(slot); 1571 return (EBUSY); 1572 } 1573 if (sdhci_debug > 1) { 1574 slot_printf(slot, 1575 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1576 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1577 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1578 (req->cmd->data)?req->cmd->data->flags:0); 1579 } 1580 slot->req = req; 1581 slot->flags = 0; 1582 sdhci_start(slot); 1583 SDHCI_UNLOCK(slot); 1584 if (dumping) { 1585 while (slot->req != NULL) { 1586 sdhci_generic_intr(slot); 1587 DELAY(10); 1588 } 1589 } 1590 return (0); 1591 } 1592 1593 int 1594 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev) 1595 { 1596 struct sdhci_slot *slot = device_get_ivars(reqdev); 1597 uint32_t val; 1598 1599 SDHCI_LOCK(slot); 1600 val = RD4(slot, SDHCI_PRESENT_STATE); 1601 SDHCI_UNLOCK(slot); 1602 return (!(val & SDHCI_WRITE_PROTECT)); 1603 } 1604 1605 int 1606 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev) 1607 { 1608 struct sdhci_slot *slot = device_get_ivars(reqdev); 1609 int err = 0; 1610 1611 SDHCI_LOCK(slot); 1612 while (slot->bus_busy) 1613 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 1614 slot->bus_busy++; 1615 /* Activate led. */ 1616 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1617 SDHCI_UNLOCK(slot); 1618 return (err); 1619 } 1620 1621 int 1622 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev) 1623 { 1624 struct sdhci_slot *slot = device_get_ivars(reqdev); 1625 1626 SDHCI_LOCK(slot); 1627 /* Deactivate led. */ 1628 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1629 slot->bus_busy--; 1630 SDHCI_UNLOCK(slot); 1631 wakeup(slot); 1632 return (0); 1633 } 1634 1635 static void 1636 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1637 { 1638 1639 if (!slot->curcmd) { 1640 slot_printf(slot, "Got command interrupt 0x%08x, but " 1641 "there is no active command.\n", intmask); 1642 sdhci_dumpregs(slot); 1643 return; 1644 } 1645 if (intmask & SDHCI_INT_TIMEOUT) 1646 slot->curcmd->error = MMC_ERR_TIMEOUT; 1647 else if (intmask & SDHCI_INT_CRC) 1648 slot->curcmd->error = MMC_ERR_BADCRC; 1649 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1650 slot->curcmd->error = MMC_ERR_FIFO; 1651 1652 sdhci_finish_command(slot); 1653 } 1654 1655 static void 1656 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1657 { 1658 struct mmc_data *data; 1659 size_t left; 1660 1661 if (!slot->curcmd) { 1662 slot_printf(slot, "Got data interrupt 0x%08x, but " 1663 "there is no active command.\n", intmask); 1664 sdhci_dumpregs(slot); 1665 return; 1666 } 1667 if (slot->curcmd->data == NULL && 1668 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1669 slot_printf(slot, "Got data interrupt 0x%08x, but " 1670 "there is no active data operation.\n", 1671 intmask); 1672 sdhci_dumpregs(slot); 1673 return; 1674 } 1675 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1676 slot->curcmd->error = MMC_ERR_TIMEOUT; 1677 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1678 slot->curcmd->error = MMC_ERR_BADCRC; 1679 if (slot->curcmd->data == NULL && 1680 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1681 SDHCI_INT_DMA_END))) { 1682 slot_printf(slot, "Got data interrupt 0x%08x, but " 1683 "there is busy-only command.\n", intmask); 1684 sdhci_dumpregs(slot); 1685 slot->curcmd->error = MMC_ERR_INVALID; 1686 } 1687 if (slot->curcmd->error) { 1688 /* No need to continue after any error. */ 1689 goto done; 1690 } 1691 1692 /* Handle PIO interrupt. */ 1693 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 1694 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 1695 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 1696 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, 1697 &intmask); 1698 slot->flags |= PLATFORM_DATA_STARTED; 1699 } else 1700 sdhci_transfer_pio(slot); 1701 } 1702 /* Handle DMA border. */ 1703 if (intmask & SDHCI_INT_DMA_END) { 1704 data = slot->curcmd->data; 1705 1706 /* Unload DMA buffer ... */ 1707 left = data->len - slot->offset; 1708 if (data->flags & MMC_DATA_READ) { 1709 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1710 BUS_DMASYNC_POSTREAD); 1711 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1712 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE); 1713 } else { 1714 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1715 BUS_DMASYNC_POSTWRITE); 1716 } 1717 /* ... and reload it again. */ 1718 slot->offset += DMA_BLOCK_SIZE; 1719 left = data->len - slot->offset; 1720 if (data->flags & MMC_DATA_READ) { 1721 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1722 BUS_DMASYNC_PREREAD); 1723 } else { 1724 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1725 (left < DMA_BLOCK_SIZE)? left : DMA_BLOCK_SIZE); 1726 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1727 BUS_DMASYNC_PREWRITE); 1728 } 1729 /* Interrupt aggregation: Mask border interrupt 1730 * for the last page. */ 1731 if (left == DMA_BLOCK_SIZE) { 1732 slot->intmask &= ~SDHCI_INT_DMA_END; 1733 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1734 } 1735 /* Restart DMA. */ 1736 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1737 } 1738 /* We have got all data. */ 1739 if (intmask & SDHCI_INT_DATA_END) { 1740 if (slot->flags & PLATFORM_DATA_STARTED) { 1741 slot->flags &= ~PLATFORM_DATA_STARTED; 1742 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1743 } else 1744 sdhci_finish_data(slot); 1745 } 1746 done: 1747 if (slot->curcmd != NULL && slot->curcmd->error != 0) { 1748 if (slot->flags & PLATFORM_DATA_STARTED) { 1749 slot->flags &= ~PLATFORM_DATA_STARTED; 1750 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1751 } else 1752 sdhci_finish_data(slot); 1753 } 1754 } 1755 1756 static void 1757 sdhci_acmd_irq(struct sdhci_slot *slot) 1758 { 1759 uint16_t err; 1760 1761 err = RD4(slot, SDHCI_ACMD12_ERR); 1762 if (!slot->curcmd) { 1763 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1764 "there is no active command.\n", err); 1765 sdhci_dumpregs(slot); 1766 return; 1767 } 1768 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1769 sdhci_reset(slot, SDHCI_RESET_CMD); 1770 } 1771 1772 void 1773 sdhci_generic_intr(struct sdhci_slot *slot) 1774 { 1775 uint32_t intmask, present; 1776 1777 SDHCI_LOCK(slot); 1778 /* Read slot interrupt status. */ 1779 intmask = RD4(slot, SDHCI_INT_STATUS); 1780 if (intmask == 0 || intmask == 0xffffffff) { 1781 SDHCI_UNLOCK(slot); 1782 return; 1783 } 1784 if (sdhci_debug > 2) 1785 slot_printf(slot, "Interrupt %#x\n", intmask); 1786 1787 /* Handle card presence interrupts. */ 1788 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1789 present = (intmask & SDHCI_INT_CARD_INSERT) != 0; 1790 slot->intmask &= 1791 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1792 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE : 1793 SDHCI_INT_CARD_INSERT; 1794 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 1795 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1796 WR4(slot, SDHCI_INT_STATUS, intmask & 1797 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1798 sdhci_handle_card_present_locked(slot, present); 1799 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1800 } 1801 /* Handle command interrupts. */ 1802 if (intmask & SDHCI_INT_CMD_MASK) { 1803 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1804 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1805 } 1806 /* Handle data interrupts. */ 1807 if (intmask & SDHCI_INT_DATA_MASK) { 1808 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1809 /* Don't call data_irq in case of errored command. */ 1810 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0) 1811 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1812 } 1813 /* Handle AutoCMD12 error interrupt. */ 1814 if (intmask & SDHCI_INT_ACMD12ERR) { 1815 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1816 sdhci_acmd_irq(slot); 1817 } 1818 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1819 intmask &= ~SDHCI_INT_ACMD12ERR; 1820 intmask &= ~SDHCI_INT_ERROR; 1821 /* Handle bus power interrupt. */ 1822 if (intmask & SDHCI_INT_BUS_POWER) { 1823 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1824 slot_printf(slot, 1825 "Card is consuming too much power!\n"); 1826 intmask &= ~SDHCI_INT_BUS_POWER; 1827 } 1828 1829 /* The rest is unknown. */ 1830 if (intmask) { 1831 WR4(slot, SDHCI_INT_STATUS, intmask); 1832 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1833 intmask); 1834 sdhci_dumpregs(slot); 1835 } 1836 1837 SDHCI_UNLOCK(slot); 1838 } 1839 1840 int 1841 sdhci_generic_read_ivar(device_t bus, device_t child, int which, 1842 uintptr_t *result) 1843 { 1844 struct sdhci_slot *slot = device_get_ivars(child); 1845 1846 switch (which) { 1847 default: 1848 return (EINVAL); 1849 case MMCBR_IVAR_BUS_MODE: 1850 *result = slot->host.ios.bus_mode; 1851 break; 1852 case MMCBR_IVAR_BUS_WIDTH: 1853 *result = slot->host.ios.bus_width; 1854 break; 1855 case MMCBR_IVAR_CHIP_SELECT: 1856 *result = slot->host.ios.chip_select; 1857 break; 1858 case MMCBR_IVAR_CLOCK: 1859 *result = slot->host.ios.clock; 1860 break; 1861 case MMCBR_IVAR_F_MIN: 1862 *result = slot->host.f_min; 1863 break; 1864 case MMCBR_IVAR_F_MAX: 1865 *result = slot->host.f_max; 1866 break; 1867 case MMCBR_IVAR_HOST_OCR: 1868 *result = slot->host.host_ocr; 1869 break; 1870 case MMCBR_IVAR_MODE: 1871 *result = slot->host.mode; 1872 break; 1873 case MMCBR_IVAR_OCR: 1874 *result = slot->host.ocr; 1875 break; 1876 case MMCBR_IVAR_POWER_MODE: 1877 *result = slot->host.ios.power_mode; 1878 break; 1879 case MMCBR_IVAR_VDD: 1880 *result = slot->host.ios.vdd; 1881 break; 1882 case MMCBR_IVAR_VCCQ: 1883 *result = slot->host.ios.vccq; 1884 break; 1885 case MMCBR_IVAR_CAPS: 1886 *result = slot->host.caps; 1887 break; 1888 case MMCBR_IVAR_TIMING: 1889 *result = slot->host.ios.timing; 1890 break; 1891 case MMCBR_IVAR_MAX_DATA: 1892 *result = 65535; 1893 break; 1894 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: 1895 /* 1896 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs. 1897 */ 1898 *result = 1000000; 1899 break; 1900 } 1901 return (0); 1902 } 1903 1904 int 1905 sdhci_generic_write_ivar(device_t bus, device_t child, int which, 1906 uintptr_t value) 1907 { 1908 struct sdhci_slot *slot = device_get_ivars(child); 1909 uint32_t clock, max_clock; 1910 int i; 1911 1912 if (sdhci_debug > 1) 1913 slot_printf(slot, "%s: var=%d\n", __func__, which); 1914 switch (which) { 1915 default: 1916 return (EINVAL); 1917 case MMCBR_IVAR_BUS_MODE: 1918 slot->host.ios.bus_mode = value; 1919 break; 1920 case MMCBR_IVAR_BUS_WIDTH: 1921 slot->host.ios.bus_width = value; 1922 break; 1923 case MMCBR_IVAR_CHIP_SELECT: 1924 slot->host.ios.chip_select = value; 1925 break; 1926 case MMCBR_IVAR_CLOCK: 1927 if (value > 0) { 1928 max_clock = slot->max_clk; 1929 clock = max_clock; 1930 1931 if (slot->version < SDHCI_SPEC_300) { 1932 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 1933 i <<= 1) { 1934 if (clock <= value) 1935 break; 1936 clock >>= 1; 1937 } 1938 } else { 1939 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 1940 i += 2) { 1941 if (clock <= value) 1942 break; 1943 clock = max_clock / (i + 2); 1944 } 1945 } 1946 1947 slot->host.ios.clock = clock; 1948 } else 1949 slot->host.ios.clock = 0; 1950 break; 1951 case MMCBR_IVAR_MODE: 1952 slot->host.mode = value; 1953 break; 1954 case MMCBR_IVAR_OCR: 1955 slot->host.ocr = value; 1956 break; 1957 case MMCBR_IVAR_POWER_MODE: 1958 slot->host.ios.power_mode = value; 1959 break; 1960 case MMCBR_IVAR_VDD: 1961 slot->host.ios.vdd = value; 1962 break; 1963 case MMCBR_IVAR_VCCQ: 1964 slot->host.ios.vccq = value; 1965 break; 1966 case MMCBR_IVAR_TIMING: 1967 slot->host.ios.timing = value; 1968 break; 1969 case MMCBR_IVAR_CAPS: 1970 case MMCBR_IVAR_HOST_OCR: 1971 case MMCBR_IVAR_F_MIN: 1972 case MMCBR_IVAR_F_MAX: 1973 case MMCBR_IVAR_MAX_DATA: 1974 return (EINVAL); 1975 } 1976 return (0); 1977 } 1978 1979 #ifdef MMCCAM 1980 /* CAM-related functions */ 1981 #include <cam/cam.h> 1982 #include <cam/cam_ccb.h> 1983 #include <cam/cam_debug.h> 1984 #include <cam/cam_sim.h> 1985 #include <cam/cam_xpt_sim.h> 1986 1987 void 1988 sdhci_cam_start_slot(struct sdhci_slot *slot) 1989 { 1990 if ((slot->devq = cam_simq_alloc(1)) == NULL) { 1991 goto fail; 1992 } 1993 1994 mtx_init(&slot->sim_mtx, "sdhcisim", NULL, MTX_DEF); 1995 slot->sim = cam_sim_alloc(sdhci_cam_action, sdhci_cam_poll, 1996 "sdhci_slot", slot, device_get_unit(slot->bus), 1997 &slot->sim_mtx, 1, 1, slot->devq); 1998 1999 if (slot->sim == NULL) { 2000 cam_simq_free(slot->devq); 2001 slot_printf(slot, "cannot allocate CAM SIM\n"); 2002 goto fail; 2003 } 2004 2005 mtx_lock(&slot->sim_mtx); 2006 if (xpt_bus_register(slot->sim, slot->bus, 0) != 0) { 2007 slot_printf(slot, 2008 "cannot register SCSI pass-through bus\n"); 2009 cam_sim_free(slot->sim, FALSE); 2010 cam_simq_free(slot->devq); 2011 mtx_unlock(&slot->sim_mtx); 2012 goto fail; 2013 } 2014 2015 mtx_unlock(&slot->sim_mtx); 2016 /* End CAM-specific init */ 2017 slot->card_present = 0; 2018 sdhci_card_task(slot, 0); 2019 return; 2020 2021 fail: 2022 if (slot->sim != NULL) { 2023 mtx_lock(&slot->sim_mtx); 2024 xpt_bus_deregister(cam_sim_path(slot->sim)); 2025 cam_sim_free(slot->sim, FALSE); 2026 mtx_unlock(&slot->sim_mtx); 2027 } 2028 2029 if (slot->devq != NULL) 2030 cam_simq_free(slot->devq); 2031 } 2032 2033 static void 2034 sdhci_cam_handle_mmcio(struct cam_sim *sim, union ccb *ccb) 2035 { 2036 struct sdhci_slot *slot; 2037 2038 slot = cam_sim_softc(sim); 2039 2040 sdhci_cam_request(slot, ccb); 2041 } 2042 2043 void 2044 sdhci_cam_action(struct cam_sim *sim, union ccb *ccb) 2045 { 2046 struct sdhci_slot *slot; 2047 2048 slot = cam_sim_softc(sim); 2049 if (slot == NULL) { 2050 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2051 xpt_done(ccb); 2052 return; 2053 } 2054 2055 mtx_assert(&slot->sim_mtx, MA_OWNED); 2056 2057 switch (ccb->ccb_h.func_code) { 2058 case XPT_PATH_INQ: 2059 { 2060 struct ccb_pathinq *cpi; 2061 2062 cpi = &ccb->cpi; 2063 cpi->version_num = 1; 2064 cpi->hba_inquiry = 0; 2065 cpi->target_sprt = 0; 2066 cpi->hba_misc = PIM_NOBUSRESET | PIM_SEQSCAN; 2067 cpi->hba_eng_cnt = 0; 2068 cpi->max_target = 0; 2069 cpi->max_lun = 0; 2070 cpi->initiator_id = 1; 2071 cpi->maxio = MAXPHYS; 2072 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2073 strncpy(cpi->hba_vid, "Deglitch Networks", HBA_IDLEN); 2074 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2075 cpi->unit_number = cam_sim_unit(sim); 2076 cpi->bus_id = cam_sim_bus(sim); 2077 cpi->base_transfer_speed = 100; /* XXX WTF? */ 2078 cpi->protocol = PROTO_MMCSD; 2079 cpi->protocol_version = SCSI_REV_0; 2080 cpi->transport = XPORT_MMCSD; 2081 cpi->transport_version = 0; 2082 2083 cpi->ccb_h.status = CAM_REQ_CMP; 2084 break; 2085 } 2086 case XPT_GET_TRAN_SETTINGS: 2087 { 2088 struct ccb_trans_settings *cts = &ccb->cts; 2089 2090 if (sdhci_debug > 1) 2091 slot_printf(slot, "Got XPT_GET_TRAN_SETTINGS\n"); 2092 2093 cts->protocol = PROTO_MMCSD; 2094 cts->protocol_version = 1; 2095 cts->transport = XPORT_MMCSD; 2096 cts->transport_version = 1; 2097 cts->xport_specific.valid = 0; 2098 cts->proto_specific.mmc.host_ocr = slot->host.host_ocr; 2099 cts->proto_specific.mmc.host_f_min = slot->host.f_min; 2100 cts->proto_specific.mmc.host_f_max = slot->host.f_max; 2101 cts->proto_specific.mmc.host_caps = slot->host.caps; 2102 memcpy(&cts->proto_specific.mmc.ios, &slot->host.ios, sizeof(struct mmc_ios)); 2103 ccb->ccb_h.status = CAM_REQ_CMP; 2104 break; 2105 } 2106 case XPT_SET_TRAN_SETTINGS: 2107 { 2108 if (sdhci_debug > 1) 2109 slot_printf(slot, "Got XPT_SET_TRAN_SETTINGS\n"); 2110 sdhci_cam_settran_settings(slot, ccb); 2111 ccb->ccb_h.status = CAM_REQ_CMP; 2112 break; 2113 } 2114 case XPT_RESET_BUS: 2115 if (sdhci_debug > 1) 2116 slot_printf(slot, "Got XPT_RESET_BUS, ACK it...\n"); 2117 ccb->ccb_h.status = CAM_REQ_CMP; 2118 break; 2119 case XPT_MMC_IO: 2120 /* 2121 * Here is the HW-dependent part of 2122 * sending the command to the underlying h/w 2123 * At some point in the future an interrupt comes. 2124 * Then the request will be marked as completed. 2125 */ 2126 if (sdhci_debug > 1) 2127 slot_printf(slot, "Got XPT_MMC_IO\n"); 2128 ccb->ccb_h.status = CAM_REQ_INPROG; 2129 2130 sdhci_cam_handle_mmcio(sim, ccb); 2131 return; 2132 /* NOTREACHED */ 2133 break; 2134 default: 2135 ccb->ccb_h.status = CAM_REQ_INVALID; 2136 break; 2137 } 2138 xpt_done(ccb); 2139 return; 2140 } 2141 2142 void 2143 sdhci_cam_poll(struct cam_sim *sim) 2144 { 2145 return; 2146 } 2147 2148 int sdhci_cam_get_possible_host_clock(struct sdhci_slot *slot, int proposed_clock) { 2149 int max_clock, clock, i; 2150 2151 if (proposed_clock == 0) 2152 return 0; 2153 max_clock = slot->max_clk; 2154 clock = max_clock; 2155 2156 if (slot->version < SDHCI_SPEC_300) { 2157 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 2158 i <<= 1) { 2159 if (clock <= proposed_clock) 2160 break; 2161 clock >>= 1; 2162 } 2163 } else { 2164 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 2165 i += 2) { 2166 if (clock <= proposed_clock) 2167 break; 2168 clock = max_clock / (i + 2); 2169 } 2170 } 2171 return clock; 2172 } 2173 2174 int 2175 sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb) 2176 { 2177 struct mmc_ios *ios; 2178 struct mmc_ios *new_ios; 2179 struct ccb_trans_settings_mmc *cts; 2180 2181 ios = &slot->host.ios; 2182 2183 cts = &ccb->cts.proto_specific.mmc; 2184 new_ios = &cts->ios; 2185 2186 /* Update only requested fields */ 2187 if (cts->ios_valid & MMC_CLK) { 2188 ios->clock = sdhci_cam_get_possible_host_clock(slot, new_ios->clock); 2189 slot_printf(slot, "Clock => %d\n", ios->clock); 2190 } 2191 if (cts->ios_valid & MMC_VDD) { 2192 ios->vdd = new_ios->vdd; 2193 slot_printf(slot, "VDD => %d\n", ios->vdd); 2194 } 2195 if (cts->ios_valid & MMC_CS) { 2196 ios->chip_select = new_ios->chip_select; 2197 slot_printf(slot, "CS => %d\n", ios->chip_select); 2198 } 2199 if (cts->ios_valid & MMC_BW) { 2200 ios->bus_width = new_ios->bus_width; 2201 slot_printf(slot, "Bus width => %d\n", ios->bus_width); 2202 } 2203 if (cts->ios_valid & MMC_PM) { 2204 ios->power_mode = new_ios->power_mode; 2205 slot_printf(slot, "Power mode => %d\n", ios->power_mode); 2206 } 2207 if (cts->ios_valid & MMC_BT) { 2208 ios->timing = new_ios->timing; 2209 slot_printf(slot, "Timing => %d\n", ios->timing); 2210 } 2211 if (cts->ios_valid & MMC_BM) { 2212 ios->bus_mode = new_ios->bus_mode; 2213 slot_printf(slot, "Bus mode => %d\n", ios->bus_mode); 2214 } 2215 2216 /* XXX Provide a way to call a chip-specific IOS update, required for TI */ 2217 return (sdhci_cam_update_ios(slot)); 2218 } 2219 2220 int 2221 sdhci_cam_update_ios(struct sdhci_slot *slot) 2222 { 2223 struct mmc_ios *ios = &slot->host.ios; 2224 2225 slot_printf(slot, "%s: power_mode=%d, clk=%d, bus_width=%d, timing=%d\n", 2226 __func__, ios->power_mode, ios->clock, ios->bus_width, ios->timing); 2227 SDHCI_LOCK(slot); 2228 /* Do full reset on bus power down to clear from any state. */ 2229 if (ios->power_mode == power_off) { 2230 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 2231 sdhci_init(slot); 2232 } 2233 /* Configure the bus. */ 2234 sdhci_set_clock(slot, ios->clock); 2235 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 2236 if (ios->bus_width == bus_width_8) { 2237 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 2238 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 2239 } else if (ios->bus_width == bus_width_4) { 2240 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 2241 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 2242 } else if (ios->bus_width == bus_width_1) { 2243 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 2244 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 2245 } else { 2246 panic("Invalid bus width: %d", ios->bus_width); 2247 } 2248 if (ios->timing == bus_timing_hs && 2249 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 2250 slot->hostctrl |= SDHCI_CTRL_HISPD; 2251 else 2252 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 2253 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 2254 /* Some controllers like reset after bus changes. */ 2255 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 2256 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 2257 2258 SDHCI_UNLOCK(slot); 2259 return (0); 2260 } 2261 2262 int 2263 sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb) 2264 { 2265 struct ccb_mmcio *mmcio; 2266 2267 mmcio = &ccb->mmcio; 2268 2269 SDHCI_LOCK(slot); 2270 /* if (slot->req != NULL) { 2271 SDHCI_UNLOCK(slot); 2272 return (EBUSY); 2273 } 2274 */ 2275 if (sdhci_debug > 1) { 2276 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 2277 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags, 2278 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0, 2279 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0); 2280 } 2281 if (mmcio->cmd.data != NULL) { 2282 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0) 2283 panic("data->len = %d, data->flags = %d -- something is b0rked", 2284 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags); 2285 } 2286 slot->ccb = ccb; 2287 slot->flags = 0; 2288 sdhci_start(slot); 2289 SDHCI_UNLOCK(slot); 2290 if (dumping) { 2291 while (slot->ccb != NULL) { 2292 sdhci_generic_intr(slot); 2293 DELAY(10); 2294 } 2295 } 2296 return (0); 2297 } 2298 #endif /* MMCCAM */ 2299 2300 MODULE_VERSION(sdhci, 1); 2301