1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/callout.h> 33 #include <sys/conf.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/resource.h> 39 #include <sys/rman.h> 40 #include <sys/sysctl.h> 41 #include <sys/taskqueue.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <machine/stdarg.h> 46 47 #include <dev/mmc/bridge.h> 48 #include <dev/mmc/mmcreg.h> 49 #include <dev/mmc/mmcbrvar.h> 50 51 #include "mmcbr_if.h" 52 #include "sdhci.h" 53 #include "sdhci_if.h" 54 55 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 56 57 static int sdhci_debug; 58 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, 59 "Debug level"); 60 u_int sdhci_quirk_clear = 0; 61 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_clear, CTLFLAG_RWTUN, &sdhci_quirk_clear, 62 0, "Mask of quirks to clear"); 63 u_int sdhci_quirk_set = 0; 64 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_set, CTLFLAG_RWTUN, &sdhci_quirk_set, 0, 65 "Mask of quirks to set"); 66 67 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 68 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 69 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 70 #define RD_MULTI_4(slot, off, ptr, count) \ 71 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 72 73 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 74 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 75 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 76 #define WR_MULTI_4(slot, off, ptr, count) \ 77 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 78 79 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 80 static void sdhci_start(struct sdhci_slot *slot); 81 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 82 83 static void sdhci_card_poll(void *); 84 static void sdhci_card_task(void *, int); 85 86 /* helper routines */ 87 static void sdhci_dumpregs(struct sdhci_slot *slot); 88 static int slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 89 __printflike(2, 3); 90 91 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 92 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 93 #define SDHCI_LOCK_INIT(_slot) \ 94 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 95 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 96 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 97 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 98 99 #define SDHCI_DEFAULT_MAX_FREQ 50 100 101 #define SDHCI_200_MAX_DIVIDER 256 102 #define SDHCI_300_MAX_DIVIDER 2046 103 104 #define SDHCI_CARD_PRESENT_TICKS (hz / 5) 105 #define SDHCI_INSERT_DELAY_TICKS (hz / 2) 106 107 /* 108 * Broadcom BCM577xx Controller Constants 109 */ 110 /* Maximum divider supported by the default clock source. */ 111 #define BCM577XX_DEFAULT_MAX_DIVIDER 256 112 /* Alternative clock's base frequency. */ 113 #define BCM577XX_ALT_CLOCK_BASE 63000000 114 115 #define BCM577XX_HOST_CONTROL 0x198 116 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF 117 #define BCM577XX_CTRL_CLKSEL_SHIFT 12 118 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0 119 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3 120 121 static void 122 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 123 { 124 125 if (error != 0) { 126 printf("getaddr: error %d\n", error); 127 return; 128 } 129 *(bus_addr_t *)arg = segs[0].ds_addr; 130 } 131 132 static int 133 slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 134 { 135 va_list ap; 136 int retval; 137 138 retval = printf("%s-slot%d: ", 139 device_get_nameunit(slot->bus), slot->num); 140 141 va_start(ap, fmt); 142 retval += vprintf(fmt, ap); 143 va_end(ap); 144 return (retval); 145 } 146 147 static void 148 sdhci_dumpregs(struct sdhci_slot *slot) 149 { 150 151 slot_printf(slot, 152 "============== REGISTER DUMP ==============\n"); 153 154 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 155 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 156 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 157 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 158 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 159 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 160 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 161 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 162 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 163 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 164 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 165 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 166 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 167 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 168 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 169 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 170 slot_printf(slot, "AC12 err: 0x%08x | Host ctl2: 0x%08x\n", 171 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2)); 172 slot_printf(slot, "Caps: 0x%08x | Caps2: 0x%08x\n", 173 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2)); 174 slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n", 175 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR)); 176 slot_printf(slot, "ADMA addr: 0x%08x | Slot int: 0x%08x\n", 177 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS)); 178 179 slot_printf(slot, 180 "===========================================\n"); 181 } 182 183 static void 184 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 185 { 186 int timeout; 187 uint32_t clock; 188 189 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 190 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot)) 191 return; 192 } 193 194 /* Some controllers need this kick or reset won't work. */ 195 if ((mask & SDHCI_RESET_ALL) == 0 && 196 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 197 /* This is to force an update */ 198 clock = slot->clock; 199 slot->clock = 0; 200 sdhci_set_clock(slot, clock); 201 } 202 203 if (mask & SDHCI_RESET_ALL) { 204 slot->clock = 0; 205 slot->power = 0; 206 } 207 208 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 209 210 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) { 211 /* 212 * Resets on TI OMAPs and AM335x are incompatible with SDHCI 213 * specification. The reset bit has internal propagation delay, 214 * so a fast read after write returns 0 even if reset process is 215 * in progress. The workaround is to poll for 1 before polling 216 * for 0. In the worst case, if we miss seeing it asserted the 217 * time we spent waiting is enough to ensure the reset finishes. 218 */ 219 timeout = 10000; 220 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) { 221 if (timeout <= 0) 222 break; 223 timeout--; 224 DELAY(1); 225 } 226 } 227 228 /* Wait max 100 ms */ 229 timeout = 10000; 230 /* Controller clears the bits when it's done */ 231 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) { 232 if (timeout <= 0) { 233 slot_printf(slot, "Reset 0x%x never completed.\n", 234 mask); 235 sdhci_dumpregs(slot); 236 return; 237 } 238 timeout--; 239 DELAY(10); 240 } 241 } 242 243 static void 244 sdhci_init(struct sdhci_slot *slot) 245 { 246 247 sdhci_reset(slot, SDHCI_RESET_ALL); 248 249 /* Enable interrupts. */ 250 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 251 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 252 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 253 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 254 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 255 SDHCI_INT_ACMD12ERR; 256 257 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 258 !(slot->opt & SDHCI_NON_REMOVABLE)) { 259 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; 260 } 261 262 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 263 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 264 } 265 266 static void 267 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 268 { 269 uint32_t clk_base; 270 uint32_t clk_sel; 271 uint32_t res; 272 uint16_t clk; 273 uint16_t div; 274 int timeout; 275 276 if (clock == slot->clock) 277 return; 278 slot->clock = clock; 279 280 /* Turn off the clock. */ 281 clk = RD2(slot, SDHCI_CLOCK_CONTROL); 282 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); 283 /* If no clock requested - leave it so. */ 284 if (clock == 0) 285 return; 286 287 /* Determine the clock base frequency */ 288 clk_base = slot->max_clk; 289 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) { 290 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & 291 BCM577XX_CTRL_CLKSEL_MASK; 292 293 /* 294 * Select clock source appropriate for the requested frequency. 295 */ 296 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) { 297 clk_base = BCM577XX_ALT_CLOCK_BASE; 298 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << 299 BCM577XX_CTRL_CLKSEL_SHIFT); 300 } else { 301 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << 302 BCM577XX_CTRL_CLKSEL_SHIFT); 303 } 304 305 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); 306 } 307 308 /* Recalculate timeout clock frequency based on the new sd clock. */ 309 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 310 slot->timeout_clk = slot->clock / 1000; 311 312 if (slot->version < SDHCI_SPEC_300) { 313 /* Looking for highest freq <= clock. */ 314 res = clk_base; 315 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 316 if (res <= clock) 317 break; 318 res >>= 1; 319 } 320 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 321 div >>= 1; 322 } else { 323 /* Version 3.0 divisors are multiples of two up to 1023 * 2 */ 324 if (clock >= clk_base) 325 div = 0; 326 else { 327 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 328 if ((clk_base / div) <= clock) 329 break; 330 } 331 } 332 div >>= 1; 333 } 334 335 if (bootverbose || sdhci_debug) 336 slot_printf(slot, "Divider %d for freq %d (base %d)\n", 337 div, clock, clk_base); 338 339 /* Now we have got divider, set it. */ 340 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 341 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 342 << SDHCI_DIVIDER_HI_SHIFT; 343 344 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 345 /* Enable clock. */ 346 clk |= SDHCI_CLOCK_INT_EN; 347 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 348 /* Wait up to 10 ms until it stabilize. */ 349 timeout = 10; 350 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 351 & SDHCI_CLOCK_INT_STABLE)) { 352 if (timeout == 0) { 353 slot_printf(slot, 354 "Internal clock never stabilised.\n"); 355 sdhci_dumpregs(slot); 356 return; 357 } 358 timeout--; 359 DELAY(1000); 360 } 361 /* Pass clock signal to the bus. */ 362 clk |= SDHCI_CLOCK_CARD_EN; 363 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 364 } 365 366 static void 367 sdhci_set_power(struct sdhci_slot *slot, u_char power) 368 { 369 uint8_t pwr; 370 371 if (slot->power == power) 372 return; 373 374 slot->power = power; 375 376 /* Turn off the power. */ 377 pwr = 0; 378 WR1(slot, SDHCI_POWER_CONTROL, pwr); 379 /* If power down requested - leave it so. */ 380 if (power == 0) 381 return; 382 /* Set voltage. */ 383 switch (1 << power) { 384 case MMC_OCR_LOW_VOLTAGE: 385 pwr |= SDHCI_POWER_180; 386 break; 387 case MMC_OCR_290_300: 388 case MMC_OCR_300_310: 389 pwr |= SDHCI_POWER_300; 390 break; 391 case MMC_OCR_320_330: 392 case MMC_OCR_330_340: 393 pwr |= SDHCI_POWER_330; 394 break; 395 } 396 WR1(slot, SDHCI_POWER_CONTROL, pwr); 397 /* Turn on the power. */ 398 pwr |= SDHCI_POWER_ON; 399 WR1(slot, SDHCI_POWER_CONTROL, pwr); 400 401 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) { 402 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10); 403 DELAY(10); 404 WR1(slot, SDHCI_POWER_CONTROL, pwr); 405 DELAY(300); 406 } 407 } 408 409 static void 410 sdhci_read_block_pio(struct sdhci_slot *slot) 411 { 412 uint32_t data; 413 char *buffer; 414 size_t left; 415 416 buffer = slot->curcmd->data->data; 417 buffer += slot->offset; 418 /* Transfer one block at a time. */ 419 left = min(512, slot->curcmd->data->len - slot->offset); 420 slot->offset += left; 421 422 /* If we are too fast, broken controllers return zeroes. */ 423 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 424 DELAY(10); 425 /* Handle unaligned and aligned buffer cases. */ 426 if ((intptr_t)buffer & 3) { 427 while (left > 3) { 428 data = RD4(slot, SDHCI_BUFFER); 429 buffer[0] = data; 430 buffer[1] = (data >> 8); 431 buffer[2] = (data >> 16); 432 buffer[3] = (data >> 24); 433 buffer += 4; 434 left -= 4; 435 } 436 } else { 437 RD_MULTI_4(slot, SDHCI_BUFFER, 438 (uint32_t *)buffer, left >> 2); 439 left &= 3; 440 } 441 /* Handle uneven size case. */ 442 if (left > 0) { 443 data = RD4(slot, SDHCI_BUFFER); 444 while (left > 0) { 445 *(buffer++) = data; 446 data >>= 8; 447 left--; 448 } 449 } 450 } 451 452 static void 453 sdhci_write_block_pio(struct sdhci_slot *slot) 454 { 455 uint32_t data = 0; 456 char *buffer; 457 size_t left; 458 459 buffer = slot->curcmd->data->data; 460 buffer += slot->offset; 461 /* Transfer one block at a time. */ 462 left = min(512, slot->curcmd->data->len - slot->offset); 463 slot->offset += left; 464 465 /* Handle unaligned and aligned buffer cases. */ 466 if ((intptr_t)buffer & 3) { 467 while (left > 3) { 468 data = buffer[0] + 469 (buffer[1] << 8) + 470 (buffer[2] << 16) + 471 (buffer[3] << 24); 472 left -= 4; 473 buffer += 4; 474 WR4(slot, SDHCI_BUFFER, data); 475 } 476 } else { 477 WR_MULTI_4(slot, SDHCI_BUFFER, 478 (uint32_t *)buffer, left >> 2); 479 left &= 3; 480 } 481 /* Handle uneven size case. */ 482 if (left > 0) { 483 while (left > 0) { 484 data <<= 8; 485 data += *(buffer++); 486 left--; 487 } 488 WR4(slot, SDHCI_BUFFER, data); 489 } 490 } 491 492 static void 493 sdhci_transfer_pio(struct sdhci_slot *slot) 494 { 495 496 /* Read as many blocks as possible. */ 497 if (slot->curcmd->data->flags & MMC_DATA_READ) { 498 while (RD4(slot, SDHCI_PRESENT_STATE) & 499 SDHCI_DATA_AVAILABLE) { 500 sdhci_read_block_pio(slot); 501 if (slot->offset >= slot->curcmd->data->len) 502 break; 503 } 504 } else { 505 while (RD4(slot, SDHCI_PRESENT_STATE) & 506 SDHCI_SPACE_AVAILABLE) { 507 sdhci_write_block_pio(slot); 508 if (slot->offset >= slot->curcmd->data->len) 509 break; 510 } 511 } 512 } 513 514 static void 515 sdhci_card_task(void *arg, int pending __unused) 516 { 517 struct sdhci_slot *slot = arg; 518 device_t d; 519 520 SDHCI_LOCK(slot); 521 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) { 522 if (slot->dev == NULL) { 523 /* If card is present - attach mmc bus. */ 524 if (bootverbose || sdhci_debug) 525 slot_printf(slot, "Card inserted\n"); 526 slot->dev = device_add_child(slot->bus, "mmc", -1); 527 device_set_ivars(slot->dev, slot); 528 SDHCI_UNLOCK(slot); 529 device_probe_and_attach(slot->dev); 530 } else 531 SDHCI_UNLOCK(slot); 532 } else { 533 if (slot->dev != NULL) { 534 /* If no card present - detach mmc bus. */ 535 if (bootverbose || sdhci_debug) 536 slot_printf(slot, "Card removed\n"); 537 d = slot->dev; 538 slot->dev = NULL; 539 SDHCI_UNLOCK(slot); 540 device_delete_child(slot->bus, d); 541 } else 542 SDHCI_UNLOCK(slot); 543 } 544 } 545 546 static void 547 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present) 548 { 549 bool was_present; 550 551 /* 552 * If there was no card and now there is one, schedule the task to 553 * create the child device after a short delay. The delay is to 554 * debounce the card insert (sometimes the card detect pin stabilizes 555 * before the other pins have made good contact). 556 * 557 * If there was a card present and now it's gone, immediately schedule 558 * the task to delete the child device. No debouncing -- gone is gone, 559 * because once power is removed, a full card re-init is needed, and 560 * that happens by deleting and recreating the child device. 561 */ 562 was_present = slot->dev != NULL; 563 if (!was_present && is_present) { 564 taskqueue_enqueue_timeout(taskqueue_swi_giant, 565 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS); 566 } else if (was_present && !is_present) { 567 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 568 } 569 } 570 571 void 572 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present) 573 { 574 575 SDHCI_LOCK(slot); 576 sdhci_handle_card_present_locked(slot, is_present); 577 SDHCI_UNLOCK(slot); 578 } 579 580 static void 581 sdhci_card_poll(void *arg) 582 { 583 struct sdhci_slot *slot = arg; 584 585 sdhci_handle_card_present(slot, 586 SDHCI_GET_CARD_PRESENT(slot->bus, slot)); 587 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS, 588 sdhci_card_poll, slot); 589 } 590 591 int 592 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 593 { 594 uint32_t caps, caps2, freq, host_caps; 595 int err; 596 597 SDHCI_LOCK_INIT(slot); 598 slot->num = num; 599 slot->bus = dev; 600 601 /* Allocate DMA tag. */ 602 err = bus_dma_tag_create(bus_get_dma_tag(dev), 603 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 604 BUS_SPACE_MAXADDR, NULL, NULL, 605 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 606 BUS_DMA_ALLOCNOW, NULL, NULL, 607 &slot->dmatag); 608 if (err != 0) { 609 device_printf(dev, "Can't create DMA tag\n"); 610 SDHCI_LOCK_DESTROY(slot); 611 return (err); 612 } 613 /* Allocate DMA memory. */ 614 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 615 BUS_DMA_NOWAIT, &slot->dmamap); 616 if (err != 0) { 617 device_printf(dev, "Can't alloc DMA memory\n"); 618 SDHCI_LOCK_DESTROY(slot); 619 return (err); 620 } 621 /* Map the memory. */ 622 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 623 (void *)slot->dmamem, DMA_BLOCK_SIZE, 624 sdhci_getaddr, &slot->paddr, 0); 625 if (err != 0 || slot->paddr == 0) { 626 device_printf(dev, "Can't load DMA memory\n"); 627 SDHCI_LOCK_DESTROY(slot); 628 if (err) 629 return (err); 630 else 631 return (EFAULT); 632 } 633 634 /* Initialize slot. */ 635 sdhci_init(slot); 636 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 637 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 638 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) { 639 caps = slot->caps; 640 caps2 = slot->caps2; 641 } else { 642 caps = RD4(slot, SDHCI_CAPABILITIES); 643 if (slot->version >= SDHCI_SPEC_300) 644 caps2 = RD4(slot, SDHCI_CAPABILITIES2); 645 else 646 caps2 = 0; 647 } 648 /* Calculate base clock frequency. */ 649 if (slot->version >= SDHCI_SPEC_300) 650 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 651 SDHCI_CLOCK_BASE_SHIFT; 652 else 653 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> 654 SDHCI_CLOCK_BASE_SHIFT; 655 if (freq != 0) 656 slot->max_clk = freq * 1000000; 657 /* 658 * If the frequency wasn't in the capabilities and the hardware driver 659 * hasn't already set max_clk we're probably not going to work right 660 * with an assumption, so complain about it. 661 */ 662 if (slot->max_clk == 0) { 663 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; 664 device_printf(dev, "Hardware doesn't specify base clock " 665 "frequency, using %dMHz as default.\n", 666 SDHCI_DEFAULT_MAX_FREQ); 667 } 668 /* Calculate/set timeout clock frequency. */ 669 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 670 slot->timeout_clk = slot->max_clk / 1000; 671 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) { 672 slot->timeout_clk = 1000; 673 } else { 674 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >> 675 SDHCI_TIMEOUT_CLK_SHIFT; 676 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 677 slot->timeout_clk *= 1000; 678 } 679 /* 680 * If the frequency wasn't in the capabilities and the hardware driver 681 * hasn't already set timeout_clk we'll probably work okay using the 682 * max timeout, but still mention it. 683 */ 684 if (slot->timeout_clk == 0) { 685 device_printf(dev, "Hardware doesn't specify timeout clock " 686 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 687 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 688 } 689 690 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 691 slot->host.f_max = slot->max_clk; 692 slot->host.host_ocr = 0; 693 if (caps & SDHCI_CAN_VDD_330) 694 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 695 if (caps & SDHCI_CAN_VDD_300) 696 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 697 if (caps & SDHCI_CAN_VDD_180) 698 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 699 if (slot->host.host_ocr == 0) { 700 device_printf(dev, "Hardware doesn't report any " 701 "support voltages.\n"); 702 } 703 host_caps = MMC_CAP_4_BIT_DATA; 704 if (caps & SDHCI_CAN_DO_8BITBUS) 705 host_caps |= MMC_CAP_8_BIT_DATA; 706 if (caps & SDHCI_CAN_DO_HISPD) 707 host_caps |= MMC_CAP_HSPEED; 708 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC) 709 host_caps |= MMC_CAP_BOOT_NOACC; 710 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY) 711 host_caps |= MMC_CAP_WAIT_WHILE_BUSY; 712 if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50)) 713 host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 714 if (caps2 & SDHCI_CAN_SDR104) { 715 host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 716 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200)) 717 host_caps |= MMC_CAP_MMC_HS200; 718 } else if (caps2 & SDHCI_CAN_SDR50) 719 host_caps |= MMC_CAP_UHS_SDR50; 720 if (caps2 & SDHCI_CAN_DDR50 && 721 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50)) 722 host_caps |= MMC_CAP_UHS_DDR50; 723 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52) 724 host_caps |= MMC_CAP_MMC_DDR52; 725 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 && 726 caps2 & SDHCI_CAN_MMC_HS400) 727 host_caps |= MMC_CAP_MMC_HS400; 728 host_caps |= MMC_CAP_SIGNALING_330; 729 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 730 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_DDR50 | 731 MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 | 732 MMC_CAP_MMC_HS400_180)) 733 host_caps |= MMC_CAP_SIGNALING_180; 734 if (caps2 & SDHCI_CAN_DRIVE_TYPE_A) 735 host_caps |= MMC_CAP_DRIVER_TYPE_A; 736 if (caps2 & SDHCI_CAN_DRIVE_TYPE_C) 737 host_caps |= MMC_CAP_DRIVER_TYPE_C; 738 if (caps2 & SDHCI_CAN_DRIVE_TYPE_D) 739 host_caps |= MMC_CAP_DRIVER_TYPE_D; 740 slot->host.caps = host_caps; 741 742 /* Decide if we have usable DMA. */ 743 if (caps & SDHCI_CAN_DO_DMA) 744 slot->opt |= SDHCI_HAVE_DMA; 745 746 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 747 slot->opt &= ~SDHCI_HAVE_DMA; 748 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 749 slot->opt |= SDHCI_HAVE_DMA; 750 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE) 751 slot->opt |= SDHCI_NON_REMOVABLE; 752 753 /* 754 * Use platform-provided transfer backend 755 * with PIO as a fallback mechanism 756 */ 757 if (slot->opt & SDHCI_PLATFORM_TRANSFER) 758 slot->opt &= ~SDHCI_HAVE_DMA; 759 760 if (bootverbose || sdhci_debug) { 761 slot_printf(slot, 762 "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s\n", 763 slot->max_clk / 1000000, 764 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 765 (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" : 766 ((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"), 767 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 768 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 769 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 770 (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "", 771 (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "", 772 (caps2 & SDHCI_CAN_DRIVE_TYPE_A) ? "A" : "", 773 (caps2 & SDHCI_CAN_DRIVE_TYPE_C) ? "C" : "", 774 (caps2 & SDHCI_CAN_DRIVE_TYPE_D) ? "D" : "", 775 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 776 if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | 777 MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) 778 slot_printf(slot, "eMMC:%s%s%s%s\n", 779 (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "", 780 (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "", 781 (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "", 782 ((host_caps & 783 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) == 784 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ? 785 " HS400ES" : ""); 786 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 787 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104)) 788 slot_printf(slot, "UHS-I:%s%s%s%s%s\n", 789 (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "", 790 (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "", 791 (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "", 792 (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "", 793 (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : ""); 794 sdhci_dumpregs(slot); 795 } 796 797 slot->timeout = 10; 798 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus), 799 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO, 800 "timeout", CTLFLAG_RW, &slot->timeout, 0, 801 "Maximum timeout for SDHCI transfers (in secs)"); 802 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 803 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0, 804 sdhci_card_task, slot); 805 callout_init(&slot->card_poll_callout, 1); 806 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0); 807 808 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 809 !(slot->opt & SDHCI_NON_REMOVABLE)) { 810 callout_reset(&slot->card_poll_callout, 811 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot); 812 } 813 814 return (0); 815 } 816 817 void 818 sdhci_start_slot(struct sdhci_slot *slot) 819 { 820 821 sdhci_card_task(slot, 0); 822 } 823 824 int 825 sdhci_cleanup_slot(struct sdhci_slot *slot) 826 { 827 device_t d; 828 829 callout_drain(&slot->timeout_callout); 830 callout_drain(&slot->card_poll_callout); 831 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 832 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task); 833 834 SDHCI_LOCK(slot); 835 d = slot->dev; 836 slot->dev = NULL; 837 SDHCI_UNLOCK(slot); 838 if (d != NULL) 839 device_delete_child(slot->bus, d); 840 841 SDHCI_LOCK(slot); 842 sdhci_reset(slot, SDHCI_RESET_ALL); 843 SDHCI_UNLOCK(slot); 844 bus_dmamap_unload(slot->dmatag, slot->dmamap); 845 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 846 bus_dma_tag_destroy(slot->dmatag); 847 848 SDHCI_LOCK_DESTROY(slot); 849 850 return (0); 851 } 852 853 int 854 sdhci_generic_suspend(struct sdhci_slot *slot) 855 { 856 857 sdhci_reset(slot, SDHCI_RESET_ALL); 858 859 return (0); 860 } 861 862 int 863 sdhci_generic_resume(struct sdhci_slot *slot) 864 { 865 866 sdhci_init(slot); 867 868 return (0); 869 } 870 871 uint32_t 872 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot) 873 { 874 875 if (slot->version >= SDHCI_SPEC_300) 876 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 877 else 878 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 879 } 880 881 bool 882 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot) 883 { 884 885 if (slot->opt & SDHCI_NON_REMOVABLE) 886 return true; 887 888 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 889 } 890 891 void 892 sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot) 893 { 894 struct mmc_ios *ios; 895 uint16_t hostctrl2; 896 897 if (slot->version < SDHCI_SPEC_300) 898 return; 899 900 ios = &slot->host.ios; 901 sdhci_set_clock(slot, 0); 902 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 903 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK; 904 if (ios->timing == bus_timing_mmc_hs400 || 905 ios->timing == bus_timing_mmc_hs400es) 906 hostctrl2 |= SDHCI_CTRL2_MMC_HS400; 907 else if (ios->clock > SD_SDR50_MAX) 908 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104; 909 else if (ios->clock > SD_SDR25_MAX) 910 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50; 911 else if (ios->clock > SD_SDR12_MAX) { 912 if (ios->timing == bus_timing_uhs_ddr50 || 913 ios->timing == bus_timing_mmc_ddr52) 914 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50; 915 else 916 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25; 917 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) 918 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12; 919 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 920 sdhci_set_clock(slot, ios->clock); 921 } 922 923 int 924 sdhci_generic_update_ios(device_t brdev, device_t reqdev) 925 { 926 struct sdhci_slot *slot = device_get_ivars(reqdev); 927 struct mmc_ios *ios = &slot->host.ios; 928 929 SDHCI_LOCK(slot); 930 /* Do full reset on bus power down to clear from any state. */ 931 if (ios->power_mode == power_off) { 932 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 933 sdhci_init(slot); 934 } 935 /* Configure the bus. */ 936 sdhci_set_clock(slot, ios->clock); 937 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 938 if (ios->bus_width == bus_width_8) { 939 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 940 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 941 } else if (ios->bus_width == bus_width_4) { 942 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 943 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 944 } else if (ios->bus_width == bus_width_1) { 945 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 946 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 947 } else { 948 panic("Invalid bus width: %d", ios->bus_width); 949 } 950 if (ios->clock > SD_SDR12_MAX && 951 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 952 slot->hostctrl |= SDHCI_CTRL_HISPD; 953 else 954 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 955 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 956 SDHCI_SET_UHS_TIMING(brdev, slot); 957 /* Some controllers like reset after bus changes. */ 958 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 959 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 960 961 SDHCI_UNLOCK(slot); 962 return (0); 963 } 964 965 int 966 sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev) 967 { 968 struct sdhci_slot *slot = device_get_ivars(reqdev); 969 enum mmc_vccq vccq; 970 int err; 971 uint16_t hostctrl2; 972 973 if (slot->version < SDHCI_SPEC_300) 974 return (0); 975 976 err = 0; 977 vccq = slot->host.ios.vccq; 978 SDHCI_LOCK(slot); 979 sdhci_set_clock(slot, 0); 980 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 981 switch (vccq) { 982 case vccq_330: 983 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 984 goto done; 985 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE; 986 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 987 DELAY(5000); 988 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 989 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 990 goto done; 991 err = EAGAIN; 992 break; 993 case vccq_180: 994 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) { 995 err = EINVAL; 996 goto done; 997 } 998 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 999 goto done; 1000 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE; 1001 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1002 DELAY(5000); 1003 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1004 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 1005 goto done; 1006 err = EAGAIN; 1007 break; 1008 default: 1009 slot_printf(slot, 1010 "Attempt to set unsupported signaling voltage\n"); 1011 err = EINVAL; 1012 break; 1013 } 1014 done: 1015 sdhci_set_clock(slot, slot->host.ios.clock); 1016 SDHCI_UNLOCK(slot); 1017 return (err); 1018 } 1019 1020 static void 1021 sdhci_req_done(struct sdhci_slot *slot) 1022 { 1023 struct mmc_request *req; 1024 1025 if (slot->req != NULL && slot->curcmd != NULL) { 1026 callout_stop(&slot->timeout_callout); 1027 req = slot->req; 1028 slot->req = NULL; 1029 slot->curcmd = NULL; 1030 req->done(req); 1031 } 1032 } 1033 1034 static void 1035 sdhci_timeout(void *arg) 1036 { 1037 struct sdhci_slot *slot = arg; 1038 1039 if (slot->curcmd != NULL) { 1040 slot_printf(slot, " Controller timeout\n"); 1041 sdhci_dumpregs(slot); 1042 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1043 slot->curcmd->error = MMC_ERR_TIMEOUT; 1044 sdhci_req_done(slot); 1045 } else { 1046 slot_printf(slot, " Spurious timeout - no active command\n"); 1047 } 1048 } 1049 1050 static void 1051 sdhci_set_transfer_mode(struct sdhci_slot *slot, struct mmc_data *data) 1052 { 1053 uint16_t mode; 1054 1055 if (data == NULL) 1056 return; 1057 1058 mode = SDHCI_TRNS_BLK_CNT_EN; 1059 if (data->len > 512) 1060 mode |= SDHCI_TRNS_MULTI; 1061 if (data->flags & MMC_DATA_READ) 1062 mode |= SDHCI_TRNS_READ; 1063 if (slot->req->stop && !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) 1064 mode |= SDHCI_TRNS_ACMD12; 1065 if (slot->flags & SDHCI_USE_DMA) 1066 mode |= SDHCI_TRNS_DMA; 1067 1068 WR2(slot, SDHCI_TRANSFER_MODE, mode); 1069 } 1070 1071 static void 1072 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 1073 { 1074 int flags, timeout; 1075 uint32_t mask; 1076 1077 slot->curcmd = cmd; 1078 slot->cmd_done = 0; 1079 1080 cmd->error = MMC_ERR_NONE; 1081 1082 /* This flags combination is not supported by controller. */ 1083 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1084 slot_printf(slot, "Unsupported response type!\n"); 1085 cmd->error = MMC_ERR_FAILED; 1086 sdhci_req_done(slot); 1087 return; 1088 } 1089 1090 /* 1091 * Do not issue command if there is no card, clock or power. 1092 * Controller will not detect timeout without clock active. 1093 */ 1094 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) || 1095 slot->power == 0 || 1096 slot->clock == 0) { 1097 cmd->error = MMC_ERR_FAILED; 1098 sdhci_req_done(slot); 1099 return; 1100 } 1101 /* Always wait for free CMD bus. */ 1102 mask = SDHCI_CMD_INHIBIT; 1103 /* Wait for free DAT if we have data or busy signal. */ 1104 if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 1105 mask |= SDHCI_DAT_INHIBIT; 1106 /* We shouldn't wait for DAT for stop commands. */ 1107 if (cmd == slot->req->stop) 1108 mask &= ~SDHCI_DAT_INHIBIT; 1109 /* 1110 * Wait for bus no more then 250 ms. Typically there will be no wait 1111 * here at all, but when writing a crash dump we may be bypassing the 1112 * host platform's interrupt handler, and in some cases that handler 1113 * may be working around hardware quirks such as not respecting r1b 1114 * busy indications. In those cases, this wait-loop serves the purpose 1115 * of waiting for the prior command and data transfers to be done, and 1116 * SD cards are allowed to take up to 250ms for write and erase ops. 1117 * (It's usually more like 20-30ms in the real world.) 1118 */ 1119 timeout = 250; 1120 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) { 1121 if (timeout == 0) { 1122 slot_printf(slot, "Controller never released " 1123 "inhibit bit(s).\n"); 1124 sdhci_dumpregs(slot); 1125 cmd->error = MMC_ERR_FAILED; 1126 sdhci_req_done(slot); 1127 return; 1128 } 1129 timeout--; 1130 DELAY(1000); 1131 } 1132 1133 /* Prepare command flags. */ 1134 if (!(cmd->flags & MMC_RSP_PRESENT)) 1135 flags = SDHCI_CMD_RESP_NONE; 1136 else if (cmd->flags & MMC_RSP_136) 1137 flags = SDHCI_CMD_RESP_LONG; 1138 else if (cmd->flags & MMC_RSP_BUSY) 1139 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1140 else 1141 flags = SDHCI_CMD_RESP_SHORT; 1142 if (cmd->flags & MMC_RSP_CRC) 1143 flags |= SDHCI_CMD_CRC; 1144 if (cmd->flags & MMC_RSP_OPCODE) 1145 flags |= SDHCI_CMD_INDEX; 1146 if (cmd->data) 1147 flags |= SDHCI_CMD_DATA; 1148 if (cmd->opcode == MMC_STOP_TRANSMISSION) 1149 flags |= SDHCI_CMD_TYPE_ABORT; 1150 /* Prepare data. */ 1151 sdhci_start_data(slot, cmd->data); 1152 /* 1153 * Interrupt aggregation: To reduce total number of interrupts 1154 * group response interrupt with data interrupt when possible. 1155 * If there going to be data interrupt, mask response one. 1156 */ 1157 if (slot->data_done == 0) { 1158 WR4(slot, SDHCI_SIGNAL_ENABLE, 1159 slot->intmask &= ~SDHCI_INT_RESPONSE); 1160 } 1161 /* Set command argument. */ 1162 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 1163 /* Set data transfer mode. */ 1164 sdhci_set_transfer_mode(slot, cmd->data); 1165 /* Start command. */ 1166 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 1167 /* Start timeout callout. */ 1168 callout_reset(&slot->timeout_callout, slot->timeout * hz, 1169 sdhci_timeout, slot); 1170 } 1171 1172 static void 1173 sdhci_finish_command(struct sdhci_slot *slot) 1174 { 1175 int i; 1176 uint32_t val; 1177 uint8_t extra; 1178 1179 slot->cmd_done = 1; 1180 /* 1181 * Interrupt aggregation: Restore command interrupt. 1182 * Main restore point for the case when command interrupt 1183 * happened first. 1184 */ 1185 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 1186 /* In case of error - reset host and return. */ 1187 if (slot->curcmd->error) { 1188 sdhci_reset(slot, SDHCI_RESET_CMD); 1189 sdhci_reset(slot, SDHCI_RESET_DATA); 1190 sdhci_start(slot); 1191 return; 1192 } 1193 /* If command has response - fetch it. */ 1194 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 1195 if (slot->curcmd->flags & MMC_RSP_136) { 1196 /* CRC is stripped so we need one byte shift. */ 1197 extra = 0; 1198 for (i = 0; i < 4; i++) { 1199 val = RD4(slot, SDHCI_RESPONSE + i * 4); 1200 if (slot->quirks & 1201 SDHCI_QUIRK_DONT_SHIFT_RESPONSE) 1202 slot->curcmd->resp[3 - i] = val; 1203 else { 1204 slot->curcmd->resp[3 - i] = 1205 (val << 8) | extra; 1206 extra = val >> 24; 1207 } 1208 } 1209 } else 1210 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 1211 } 1212 /* If data ready - finish. */ 1213 if (slot->data_done) 1214 sdhci_start(slot); 1215 } 1216 1217 static void 1218 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 1219 { 1220 uint32_t target_timeout, current_timeout; 1221 uint8_t div; 1222 1223 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1224 slot->data_done = 1; 1225 return; 1226 } 1227 1228 slot->data_done = 0; 1229 1230 /* Calculate and set data timeout.*/ 1231 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 1232 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 1233 div = 0xE; 1234 } else { 1235 target_timeout = 1000000; 1236 div = 0; 1237 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 1238 while (current_timeout < target_timeout && div < 0xE) { 1239 ++div; 1240 current_timeout <<= 1; 1241 } 1242 /* Compensate for an off-by-one error in the CaFe chip.*/ 1243 if (div < 0xE && 1244 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 1245 ++div; 1246 } 1247 } 1248 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 1249 1250 if (data == NULL) 1251 return; 1252 1253 /* Use DMA if possible. */ 1254 if ((slot->opt & SDHCI_HAVE_DMA)) 1255 slot->flags |= SDHCI_USE_DMA; 1256 /* If data is small, broken DMA may return zeroes instead of data, */ 1257 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 1258 (data->len <= 512)) 1259 slot->flags &= ~SDHCI_USE_DMA; 1260 /* Some controllers require even block sizes. */ 1261 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 1262 ((data->len) & 0x3)) 1263 slot->flags &= ~SDHCI_USE_DMA; 1264 /* Load DMA buffer. */ 1265 if (slot->flags & SDHCI_USE_DMA) { 1266 if (data->flags & MMC_DATA_READ) 1267 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1268 BUS_DMASYNC_PREREAD); 1269 else { 1270 memcpy(slot->dmamem, data->data, 1271 (data->len < DMA_BLOCK_SIZE) ? 1272 data->len : DMA_BLOCK_SIZE); 1273 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1274 BUS_DMASYNC_PREWRITE); 1275 } 1276 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1277 /* Interrupt aggregation: Mask border interrupt 1278 * for the last page and unmask else. */ 1279 if (data->len == DMA_BLOCK_SIZE) 1280 slot->intmask &= ~SDHCI_INT_DMA_END; 1281 else 1282 slot->intmask |= SDHCI_INT_DMA_END; 1283 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1284 } 1285 /* Current data offset for both PIO and DMA. */ 1286 slot->offset = 0; 1287 /* Set block size and request IRQ on 4K border. */ 1288 WR2(slot, SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, 1289 (data->len < 512) ? data->len : 512)); 1290 /* Set block count. */ 1291 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 1292 } 1293 1294 void 1295 sdhci_finish_data(struct sdhci_slot *slot) 1296 { 1297 struct mmc_data *data = slot->curcmd->data; 1298 size_t left; 1299 1300 /* Interrupt aggregation: Restore command interrupt. 1301 * Auxiliary restore point for the case when data interrupt 1302 * happened first. */ 1303 if (!slot->cmd_done) { 1304 WR4(slot, SDHCI_SIGNAL_ENABLE, 1305 slot->intmask |= SDHCI_INT_RESPONSE); 1306 } 1307 /* Unload rest of data from DMA buffer. */ 1308 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA) && 1309 slot->curcmd->data != NULL) { 1310 if (data->flags & MMC_DATA_READ) { 1311 left = data->len - slot->offset; 1312 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1313 BUS_DMASYNC_POSTREAD); 1314 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1315 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE); 1316 } else 1317 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1318 BUS_DMASYNC_POSTWRITE); 1319 } 1320 slot->data_done = 1; 1321 /* If there was error - reset the host. */ 1322 if (slot->curcmd->error) { 1323 sdhci_reset(slot, SDHCI_RESET_CMD); 1324 sdhci_reset(slot, SDHCI_RESET_DATA); 1325 sdhci_start(slot); 1326 return; 1327 } 1328 /* If we already have command response - finish. */ 1329 if (slot->cmd_done) 1330 sdhci_start(slot); 1331 } 1332 1333 static void 1334 sdhci_start(struct sdhci_slot *slot) 1335 { 1336 struct mmc_request *req; 1337 1338 req = slot->req; 1339 if (req == NULL) 1340 return; 1341 1342 if (!(slot->flags & CMD_STARTED)) { 1343 slot->flags |= CMD_STARTED; 1344 sdhci_start_command(slot, req->cmd); 1345 return; 1346 } 1347 if ((slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP) && 1348 !(slot->flags & STOP_STARTED) && req->stop) { 1349 slot->flags |= STOP_STARTED; 1350 sdhci_start_command(slot, req->stop); 1351 return; 1352 } 1353 if (sdhci_debug > 1) 1354 slot_printf(slot, "result: %d\n", req->cmd->error); 1355 if (!req->cmd->error && 1356 ((slot->curcmd == req->stop && 1357 (slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) || 1358 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 1359 sdhci_reset(slot, SDHCI_RESET_CMD); 1360 sdhci_reset(slot, SDHCI_RESET_DATA); 1361 } 1362 1363 sdhci_req_done(slot); 1364 } 1365 1366 int 1367 sdhci_generic_request(device_t brdev __unused, device_t reqdev, 1368 struct mmc_request *req) 1369 { 1370 struct sdhci_slot *slot = device_get_ivars(reqdev); 1371 1372 SDHCI_LOCK(slot); 1373 if (slot->req != NULL) { 1374 SDHCI_UNLOCK(slot); 1375 return (EBUSY); 1376 } 1377 if (sdhci_debug > 1) { 1378 slot_printf(slot, 1379 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1380 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1381 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1382 (req->cmd->data)?req->cmd->data->flags:0); 1383 } 1384 slot->req = req; 1385 slot->flags = 0; 1386 sdhci_start(slot); 1387 SDHCI_UNLOCK(slot); 1388 if (dumping) { 1389 while (slot->req != NULL) { 1390 sdhci_generic_intr(slot); 1391 DELAY(10); 1392 } 1393 } 1394 return (0); 1395 } 1396 1397 int 1398 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev) 1399 { 1400 struct sdhci_slot *slot = device_get_ivars(reqdev); 1401 uint32_t val; 1402 1403 SDHCI_LOCK(slot); 1404 val = RD4(slot, SDHCI_PRESENT_STATE); 1405 SDHCI_UNLOCK(slot); 1406 return (!(val & SDHCI_WRITE_PROTECT)); 1407 } 1408 1409 int 1410 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev) 1411 { 1412 struct sdhci_slot *slot = device_get_ivars(reqdev); 1413 int err = 0; 1414 1415 SDHCI_LOCK(slot); 1416 while (slot->bus_busy) 1417 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 1418 slot->bus_busy++; 1419 /* Activate led. */ 1420 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1421 SDHCI_UNLOCK(slot); 1422 return (err); 1423 } 1424 1425 int 1426 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev) 1427 { 1428 struct sdhci_slot *slot = device_get_ivars(reqdev); 1429 1430 SDHCI_LOCK(slot); 1431 /* Deactivate led. */ 1432 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1433 slot->bus_busy--; 1434 SDHCI_UNLOCK(slot); 1435 wakeup(slot); 1436 return (0); 1437 } 1438 1439 static void 1440 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1441 { 1442 1443 if (!slot->curcmd) { 1444 slot_printf(slot, "Got command interrupt 0x%08x, but " 1445 "there is no active command.\n", intmask); 1446 sdhci_dumpregs(slot); 1447 return; 1448 } 1449 if (intmask & SDHCI_INT_TIMEOUT) 1450 slot->curcmd->error = MMC_ERR_TIMEOUT; 1451 else if (intmask & SDHCI_INT_CRC) 1452 slot->curcmd->error = MMC_ERR_BADCRC; 1453 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1454 slot->curcmd->error = MMC_ERR_FIFO; 1455 1456 sdhci_finish_command(slot); 1457 } 1458 1459 static void 1460 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1461 { 1462 struct mmc_data *data; 1463 size_t left; 1464 1465 if (!slot->curcmd) { 1466 slot_printf(slot, "Got data interrupt 0x%08x, but " 1467 "there is no active command.\n", intmask); 1468 sdhci_dumpregs(slot); 1469 return; 1470 } 1471 if (slot->curcmd->data == NULL && 1472 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1473 slot_printf(slot, "Got data interrupt 0x%08x, but " 1474 "there is no active data operation.\n", 1475 intmask); 1476 sdhci_dumpregs(slot); 1477 return; 1478 } 1479 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1480 slot->curcmd->error = MMC_ERR_TIMEOUT; 1481 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1482 slot->curcmd->error = MMC_ERR_BADCRC; 1483 if (slot->curcmd->data == NULL && 1484 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1485 SDHCI_INT_DMA_END))) { 1486 slot_printf(slot, "Got data interrupt 0x%08x, but " 1487 "there is busy-only command.\n", intmask); 1488 sdhci_dumpregs(slot); 1489 slot->curcmd->error = MMC_ERR_INVALID; 1490 } 1491 if (slot->curcmd->error) { 1492 /* No need to continue after any error. */ 1493 goto done; 1494 } 1495 1496 /* Handle PIO interrupt. */ 1497 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 1498 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 1499 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 1500 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, 1501 &intmask); 1502 slot->flags |= PLATFORM_DATA_STARTED; 1503 } else 1504 sdhci_transfer_pio(slot); 1505 } 1506 /* Handle DMA border. */ 1507 if (intmask & SDHCI_INT_DMA_END) { 1508 data = slot->curcmd->data; 1509 1510 /* Unload DMA buffer ... */ 1511 left = data->len - slot->offset; 1512 if (data->flags & MMC_DATA_READ) { 1513 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1514 BUS_DMASYNC_POSTREAD); 1515 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1516 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE); 1517 } else { 1518 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1519 BUS_DMASYNC_POSTWRITE); 1520 } 1521 /* ... and reload it again. */ 1522 slot->offset += DMA_BLOCK_SIZE; 1523 left = data->len - slot->offset; 1524 if (data->flags & MMC_DATA_READ) { 1525 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1526 BUS_DMASYNC_PREREAD); 1527 } else { 1528 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1529 (left < DMA_BLOCK_SIZE)? left : DMA_BLOCK_SIZE); 1530 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1531 BUS_DMASYNC_PREWRITE); 1532 } 1533 /* Interrupt aggregation: Mask border interrupt 1534 * for the last page. */ 1535 if (left == DMA_BLOCK_SIZE) { 1536 slot->intmask &= ~SDHCI_INT_DMA_END; 1537 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1538 } 1539 /* Restart DMA. */ 1540 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1541 } 1542 /* We have got all data. */ 1543 if (intmask & SDHCI_INT_DATA_END) { 1544 if (slot->flags & PLATFORM_DATA_STARTED) { 1545 slot->flags &= ~PLATFORM_DATA_STARTED; 1546 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1547 } else 1548 sdhci_finish_data(slot); 1549 } 1550 done: 1551 if (slot->curcmd != NULL && slot->curcmd->error != 0) { 1552 if (slot->flags & PLATFORM_DATA_STARTED) { 1553 slot->flags &= ~PLATFORM_DATA_STARTED; 1554 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1555 } else 1556 sdhci_finish_data(slot); 1557 } 1558 } 1559 1560 static void 1561 sdhci_acmd_irq(struct sdhci_slot *slot) 1562 { 1563 uint16_t err; 1564 1565 err = RD4(slot, SDHCI_ACMD12_ERR); 1566 if (!slot->curcmd) { 1567 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1568 "there is no active command.\n", err); 1569 sdhci_dumpregs(slot); 1570 return; 1571 } 1572 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1573 sdhci_reset(slot, SDHCI_RESET_CMD); 1574 } 1575 1576 void 1577 sdhci_generic_intr(struct sdhci_slot *slot) 1578 { 1579 uint32_t intmask, present; 1580 1581 SDHCI_LOCK(slot); 1582 /* Read slot interrupt status. */ 1583 intmask = RD4(slot, SDHCI_INT_STATUS); 1584 if (intmask == 0 || intmask == 0xffffffff) { 1585 SDHCI_UNLOCK(slot); 1586 return; 1587 } 1588 if (sdhci_debug > 2) 1589 slot_printf(slot, "Interrupt %#x\n", intmask); 1590 1591 /* Handle card presence interrupts. */ 1592 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1593 present = (intmask & SDHCI_INT_CARD_INSERT) != 0; 1594 slot->intmask &= 1595 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1596 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE : 1597 SDHCI_INT_CARD_INSERT; 1598 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 1599 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1600 WR4(slot, SDHCI_INT_STATUS, intmask & 1601 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1602 sdhci_handle_card_present_locked(slot, present); 1603 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1604 } 1605 /* Handle command interrupts. */ 1606 if (intmask & SDHCI_INT_CMD_MASK) { 1607 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1608 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1609 } 1610 /* Handle data interrupts. */ 1611 if (intmask & SDHCI_INT_DATA_MASK) { 1612 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1613 /* Don't call data_irq in case of errored command. */ 1614 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0) 1615 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1616 } 1617 /* Handle AutoCMD12 error interrupt. */ 1618 if (intmask & SDHCI_INT_ACMD12ERR) { 1619 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1620 sdhci_acmd_irq(slot); 1621 } 1622 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1623 intmask &= ~SDHCI_INT_ACMD12ERR; 1624 intmask &= ~SDHCI_INT_ERROR; 1625 /* Handle bus power interrupt. */ 1626 if (intmask & SDHCI_INT_BUS_POWER) { 1627 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1628 slot_printf(slot, 1629 "Card is consuming too much power!\n"); 1630 intmask &= ~SDHCI_INT_BUS_POWER; 1631 } 1632 /* The rest is unknown. */ 1633 if (intmask) { 1634 WR4(slot, SDHCI_INT_STATUS, intmask); 1635 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1636 intmask); 1637 sdhci_dumpregs(slot); 1638 } 1639 1640 SDHCI_UNLOCK(slot); 1641 } 1642 1643 int 1644 sdhci_generic_read_ivar(device_t bus, device_t child, int which, 1645 uintptr_t *result) 1646 { 1647 struct sdhci_slot *slot = device_get_ivars(child); 1648 1649 switch (which) { 1650 default: 1651 return (EINVAL); 1652 case MMCBR_IVAR_BUS_MODE: 1653 *result = slot->host.ios.bus_mode; 1654 break; 1655 case MMCBR_IVAR_BUS_WIDTH: 1656 *result = slot->host.ios.bus_width; 1657 break; 1658 case MMCBR_IVAR_CHIP_SELECT: 1659 *result = slot->host.ios.chip_select; 1660 break; 1661 case MMCBR_IVAR_CLOCK: 1662 *result = slot->host.ios.clock; 1663 break; 1664 case MMCBR_IVAR_F_MIN: 1665 *result = slot->host.f_min; 1666 break; 1667 case MMCBR_IVAR_F_MAX: 1668 *result = slot->host.f_max; 1669 break; 1670 case MMCBR_IVAR_HOST_OCR: 1671 *result = slot->host.host_ocr; 1672 break; 1673 case MMCBR_IVAR_MODE: 1674 *result = slot->host.mode; 1675 break; 1676 case MMCBR_IVAR_OCR: 1677 *result = slot->host.ocr; 1678 break; 1679 case MMCBR_IVAR_POWER_MODE: 1680 *result = slot->host.ios.power_mode; 1681 break; 1682 case MMCBR_IVAR_VDD: 1683 *result = slot->host.ios.vdd; 1684 break; 1685 case MMCBR_IVAR_VCCQ: 1686 *result = slot->host.ios.vccq; 1687 break; 1688 case MMCBR_IVAR_CAPS: 1689 *result = slot->host.caps; 1690 break; 1691 case MMCBR_IVAR_TIMING: 1692 *result = slot->host.ios.timing; 1693 break; 1694 case MMCBR_IVAR_MAX_DATA: 1695 *result = 65535; 1696 break; 1697 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: 1698 /* 1699 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs. 1700 */ 1701 *result = 1000000; 1702 break; 1703 } 1704 return (0); 1705 } 1706 1707 int 1708 sdhci_generic_write_ivar(device_t bus, device_t child, int which, 1709 uintptr_t value) 1710 { 1711 struct sdhci_slot *slot = device_get_ivars(child); 1712 uint32_t clock, max_clock; 1713 int i; 1714 1715 switch (which) { 1716 default: 1717 return (EINVAL); 1718 case MMCBR_IVAR_BUS_MODE: 1719 slot->host.ios.bus_mode = value; 1720 break; 1721 case MMCBR_IVAR_BUS_WIDTH: 1722 slot->host.ios.bus_width = value; 1723 break; 1724 case MMCBR_IVAR_CHIP_SELECT: 1725 slot->host.ios.chip_select = value; 1726 break; 1727 case MMCBR_IVAR_CLOCK: 1728 if (value > 0) { 1729 max_clock = slot->max_clk; 1730 clock = max_clock; 1731 1732 if (slot->version < SDHCI_SPEC_300) { 1733 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 1734 i <<= 1) { 1735 if (clock <= value) 1736 break; 1737 clock >>= 1; 1738 } 1739 } else { 1740 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 1741 i += 2) { 1742 if (clock <= value) 1743 break; 1744 clock = max_clock / (i + 2); 1745 } 1746 } 1747 1748 slot->host.ios.clock = clock; 1749 } else 1750 slot->host.ios.clock = 0; 1751 break; 1752 case MMCBR_IVAR_MODE: 1753 slot->host.mode = value; 1754 break; 1755 case MMCBR_IVAR_OCR: 1756 slot->host.ocr = value; 1757 break; 1758 case MMCBR_IVAR_POWER_MODE: 1759 slot->host.ios.power_mode = value; 1760 break; 1761 case MMCBR_IVAR_VDD: 1762 slot->host.ios.vdd = value; 1763 break; 1764 case MMCBR_IVAR_VCCQ: 1765 slot->host.ios.vccq = value; 1766 break; 1767 case MMCBR_IVAR_TIMING: 1768 slot->host.ios.timing = value; 1769 break; 1770 case MMCBR_IVAR_CAPS: 1771 case MMCBR_IVAR_HOST_OCR: 1772 case MMCBR_IVAR_F_MIN: 1773 case MMCBR_IVAR_F_MAX: 1774 case MMCBR_IVAR_MAX_DATA: 1775 return (EINVAL); 1776 } 1777 return (0); 1778 } 1779 1780 MODULE_VERSION(sdhci, 1); 1781