1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef __SDHCI_H__ 29 #define __SDHCI_H__ 30 31 #include "opt_mmccam.h" 32 33 #define DMA_BLOCK_SIZE 4096 34 #define DMA_BOUNDARY 0 /* DMA reload every 4K */ 35 36 /* Controller doesn't honor resets unless we touch the clock register */ 37 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1 << 0) 38 /* Controller really supports DMA */ 39 #define SDHCI_QUIRK_FORCE_DMA (1 << 1) 40 /* Controller has unusable DMA engine */ 41 #define SDHCI_QUIRK_BROKEN_DMA (1 << 2) 42 /* Controller doesn't like to be reset when there is no card inserted. */ 43 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1 << 3) 44 /* Controller has flaky internal state so reset it on each ios change */ 45 #define SDHCI_QUIRK_RESET_ON_IOS (1 << 4) 46 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 47 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1 << 5) 48 /* Controller needs to be reset after each request to stay stable */ 49 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1 << 6) 50 /* Controller has an off-by-one issue with timeout value */ 51 #define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1 << 7) 52 /* Controller has broken read timings */ 53 #define SDHCI_QUIRK_BROKEN_TIMINGS (1 << 8) 54 /* Controller needs lowered frequency */ 55 #define SDHCI_QUIRK_LOWER_FREQUENCY (1 << 9) 56 /* Data timeout is invalid, should use SD clock */ 57 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1 << 10) 58 /* Timeout value is invalid, should be overriden */ 59 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1 << 11) 60 /* SDHCI_CAPABILITIES is invalid */ 61 #define SDHCI_QUIRK_MISSING_CAPS (1 << 12) 62 /* Hardware shifts the 136-bit response, don't do it in software. */ 63 #define SDHCI_QUIRK_DONT_SHIFT_RESPONSE (1 << 13) 64 /* Wait to see reset bit asserted before waiting for de-asserted */ 65 #define SDHCI_QUIRK_WAITFOR_RESET_ASSERTED (1 << 14) 66 /* Leave controller in standard mode when putting card in HS mode. */ 67 #define SDHCI_QUIRK_DONT_SET_HISPD_BIT (1 << 15) 68 /* Alternate clock source is required when supplying a 400 KHz clock. */ 69 #define SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC (1 << 16) 70 /* Card insert/remove interrupts don't work, polling required. */ 71 #define SDHCI_QUIRK_POLL_CARD_PRESENT (1 << 17) 72 /* All controller slots are non-removable. */ 73 #define SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE (1 << 18) 74 /* Issue custom Intel controller reset sequence after power-up. */ 75 #define SDHCI_QUIRK_INTEL_POWER_UP_RESET (1 << 19) 76 /* Data timeout is invalid, use 1 MHz clock instead. */ 77 #define SDHCI_QUIRK_DATA_TIMEOUT_1MHZ (1 << 20) 78 /* Controller doesn't allow access boot partitions. */ 79 #define SDHCI_QUIRK_BOOT_NOACC (1 << 21) 80 /* Controller waits for busy responses. */ 81 #define SDHCI_QUIRK_WAIT_WHILE_BUSY (1 << 22) 82 /* Controller supports eMMC DDR52 mode. */ 83 #define SDHCI_QUIRK_MMC_DDR52 (1 << 23) 84 /* Controller support for UHS DDR50 mode is broken. */ 85 #define SDHCI_QUIRK_BROKEN_UHS_DDR50 (1 << 24) 86 /* Controller support for eMMC HS200 mode is broken. */ 87 #define SDHCI_QUIRK_BROKEN_MMC_HS200 (1 << 25) 88 /* Controller reports support for eMMC HS400 mode as SDHCI_CAN_MMC_HS400. */ 89 #define SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 (1 << 26) 90 /* Controller support for SDHCI_CTRL2_PRESET_VALUE is broken. */ 91 #define SDHCI_QUIRK_PRESET_VALUE_BROKEN (1 << 27) 92 /* Controller does not support or the support for ACMD12 is broken. */ 93 #define SDHCI_QUIRK_BROKEN_AUTO_STOP (1 << 28) 94 95 /* 96 * Controller registers 97 */ 98 #define SDHCI_DMA_ADDRESS 0x00 99 100 #define SDHCI_BLOCK_SIZE 0x04 101 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 102 103 #define SDHCI_BLOCK_COUNT 0x06 104 105 #define SDHCI_ARGUMENT 0x08 106 107 #define SDHCI_TRANSFER_MODE 0x0C 108 #define SDHCI_TRNS_DMA 0x01 109 #define SDHCI_TRNS_BLK_CNT_EN 0x02 110 #define SDHCI_TRNS_ACMD12 0x04 111 #define SDHCI_TRNS_READ 0x10 112 #define SDHCI_TRNS_MULTI 0x20 113 114 #define SDHCI_COMMAND_FLAGS 0x0E 115 #define SDHCI_CMD_RESP_NONE 0x00 116 #define SDHCI_CMD_RESP_LONG 0x01 117 #define SDHCI_CMD_RESP_SHORT 0x02 118 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 119 #define SDHCI_CMD_RESP_MASK 0x03 120 #define SDHCI_CMD_CRC 0x08 121 #define SDHCI_CMD_INDEX 0x10 122 #define SDHCI_CMD_DATA 0x20 123 #define SDHCI_CMD_TYPE_NORMAL 0x00 124 #define SDHCI_CMD_TYPE_SUSPEND 0x40 125 #define SDHCI_CMD_TYPE_RESUME 0x80 126 #define SDHCI_CMD_TYPE_ABORT 0xc0 127 #define SDHCI_CMD_TYPE_MASK 0xc0 128 129 #define SDHCI_COMMAND 0x0F 130 131 #define SDHCI_RESPONSE 0x10 132 133 #define SDHCI_BUFFER 0x20 134 135 #define SDHCI_PRESENT_STATE 0x24 136 #define SDHCI_CMD_INHIBIT 0x00000001 137 #define SDHCI_DAT_INHIBIT 0x00000002 138 #define SDHCI_DAT_ACTIVE 0x00000004 139 #define SDHCI_RETUNE_REQUEST 0x00000008 140 #define SDHCI_DOING_WRITE 0x00000100 141 #define SDHCI_DOING_READ 0x00000200 142 #define SDHCI_SPACE_AVAILABLE 0x00000400 143 #define SDHCI_DATA_AVAILABLE 0x00000800 144 #define SDHCI_CARD_PRESENT 0x00010000 145 #define SDHCI_CARD_STABLE 0x00020000 146 #define SDHCI_CARD_PIN 0x00040000 147 #define SDHCI_WRITE_PROTECT 0x00080000 148 #define SDHCI_STATE_DAT_MASK 0x00f00000 149 #define SDHCI_STATE_CMD 0x01000000 150 151 #define SDHCI_HOST_CONTROL 0x28 152 #define SDHCI_CTRL_LED 0x01 153 #define SDHCI_CTRL_4BITBUS 0x02 154 #define SDHCI_CTRL_HISPD 0x04 155 #define SDHCI_CTRL_SDMA 0x08 156 #define SDHCI_CTRL_ADMA2 0x10 157 #define SDHCI_CTRL_ADMA264 0x18 158 #define SDHCI_CTRL_DMA_MASK 0x18 159 #define SDHCI_CTRL_8BITBUS 0x20 160 #define SDHCI_CTRL_CARD_DET 0x40 161 #define SDHCI_CTRL_FORCE_CARD 0x80 162 163 #define SDHCI_POWER_CONTROL 0x29 164 #define SDHCI_POWER_ON 0x01 165 #define SDHCI_POWER_180 0x0A 166 #define SDHCI_POWER_300 0x0C 167 #define SDHCI_POWER_330 0x0E 168 169 #define SDHCI_BLOCK_GAP_CONTROL 0x2A 170 171 #define SDHCI_WAKE_UP_CONTROL 0x2B 172 173 #define SDHCI_CLOCK_CONTROL 0x2C 174 #define SDHCI_DIVIDER_MASK 0xff 175 #define SDHCI_DIVIDER_MASK_LEN 8 176 #define SDHCI_DIVIDER_SHIFT 8 177 #define SDHCI_DIVIDER_HI_MASK 3 178 #define SDHCI_DIVIDER_HI_SHIFT 6 179 #define SDHCI_CLOCK_CARD_EN 0x0004 180 #define SDHCI_CLOCK_INT_STABLE 0x0002 181 #define SDHCI_CLOCK_INT_EN 0x0001 182 #define SDHCI_DIVIDERS_MASK \ 183 ((SDHCI_DIVIDER_MASK << SDHCI_DIVIDER_SHIFT) | \ 184 (SDHCI_DIVIDER_HI_MASK << SDHCI_DIVIDER_HI_SHIFT)) 185 186 #define SDHCI_TIMEOUT_CONTROL 0x2E 187 188 #define SDHCI_SOFTWARE_RESET 0x2F 189 #define SDHCI_RESET_ALL 0x01 190 #define SDHCI_RESET_CMD 0x02 191 #define SDHCI_RESET_DATA 0x04 192 193 #define SDHCI_INT_STATUS 0x30 194 #define SDHCI_INT_ENABLE 0x34 195 #define SDHCI_SIGNAL_ENABLE 0x38 196 #define SDHCI_INT_RESPONSE 0x00000001 197 #define SDHCI_INT_DATA_END 0x00000002 198 #define SDHCI_INT_BLOCK_GAP 0x00000004 199 #define SDHCI_INT_DMA_END 0x00000008 200 #define SDHCI_INT_SPACE_AVAIL 0x00000010 201 #define SDHCI_INT_DATA_AVAIL 0x00000020 202 #define SDHCI_INT_CARD_INSERT 0x00000040 203 #define SDHCI_INT_CARD_REMOVE 0x00000080 204 #define SDHCI_INT_CARD_INT 0x00000100 205 #define SDHCI_INT_INT_A 0x00000200 206 #define SDHCI_INT_INT_B 0x00000400 207 #define SDHCI_INT_INT_C 0x00000800 208 #define SDHCI_INT_RETUNE 0x00001000 209 #define SDHCI_INT_ERROR 0x00008000 210 #define SDHCI_INT_TIMEOUT 0x00010000 211 #define SDHCI_INT_CRC 0x00020000 212 #define SDHCI_INT_END_BIT 0x00040000 213 #define SDHCI_INT_INDEX 0x00080000 214 #define SDHCI_INT_DATA_TIMEOUT 0x00100000 215 #define SDHCI_INT_DATA_CRC 0x00200000 216 #define SDHCI_INT_DATA_END_BIT 0x00400000 217 #define SDHCI_INT_BUS_POWER 0x00800000 218 #define SDHCI_INT_ACMD12ERR 0x01000000 219 #define SDHCI_INT_ADMAERR 0x02000000 220 #define SDHCI_INT_TUNEERR 0x04000000 221 222 #define SDHCI_INT_NORMAL_MASK 0x00007FFF 223 #define SDHCI_INT_ERROR_MASK 0xFFFF8000 224 225 #define SDHCI_INT_CMD_ERROR_MASK (SDHCI_INT_TIMEOUT | \ 226 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 227 228 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_CMD_ERROR_MASK) 229 230 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 231 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 232 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 233 SDHCI_INT_DATA_END_BIT) 234 235 #define SDHCI_ACMD12_ERR 0x3C 236 237 #define SDHCI_HOST_CONTROL2 0x3E 238 #define SDHCI_CTRL2_PRESET_VALUE 0x8000 239 #define SDHCI_CTRL2_ASYNC_INTR 0x4000 240 #define SDHCI_CTRL2_SAMPLING_CLOCK 0x0080 241 #define SDHCI_CTRL2_EXEC_TUNING 0x0040 242 #define SDHCI_CTRL2_DRIVER_TYPE_MASK 0x0030 243 #define SDHCI_CTRL2_DRIVER_TYPE_B 0x0000 244 #define SDHCI_CTRL2_DRIVER_TYPE_A 0x0010 245 #define SDHCI_CTRL2_DRIVER_TYPE_C 0x0020 246 #define SDHCI_CTRL2_DRIVER_TYPE_D 0x0030 247 #define SDHCI_CTRL2_S18_ENABLE 0x0008 248 #define SDHCI_CTRL2_UHS_MASK 0x0007 249 #define SDHCI_CTRL2_UHS_SDR12 0x0000 250 #define SDHCI_CTRL2_UHS_SDR25 0x0001 251 #define SDHCI_CTRL2_UHS_SDR50 0x0002 252 #define SDHCI_CTRL2_UHS_SDR104 0x0003 253 #define SDHCI_CTRL2_UHS_DDR50 0x0004 254 #define SDHCI_CTRL2_MMC_HS400 0x0005 /* non-standard */ 255 256 #define SDHCI_CAPABILITIES 0x40 257 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 258 #define SDHCI_TIMEOUT_CLK_SHIFT 0 259 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 260 #define SDHCI_CLOCK_BASE_MASK 0x00003F00 261 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 262 #define SDHCI_CLOCK_BASE_SHIFT 8 263 #define SDHCI_MAX_BLOCK_MASK 0x00030000 264 #define SDHCI_MAX_BLOCK_SHIFT 16 265 #define SDHCI_CAN_DO_8BITBUS 0x00040000 266 #define SDHCI_CAN_DO_ADMA2 0x00080000 267 #define SDHCI_CAN_DO_HISPD 0x00200000 268 #define SDHCI_CAN_DO_DMA 0x00400000 269 #define SDHCI_CAN_DO_SUSPEND 0x00800000 270 #define SDHCI_CAN_VDD_330 0x01000000 271 #define SDHCI_CAN_VDD_300 0x02000000 272 #define SDHCI_CAN_VDD_180 0x04000000 273 #define SDHCI_CAN_DO_64BIT 0x10000000 274 #define SDHCI_CAN_ASYNC_INTR 0x20000000 275 #define SDHCI_SLOTTYPE_MASK 0xC0000000 276 #define SDHCI_SLOTTYPE_REMOVABLE 0x00000000 277 #define SDHCI_SLOTTYPE_EMBEDDED 0x40000000 278 #define SDHCI_SLOTTYPE_SHARED 0x80000000 279 280 #define SDHCI_CAPABILITIES2 0x44 281 #define SDHCI_CAN_SDR50 0x00000001 282 #define SDHCI_CAN_SDR104 0x00000002 283 #define SDHCI_CAN_DDR50 0x00000004 284 #define SDHCI_CAN_DRIVE_TYPE_A 0x00000010 285 #define SDHCI_CAN_DRIVE_TYPE_C 0x00000020 286 #define SDHCI_CAN_DRIVE_TYPE_D 0x00000040 287 #define SDHCI_RETUNE_CNT_MASK 0x00000F00 288 #define SDHCI_RETUNE_CNT_SHIFT 8 289 #define SDHCI_TUNE_SDR50 0x00002000 290 #define SDHCI_RETUNE_MODES_MASK 0x0000C000 291 #define SDHCI_RETUNE_MODES_SHIFT 14 292 #define SDHCI_CLOCK_MULT_MASK 0x00FF0000 293 #define SDHCI_CLOCK_MULT_SHIFT 16 294 #define SDHCI_CAN_MMC_HS400 0x80000000 /* non-standard */ 295 296 #define SDHCI_MAX_CURRENT 0x48 297 #define SDHCI_FORCE_AUTO_EVENT 0x50 298 #define SDHCI_FORCE_INTR_EVENT 0x52 299 300 #define SDHCI_ADMA_ERR 0x54 301 #define SDHCI_ADMA_ERR_LENGTH 0x04 302 #define SDHCI_ADMA_ERR_STATE_MASK 0x03 303 #define SDHCI_ADMA_ERR_STATE_STOP 0x00 304 #define SDHCI_ADMA_ERR_STATE_FDS 0x01 305 #define SDHCI_ADMA_ERR_STATE_TFR 0x03 306 307 #define SDHCI_ADMA_ADDRESS_LO 0x58 308 #define SDHCI_ADMA_ADDRESS_HI 0x5C 309 310 #define SDHCI_PRESET_VALUE 0x60 311 #define SDHCI_SHARED_BUS_CTRL 0xE0 312 313 #define SDHCI_SLOT_INT_STATUS 0xFC 314 315 #define SDHCI_HOST_VERSION 0xFE 316 #define SDHCI_VENDOR_VER_MASK 0xFF00 317 #define SDHCI_VENDOR_VER_SHIFT 8 318 #define SDHCI_SPEC_VER_MASK 0x00FF 319 #define SDHCI_SPEC_VER_SHIFT 0 320 #define SDHCI_SPEC_100 0 321 #define SDHCI_SPEC_200 1 322 #define SDHCI_SPEC_300 2 323 #define SDHCI_SPEC_400 3 324 325 SYSCTL_DECL(_hw_sdhci); 326 327 extern u_int sdhci_quirk_clear; 328 extern u_int sdhci_quirk_set; 329 330 struct sdhci_slot { 331 u_int quirks; /* Chip specific quirks */ 332 u_int caps; /* Override SDHCI_CAPABILITIES */ 333 u_int caps2; /* Override SDHCI_CAPABILITIES2 */ 334 device_t bus; /* Bus device */ 335 device_t dev; /* Slot device */ 336 u_char num; /* Slot number */ 337 u_char opt; /* Slot options */ 338 #define SDHCI_HAVE_DMA 0x01 339 #define SDHCI_PLATFORM_TRANSFER 0x02 340 #define SDHCI_NON_REMOVABLE 0x04 341 u_char version; 342 int timeout; /* Transfer timeout */ 343 uint32_t max_clk; /* Max possible freq */ 344 uint32_t timeout_clk; /* Timeout freq */ 345 bus_dma_tag_t dmatag; 346 bus_dmamap_t dmamap; 347 u_char *dmamem; 348 bus_addr_t paddr; /* DMA buffer address */ 349 struct task card_task; /* Card presence check task */ 350 struct timeout_task 351 card_delayed_task;/* Card insert delayed task */ 352 struct callout card_poll_callout;/* Card present polling callout */ 353 struct callout timeout_callout;/* Card command/data response timeout */ 354 struct mmc_host host; /* Host parameters */ 355 struct mmc_request *req; /* Current request */ 356 struct mmc_command *curcmd; /* Current command of current request */ 357 358 uint32_t intmask; /* Current interrupt mask */ 359 uint32_t clock; /* Current clock freq. */ 360 size_t offset; /* Data buffer offset */ 361 uint8_t hostctrl; /* Current host control register */ 362 u_char power; /* Current power */ 363 u_char bus_busy; /* Bus busy status */ 364 u_char cmd_done; /* CMD command part done flag */ 365 u_char data_done; /* DAT command part done flag */ 366 u_char flags; /* Request execution flags */ 367 #define CMD_STARTED 1 368 #define STOP_STARTED 2 369 #define SDHCI_USE_DMA 4 /* Use DMA for this req. */ 370 #define PLATFORM_DATA_STARTED 8 /* Data xfer is handled by platform */ 371 struct mtx mtx; /* Slot mutex */ 372 373 #ifdef MMCCAM 374 /* CAM stuff */ 375 union ccb *ccb; 376 struct cam_devq *devq; 377 struct cam_sim *sim; 378 struct mtx sim_mtx; 379 u_char card_present; /* XXX Maybe derive this from elsewhere? */ 380 #endif 381 }; 382 383 int sdhci_generic_read_ivar(device_t bus, device_t child, int which, 384 uintptr_t *result); 385 int sdhci_generic_write_ivar(device_t bus, device_t child, int which, 386 uintptr_t value); 387 int sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num); 388 void sdhci_start_slot(struct sdhci_slot *slot); 389 /* performs generic clean-up for platform transfers */ 390 void sdhci_finish_data(struct sdhci_slot *slot); 391 int sdhci_cleanup_slot(struct sdhci_slot *slot); 392 int sdhci_generic_suspend(struct sdhci_slot *slot); 393 int sdhci_generic_resume(struct sdhci_slot *slot); 394 int sdhci_generic_update_ios(device_t brdev, device_t reqdev); 395 int sdhci_generic_switch_vccq(device_t brdev, device_t reqdev); 396 int sdhci_generic_request(device_t brdev, device_t reqdev, 397 struct mmc_request *req); 398 int sdhci_generic_get_ro(device_t brdev, device_t reqdev); 399 int sdhci_generic_acquire_host(device_t brdev, device_t reqdev); 400 int sdhci_generic_release_host(device_t brdev, device_t reqdev); 401 void sdhci_generic_intr(struct sdhci_slot *slot); 402 uint32_t sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot); 403 bool sdhci_generic_get_card_present(device_t brdev, struct sdhci_slot *slot); 404 void sdhci_generic_set_uhs_timing(device_t brdev, struct sdhci_slot *slot); 405 void sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present); 406 407 #ifdef MMCCAM 408 /* CAM-related */ 409 void sdhci_cam_start_slot(struct sdhci_slot *slot); 410 #endif 411 412 #endif /* __SDHCI_H__ */ 413