1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2020 Alstom Group. 5 * Copyright (c) 2020 Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* eSDHC controller driver for NXP QorIQ Layerscape SoCs. */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/endian.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/rman.h> 39 #include <sys/sysctl.h> 40 #include <sys/taskqueue.h> 41 42 #include <machine/bus.h> 43 #include <machine/resource.h> 44 45 #include <dev/extres/clk/clk.h> 46 #include <dev/mmc/bridge.h> 47 #include <dev/mmc/mmcbrvar.h> 48 #include <dev/mmc/mmc_fdt_helpers.h> 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 #include <dev/sdhci/sdhci.h> 52 #include <dev/sdhci/sdhci_fdt_gpio.h> 53 54 #include "mmcbr_if.h" 55 #include "sdhci_if.h" 56 57 #define RD4 (sc->read) 58 #define WR4 (sc->write) 59 60 #define SDHCI_FSL_PRES_STATE 0x24 61 #define SDHCI_FSL_PRES_SDSTB (1 << 3) 62 #define SDHCI_FSL_PRES_COMPAT_MASK 0x000f0f07 63 64 #define SDHCI_FSL_PROT_CTRL 0x28 65 #define SDHCI_FSL_PROT_CTRL_WIDTH_1BIT (0 << 1) 66 #define SDHCI_FSL_PROT_CTRL_WIDTH_4BIT (1 << 1) 67 #define SDHCI_FSL_PROT_CTRL_WIDTH_8BIT (2 << 1) 68 #define SDHCI_FSL_PROT_CTRL_WIDTH_MASK (3 << 1) 69 #define SDHCI_FSL_PROT_CTRL_BYTE_SWAP (0 << 4) 70 #define SDHCI_FSL_PROT_CTRL_BYTE_NATIVE (2 << 4) 71 #define SDHCI_FSL_PROT_CTRL_BYTE_MASK (3 << 4) 72 #define SDHCI_FSL_PROT_CTRL_DMA_MASK (3 << 8) 73 74 #define SDHCI_FSL_SYS_CTRL 0x2c 75 #define SDHCI_FSL_CLK_IPGEN (1 << 0) 76 #define SDHCI_FSL_CLK_SDCLKEN (1 << 3) 77 #define SDHCI_FSL_CLK_DIVIDER_MASK 0x000000f0 78 #define SDHCI_FSL_CLK_DIVIDER_SHIFT 4 79 #define SDHCI_FSL_CLK_PRESCALE_MASK 0x0000ff00 80 #define SDHCI_FSL_CLK_PRESCALE_SHIFT 8 81 82 #define SDHCI_FSL_WTMK_LVL 0x44 83 #define SDHCI_FSL_WTMK_RD_512B (0 << 0) 84 #define SDHCI_FSL_WTMK_WR_512B (0 << 15) 85 86 #define SDHCI_FSL_HOST_VERSION 0xfc 87 #define SDHCI_FSL_CAPABILITIES2 0x114 88 89 #define SDHCI_FSL_ESDHC_CTRL 0x40c 90 #define SDHCI_FSL_ESDHC_CTRL_SNOOP (1 << 6) 91 #define SDHCI_FSL_ESDHC_CTRL_CLK_DIV2 (1 << 19) 92 93 #define SDHCI_FSL_CAN_VDD_MASK \ 94 (SDHCI_CAN_VDD_180 | SDHCI_CAN_VDD_300 | SDHCI_CAN_VDD_330) 95 96 struct sdhci_fsl_fdt_softc { 97 device_t dev; 98 const struct sdhci_fsl_fdt_soc_data *soc_data; 99 struct resource *mem_res; 100 struct resource *irq_res; 101 void *irq_cookie; 102 uint32_t baseclk_hz; 103 uint32_t maxclk_hz; 104 struct sdhci_fdt_gpio *gpio; 105 struct sdhci_slot slot; 106 bool slot_init_done; 107 uint32_t cmd_and_mode; 108 uint16_t sdclk_bits; 109 struct mmc_fdt_helper fdt_helper; 110 111 uint32_t (* read)(struct sdhci_fsl_fdt_softc *, bus_size_t); 112 void (* write)(struct sdhci_fsl_fdt_softc *, bus_size_t, uint32_t); 113 }; 114 115 struct sdhci_fsl_fdt_soc_data { 116 int quirks; 117 int baseclk_div; 118 }; 119 120 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1028a_soc_data = { 121 .quirks = SDHCI_QUIRK_DONT_SET_HISPD_BIT | 122 SDHCI_QUIRK_BROKEN_AUTO_STOP | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, 123 .baseclk_div = 2, 124 }; 125 126 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1046a_soc_data = { 127 .quirks = SDHCI_QUIRK_DONT_SET_HISPD_BIT | SDHCI_QUIRK_BROKEN_AUTO_STOP, 128 .baseclk_div = 2, 129 }; 130 131 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_gen_data = { 132 .quirks = 0, 133 .baseclk_div = 1, 134 }; 135 136 static const struct ofw_compat_data sdhci_fsl_fdt_compat_data[] = { 137 {"fsl,ls1028a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1028a_soc_data}, 138 {"fsl,ls1046a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1046a_soc_data}, 139 {"fsl,esdhc", (uintptr_t)&sdhci_fsl_fdt_gen_data}, 140 {NULL, 0} 141 }; 142 143 static uint32_t 144 read_be(struct sdhci_fsl_fdt_softc *sc, bus_size_t off) 145 { 146 147 return (be32toh(bus_read_4(sc->mem_res, off))); 148 } 149 150 static void 151 write_be(struct sdhci_fsl_fdt_softc *sc, bus_size_t off, uint32_t val) 152 { 153 154 bus_write_4(sc->mem_res, off, htobe32(val)); 155 } 156 157 static uint32_t 158 read_le(struct sdhci_fsl_fdt_softc *sc, bus_size_t off) 159 { 160 161 return (bus_read_4(sc->mem_res, off)); 162 } 163 164 static void 165 write_le(struct sdhci_fsl_fdt_softc *sc, bus_size_t off, uint32_t val) 166 { 167 168 bus_write_4(sc->mem_res, off, val); 169 } 170 171 172 static uint16_t 173 sdhci_fsl_fdt_get_clock(struct sdhci_fsl_fdt_softc *sc) 174 { 175 uint16_t val; 176 177 val = sc->sdclk_bits | SDHCI_CLOCK_INT_EN; 178 if (RD4(sc, SDHCI_FSL_PRES_STATE) & SDHCI_FSL_PRES_SDSTB) 179 val |= SDHCI_CLOCK_INT_STABLE; 180 if (RD4(sc, SDHCI_FSL_SYS_CTRL) & SDHCI_FSL_CLK_SDCLKEN) 181 val |= SDHCI_CLOCK_CARD_EN; 182 183 return (val); 184 } 185 186 static void 187 fsl_sdhc_fdt_set_clock(struct sdhci_fsl_fdt_softc *sc, uint16_t val) 188 { 189 uint32_t div, freq, prescale, val32; 190 191 sc->sdclk_bits = val & SDHCI_DIVIDERS_MASK; 192 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 193 194 if ((val & SDHCI_CLOCK_CARD_EN) == 0) { 195 WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHCI_FSL_CLK_SDCLKEN); 196 return; 197 } 198 199 div = ((val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK) | 200 ((val >> SDHCI_DIVIDER_HI_SHIFT) & SDHCI_DIVIDER_HI_MASK) << 201 SDHCI_DIVIDER_MASK_LEN; 202 if (div == 0) 203 freq = sc->maxclk_hz; 204 else 205 freq = sc->maxclk_hz / (2 * div); 206 207 for (prescale = 2; freq < sc->baseclk_hz / (prescale * 16); ) 208 prescale <<= 1; 209 for (div = 1; freq < sc->baseclk_hz / (prescale * div); ) 210 ++div; 211 212 #ifdef DEBUG 213 device_printf(sc->dev, 214 "Desired SD/MMC freq: %d, actual: %d; base %d prescale %d divisor %d\n", 215 freq, sc->baseclk_hz / (prescale * div), 216 sc->baseclk_hz, prescale, div); 217 #endif 218 219 prescale >>= 1; 220 div -= 1; 221 222 val32 &= ~(SDHCI_FSL_CLK_DIVIDER_MASK | SDHCI_FSL_CLK_PRESCALE_MASK); 223 val32 |= div << SDHCI_FSL_CLK_DIVIDER_SHIFT; 224 val32 |= prescale << SDHCI_FSL_CLK_PRESCALE_SHIFT; 225 val32 |= SDHCI_FSL_CLK_IPGEN | SDHCI_FSL_CLK_SDCLKEN; 226 WR4(sc, SDHCI_CLOCK_CONTROL, val32); 227 } 228 229 static uint8_t 230 sdhci_fsl_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 231 { 232 struct sdhci_fsl_fdt_softc *sc; 233 uint32_t wrk32, val32; 234 235 sc = device_get_softc(dev); 236 237 switch (off) { 238 case SDHCI_HOST_CONTROL: 239 wrk32 = RD4(sc, SDHCI_FSL_PROT_CTRL); 240 val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET | 241 SDHCI_CTRL_FORCE_CARD); 242 if (wrk32 & SDHCI_FSL_PROT_CTRL_WIDTH_4BIT) 243 val32 |= SDHCI_CTRL_4BITBUS; 244 else if (wrk32 & SDHCI_FSL_PROT_CTRL_WIDTH_8BIT) 245 val32 |= SDHCI_CTRL_8BITBUS; 246 return (val32); 247 case SDHCI_POWER_CONTROL: 248 return (SDHCI_POWER_ON | SDHCI_POWER_300); 249 default: 250 break; 251 } 252 253 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT8_MAX); 254 } 255 256 static uint16_t 257 sdhci_fsl_fdt_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 258 { 259 struct sdhci_fsl_fdt_softc *sc; 260 uint32_t val32; 261 262 sc = device_get_softc(dev); 263 264 switch (off) { 265 case SDHCI_CLOCK_CONTROL: 266 return (sdhci_fsl_fdt_get_clock(sc)); 267 case SDHCI_HOST_VERSION: 268 return (RD4(sc, SDHCI_FSL_HOST_VERSION) & UINT16_MAX); 269 case SDHCI_TRANSFER_MODE: 270 return (sc->cmd_and_mode & UINT16_MAX); 271 case SDHCI_COMMAND_FLAGS: 272 return (sc->cmd_and_mode >> 16); 273 case SDHCI_SLOT_INT_STATUS: 274 /* 275 * eSDHC hardware manages only a single slot. 276 * Synthesize a slot interrupt status register for slot 1 below. 277 */ 278 val32 = RD4(sc, SDHCI_INT_STATUS); 279 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE); 280 return (!!val32); 281 default: 282 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT16_MAX); 283 } 284 } 285 286 static uint32_t 287 sdhci_fsl_fdt_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 288 { 289 struct sdhci_fsl_fdt_softc *sc; 290 uint32_t wrk32, val32; 291 292 sc = device_get_softc(dev); 293 294 if (off == SDHCI_BUFFER) 295 return (bus_read_4(sc->mem_res, off)); 296 if (off == SDHCI_CAPABILITIES2) 297 off = SDHCI_FSL_CAPABILITIES2; 298 299 val32 = RD4(sc, off); 300 301 if (off == SDHCI_PRESENT_STATE) { 302 wrk32 = val32; 303 val32 &= SDHCI_FSL_PRES_COMPAT_MASK; 304 val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK; 305 val32 |= (wrk32 << 1) & SDHCI_STATE_CMD; 306 } 307 308 return (val32); 309 } 310 311 static void 312 sdhci_fsl_fdt_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 313 uint32_t *data, bus_size_t count) 314 { 315 struct sdhci_fsl_fdt_softc *sc; 316 317 sc = device_get_softc(dev); 318 bus_read_multi_4(sc->mem_res, off, data, count); 319 } 320 321 static void 322 sdhci_fsl_fdt_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 323 uint8_t val) 324 { 325 struct sdhci_fsl_fdt_softc *sc; 326 uint32_t val32; 327 328 sc = device_get_softc(dev); 329 330 switch (off) { 331 case SDHCI_HOST_CONTROL: 332 val32 = RD4(sc, SDHCI_FSL_PROT_CTRL); 333 val32 &= ~SDHCI_FSL_PROT_CTRL_WIDTH_MASK; 334 val32 |= (val & SDHCI_CTRL_LED); 335 336 if (val & SDHCI_CTRL_8BITBUS) 337 val32 |= SDHCI_FSL_PROT_CTRL_WIDTH_8BIT; 338 else 339 /* Bus width is 1-bit when this flag is not set. */ 340 val32 |= (val & SDHCI_CTRL_4BITBUS); 341 /* Enable SDMA by masking out this field. */ 342 val32 &= ~SDHCI_FSL_PROT_CTRL_DMA_MASK; 343 val32 &= ~(SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD); 344 val32 |= (val & (SDHCI_CTRL_CARD_DET | 345 SDHCI_CTRL_FORCE_CARD)); 346 WR4(sc, SDHCI_FSL_PROT_CTRL, val32); 347 return; 348 case SDHCI_POWER_CONTROL: 349 return; 350 case SDHCI_SOFTWARE_RESET: 351 val &= ~SDHCI_RESET_ALL; 352 /* FALLTHROUGH. */ 353 default: 354 val32 = RD4(sc, off & ~3); 355 val32 &= ~(UINT8_MAX << (off & 3) * 8); 356 val32 |= (val << (off & 3) * 8); 357 WR4(sc, off & ~3, val32); 358 return; 359 } 360 } 361 362 static void 363 sdhci_fsl_fdt_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 364 uint16_t val) 365 { 366 struct sdhci_fsl_fdt_softc *sc; 367 uint32_t val32; 368 369 sc = device_get_softc(dev); 370 371 switch (off) { 372 case SDHCI_CLOCK_CONTROL: 373 fsl_sdhc_fdt_set_clock(sc, val); 374 return; 375 /* 376 * eSDHC hardware combines command and mode into a single 377 * register. Cache it here, so that command isn't written 378 * until after mode. 379 */ 380 case SDHCI_TRANSFER_MODE: 381 sc->cmd_and_mode = val; 382 return; 383 case SDHCI_COMMAND_FLAGS: 384 sc->cmd_and_mode = 385 (sc->cmd_and_mode & UINT16_MAX) | (val << 16); 386 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 387 sc->cmd_and_mode = 0; 388 return; 389 default: 390 val32 = RD4(sc, off & ~3); 391 val32 &= ~(UINT16_MAX << (off & 3) * 8); 392 val32 |= ((val & UINT16_MAX) << (off & 3) * 8); 393 WR4(sc, off & ~3, val32); 394 return; 395 } 396 } 397 398 static void 399 sdhci_fsl_fdt_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 400 uint32_t val) 401 { 402 struct sdhci_fsl_fdt_softc *sc; 403 404 sc = device_get_softc(dev); 405 406 switch (off) { 407 case SDHCI_BUFFER: 408 bus_write_4(sc->mem_res, off, val); 409 return; 410 /* 411 * eSDHC hardware lacks support for the SDMA buffer boundary 412 * feature and instead generates SDHCI_INT_DMA_END interrupts 413 * after each completed DMA data transfer. 414 * Since this duplicates the SDHCI_INT_DATA_END functionality, 415 * mask out the unneeded SDHCI_INT_DMA_END interrupt. 416 */ 417 case SDHCI_INT_ENABLE: 418 case SDHCI_SIGNAL_ENABLE: 419 val &= ~SDHCI_INT_DMA_END; 420 /* FALLTHROUGH. */ 421 default: 422 WR4(sc, off, val); 423 return; 424 } 425 } 426 427 static void 428 sdhci_fsl_fdt_write_multi_4(device_t dev, struct sdhci_slot *slot, 429 bus_size_t off, uint32_t *data, bus_size_t count) 430 { 431 struct sdhci_fsl_fdt_softc *sc; 432 433 sc = device_get_softc(dev); 434 bus_write_multi_4(sc->mem_res, off, data, count); 435 } 436 437 static void 438 sdhci_fsl_fdt_irq(void *arg) 439 { 440 struct sdhci_fsl_fdt_softc *sc; 441 442 sc = arg; 443 sdhci_generic_intr(&sc->slot); 444 return; 445 } 446 447 static int 448 sdhci_fsl_fdt_update_ios(device_t brdev, device_t reqdev) 449 { 450 int err; 451 struct sdhci_fsl_fdt_softc *sc; 452 struct mmc_ios *ios; 453 struct sdhci_slot *slot; 454 455 err = sdhci_generic_update_ios(brdev, reqdev); 456 if (err != 0) 457 return (err); 458 459 sc = device_get_softc(brdev); 460 slot = device_get_ivars(reqdev); 461 ios = &slot->host.ios; 462 463 switch (ios->power_mode) { 464 case power_on: 465 break; 466 case power_off: 467 if (bootverbose) 468 device_printf(sc->dev, "Powering down sd/mmc\n"); 469 470 if (sc->fdt_helper.vmmc_supply) 471 regulator_disable(sc->fdt_helper.vmmc_supply); 472 if (sc->fdt_helper.vqmmc_supply) 473 regulator_disable(sc->fdt_helper.vqmmc_supply); 474 break; 475 case power_up: 476 if (bootverbose) 477 device_printf(sc->dev, "Powering up sd/mmc\n"); 478 479 if (sc->fdt_helper.vmmc_supply) 480 regulator_enable(sc->fdt_helper.vmmc_supply); 481 if (sc->fdt_helper.vqmmc_supply) 482 regulator_enable(sc->fdt_helper.vqmmc_supply); 483 break; 484 }; 485 486 return (0); 487 } 488 489 static int 490 sdhci_fsl_fdt_switch_vccq(device_t brdev, device_t reqdev) 491 { 492 struct sdhci_fsl_fdt_softc *sc; 493 struct sdhci_slot *slot; 494 int uvolt, err; 495 496 sc = device_get_softc(brdev); 497 498 if (sc->fdt_helper.vqmmc_supply == NULL) 499 return EOPNOTSUPP; 500 501 err = sdhci_generic_switch_vccq(brdev, reqdev); 502 if (err != 0) 503 return (err); 504 505 slot = device_get_ivars(reqdev); 506 switch (slot->host.ios.vccq) { 507 case vccq_180: 508 uvolt = 1800000; 509 break; 510 case vccq_330: 511 uvolt = 3300000; 512 break; 513 default: 514 return EINVAL; 515 } 516 517 err = regulator_set_voltage(sc->fdt_helper.vqmmc_supply, uvolt, uvolt); 518 if (err != 0) { 519 device_printf(sc->dev, 520 "Cannot set vqmmc to %d<->%d\n", uvolt, uvolt); 521 return (err); 522 } 523 524 return (0); 525 } 526 527 static int 528 sdhci_fsl_fdt_get_ro(device_t bus, device_t child) 529 { 530 struct sdhci_fsl_fdt_softc *sc; 531 532 sc = device_get_softc(bus); 533 return (sdhci_fdt_gpio_get_readonly(sc->gpio)); 534 } 535 536 static bool 537 sdhci_fsl_fdt_get_card_present(device_t dev, struct sdhci_slot *slot) 538 { 539 struct sdhci_fsl_fdt_softc *sc; 540 541 sc = device_get_softc(dev); 542 return (sdhci_fdt_gpio_get_present(sc->gpio)); 543 } 544 545 static uint32_t 546 sdhci_fsl_fdt_vddrange_to_mask(device_t dev, uint32_t *vdd_ranges, int len) 547 { 548 uint32_t vdd_min, vdd_max; 549 uint32_t vdd_mask = 0; 550 int i; 551 552 /* Ranges are organized as pairs of values. */ 553 if ((len % 2) != 0) { 554 device_printf(dev, "Invalid voltage range\n"); 555 return (0); 556 } 557 len = len / 2; 558 559 for (i = 0; i < len; i++) { 560 vdd_min = vdd_ranges[2 * i]; 561 vdd_max = vdd_ranges[2 * i + 1]; 562 563 if (vdd_min > vdd_max || vdd_min < 1650 || vdd_min > 3600 || 564 vdd_max < 1650 || vdd_max > 3600) { 565 device_printf(dev, "Voltage range %d - %d is out of bounds\n", 566 vdd_min, vdd_max); 567 return (0); 568 } 569 570 if (vdd_min <= 1800 && vdd_max >= 1800) 571 vdd_mask |= SDHCI_CAN_VDD_180; 572 if (vdd_min <= 3000 && vdd_max >= 3000) 573 vdd_mask |= SDHCI_CAN_VDD_300; 574 if (vdd_min <= 3300 && vdd_max >= 3300) 575 vdd_mask |= SDHCI_CAN_VDD_330; 576 } 577 578 return (vdd_mask); 579 } 580 581 static void 582 sdhci_fsl_fdt_of_parse(device_t dev) 583 { 584 struct sdhci_fsl_fdt_softc *sc; 585 phandle_t node; 586 pcell_t *voltage_ranges; 587 uint32_t vdd_mask = 0; 588 ssize_t num_ranges; 589 590 sc = device_get_softc(dev); 591 node = ofw_bus_get_node(dev); 592 593 /* Call mmc_fdt_parse in order to get mmc related properties. */ 594 mmc_fdt_parse(dev, node, &sc->fdt_helper, &sc->slot.host); 595 596 sc->slot.caps = sdhci_fsl_fdt_read_4(dev, &sc->slot, 597 SDHCI_CAPABILITIES) & ~(SDHCI_CAN_DO_SUSPEND); 598 sc->slot.caps2 = sdhci_fsl_fdt_read_4(dev, &sc->slot, 599 SDHCI_CAPABILITIES2); 600 601 /* Parse the "voltage-ranges" dts property. */ 602 num_ranges = OF_getencprop_alloc(node, "voltage-ranges", 603 (void **) &voltage_ranges); 604 if (num_ranges <= 0) 605 return; 606 vdd_mask = sdhci_fsl_fdt_vddrange_to_mask(dev, voltage_ranges, 607 num_ranges / sizeof(uint32_t)); 608 OF_prop_free(voltage_ranges); 609 610 /* Overwrite voltage caps only if we got something from dts. */ 611 if (vdd_mask != 0 && 612 (vdd_mask != (sc->slot.caps & SDHCI_FSL_CAN_VDD_MASK))) { 613 sc->slot.caps &= ~(SDHCI_FSL_CAN_VDD_MASK); 614 sc->slot.caps |= vdd_mask; 615 sc->slot.quirks |= SDHCI_QUIRK_MISSING_CAPS; 616 } 617 } 618 619 static int 620 sdhci_fsl_fdt_attach(device_t dev) 621 { 622 struct sdhci_fsl_fdt_softc *sc; 623 struct mmc_host *host; 624 uint32_t val, buf_order; 625 uintptr_t ocd_data; 626 uint64_t clk_hz; 627 phandle_t node; 628 int rid, ret; 629 clk_t clk; 630 631 node = ofw_bus_get_node(dev); 632 sc = device_get_softc(dev); 633 ocd_data = ofw_bus_search_compatible(dev, 634 sdhci_fsl_fdt_compat_data)->ocd_data; 635 sc->soc_data = (struct sdhci_fsl_fdt_soc_data *)ocd_data; 636 sc->dev = dev; 637 sc->slot.quirks = sc->soc_data->quirks; 638 host = &sc->slot.host; 639 640 rid = 0; 641 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 642 RF_ACTIVE); 643 if (sc->mem_res == NULL) { 644 device_printf(dev, 645 "Could not allocate resources for controller\n"); 646 return (ENOMEM); 647 } 648 649 rid = 0; 650 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 651 RF_ACTIVE); 652 if (sc->irq_res == NULL) { 653 device_printf(dev, 654 "Could not allocate irq resources for controller\n"); 655 ret = ENOMEM; 656 goto err_free_mem; 657 } 658 659 ret = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 660 NULL, sdhci_fsl_fdt_irq, sc, &sc->irq_cookie); 661 if (ret != 0) { 662 device_printf(dev, "Could not setup IRQ handler\n"); 663 goto err_free_irq_res; 664 } 665 666 ret = clk_get_by_ofw_index(dev, node, 0, &clk); 667 if (ret != 0) { 668 device_printf(dev, "Parent clock not found\n"); 669 goto err_free_irq; 670 } 671 672 ret = clk_get_freq(clk, &clk_hz); 673 if (ret != 0) { 674 device_printf(dev, 675 "Could not get parent clock frequency\n"); 676 goto err_free_irq; 677 } 678 679 sc->baseclk_hz = clk_hz / sc->soc_data->baseclk_div; 680 681 /* Figure out eSDHC block endianness before we touch any HW regs. */ 682 if (OF_hasprop(node, "little-endian")) { 683 sc->read = read_le; 684 sc->write = write_le; 685 buf_order = SDHCI_FSL_PROT_CTRL_BYTE_NATIVE; 686 } else { 687 sc->read = read_be; 688 sc->write = write_be; 689 buf_order = SDHCI_FSL_PROT_CTRL_BYTE_SWAP; 690 } 691 692 sdhci_fsl_fdt_of_parse(dev); 693 sc->maxclk_hz = host->f_max ? host->f_max : sc->baseclk_hz; 694 695 /* 696 * Setting this register affects byte order in SDHCI_BUFFER only. 697 * If the eSDHC block is connected over a big-endian bus, the data 698 * read from/written to the buffer will be already byte swapped. 699 * In such a case, setting SDHCI_FSL_PROT_CTRL_BYTE_SWAP will convert 700 * the byte order again, resulting in a native byte order. 701 * The read/write callbacks accommodate for this behavior. 702 */ 703 val = RD4(sc, SDHCI_FSL_PROT_CTRL); 704 val &= ~SDHCI_FSL_PROT_CTRL_BYTE_MASK; 705 WR4(sc, SDHCI_FSL_PROT_CTRL, val | buf_order); 706 707 /* 708 * Gate the SD clock and set its source to 709 * peripheral clock / baseclk_div. The frequency in baseclk_hz is set 710 * to match this. 711 */ 712 val = RD4(sc, SDHCI_CLOCK_CONTROL); 713 WR4(sc, SDHCI_CLOCK_CONTROL, val & ~SDHCI_FSL_CLK_SDCLKEN); 714 val = RD4(sc, SDHCI_FSL_ESDHC_CTRL); 715 WR4(sc, SDHCI_FSL_ESDHC_CTRL, val | SDHCI_FSL_ESDHC_CTRL_CLK_DIV2); 716 sc->slot.max_clk = sc->maxclk_hz; 717 sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot); 718 719 /* 720 * Set the buffer watermark level to 128 words (512 bytes) for both 721 * read and write. The hardware has a restriction that when the read or 722 * write ready status is asserted, that means you can read exactly the 723 * number of words set in the watermark register before you have to 724 * re-check the status and potentially wait for more data. The main 725 * sdhci driver provides no hook for doing status checking on less than 726 * a full block boundary, so we set the watermark level to be a full 727 * block. Reads and writes where the block size is less than the 728 * watermark size will work correctly too, no need to change the 729 * watermark for different size blocks. However, 128 is the maximum 730 * allowed for the watermark, so PIO is limitted to 512 byte blocks. 731 */ 732 WR4(sc, SDHCI_FSL_WTMK_LVL, SDHCI_FSL_WTMK_WR_512B | 733 SDHCI_FSL_WTMK_RD_512B); 734 735 ret = sdhci_init_slot(dev, &sc->slot, 0); 736 if (ret != 0) 737 goto err_free_gpio; 738 sc->slot_init_done = true; 739 sdhci_start_slot(&sc->slot); 740 741 return (bus_generic_attach(dev)); 742 743 err_free_gpio: 744 sdhci_fdt_gpio_teardown(sc->gpio); 745 err_free_irq: 746 bus_teardown_intr(dev, sc->irq_res, sc->irq_cookie); 747 err_free_irq_res: 748 bus_free_resource(dev, SYS_RES_IRQ, sc->irq_res); 749 err_free_mem: 750 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 751 return (ret); 752 } 753 754 static int 755 sdhci_fsl_fdt_detach(device_t dev) 756 { 757 struct sdhci_fsl_fdt_softc *sc; 758 759 sc = device_get_softc(dev); 760 if (sc->slot_init_done) 761 sdhci_cleanup_slot(&sc->slot); 762 if (sc->gpio != NULL) 763 sdhci_fdt_gpio_teardown(sc->gpio); 764 if (sc->irq_cookie != NULL) 765 bus_teardown_intr(dev, sc->irq_res, sc->irq_cookie); 766 if (sc->irq_res != NULL) 767 bus_free_resource(dev, SYS_RES_IRQ, sc->irq_res); 768 if (sc->mem_res != NULL) 769 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 770 return (0); 771 } 772 773 static int 774 sdhci_fsl_fdt_probe(device_t dev) 775 { 776 777 if (!ofw_bus_status_okay(dev)) 778 return (ENXIO); 779 780 if (!ofw_bus_search_compatible(dev, 781 sdhci_fsl_fdt_compat_data)->ocd_data) 782 return (ENXIO); 783 784 device_set_desc(dev, "NXP QorIQ Layerscape eSDHC controller"); 785 return (BUS_PROBE_DEFAULT); 786 } 787 788 static int 789 sdhci_fsl_fdt_read_ivar(device_t bus, device_t child, int which, 790 uintptr_t *result) 791 { 792 struct sdhci_slot *slot = device_get_ivars(child); 793 794 if (which == MMCBR_IVAR_MAX_DATA && (slot->opt & SDHCI_HAVE_DMA)) { 795 /* 796 * In the absence of SDMA buffer boundary functionality, 797 * limit the maximum data length per read/write command 798 * to bounce buffer size. 799 */ 800 *result = howmany(slot->sdma_bbufsz, 512); 801 return (0); 802 } 803 return (sdhci_generic_read_ivar(bus, child, which, result)); 804 } 805 806 static const device_method_t sdhci_fsl_fdt_methods[] = { 807 /* Device interface. */ 808 DEVMETHOD(device_probe, sdhci_fsl_fdt_probe), 809 DEVMETHOD(device_attach, sdhci_fsl_fdt_attach), 810 DEVMETHOD(device_detach, sdhci_fsl_fdt_detach), 811 812 /* Bus interface. */ 813 DEVMETHOD(bus_read_ivar, sdhci_fsl_fdt_read_ivar), 814 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 815 816 /* MMC bridge interface. */ 817 DEVMETHOD(mmcbr_request, sdhci_generic_request), 818 DEVMETHOD(mmcbr_get_ro, sdhci_fsl_fdt_get_ro), 819 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 820 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 821 DEVMETHOD(mmcbr_switch_vccq, sdhci_fsl_fdt_switch_vccq), 822 DEVMETHOD(mmcbr_update_ios, sdhci_fsl_fdt_update_ios), 823 824 /* SDHCI accessors. */ 825 DEVMETHOD(sdhci_read_1, sdhci_fsl_fdt_read_1), 826 DEVMETHOD(sdhci_read_2, sdhci_fsl_fdt_read_2), 827 DEVMETHOD(sdhci_read_4, sdhci_fsl_fdt_read_4), 828 DEVMETHOD(sdhci_read_multi_4, sdhci_fsl_fdt_read_multi_4), 829 DEVMETHOD(sdhci_write_1, sdhci_fsl_fdt_write_1), 830 DEVMETHOD(sdhci_write_2, sdhci_fsl_fdt_write_2), 831 DEVMETHOD(sdhci_write_4, sdhci_fsl_fdt_write_4), 832 DEVMETHOD(sdhci_write_multi_4, sdhci_fsl_fdt_write_multi_4), 833 DEVMETHOD(sdhci_get_card_present, sdhci_fsl_fdt_get_card_present), 834 DEVMETHOD_END 835 }; 836 837 static devclass_t sdhci_fsl_fdt_devclass; 838 static driver_t sdhci_fsl_fdt_driver = { 839 "sdhci_fsl_fdt", 840 sdhci_fsl_fdt_methods, 841 sizeof(struct sdhci_fsl_fdt_softc), 842 }; 843 844 DRIVER_MODULE(sdhci_fsl_fdt, simplebus, sdhci_fsl_fdt_driver, 845 sdhci_fsl_fdt_devclass, NULL, NULL); 846 SDHCI_DEPEND(sdhci_fsl_fdt); 847 848 #ifndef MMCCAM 849 MMC_DECLARE_BRIDGE(sdhci_fsl_fdt); 850 #endif 851