1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2008-2009 Semihalf, Piotr Ziecik 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 21 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 22 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 23 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 24 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #ifndef _SEC_H 31 #define _SEC_H 32 33 /* 34 * Each SEC channel can hold up to 24 descriptors. All 4 channels can be 35 * simultaneously active holding 96 descriptors. Each descriptor can use 0 or 36 * more link table entries depending of size and granulation of input/output 37 * data. One link table entry is needed for each 65535 bytes of data. 38 */ 39 40 /* Driver settings */ 41 #define SEC_TIMEOUT 100000 42 #define SEC_MAX_SESSIONS 256 43 #define SEC_DESCRIPTORS 256 /* Must be power of 2 */ 44 #define SEC_LT_ENTRIES 1024 /* Must be power of 2 */ 45 #define SEC_MAX_IV_LEN 16 46 #define SEC_MAX_KEY_LEN 64 47 48 /* SEC information */ 49 #define SEC_20_ID 0x0000000000000040ULL 50 #define SEC_30_ID 0x0030030000000000ULL 51 #define SEC_31_ID 0x0030030100000000ULL 52 #define SEC_CHANNELS 4 53 #define SEC_POINTERS 7 54 #define SEC_MAX_DMA_BLOCK_SIZE 0xFFFF 55 #define SEC_MAX_FIFO_LEVEL 24 56 #define SEC_DMA_ALIGNMENT 8 57 58 #define __packed__ __attribute__ ((__packed__)) 59 60 struct sec_softc; 61 struct sec_session; 62 63 /* SEC descriptor definition */ 64 struct sec_hw_desc_ptr { 65 u_int shdp_length : 16; 66 u_int shdp_j : 1; 67 u_int shdp_extent : 7; 68 u_int __padding0 : 4; 69 uint64_t shdp_ptr : 36; 70 } __packed__; 71 72 struct sec_hw_desc { 73 union __packed__ { 74 struct __packed__ { 75 u_int eu_sel0 : 4; 76 u_int mode0 : 8; 77 u_int eu_sel1 : 4; 78 u_int mode1 : 8; 79 u_int desc_type : 5; 80 u_int __padding0 : 1; 81 u_int dir : 1; 82 u_int dn : 1; 83 u_int __padding1 : 32; 84 } request; 85 struct __packed__ { 86 u_int done : 8; 87 u_int __padding0 : 27; 88 u_int iccr0 : 2; 89 u_int __padding1 : 6; 90 u_int iccr1 : 2; 91 u_int __padding2 : 19; 92 } feedback; 93 } shd_control; 94 95 struct sec_hw_desc_ptr shd_pointer[SEC_POINTERS]; 96 97 /* Data below is mapped to descriptor pointers */ 98 uint8_t shd_iv[SEC_MAX_IV_LEN]; 99 uint8_t shd_key[SEC_MAX_KEY_LEN]; 100 uint8_t shd_mkey[SEC_MAX_KEY_LEN]; 101 } __packed__; 102 103 #define shd_eu_sel0 shd_control.request.eu_sel0 104 #define shd_mode0 shd_control.request.mode0 105 #define shd_eu_sel1 shd_control.request.eu_sel1 106 #define shd_mode1 shd_control.request.mode1 107 #define shd_desc_type shd_control.request.desc_type 108 #define shd_dir shd_control.request.dir 109 #define shd_dn shd_control.request.dn 110 #define shd_done shd_control.feedback.done 111 #define shd_iccr0 shd_control.feedback.iccr0 112 #define shd_iccr1 shd_control.feedback.iccr1 113 114 /* SEC link table entries definition */ 115 struct sec_hw_lt { 116 u_int shl_length : 16; 117 u_int __padding0 : 6; 118 u_int shl_r : 1; 119 u_int shl_n : 1; 120 u_int __padding1 : 4; 121 uint64_t shl_ptr : 36; 122 } __packed__; 123 124 struct sec_dma_mem { 125 void *dma_vaddr; 126 bus_addr_t dma_paddr; 127 bus_dma_tag_t dma_tag; 128 bus_dmamap_t dma_map; 129 u_int dma_is_map; 130 }; 131 132 struct sec_desc { 133 struct sec_hw_desc *sd_desc; 134 bus_addr_t sd_desc_paddr; 135 struct sec_dma_mem sd_ptr_dmem[SEC_POINTERS]; 136 struct cryptop *sd_crp; 137 u_int sd_lt_used; 138 u_int sd_error; 139 }; 140 141 struct sec_lt { 142 struct sec_hw_lt *sl_lt; 143 bus_addr_t sl_lt_paddr; 144 }; 145 146 struct sec_eu_methods { 147 int (*sem_newsession)(struct sec_softc *sc, 148 struct sec_session *ses, struct cryptoini *enc, 149 struct cryptoini *mac); 150 int (*sem_make_desc)(struct sec_softc *sc, 151 struct sec_session *ses, struct sec_desc *desc, 152 struct cryptop *crp, int buftype); 153 }; 154 155 struct sec_session { 156 struct sec_eu_methods *ss_eu; 157 uint8_t ss_key[SEC_MAX_KEY_LEN]; 158 uint8_t ss_mkey[SEC_MAX_KEY_LEN]; 159 u_int ss_klen; 160 u_int ss_mklen; 161 u_int ss_ivlen; 162 }; 163 164 struct sec_desc_map_info { 165 struct sec_softc *sdmi_sc; 166 bus_size_t sdmi_size; 167 bus_size_t sdmi_offset; 168 struct sec_lt *sdmi_lt_first; 169 struct sec_lt *sdmi_lt_last; 170 u_int sdmi_lt_used; 171 }; 172 173 struct sec_softc { 174 device_t sc_dev; 175 int32_t sc_cid; 176 int sc_blocked; 177 int sc_shutdown; 178 u_int sc_version; 179 180 uint64_t sc_int_error_mask; 181 uint64_t sc_channel_idle_mask; 182 183 struct mtx sc_controller_lock; 184 struct mtx sc_descriptors_lock; 185 186 struct sec_desc sc_desc[SEC_DESCRIPTORS]; 187 u_int sc_free_desc_get_cnt; 188 u_int sc_free_desc_put_cnt; 189 u_int sc_ready_desc_get_cnt; 190 u_int sc_ready_desc_put_cnt; 191 u_int sc_queued_desc_get_cnt; 192 u_int sc_queued_desc_put_cnt; 193 194 struct sec_lt sc_lt[SEC_LT_ENTRIES + 1]; 195 u_int sc_lt_alloc_cnt; 196 u_int sc_lt_free_cnt; 197 198 struct sec_dma_mem sc_desc_dmem; /* descriptors DMA memory */ 199 struct sec_dma_mem sc_lt_dmem; /* link tables DMA memory */ 200 201 struct resource *sc_rres; /* register resource */ 202 int sc_rrid; /* register rid */ 203 struct { 204 bus_space_tag_t bst; 205 bus_space_handle_t bsh; 206 } sc_bas; 207 208 struct resource *sc_pri_ires; /* primary irq resource */ 209 void *sc_pri_ihand; /* primary irq handler */ 210 int sc_pri_irid; /* primary irq resource id */ 211 212 struct resource *sc_sec_ires; /* secondary irq resource */ 213 void *sc_sec_ihand; /* secondary irq handler */ 214 int sc_sec_irid; /* secondary irq resource id */ 215 }; 216 217 /* Locking macros */ 218 #define SEC_LOCK(sc, what) \ 219 mtx_lock(&(sc)->sc_ ## what ## _lock) 220 #define SEC_UNLOCK(sc, what) \ 221 mtx_unlock(&(sc)->sc_ ## what ## _lock) 222 #define SEC_LOCK_ASSERT(sc, what) \ 223 mtx_assert(&(sc)->sc_ ## what ## _lock, MA_OWNED) 224 225 /* Read/Write definitions */ 226 #define SEC_READ(sc, reg) \ 227 bus_space_read_8((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg)) 228 #define SEC_WRITE(sc, reg, val) \ 229 bus_space_write_8((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg), (val)) 230 231 /* Base allocation macros (warning: wrap must be 2^n) */ 232 #define SEC_CNT_INIT(sc, cnt, wrap) \ 233 (((sc)->cnt) = ((wrap) - 1)) 234 #define SEC_ADD(sc, cnt, wrap, val) \ 235 ((sc)->cnt = (((sc)->cnt) + (val)) & ((wrap) - 1)) 236 #define SEC_INC(sc, cnt, wrap) \ 237 SEC_ADD(sc, cnt, wrap, 1) 238 #define SEC_DEC(sc, cnt, wrap) \ 239 SEC_ADD(sc, cnt, wrap, -1) 240 #define SEC_GET_GENERIC(sc, tab, cnt, wrap) \ 241 ((sc)->tab[SEC_INC(sc, cnt, wrap)]) 242 #define SEC_PUT_GENERIC(sc, tab, cnt, wrap, val) \ 243 ((sc)->tab[SEC_INC(sc, cnt, wrap)] = val) 244 245 /* Interface for descriptors */ 246 #define SEC_GET_FREE_DESC(sc) \ 247 &SEC_GET_GENERIC(sc, sc_desc, sc_free_desc_get_cnt, SEC_DESCRIPTORS) 248 249 #define SEC_PUT_BACK_FREE_DESC(sc) \ 250 SEC_DEC(sc, sc_free_desc_get_cnt, SEC_DESCRIPTORS) 251 252 #define SEC_DESC_FREE2READY(sc) \ 253 SEC_INC(sc, sc_ready_desc_put_cnt, SEC_DESCRIPTORS) 254 255 #define SEC_GET_READY_DESC(sc) \ 256 &SEC_GET_GENERIC(sc, sc_desc, sc_ready_desc_get_cnt, SEC_DESCRIPTORS) 257 258 #define SEC_PUT_BACK_READY_DESC(sc) \ 259 SEC_DEC(sc, sc_ready_desc_get_cnt, SEC_DESCRIPTORS) 260 261 #define SEC_DESC_READY2QUEUED(sc) \ 262 SEC_INC(sc, sc_queued_desc_put_cnt, SEC_DESCRIPTORS) 263 264 #define SEC_GET_QUEUED_DESC(sc) \ 265 &SEC_GET_GENERIC(sc, sc_desc, sc_queued_desc_get_cnt, SEC_DESCRIPTORS) 266 267 #define SEC_PUT_BACK_QUEUED_DESC(sc) \ 268 SEC_DEC(sc, sc_queued_desc_get_cnt, SEC_DESCRIPTORS) 269 270 #define SEC_DESC_QUEUED2FREE(sc) \ 271 SEC_INC(sc, sc_free_desc_put_cnt, SEC_DESCRIPTORS) 272 273 #define SEC_FREE_DESC_CNT(sc) \ 274 (((sc)->sc_free_desc_put_cnt - (sc)->sc_free_desc_get_cnt - 1) \ 275 & (SEC_DESCRIPTORS - 1)) 276 277 #define SEC_READY_DESC_CNT(sc) \ 278 (((sc)->sc_ready_desc_put_cnt - (sc)->sc_ready_desc_get_cnt) & \ 279 (SEC_DESCRIPTORS - 1)) 280 281 #define SEC_QUEUED_DESC_CNT(sc) \ 282 (((sc)->sc_queued_desc_put_cnt - (sc)->sc_queued_desc_get_cnt) \ 283 & (SEC_DESCRIPTORS - 1)) 284 285 #define SEC_DESC_SYNC(sc, mode) do { \ 286 sec_sync_dma_mem(&((sc)->sc_desc_dmem), (mode)); \ 287 sec_sync_dma_mem(&((sc)->sc_lt_dmem), (mode)); \ 288 } while (0) 289 290 #define SEC_DESC_SYNC_POINTERS(desc, mode) do { \ 291 u_int i; \ 292 for (i = 0; i < SEC_POINTERS; i++) \ 293 sec_sync_dma_mem(&((desc)->sd_ptr_dmem[i]), (mode)); \ 294 } while (0) 295 296 #define SEC_DESC_FREE_POINTERS(desc) do { \ 297 u_int i; \ 298 for (i = 0; i < SEC_POINTERS; i++) \ 299 sec_free_dma_mem(&(desc)->sd_ptr_dmem[i]); \ 300 } while (0); 301 302 #define SEC_DESC_PUT_BACK_LT(sc, desc) \ 303 SEC_PUT_BACK_LT(sc, (desc)->sd_lt_used) 304 305 #define SEC_DESC_FREE_LT(sc, desc) \ 306 SEC_FREE_LT(sc, (desc)->sd_lt_used) 307 308 /* Interface for link tables */ 309 #define SEC_ALLOC_LT_ENTRY(sc) \ 310 &SEC_GET_GENERIC(sc, sc_lt, sc_lt_alloc_cnt, SEC_LT_ENTRIES) 311 312 #define SEC_PUT_BACK_LT(sc, num) \ 313 SEC_ADD(sc, sc_lt_alloc_cnt, SEC_LT_ENTRIES, -(num)) 314 315 #define SEC_FREE_LT(sc, num) \ 316 SEC_ADD(sc, sc_lt_free_cnt, SEC_LT_ENTRIES, num) 317 318 #define SEC_FREE_LT_CNT(sc) \ 319 (((sc)->sc_lt_free_cnt - (sc)->sc_lt_alloc_cnt - 1) \ 320 & (SEC_LT_ENTRIES - 1)) 321 322 /* DMA Maping defines */ 323 #define SEC_MEMORY 0 324 #define SEC_UIO 1 325 #define SEC_MBUF 2 326 327 /* Size of SEC registers area */ 328 #define SEC_IO_SIZE 0x10000 329 330 /* SEC Controller registers */ 331 #define SEC_IER 0x1008 332 #define SEC_INT_CH_DN(n) (1ULL << (((n) * 2) + 32)) 333 #define SEC_INT_CH_ERR(n) (1ULL << (((n) * 2) + 33)) 334 #define SEC_INT_ITO (1ULL << 55) 335 336 #define SEC_ISR 0x1010 337 #define SEC_ICR 0x1018 338 #define SEC_ID 0x1020 339 340 #define SEC_EUASR 0x1028 341 #define SEC_EUASR_RNGU(r) (((r) >> 0) & 0xF) 342 #define SEC_EUASR_PKEU(r) (((r) >> 8) & 0xF) 343 #define SEC_EUASR_KEU(r) (((r) >> 16) & 0xF) 344 #define SEC_EUASR_CRCU(r) (((r) >> 20) & 0xF) 345 #define SEC_EUASR_DEU(r) (((r) >> 32) & 0xF) 346 #define SEC_EUASR_AESU(r) (((r) >> 40) & 0xF) 347 #define SEC_EUASR_MDEU(r) (((r) >> 48) & 0xF) 348 #define SEC_EUASR_AFEU(r) (((r) >> 56) & 0xF) 349 350 #define SEC_MCR 0x1030 351 #define SEC_MCR_SWR (1ULL << 32) 352 353 /* SEC Channel registers */ 354 #define SEC_CHAN_CCR(n) (((n) * 0x100) + 0x1108) 355 #define SEC_CHAN_CCR_CDIE (1ULL << 1) 356 #define SEC_CHAN_CCR_NT (1ULL << 2) 357 #define SEC_CHAN_CCR_AWSE (1ULL << 3) 358 #define SEC_CHAN_CCR_CDWE (1ULL << 4) 359 #define SEC_CHAN_CCR_BS (1ULL << 8) 360 #define SEC_CHAN_CCR_WGN (1ULL << 13) 361 #define SEC_CHAN_CCR_R (1ULL << 32) 362 #define SEC_CHAN_CCR_CON (1ULL << 33) 363 364 #define SEC_CHAN_CSR(n) (((n) * 0x100) + 0x1110) 365 #define SEC_CHAN_CSR2_FFLVL_M 0x1FULL 366 #define SEC_CHAN_CSR2_FFLVL_S 56 367 #define SEC_CHAN_CSR2_GSTATE_M 0x0FULL 368 #define SEC_CHAN_CSR2_GSTATE_S 48 369 #define SEC_CHAN_CSR2_PSTATE_M 0x0FULL 370 #define SEC_CHAN_CSR2_PSTATE_S 40 371 #define SEC_CHAN_CSR2_MSTATE_M 0x3FULL 372 #define SEC_CHAN_CSR2_MSTATE_S 32 373 #define SEC_CHAN_CSR3_FFLVL_M 0x1FULL 374 #define SEC_CHAN_CSR3_FFLVL_S 24 375 #define SEC_CHAN_CSR3_MSTATE_M 0x1FFULL 376 #define SEC_CHAN_CSR3_MSTATE_S 32 377 #define SEC_CHAN_CSR3_PSTATE_M 0x7FULL 378 #define SEC_CHAN_CSR3_PSTATE_S 48 379 #define SEC_CHAN_CSR3_GSTATE_M 0x7FULL 380 #define SEC_CHAN_CSR3_GSTATE_S 56 381 382 #define SEC_CHAN_CDPR(n) (((n) * 0x100) + 0x1140) 383 #define SEC_CHAN_FF(n) (((n) * 0x100) + 0x1148) 384 385 /* SEC Execution Units numbers */ 386 #define SEC_EU_NONE 0x0 387 #define SEC_EU_AFEU 0x1 388 #define SEC_EU_DEU 0x2 389 #define SEC_EU_MDEU_A 0x3 390 #define SEC_EU_MDEU_B 0xB 391 #define SEC_EU_RNGU 0x4 392 #define SEC_EU_PKEU 0x5 393 #define SEC_EU_AESU 0x6 394 #define SEC_EU_KEU 0x7 395 #define SEC_EU_CRCU 0x8 396 397 /* SEC descriptor types */ 398 #define SEC_DT_COMMON_NONSNOOP 0x02 399 #define SEC_DT_HMAC_SNOOP 0x04 400 401 /* SEC AESU declarations and definitions */ 402 #define SEC_AESU_MODE_ED (1ULL << 0) 403 #define SEC_AESU_MODE_CBC (1ULL << 1) 404 405 /* SEC DEU declarations and definitions */ 406 #define SEC_DEU_MODE_ED (1ULL << 0) 407 #define SEC_DEU_MODE_TS (1ULL << 1) 408 #define SEC_DEU_MODE_CBC (1ULL << 2) 409 410 /* SEC MDEU declarations and definitions */ 411 #define SEC_HMAC_HASH_LEN 12 412 #define SEC_MDEU_MODE_SHA1 0x00 /* MDEU A */ 413 #define SEC_MDEU_MODE_SHA384 0x00 /* MDEU B */ 414 #define SEC_MDEU_MODE_SHA256 0x01 415 #define SEC_MDEU_MODE_MD5 0x02 /* MDEU A */ 416 #define SEC_MDEU_MODE_SHA512 0x02 /* MDEU B */ 417 #define SEC_MDEU_MODE_SHA224 0x03 418 #define SEC_MDEU_MODE_PD (1ULL << 2) 419 #define SEC_MDEU_MODE_HMAC (1ULL << 3) 420 #define SEC_MDEU_MODE_INIT (1ULL << 4) 421 #define SEC_MDEU_MODE_SMAC (1ULL << 5) 422 #define SEC_MDEU_MODE_CICV (1ULL << 6) 423 #define SEC_MDEU_MODE_CONT (1ULL << 7) 424 425 #endif 426