xref: /freebsd/sys/dev/sec/sec.h (revision aa0a1e58)
1 /*-
2  * Copyright (C) 2008-2009 Semihalf, Piotr Ziecik
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
17  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
18  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
19  * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
20  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
21  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
22  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
23  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24  *
25  * $FreeBSD$
26  */
27 
28 #ifndef	_SEC_H
29 #define _SEC_H
30 
31 /*
32  * Each SEC channel can hold up to 24 descriptors. All 4 channels can be
33  * simultaneously active holding 96 descriptors. Each descriptor can use 0 or
34  * more link table entries depending of size and granulation of input/output
35  * data. One link table entry is needed for each 65535 bytes of data.
36  */
37 
38 /* Driver settings */
39 #define SEC_TIMEOUT			100000
40 #define SEC_MAX_SESSIONS		256
41 #define SEC_DESCRIPTORS			256	/* Must be power of 2 */
42 #define SEC_LT_ENTRIES			1024	/* Must be power of 2 */
43 #define SEC_MAX_IV_LEN			16
44 #define SEC_MAX_KEY_LEN			64
45 
46 /* SEC information */
47 #define SEC_20_ID			0x0000000000000040ULL
48 #define SEC_30_ID			0x0030030000000000ULL
49 #define SEC_CHANNELS			4
50 #define SEC_POINTERS			7
51 #define SEC_MAX_DMA_BLOCK_SIZE		0xFFFF
52 #define SEC_MAX_FIFO_LEVEL		24
53 #define SEC_DMA_ALIGNMENT		8
54 
55 #define __packed__			__attribute__ ((__packed__))
56 
57 struct sec_softc;
58 struct sec_session;
59 
60 /* SEC descriptor definition */
61 struct sec_hw_desc_ptr {
62 	u_int		shdp_length		: 16;
63 	u_int		shdp_j			: 1;
64 	u_int		shdp_extent		: 7;
65 	u_int		__padding0		: 4;
66 	uint64_t	shdp_ptr		: 36;
67 } __packed__;
68 
69 struct sec_hw_desc {
70 	union __packed__ {
71 		struct __packed__ {
72 			u_int	eu_sel0		: 4;
73 			u_int	mode0		: 8;
74 			u_int	eu_sel1		: 4;
75 			u_int	mode1		: 8;
76 			u_int	desc_type	: 5;
77 			u_int	__padding0	: 1;
78 			u_int	dir		: 1;
79 			u_int	dn		: 1;
80 			u_int	__padding1	: 32;
81 		} request;
82 		struct __packed__ {
83 			u_int	done		: 8;
84 			u_int	__padding0	: 27;
85 			u_int	iccr0		: 2;
86 			u_int	__padding1	: 6;
87 			u_int	iccr1		: 2;
88 			u_int	__padding2	: 19;
89 		} feedback;
90 	} shd_control;
91 
92 	struct sec_hw_desc_ptr	shd_pointer[SEC_POINTERS];
93 
94 	/* Data below is mapped to descriptor pointers */
95 	uint8_t			shd_iv[SEC_MAX_IV_LEN];
96 	uint8_t			shd_key[SEC_MAX_KEY_LEN];
97 	uint8_t			shd_mkey[SEC_MAX_KEY_LEN];
98 } __packed__;
99 
100 #define shd_eu_sel0		shd_control.request.eu_sel0
101 #define shd_mode0		shd_control.request.mode0
102 #define shd_eu_sel1		shd_control.request.eu_sel1
103 #define shd_mode1		shd_control.request.mode1
104 #define shd_desc_type		shd_control.request.desc_type
105 #define shd_dir			shd_control.request.dir
106 #define shd_dn			shd_control.request.dn
107 #define shd_done		shd_control.feedback.done
108 #define shd_iccr0		shd_control.feedback.iccr0
109 #define shd_iccr1		shd_control.feedback.iccr1
110 
111 /* SEC link table entries definition */
112 struct sec_hw_lt {
113 	u_int			shl_length	: 16;
114 	u_int			__padding0	: 6;
115 	u_int			shl_r		: 1;
116 	u_int			shl_n		: 1;
117 	u_int			__padding1	: 4;
118 	uint64_t		shl_ptr		: 36;
119 } __packed__;
120 
121 struct sec_dma_mem {
122 	void			*dma_vaddr;
123 	bus_addr_t		dma_paddr;
124 	bus_dma_tag_t		dma_tag;
125 	bus_dmamap_t		dma_map;
126 	u_int			dma_is_map;
127 };
128 
129 struct sec_desc {
130 	struct sec_hw_desc	*sd_desc;
131 	bus_addr_t		sd_desc_paddr;
132 	struct sec_dma_mem	sd_ptr_dmem[SEC_POINTERS];
133 	struct cryptop		*sd_crp;
134 	u_int			sd_lt_used;
135 	u_int			sd_error;
136 };
137 
138 struct sec_lt {
139 	struct sec_hw_lt	*sl_lt;
140 	bus_addr_t		sl_lt_paddr;
141 };
142 
143 struct sec_eu_methods {
144 	int	(*sem_newsession)(struct sec_softc *sc,
145 	    struct sec_session *ses, struct cryptoini *enc,
146 	    struct cryptoini *mac);
147 	int	(*sem_make_desc)(struct sec_softc *sc,
148 	    struct sec_session *ses, struct sec_desc *desc,
149 	    struct cryptop *crp, int buftype);
150 };
151 
152 struct sec_session {
153 	u_int			ss_used;
154 	struct sec_eu_methods	*ss_eu;
155 	uint8_t			ss_key[SEC_MAX_KEY_LEN];
156 	uint8_t			ss_mkey[SEC_MAX_KEY_LEN];
157 	u_int			ss_klen;
158 	u_int			ss_mklen;
159 	u_int			ss_ivlen;
160 };
161 
162 struct sec_desc_map_info {
163 	struct sec_softc	*sdmi_sc;
164 	bus_size_t		sdmi_size;
165 	bus_size_t		sdmi_offset;
166 	struct sec_lt		*sdmi_lt_first;
167 	struct sec_lt		*sdmi_lt_last;
168 	u_int			sdmi_lt_used;
169 };
170 
171 struct sec_softc {
172 	device_t		sc_dev;
173 	int32_t			sc_cid;
174 	int			sc_blocked;
175 	int			sc_shutdown;
176 	u_int			sc_version;
177 
178 	uint64_t		sc_int_error_mask;
179 	uint64_t		sc_channel_idle_mask;
180 
181 	struct sec_session	sc_sessions[SEC_MAX_SESSIONS];
182 
183 	struct mtx		sc_controller_lock;
184 	struct mtx		sc_descriptors_lock;
185 	struct mtx		sc_sessions_lock;
186 
187 	struct sec_desc		sc_desc[SEC_DESCRIPTORS];
188 	u_int			sc_free_desc_get_cnt;
189 	u_int			sc_free_desc_put_cnt;
190 	u_int			sc_ready_desc_get_cnt;
191 	u_int			sc_ready_desc_put_cnt;
192 	u_int			sc_queued_desc_get_cnt;
193 	u_int			sc_queued_desc_put_cnt;
194 
195 	struct sec_lt		sc_lt[SEC_LT_ENTRIES + 1];
196 	u_int			sc_lt_alloc_cnt;
197 	u_int			sc_lt_free_cnt;
198 
199 	struct sec_dma_mem	sc_desc_dmem;	/* descriptors DMA memory */
200 	struct sec_dma_mem	sc_lt_dmem;	/* link tables DMA memory */
201 
202 	struct resource		*sc_rres;	/* register resource */
203         int			sc_rrid;	/* register rid */
204 	struct {
205 		bus_space_tag_t	bst;
206 		bus_space_handle_t bsh;
207 	} sc_bas;
208 
209 	struct resource		*sc_pri_ires;	/* primary irq resource */
210 	void			*sc_pri_ihand;	/* primary irq handler */
211 	int			sc_pri_irid;	/* primary irq resource id */
212 
213 	struct resource		*sc_sec_ires;	/* secondary irq resource */
214 	void			*sc_sec_ihand;	/* secondary irq handler */
215 	int			sc_sec_irid;	/* secondary irq resource id */
216 };
217 
218 /* Locking macros */
219 #define SEC_LOCK(sc, what)						\
220 	mtx_lock(&(sc)->sc_ ## what ## _lock)
221 #define SEC_UNLOCK(sc, what)						\
222 	mtx_unlock(&(sc)->sc_ ## what ## _lock)
223 #define SEC_LOCK_ASSERT(sc, what)					\
224 	mtx_assert(&(sc)->sc_ ## what ## _lock, MA_OWNED)
225 
226 /* Read/Write definitions */
227 #define SEC_READ(sc, reg)						\
228 	bus_space_read_8((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg))
229 #define SEC_WRITE(sc, reg, val)						\
230 	bus_space_write_8((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg), (val))
231 
232 /* Base allocation macros (warning: wrap must be 2^n) */
233 #define SEC_CNT_INIT(sc, cnt, wrap)					\
234 	(((sc)->cnt) = ((wrap) - 1))
235 #define SEC_ADD(sc, cnt, wrap, val)					\
236 	((sc)->cnt = (((sc)->cnt) + (val)) & ((wrap) - 1))
237 #define SEC_INC(sc, cnt, wrap)						\
238 	SEC_ADD(sc, cnt, wrap, 1)
239 #define SEC_DEC(sc, cnt, wrap)						\
240 	SEC_ADD(sc, cnt, wrap, -1)
241 #define SEC_GET_GENERIC(sc, tab, cnt, wrap)				\
242 	((sc)->tab[SEC_INC(sc, cnt, wrap)])
243 #define SEC_PUT_GENERIC(sc, tab, cnt, wrap, val)			\
244 	((sc)->tab[SEC_INC(sc, cnt, wrap)] = val)
245 
246 /* Interface for descriptors */
247 #define SEC_GET_FREE_DESC(sc)						\
248 	&SEC_GET_GENERIC(sc, sc_desc, sc_free_desc_get_cnt, SEC_DESCRIPTORS)
249 
250 #define SEC_PUT_BACK_FREE_DESC(sc)					\
251 	SEC_DEC(sc, sc_free_desc_get_cnt, SEC_DESCRIPTORS)
252 
253 #define SEC_DESC_FREE2READY(sc)						\
254 	SEC_INC(sc, sc_ready_desc_put_cnt, SEC_DESCRIPTORS)
255 
256 #define SEC_GET_READY_DESC(sc)						\
257 	&SEC_GET_GENERIC(sc, sc_desc, sc_ready_desc_get_cnt, SEC_DESCRIPTORS)
258 
259 #define SEC_PUT_BACK_READY_DESC(sc)					\
260 	SEC_DEC(sc, sc_ready_desc_get_cnt, SEC_DESCRIPTORS)
261 
262 #define SEC_DESC_READY2QUEUED(sc)					\
263 	SEC_INC(sc, sc_queued_desc_put_cnt, SEC_DESCRIPTORS)
264 
265 #define SEC_GET_QUEUED_DESC(sc)						\
266 	&SEC_GET_GENERIC(sc, sc_desc, sc_queued_desc_get_cnt, SEC_DESCRIPTORS)
267 
268 #define SEC_PUT_BACK_QUEUED_DESC(sc)					\
269 	SEC_DEC(sc, sc_queued_desc_get_cnt, SEC_DESCRIPTORS)
270 
271 #define SEC_DESC_QUEUED2FREE(sc)					\
272 	SEC_INC(sc, sc_free_desc_put_cnt, SEC_DESCRIPTORS)
273 
274 #define SEC_FREE_DESC_CNT(sc)						\
275 	(((sc)->sc_free_desc_put_cnt - (sc)->sc_free_desc_get_cnt - 1)	\
276 	& (SEC_DESCRIPTORS - 1))
277 
278 #define SEC_READY_DESC_CNT(sc)						\
279 	(((sc)->sc_ready_desc_put_cnt - (sc)->sc_ready_desc_get_cnt) &	\
280 	(SEC_DESCRIPTORS - 1))
281 
282 #define SEC_QUEUED_DESC_CNT(sc)						\
283 	(((sc)->sc_queued_desc_put_cnt - (sc)->sc_queued_desc_get_cnt)	\
284 	& (SEC_DESCRIPTORS - 1))
285 
286 #define SEC_DESC_SYNC(sc, mode) do {					\
287 	sec_sync_dma_mem(&((sc)->sc_desc_dmem), (mode));		\
288 	sec_sync_dma_mem(&((sc)->sc_lt_dmem), (mode));			\
289 } while (0)
290 
291 #define SEC_DESC_SYNC_POINTERS(desc, mode) do {				\
292 	u_int i;							\
293 	for (i = 0; i < SEC_POINTERS; i++)				\
294 		sec_sync_dma_mem(&((desc)->sd_ptr_dmem[i]), (mode));	\
295 } while (0)
296 
297 #define SEC_DESC_FREE_POINTERS(desc) do {				\
298 	u_int i;							\
299 	for (i = 0; i < SEC_POINTERS; i++)				\
300 		sec_free_dma_mem(&(desc)->sd_ptr_dmem[i]);		\
301 } while (0);
302 
303 #define SEC_DESC_PUT_BACK_LT(sc, desc)					\
304 	SEC_PUT_BACK_LT(sc, (desc)->sd_lt_used)
305 
306 #define SEC_DESC_FREE_LT(sc, desc)					\
307 	SEC_FREE_LT(sc, (desc)->sd_lt_used)
308 
309 /* Interface for link tables */
310 #define SEC_ALLOC_LT_ENTRY(sc)						\
311 	&SEC_GET_GENERIC(sc, sc_lt, sc_lt_alloc_cnt, SEC_LT_ENTRIES)
312 
313 #define SEC_PUT_BACK_LT(sc, num)					\
314 	SEC_ADD(sc, sc_lt_alloc_cnt, SEC_LT_ENTRIES, -(num))
315 
316 #define SEC_FREE_LT(sc, num)						\
317 	SEC_ADD(sc, sc_lt_free_cnt, SEC_LT_ENTRIES, num)
318 
319 #define SEC_FREE_LT_CNT(sc)						\
320 	(((sc)->sc_lt_free_cnt - (sc)->sc_lt_alloc_cnt - 1)		\
321 	& (SEC_LT_ENTRIES - 1))
322 
323 /* DMA Maping defines */
324 #define SEC_MEMORY		0
325 #define SEC_UIO			1
326 #define SEC_MBUF		2
327 
328 /* Size of SEC registers area */
329 #define SEC_IO_SIZE		0x10000
330 
331 /* SEC Controller registers */
332 #define SEC_IER			0x1008
333 #define SEC_INT_CH_DN(n)	(1ULL << (((n) * 2) + 32))
334 #define SEC_INT_CH_ERR(n)	(1ULL << (((n) * 2) + 33))
335 #define SEC_INT_ITO		(1ULL << 55)
336 
337 #define SEC_ISR			0x1010
338 #define SEC_ICR			0x1018
339 #define SEC_ID			0x1020
340 
341 #define SEC_EUASR		0x1028
342 #define SEC_EUASR_RNGU(r)	(((r) >> 0) & 0xF)
343 #define SEC_EUASR_PKEU(r)	(((r) >> 8) & 0xF)
344 #define SEC_EUASR_KEU(r)	(((r) >> 16) & 0xF)
345 #define SEC_EUASR_CRCU(r)	(((r) >> 20) & 0xF)
346 #define SEC_EUASR_DEU(r)	(((r) >> 32) & 0xF)
347 #define SEC_EUASR_AESU(r)	(((r) >> 40) & 0xF)
348 #define SEC_EUASR_MDEU(r)	(((r) >> 48) & 0xF)
349 #define SEC_EUASR_AFEU(r)	(((r) >> 56) & 0xF)
350 
351 #define SEC_MCR			0x1030
352 #define SEC_MCR_SWR		(1ULL << 32)
353 
354 /* SEC Channel registers */
355 #define SEC_CHAN_CCR(n)		(((n) * 0x100) + 0x1108)
356 #define SEC_CHAN_CCR_CDIE	(1ULL << 1)
357 #define SEC_CHAN_CCR_NT		(1ULL << 2)
358 #define SEC_CHAN_CCR_AWSE	(1ULL << 3)
359 #define SEC_CHAN_CCR_CDWE	(1ULL << 4)
360 #define SEC_CHAN_CCR_BS		(1ULL << 8)
361 #define SEC_CHAN_CCR_WGN	(1ULL << 13)
362 #define SEC_CHAN_CCR_R		(1ULL << 32)
363 #define SEC_CHAN_CCR_CON	(1ULL << 33)
364 
365 #define SEC_CHAN_CSR(n)		(((n) * 0x100) + 0x1110)
366 #define SEC_CHAN_CSR2_FFLVL_M	0x1FULL
367 #define SEC_CHAN_CSR2_FFLVL_S	56
368 #define SEC_CHAN_CSR2_GSTATE_M	0x0FULL
369 #define SEC_CHAN_CSR2_GSTATE_S	48
370 #define SEC_CHAN_CSR2_PSTATE_M	0x0FULL
371 #define SEC_CHAN_CSR2_PSTATE_S	40
372 #define SEC_CHAN_CSR2_MSTATE_M	0x3FULL
373 #define SEC_CHAN_CSR2_MSTATE_S	32
374 #define SEC_CHAN_CSR3_FFLVL_M	0x1FULL
375 #define SEC_CHAN_CSR3_FFLVL_S	24
376 #define SEC_CHAN_CSR3_MSTATE_M	0x1FFULL
377 #define SEC_CHAN_CSR3_MSTATE_S	32
378 #define SEC_CHAN_CSR3_PSTATE_M	0x7FULL
379 #define SEC_CHAN_CSR3_PSTATE_S	48
380 #define SEC_CHAN_CSR3_GSTATE_M	0x7FULL
381 #define SEC_CHAN_CSR3_GSTATE_S	56
382 
383 #define SEC_CHAN_CDPR(n)	(((n) * 0x100) + 0x1140)
384 #define SEC_CHAN_FF(n)		(((n) * 0x100) + 0x1148)
385 
386 /* SEC Execution Units numbers */
387 #define SEC_EU_NONE		0x0
388 #define SEC_EU_AFEU		0x1
389 #define SEC_EU_DEU		0x2
390 #define SEC_EU_MDEU_A		0x3
391 #define SEC_EU_MDEU_B		0xB
392 #define SEC_EU_RNGU		0x4
393 #define SEC_EU_PKEU		0x5
394 #define SEC_EU_AESU		0x6
395 #define SEC_EU_KEU		0x7
396 #define SEC_EU_CRCU		0x8
397 
398 /* SEC descriptor types */
399 #define SEC_DT_COMMON_NONSNOOP	0x02
400 #define SEC_DT_HMAC_SNOOP	0x04
401 
402 /* SEC AESU declarations and definitions */
403 #define SEC_AESU_MODE_ED	(1ULL << 0)
404 #define SEC_AESU_MODE_CBC	(1ULL << 1)
405 
406 /* SEC DEU declarations and definitions */
407 #define SEC_DEU_MODE_ED		(1ULL << 0)
408 #define SEC_DEU_MODE_TS		(1ULL << 1)
409 #define SEC_DEU_MODE_CBC	(1ULL << 2)
410 
411 /* SEC MDEU declarations and definitions */
412 #define SEC_HMAC_HASH_LEN	12
413 #define SEC_MDEU_MODE_SHA1	0x00	/* MDEU A */
414 #define SEC_MDEU_MODE_SHA384	0x00	/* MDEU B */
415 #define SEC_MDEU_MODE_SHA256	0x01
416 #define SEC_MDEU_MODE_MD5	0x02	/* MDEU A */
417 #define SEC_MDEU_MODE_SHA512	0x02	/* MDEU B */
418 #define SEC_MDEU_MODE_SHA224	0x03
419 #define SEC_MDEU_MODE_PD	(1ULL << 2)
420 #define SEC_MDEU_MODE_HMAC	(1ULL << 3)
421 #define SEC_MDEU_MODE_INIT	(1ULL << 4)
422 #define SEC_MDEU_MODE_SMAC	(1ULL << 5)
423 #define SEC_MDEU_MODE_CICV	(1ULL << 6)
424 #define SEC_MDEU_MODE_CONT	(1ULL << 7)
425 
426 #endif
427