xref: /freebsd/sys/dev/sfxge/common/efx_regs_mcdi.h (revision 5b9c547c)
1 /*-
2  * Copyright 2008-2011 Solarflare Communications Inc.  All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  *
25  * $FreeBSD$
26  */
27 
28 #ifndef _SIENA_MC_DRIVER_PCOL_H
29 #define	_SIENA_MC_DRIVER_PCOL_H
30 
31 
32 /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */
33 /* Power-on reset state */
34 #define MC_FW_STATE_POR (1)
35 /* If this is set in MC_RESET_STATE_REG then it should be
36  * possible to jump into IMEM without loading code from flash. */
37 #define MC_FW_WARM_BOOT_OK (2)
38 /* The MC main image has started to boot. */
39 #define MC_FW_STATE_BOOTING (4)
40 /* The Scheduler has started. */
41 #define MC_FW_STATE_SCHED (8)
42 
43 /* Siena MC shared memmory offsets */
44 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
45 #define	MC_SMEM_P0_DOORBELL_OFST	0x000
46 #define	MC_SMEM_P1_DOORBELL_OFST	0x004
47 /* The rest of these are firmware-defined */
48 #define	MC_SMEM_P0_PDU_OFST		0x008
49 #define	MC_SMEM_P1_PDU_OFST		0x108
50 #define	MC_SMEM_PDU_LEN			0x100
51 #define	MC_SMEM_P0_PTP_TIME_OFST	0x7f0
52 #define	MC_SMEM_P0_STATUS_OFST		0x7f8
53 #define	MC_SMEM_P1_STATUS_OFST		0x7fc
54 
55 /* Values to be written to the per-port status dword in shared
56  * memory on reboot and assert */
57 #define MC_STATUS_DWORD_REBOOT (0xb007b007)
58 #define MC_STATUS_DWORD_ASSERT (0xdeaddead)
59 
60 /* The current version of the MCDI protocol.
61  *
62  * Note that the ROM burnt into the card only talks V0, so at the very
63  * least every driver must support version 0 and MCDI_PCOL_VERSION
64  */
65 #ifdef WITH_MCDI_V2
66 #define MCDI_PCOL_VERSION 2
67 #else
68 #define MCDI_PCOL_VERSION 1
69 #endif
70 
71 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */
72 
73 /* MCDI version 1
74  *
75  * Each MCDI request starts with an MCDI_HEADER, which is a 32byte
76  * structure, filled in by the client.
77  *
78  *       0       7  8     16    20     22  23  24    31
79  *      | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS |
80  *               |                      |   |
81  *               |                      |   \--- Response
82  *               |                      \------- Error
83  *               \------------------------------ Resync (always set)
84  *
85  * The client writes it's request into MC shared memory, and rings the
86  * doorbell. Each request is completed by either by the MC writting
87  * back into shared memory, or by writting out an event.
88  *
89  * All MCDI commands support completion by shared memory response. Each
90  * request may also contain additional data (accounted for by HEADER.LEN),
91  * and some response's may also contain additional data (again, accounted
92  * for by HEADER.LEN).
93  *
94  * Some MCDI commands support completion by event, in which any associated
95  * response data is included in the event.
96  *
97  * The protocol requires one response to be delivered for every request, a
98  * request should not be sent unless the response for the previous request
99  * has been received (either by polling shared memory, or by receiving
100  * an event).
101  */
102 
103 /** Request/Response structure */
104 #define MCDI_HEADER_OFST 0
105 #define MCDI_HEADER_CODE_LBN 0
106 #define MCDI_HEADER_CODE_WIDTH 7
107 #define MCDI_HEADER_RESYNC_LBN 7
108 #define MCDI_HEADER_RESYNC_WIDTH 1
109 #define MCDI_HEADER_DATALEN_LBN 8
110 #define MCDI_HEADER_DATALEN_WIDTH 8
111 #define MCDI_HEADER_SEQ_LBN 16
112 #define MCDI_HEADER_RSVD_LBN 20
113 #define MCDI_HEADER_RSVD_WIDTH 2
114 #define MCDI_HEADER_SEQ_WIDTH 4
115 #define MCDI_HEADER_ERROR_LBN 22
116 #define MCDI_HEADER_ERROR_WIDTH 1
117 #define MCDI_HEADER_RESPONSE_LBN 23
118 #define MCDI_HEADER_RESPONSE_WIDTH 1
119 #define MCDI_HEADER_XFLAGS_LBN 24
120 #define MCDI_HEADER_XFLAGS_WIDTH 8
121 /* Request response using event */
122 #define MCDI_HEADER_XFLAGS_EVREQ 0x01
123 
124 /* Maximum number of payload bytes */
125 #ifdef WITH_MCDI_V2
126 #define MCDI_CTL_SDU_LEN_MAX 0x400
127 #else
128 #define MCDI_CTL_SDU_LEN_MAX 0xfc
129 #endif
130 
131 /* The MC can generate events for two reasons:
132  *   - To complete a shared memory request if XFLAGS_EVREQ was set
133  *   - As a notification (link state, i2c event), controlled
134  *     via MC_CMD_LOG_CTRL
135  *
136  * Both events share a common structure:
137  *
138  *  0      32     33      36    44     52     60
139  * | Data | Cont | Level | Src | Code | Rsvd |
140  *           |
141  *           \ There is another event pending in this notification
142  *
143  * If Code==CMDDONE, then the fields are further interpreted as:
144  *
145  *   - LEVEL==INFO    Command succeeded
146  *   - LEVEL==ERR     Command failed
147  *
148  *    0     8         16      24     32
149  *   | Seq | Datalen | Errno | Rsvd |
150  *
151  *   These fields are taken directly out of the standard MCDI header, i.e.,
152  *   LEVEL==ERR, Datalen == 0 => Reboot
153  *
154  * Events can be squirted out of the UART (using LOG_CTRL) without a
155  * MCDI header.  An event can be distinguished from a MCDI response by
156  * examining the first byte which is 0xc0.  This corresponds to the
157  * non-existent MCDI command MC_CMD_DEBUG_LOG.
158  *
159  *      0         7        8
160  *     | command | Resync |     = 0xc0
161  *
162  * Since the event is written in big-endian byte order, this works
163  * providing bits 56-63 of the event are 0xc0.
164  *
165  *      56     60  63
166  *     | Rsvd | Code |    = 0xc0
167  *
168  * Which means for convenience the event code is 0xc for all MC
169  * generated events.
170  */
171 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc
172 
173 
174 /* Non-existent command target */
175 #define MC_CMD_ERR_ENOENT 2
176 /* assert() has killed the MC */
177 #define MC_CMD_ERR_EINTR 4
178 /* Caller does not hold required locks */
179 #define MC_CMD_ERR_EACCES 13
180 /* Resource is currently unavailable (e.g. lock contention) */
181 #define MC_CMD_ERR_EBUSY 16
182 /* Invalid argument to target */
183 #define MC_CMD_ERR_EINVAL 22
184 /* Non-recursive resource is already acquired */
185 #define MC_CMD_ERR_EDEADLK 35
186 /* Operation not implemented */
187 #define MC_CMD_ERR_ENOSYS 38
188 /* Operation timed out */
189 #define MC_CMD_ERR_ETIME 62
190 
191 #define MC_CMD_ERR_CODE_OFST 0
192 
193 /* We define 8 "escape" commands to allow
194    for command number space extension */
195 
196 #define MC_CMD_CMD_SPACE_ESCAPE_0	      0x78
197 #define MC_CMD_CMD_SPACE_ESCAPE_1	      0x79
198 #define MC_CMD_CMD_SPACE_ESCAPE_2	      0x7A
199 #define MC_CMD_CMD_SPACE_ESCAPE_3	      0x7B
200 #define MC_CMD_CMD_SPACE_ESCAPE_4	      0x7C
201 #define MC_CMD_CMD_SPACE_ESCAPE_5	      0x7D
202 #define MC_CMD_CMD_SPACE_ESCAPE_6	      0x7E
203 #define MC_CMD_CMD_SPACE_ESCAPE_7	      0x7F
204 
205 /* Vectors in the boot ROM */
206 /* Point to the copycode entry point. */
207 #define MC_BOOTROM_COPYCODE_VEC (0x7f4)
208 /* Points to the recovery mode entry point. */
209 #define MC_BOOTROM_NOFLASH_VEC (0x7f8)
210 
211 /* The command set exported by the boot ROM (MCDI v0) */
212 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS {		\
213 	(1 << MC_CMD_READ32)	|			\
214 	(1 << MC_CMD_WRITE32)	|			\
215 	(1 << MC_CMD_COPYCODE)	|			\
216 	(1 << MC_CMD_GET_VERSION),			\
217 	0, 0, 0 }
218 
219 #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \
220 	(MC_CMD_SENSOR_ENTRY_OFST + (_x))
221 
222 #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) (  \
223         (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST+     \
224          MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST)+ \
225          ((n)*MC_CMD_DBIWROP_TYPEDEF_LEN))
226 
227 #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) (  \
228         (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST+     \
229          MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST)+ \
230          ((n)*MC_CMD_DBIWROP_TYPEDEF_LEN))
231 
232 #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) (  \
233         (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST+     \
234          MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST)+ \
235          ((n)*MC_CMD_DBIWROP_TYPEDEF_LEN))
236 
237 
238 #ifdef WITH_MCDI_V2
239 
240 /* Version 2 adds an optional argument to error returns: the errno value
241  * may be followed by the (0-based) number of the first argument that
242  * could not be processed.
243  */
244 #define MC_CMD_ERR_ARG_OFST 4
245 
246 /* Try again */
247 #define MC_CMD_ERR_EAGAIN 11
248 /* No space */
249 #define MC_CMD_ERR_ENOSPC 28
250 
251 #endif
252 
253 /* MCDI_EVENT structuredef */
254 #define	MCDI_EVENT_LEN 8
255 #define	MCDI_EVENT_CONT_LBN 32
256 #define	MCDI_EVENT_CONT_WIDTH 1
257 #define	MCDI_EVENT_LEVEL_LBN 33
258 #define	MCDI_EVENT_LEVEL_WIDTH 3
259 #define	MCDI_EVENT_LEVEL_INFO  0x0 /* enum */
260 #define	MCDI_EVENT_LEVEL_WARN 0x1 /* enum */
261 #define	MCDI_EVENT_LEVEL_ERR 0x2 /* enum */
262 #define	MCDI_EVENT_LEVEL_FATAL 0x3 /* enum */
263 #define	MCDI_EVENT_DATA_OFST 0
264 #define	MCDI_EVENT_CMDDONE_SEQ_LBN 0
265 #define	MCDI_EVENT_CMDDONE_SEQ_WIDTH 8
266 #define	MCDI_EVENT_CMDDONE_DATALEN_LBN 8
267 #define	MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8
268 #define	MCDI_EVENT_CMDDONE_ERRNO_LBN 16
269 #define	MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8
270 #define	MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0
271 #define	MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16
272 #define	MCDI_EVENT_LINKCHANGE_SPEED_LBN 16
273 #define	MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4
274 #define	MCDI_EVENT_LINKCHANGE_SPEED_100M  0x1 /* enum */
275 #define	MCDI_EVENT_LINKCHANGE_SPEED_1G  0x2 /* enum */
276 #define	MCDI_EVENT_LINKCHANGE_SPEED_10G  0x3 /* enum */
277 #define	MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20
278 #define	MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4
279 #define	MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24
280 #define	MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8
281 #define	MCDI_EVENT_SENSOREVT_MONITOR_LBN 0
282 #define	MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8
283 #define	MCDI_EVENT_SENSOREVT_STATE_LBN 8
284 #define	MCDI_EVENT_SENSOREVT_STATE_WIDTH 8
285 #define	MCDI_EVENT_SENSOREVT_VALUE_LBN 16
286 #define	MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16
287 #define	MCDI_EVENT_FWALERT_DATA_LBN 8
288 #define	MCDI_EVENT_FWALERT_DATA_WIDTH 24
289 #define	MCDI_EVENT_FWALERT_REASON_LBN 0
290 #define	MCDI_EVENT_FWALERT_REASON_WIDTH 8
291 #define	MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 /* enum */
292 #define	MCDI_EVENT_FLR_VF_LBN 0
293 #define	MCDI_EVENT_FLR_VF_WIDTH 8
294 #define	MCDI_EVENT_TX_ERR_TXQ_LBN 0
295 #define	MCDI_EVENT_TX_ERR_TXQ_WIDTH 12
296 #define	MCDI_EVENT_TX_ERR_TYPE_LBN 12
297 #define	MCDI_EVENT_TX_ERR_TYPE_WIDTH 4
298 #define	MCDI_EVENT_TX_ERR_DL_FAIL 0x1 /* enum */
299 #define	MCDI_EVENT_TX_ERR_NO_EOP 0x2 /* enum */
300 #define	MCDI_EVENT_TX_ERR_2BIG 0x3 /* enum */
301 #define	MCDI_EVENT_TX_ERR_INFO_LBN 16
302 #define	MCDI_EVENT_TX_ERR_INFO_WIDTH 16
303 #define	MCDI_EVENT_TX_FLUSH_TXQ_LBN 0
304 #define	MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12
305 #define	MCDI_EVENT_PTP_ERR_TYPE_LBN 0
306 #define	MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8
307 #define	MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 /* enum */
308 #define	MCDI_EVENT_PTP_ERR_FILTER 0x2 /* enum */
309 #define	MCDI_EVENT_PTP_ERR_FIFO 0x3 /* enum */
310 #define	MCDI_EVENT_PTP_ERR_QUEUE 0x4 /* enum */
311 #define	MCDI_EVENT_AOE_ERR_TYPE_LBN 0
312 #define	MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8
313 #define	MCDI_EVENT_AOE_NO_LOAD 0x1 /* enum */
314 #define	MCDI_EVENT_AOE_FC_ASSERT 0x2 /* enum */
315 #define	MCDI_EVENT_AOE_FC_WATCHDOG 0x3 /* enum */
316 #define	MCDI_EVENT_AOE_FC_NO_START 0x4 /* enum */
317 #define	MCDI_EVENT_AOE_FAULT 0x5 /* enum */
318 #define	MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 /* enum */
319 #define	MCDI_EVENT_AOE_LOAD 0x7 /* enum */
320 #define	MCDI_EVENT_AOE_DMA 0x8 /* enum */
321 #define	MCDI_EVENT_AOE_BYTEBLASTER 0x9 /* enum */
322 #define	MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa /* enum */
323 #define	MCDI_EVENT_AOE_PTP_STATUS 0xb /* enum */
324 #define	MCDI_EVENT_AOE_ERR_DATA_LBN 8
325 #define	MCDI_EVENT_AOE_ERR_DATA_WIDTH 8
326 #define	MCDI_EVENT_DATA_LBN 0
327 #define	MCDI_EVENT_DATA_WIDTH 32
328 #define	MCDI_EVENT_SRC_LBN 36
329 #define	MCDI_EVENT_SRC_WIDTH 8
330 #define	MCDI_EVENT_EV_CODE_LBN 60
331 #define	MCDI_EVENT_EV_CODE_WIDTH 4
332 #define	MCDI_EVENT_CODE_LBN 44
333 #define	MCDI_EVENT_CODE_WIDTH 8
334 #define	MCDI_EVENT_CODE_BADSSERT 0x1 /* enum */
335 #define	MCDI_EVENT_CODE_PMNOTICE 0x2 /* enum */
336 #define	MCDI_EVENT_CODE_CMDDONE 0x3 /* enum */
337 #define	MCDI_EVENT_CODE_LINKCHANGE 0x4 /* enum */
338 #define	MCDI_EVENT_CODE_SENSOREVT 0x5 /* enum */
339 #define	MCDI_EVENT_CODE_SCHEDERR 0x6 /* enum */
340 #define	MCDI_EVENT_CODE_REBOOT 0x7 /* enum */
341 #define	MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 /* enum */
342 #define	MCDI_EVENT_CODE_FWALERT 0x9 /* enum */
343 #define	MCDI_EVENT_CODE_FLR 0xa /* enum */
344 #define	MCDI_EVENT_CODE_TX_ERR 0xb /* enum */
345 #define	MCDI_EVENT_CODE_TX_FLUSH  0xc /* enum */
346 #define	MCDI_EVENT_CODE_PTP_RX  0xd /* enum */
347 #define	MCDI_EVENT_CODE_PTP_FAULT  0xe /* enum */
348 #define	MCDI_EVENT_CODE_PTP_PPS  0xf /* enum */
349 #define	MCDI_EVENT_CODE_AOE  0x12 /* enum */
350 #define	MCDI_EVENT_CODE_VCAL_FAIL  0x13 /* enum */
351 #define	MCDI_EVENT_CODE_HW_PPS  0x14 /* enum */
352 #define	MCDI_EVENT_CMDDONE_DATA_OFST 0
353 #define	MCDI_EVENT_CMDDONE_DATA_LBN 0
354 #define	MCDI_EVENT_CMDDONE_DATA_WIDTH 32
355 #define	MCDI_EVENT_LINKCHANGE_DATA_OFST 0
356 #define	MCDI_EVENT_LINKCHANGE_DATA_LBN 0
357 #define	MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32
358 #define	MCDI_EVENT_SENSOREVT_DATA_OFST 0
359 #define	MCDI_EVENT_SENSOREVT_DATA_LBN 0
360 #define	MCDI_EVENT_SENSOREVT_DATA_WIDTH 32
361 #define	MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0
362 #define	MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0
363 #define	MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32
364 #define	MCDI_EVENT_TX_ERR_DATA_OFST 0
365 #define	MCDI_EVENT_TX_ERR_DATA_LBN 0
366 #define	MCDI_EVENT_TX_ERR_DATA_WIDTH 32
367 #define	MCDI_EVENT_PTP_SECONDS_OFST 0
368 #define	MCDI_EVENT_PTP_SECONDS_LBN 0
369 #define	MCDI_EVENT_PTP_SECONDS_WIDTH 32
370 #define	MCDI_EVENT_PTP_NANOSECONDS_OFST 0
371 #define	MCDI_EVENT_PTP_NANOSECONDS_LBN 0
372 #define	MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32
373 #define	MCDI_EVENT_PTP_UUID_OFST 0
374 #define	MCDI_EVENT_PTP_UUID_LBN 0
375 #define	MCDI_EVENT_PTP_UUID_WIDTH 32
376 
377 /* FCDI_EVENT structuredef */
378 #define	FCDI_EVENT_LEN 8
379 #define	FCDI_EVENT_CONT_LBN 32
380 #define	FCDI_EVENT_CONT_WIDTH 1
381 #define	FCDI_EVENT_LEVEL_LBN 33
382 #define	FCDI_EVENT_LEVEL_WIDTH 3
383 #define	FCDI_EVENT_LEVEL_INFO  0x0 /* enum */
384 #define	FCDI_EVENT_LEVEL_WARN 0x1 /* enum */
385 #define	FCDI_EVENT_LEVEL_ERR 0x2 /* enum */
386 #define	FCDI_EVENT_LEVEL_FATAL 0x3 /* enum */
387 #define	FCDI_EVENT_DATA_OFST 0
388 #define	FCDI_EVENT_LINK_STATE_STATUS_LBN 0
389 #define	FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1
390 #define	FCDI_EVENT_LINK_DOWN 0x0 /* enum */
391 #define	FCDI_EVENT_LINK_UP 0x1 /* enum */
392 #define	FCDI_EVENT_DATA_LBN 0
393 #define	FCDI_EVENT_DATA_WIDTH 32
394 #define	FCDI_EVENT_SRC_LBN 36
395 #define	FCDI_EVENT_SRC_WIDTH 8
396 #define	FCDI_EVENT_EV_CODE_LBN 60
397 #define	FCDI_EVENT_EV_CODE_WIDTH 4
398 #define	FCDI_EVENT_CODE_LBN 44
399 #define	FCDI_EVENT_CODE_WIDTH 8
400 #define	FCDI_EVENT_CODE_REBOOT 0x1 /* enum */
401 #define	FCDI_EVENT_CODE_ASSERT 0x2 /* enum */
402 #define	FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 /* enum */
403 #define	FCDI_EVENT_CODE_LINK_STATE 0x4 /* enum */
404 #define	FCDI_EVENT_CODE_TIMED_READ 0x5 /* enum */
405 #define	FCDI_EVENT_CODE_PPS_IN 0x6 /* enum */
406 #define	FCDI_EVENT_CODE_PTP_TICK 0x7 /* enum */
407 #define	FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8 /* enum */
408 #define	FCDI_EVENT_CODE_PTP_STATUS 0x9 /* enum */
409 #define	FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0
410 #define	FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0
411 #define	FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32
412 #define	FCDI_EVENT_ASSERT_TYPE_LBN 36
413 #define	FCDI_EVENT_ASSERT_TYPE_WIDTH 8
414 #define	FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36
415 #define	FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8
416 #define	FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0
417 #define	FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0
418 #define	FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32
419 #define	FCDI_EVENT_LINK_STATE_DATA_OFST 0
420 #define	FCDI_EVENT_LINK_STATE_DATA_LBN 0
421 #define	FCDI_EVENT_LINK_STATE_DATA_WIDTH 32
422 #define	FCDI_EVENT_PTP_STATE_OFST 0
423 #define	FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */
424 #define	FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */
425 #define	FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */
426 #define	FCDI_EVENT_PTP_STATE_LBN 0
427 #define	FCDI_EVENT_PTP_STATE_WIDTH 32
428 #define	FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36
429 #define	FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8
430 #define	FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0
431 #define	FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0
432 #define	FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32
433 
434 /* FCDI_EXTENDED_EVENT_PPS structuredef */
435 #define	FCDI_EXTENDED_EVENT_PPS_LENMIN 16
436 #define	FCDI_EXTENDED_EVENT_PPS_LENMAX 248
437 #define	FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num))
438 #define	FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0
439 #define	FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0
440 #define	FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32
441 #define	FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8
442 #define	FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64
443 #define	FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32
444 #define	FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12
445 #define	FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96
446 #define	FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32
447 #define	FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8
448 #define	FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8
449 #define	FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8
450 #define	FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12
451 #define	FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1
452 #define	FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30
453 #define	FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64
454 #define	FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64
455 
456 
457 /***********************************/
458 /* MC_CMD_READ32
459  * Read multiple 32byte words from MC memory.
460  */
461 #define	MC_CMD_READ32 0x1
462 
463 /* MC_CMD_READ32_IN msgrequest */
464 #define	MC_CMD_READ32_IN_LEN 8
465 #define	MC_CMD_READ32_IN_ADDR_OFST 0
466 #define	MC_CMD_READ32_IN_NUMWORDS_OFST 4
467 
468 /* MC_CMD_READ32_OUT msgresponse */
469 #define	MC_CMD_READ32_OUT_LENMIN 4
470 #define	MC_CMD_READ32_OUT_LENMAX 252
471 #define	MC_CMD_READ32_OUT_LEN(num) (0+4*(num))
472 #define	MC_CMD_READ32_OUT_BUFFER_OFST 0
473 #define	MC_CMD_READ32_OUT_BUFFER_LEN 4
474 #define	MC_CMD_READ32_OUT_BUFFER_MINNUM 1
475 #define	MC_CMD_READ32_OUT_BUFFER_MAXNUM 63
476 
477 
478 /***********************************/
479 /* MC_CMD_WRITE32
480  * Write multiple 32byte words to MC memory.
481  */
482 #define	MC_CMD_WRITE32 0x2
483 
484 /* MC_CMD_WRITE32_IN msgrequest */
485 #define	MC_CMD_WRITE32_IN_LENMIN 8
486 #define	MC_CMD_WRITE32_IN_LENMAX 252
487 #define	MC_CMD_WRITE32_IN_LEN(num) (4+4*(num))
488 #define	MC_CMD_WRITE32_IN_ADDR_OFST 0
489 #define	MC_CMD_WRITE32_IN_BUFFER_OFST 4
490 #define	MC_CMD_WRITE32_IN_BUFFER_LEN 4
491 #define	MC_CMD_WRITE32_IN_BUFFER_MINNUM 1
492 #define	MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62
493 
494 /* MC_CMD_WRITE32_OUT msgresponse */
495 #define	MC_CMD_WRITE32_OUT_LEN 0
496 
497 
498 /***********************************/
499 /* MC_CMD_COPYCODE
500  * Copy MC code between two locations and jump.
501  */
502 #define	MC_CMD_COPYCODE 0x3
503 
504 /* MC_CMD_COPYCODE_IN msgrequest */
505 #define	MC_CMD_COPYCODE_IN_LEN 16
506 #define	MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0
507 #define	MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4
508 #define	MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8
509 #define	MC_CMD_COPYCODE_IN_JUMP_OFST 12
510 #define	MC_CMD_COPYCODE_JUMP_NONE 0x1 /* enum */
511 
512 /* MC_CMD_COPYCODE_OUT msgresponse */
513 #define	MC_CMD_COPYCODE_OUT_LEN 0
514 
515 
516 /***********************************/
517 /* MC_CMD_SET_FUNC
518  */
519 #define	MC_CMD_SET_FUNC  0x4
520 
521 /* MC_CMD_SET_FUNC_IN msgrequest */
522 #define	MC_CMD_SET_FUNC_IN_LEN 4
523 #define	MC_CMD_SET_FUNC_IN_FUNC_OFST 0
524 
525 /* MC_CMD_SET_FUNC_OUT msgresponse */
526 #define	MC_CMD_SET_FUNC_OUT_LEN 0
527 
528 
529 /***********************************/
530 /* MC_CMD_GET_BOOT_STATUS
531  */
532 #define	MC_CMD_GET_BOOT_STATUS 0x5
533 
534 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */
535 #define	MC_CMD_GET_BOOT_STATUS_IN_LEN 0
536 
537 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */
538 #define	MC_CMD_GET_BOOT_STATUS_OUT_LEN 8
539 #define	MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0
540 #define	MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4
541 #define	MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0
542 #define	MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1
543 #define	MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1
544 #define	MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1
545 #define	MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2
546 #define	MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1
547 
548 
549 /***********************************/
550 /* MC_CMD_GET_ASSERTS
551  * Get and clear any assertion status.
552  */
553 #define	MC_CMD_GET_ASSERTS  0x6
554 
555 /* MC_CMD_GET_ASSERTS_IN msgrequest */
556 #define	MC_CMD_GET_ASSERTS_IN_LEN 4
557 #define	MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0
558 
559 /* MC_CMD_GET_ASSERTS_OUT msgresponse */
560 #define	MC_CMD_GET_ASSERTS_OUT_LEN 140
561 #define	MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0
562 #define	MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 /* enum */
563 #define	MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 /* enum */
564 #define	MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 /* enum */
565 #define	MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 /* enum */
566 #define	MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4
567 #define	MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8
568 #define	MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4
569 #define	MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31
570 #define	MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132
571 #define	MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136
572 
573 
574 /***********************************/
575 /* MC_CMD_LOG_CTRL
576  * Configure the output stream for various events and messages.
577  */
578 #define	MC_CMD_LOG_CTRL  0x7
579 
580 /* MC_CMD_LOG_CTRL_IN msgrequest */
581 #define	MC_CMD_LOG_CTRL_IN_LEN 8
582 #define	MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0
583 #define	MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 /* enum */
584 #define	MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 /* enum */
585 #define	MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4
586 
587 /* MC_CMD_LOG_CTRL_OUT msgresponse */
588 #define	MC_CMD_LOG_CTRL_OUT_LEN 0
589 
590 
591 /***********************************/
592 /* MC_CMD_GET_VERSION
593  * Get version information about the MC firmware.
594  */
595 #define	MC_CMD_GET_VERSION  0x8
596 
597 /* MC_CMD_GET_VERSION_IN msgrequest */
598 #define	MC_CMD_GET_VERSION_IN_LEN 0
599 
600 /* MC_CMD_GET_VERSION_V0_OUT msgresponse */
601 #define	MC_CMD_GET_VERSION_V0_OUT_LEN 4
602 #define	MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0
603 #define	MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff /* enum */
604 #define	MC_CMD_GET_VERSION_OUT_FIRMWARE_BOOTROM 0xb0070000 /* enum */
605 #define	MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 /* enum */
606 #define	MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 /* enum */
607 
608 /* MC_CMD_GET_VERSION_OUT msgresponse */
609 #define	MC_CMD_GET_VERSION_OUT_LEN 32
610 /*            MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
611 /*            Enum values, see field(s): */
612 /*               MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
613 #define	MC_CMD_GET_VERSION_OUT_PCOL_OFST 4
614 #define	MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8
615 #define	MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16
616 #define	MC_CMD_GET_VERSION_OUT_VERSION_OFST 24
617 #define	MC_CMD_GET_VERSION_OUT_VERSION_LEN 8
618 #define	MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24
619 #define	MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28
620 
621 
622 /***********************************/
623 /* MC_CMD_FC
624  * Perform an FC operation
625  */
626 #define	MC_CMD_FC  0x9
627 
628 /* MC_CMD_FC_IN msgrequest */
629 #define	MC_CMD_FC_IN_LEN 4
630 #define	MC_CMD_FC_IN_OP_HDR_OFST 0
631 #define	MC_CMD_FC_IN_OP_LBN 0
632 #define	MC_CMD_FC_IN_OP_WIDTH 8
633 #define	MC_CMD_FC_OP_NULL 0x1 /* enum */
634 #define	MC_CMD_FC_OP_UNUSED 0x2 /* enum */
635 #define	MC_CMD_FC_OP_MAC 0x3 /* enum */
636 #define	MC_CMD_FC_OP_READ32 0x4 /* enum */
637 #define	MC_CMD_FC_OP_WRITE32 0x5 /* enum */
638 #define	MC_CMD_FC_OP_TRC_READ 0x6 /* enum */
639 #define	MC_CMD_FC_OP_TRC_WRITE 0x7 /* enum */
640 #define	MC_CMD_FC_OP_GET_VERSION 0x8 /* enum */
641 #define	MC_CMD_FC_OP_TRC_RX_READ 0x9 /* enum */
642 #define	MC_CMD_FC_OP_TRC_RX_WRITE 0xa /* enum */
643 #define	MC_CMD_FC_OP_SFP 0xb /* enum */
644 #define	MC_CMD_FC_OP_DDR_TEST 0xc /* enum */
645 #define	MC_CMD_FC_OP_GET_ASSERT 0xd /* enum */
646 #define	MC_CMD_FC_OP_FPGA_BUILD 0xe /* enum */
647 #define	MC_CMD_FC_OP_READ_MAP 0xf /* enum */
648 #define	MC_CMD_FC_OP_CAPABILITIES 0x10 /* enum */
649 #define	MC_CMD_FC_OP_GLOBAL_FLAGS 0x11 /* enum */
650 #define	MC_CMD_FC_OP_IO_REL 0x12 /* enum */
651 #define	MC_CMD_FC_OP_UHLINK 0x13 /* enum */
652 #define	MC_CMD_FC_OP_SET_LINK 0x14 /* enum */
653 #define	MC_CMD_FC_OP_LICENSE 0x15 /* enum */
654 #define	MC_CMD_FC_OP_STARTUP 0x16 /* enum */
655 #define	MC_CMD_FC_OP_DMA 0x17 /* enum */
656 #define	MC_CMD_FC_OP_TIMED_READ 0x18 /* enum */
657 #define	MC_CMD_FC_OP_LOG 0x19 /* enum */
658 #define	MC_CMD_FC_OP_CLOCK 0x1a /* enum */
659 #define	MC_CMD_FC_OP_DDR 0x1b /* enum */
660 #define	MC_CMD_FC_OP_TIMESTAMP 0x1c /* enum */
661 #define	MC_CMD_FC_OP_SPI 0x1d /* enum */
662 #define	MC_CMD_FC_OP_DIAG 0x1e /* enum */
663 #define	MC_CMD_FC_IN_PORT_EXT_OFST 0x0 /* enum */
664 #define	MC_CMD_FC_IN_PORT_INT_OFST 0x40 /* enum */
665 
666 /* MC_CMD_FC_IN_NULL msgrequest */
667 #define	MC_CMD_FC_IN_NULL_LEN 4
668 #define	MC_CMD_FC_IN_CMD_OFST 0
669 
670 /* MC_CMD_FC_IN_MAC msgrequest */
671 #define	MC_CMD_FC_IN_MAC_LEN 8
672 /*            MC_CMD_FC_IN_CMD_OFST 0 */
673 #define	MC_CMD_FC_IN_MAC_HEADER_OFST 4
674 #define	MC_CMD_FC_IN_MAC_OP_LBN 0
675 #define	MC_CMD_FC_IN_MAC_OP_WIDTH 8
676 #define	MC_CMD_FC_OP_MAC_OP_RECONFIGURE 0x1 /* enum */
677 #define	MC_CMD_FC_OP_MAC_OP_SET_LINK 0x2 /* enum */
678 #define	MC_CMD_FC_OP_MAC_OP_GET_STATS 0x3 /* enum */
679 #define	MC_CMD_FC_OP_MAC_OP_GET_RX_STATS 0x6 /* enum */
680 #define	MC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7 /* enum */
681 #define	MC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8 /* enum */
682 #define	MC_CMD_FC_IN_MAC_PORT_TYPE_LBN 8
683 #define	MC_CMD_FC_IN_MAC_PORT_TYPE_WIDTH 8
684 #define	MC_CMD_FC_PORT_EXT 0x0 /* enum */
685 #define	MC_CMD_FC_PORT_INT 0x1 /* enum */
686 #define	MC_CMD_FC_IN_MAC_PORT_IDX_LBN 16
687 #define	MC_CMD_FC_IN_MAC_PORT_IDX_WIDTH 8
688 #define	MC_CMD_FC_IN_MAC_CMD_FORMAT_LBN 24
689 #define	MC_CMD_FC_IN_MAC_CMD_FORMAT_WIDTH 8
690 #define	MC_CMD_FC_OP_MAC_CMD_FORMAT_DEFAULT 0x0 /* enum */
691 #define	MC_CMD_FC_OP_MAC_CMD_FORMAT_PORT_OVERRIDE 0x1 /* enum */
692 
693 /* MC_CMD_FC_IN_MAC_RECONFIGURE msgrequest */
694 #define	MC_CMD_FC_IN_MAC_RECONFIGURE_LEN 8
695 /*            MC_CMD_FC_IN_CMD_OFST 0 */
696 /*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
697 
698 /* MC_CMD_FC_IN_MAC_SET_LINK msgrequest */
699 #define	MC_CMD_FC_IN_MAC_SET_LINK_LEN 32
700 /*            MC_CMD_FC_IN_CMD_OFST 0 */
701 /*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
702 #define	MC_CMD_FC_IN_MAC_SET_LINK_MTU_OFST 8
703 #define	MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_OFST 12
704 #define	MC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16
705 #define	MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8
706 #define	MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16
707 #define	MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20
708 #define	MC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24
709 #define	MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_LBN 0
710 #define	MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_WIDTH 1
711 #define	MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_LBN 1
712 #define	MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_WIDTH 1
713 #define	MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_OFST 28
714 
715 /* MC_CMD_FC_IN_MAC_READ_STATUS msgrequest */
716 #define	MC_CMD_FC_IN_MAC_READ_STATUS_LEN 8
717 /*            MC_CMD_FC_IN_CMD_OFST 0 */
718 /*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
719 
720 /* MC_CMD_FC_IN_MAC_GET_RX_STATS msgrequest */
721 #define	MC_CMD_FC_IN_MAC_GET_RX_STATS_LEN 8
722 /*            MC_CMD_FC_IN_CMD_OFST 0 */
723 /*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
724 
725 /* MC_CMD_FC_IN_MAC_GET_TX_STATS msgrequest */
726 #define	MC_CMD_FC_IN_MAC_GET_TX_STATS_LEN 8
727 /*            MC_CMD_FC_IN_CMD_OFST 0 */
728 /*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
729 
730 /* MC_CMD_FC_IN_MAC_GET_STATS msgrequest */
731 #define	MC_CMD_FC_IN_MAC_GET_STATS_LEN 20
732 /*            MC_CMD_FC_IN_CMD_OFST 0 */
733 /*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
734 #define	MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_OFST 8
735 #define	MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_OFST 12
736 #define	MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_LBN 0
737 #define	MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_WIDTH 1
738 #define	MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_LBN 1
739 #define	MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_WIDTH 1
740 #define	MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_LBN 2
741 #define	MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_WIDTH 1
742 #define	MC_CMD_FC_IN_MAC_GET_STATS_NUM_OFST 16
743 #define	MC_CMD_FC_MAC_NSTATS_PER_BLOCK 0x1e /* enum */
744 #define	MC_CMD_FC_MAC_NBYTES_PER_STAT 0x8 /* enum */
745 
746 /* MC_CMD_FC_IN_READ32 msgrequest */
747 #define	MC_CMD_FC_IN_READ32_LEN 16
748 /*            MC_CMD_FC_IN_CMD_OFST 0 */
749 #define	MC_CMD_FC_IN_READ32_ADDR_HI_OFST 4
750 #define	MC_CMD_FC_IN_READ32_ADDR_LO_OFST 8
751 #define	MC_CMD_FC_IN_READ32_NUMWORDS_OFST 12
752 
753 /* MC_CMD_FC_IN_WRITE32 msgrequest */
754 #define	MC_CMD_FC_IN_WRITE32_LENMIN 16
755 #define	MC_CMD_FC_IN_WRITE32_LENMAX 252
756 #define	MC_CMD_FC_IN_WRITE32_LEN(num) (12+4*(num))
757 /*            MC_CMD_FC_IN_CMD_OFST 0 */
758 #define	MC_CMD_FC_IN_WRITE32_ADDR_HI_OFST 4
759 #define	MC_CMD_FC_IN_WRITE32_ADDR_LO_OFST 8
760 #define	MC_CMD_FC_IN_WRITE32_BUFFER_OFST 12
761 #define	MC_CMD_FC_IN_WRITE32_BUFFER_LEN 4
762 #define	MC_CMD_FC_IN_WRITE32_BUFFER_MINNUM 1
763 #define	MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM 60
764 
765 /* MC_CMD_FC_IN_TRC_READ msgrequest */
766 #define	MC_CMD_FC_IN_TRC_READ_LEN 12
767 /*            MC_CMD_FC_IN_CMD_OFST 0 */
768 #define	MC_CMD_FC_IN_TRC_READ_TRC_OFST 4
769 #define	MC_CMD_FC_IN_TRC_READ_CHANNEL_OFST 8
770 
771 /* MC_CMD_FC_IN_TRC_WRITE msgrequest */
772 #define	MC_CMD_FC_IN_TRC_WRITE_LEN 28
773 /*            MC_CMD_FC_IN_CMD_OFST 0 */
774 #define	MC_CMD_FC_IN_TRC_WRITE_TRC_OFST 4
775 #define	MC_CMD_FC_IN_TRC_WRITE_CHANNEL_OFST 8
776 #define	MC_CMD_FC_IN_TRC_WRITE_DATA_OFST 12
777 #define	MC_CMD_FC_IN_TRC_WRITE_DATA_LEN 4
778 #define	MC_CMD_FC_IN_TRC_WRITE_DATA_NUM 4
779 
780 /* MC_CMD_FC_IN_GET_VERSION msgrequest */
781 #define	MC_CMD_FC_IN_GET_VERSION_LEN 4
782 /*            MC_CMD_FC_IN_CMD_OFST 0 */
783 
784 /* MC_CMD_FC_IN_TRC_RX_READ msgrequest */
785 #define	MC_CMD_FC_IN_TRC_RX_READ_LEN 12
786 /*            MC_CMD_FC_IN_CMD_OFST 0 */
787 #define	MC_CMD_FC_IN_TRC_RX_READ_TRC_OFST 4
788 #define	MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_OFST 8
789 
790 /* MC_CMD_FC_IN_TRC_RX_WRITE msgrequest */
791 #define	MC_CMD_FC_IN_TRC_RX_WRITE_LEN 20
792 /*            MC_CMD_FC_IN_CMD_OFST 0 */
793 #define	MC_CMD_FC_IN_TRC_RX_WRITE_TRC_OFST 4
794 #define	MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_OFST 8
795 #define	MC_CMD_FC_IN_TRC_RX_WRITE_DATA_OFST 12
796 #define	MC_CMD_FC_IN_TRC_RX_WRITE_DATA_LEN 4
797 #define	MC_CMD_FC_IN_TRC_RX_WRITE_DATA_NUM 2
798 
799 /* MC_CMD_FC_IN_SFP msgrequest */
800 #define	MC_CMD_FC_IN_SFP_LEN 24
801 /*            MC_CMD_FC_IN_CMD_OFST 0 */
802 #define	MC_CMD_FC_IN_SFP_SPEED_OFST 4
803 #define	MC_CMD_FC_IN_SFP_COPPER_LEN_OFST 8
804 #define	MC_CMD_FC_IN_SFP_DUAL_SPEED_OFST 12
805 #define	MC_CMD_FC_IN_SFP_PRESENT_OFST 16
806 #define	MC_CMD_FC_IN_SFP_TYPE_OFST 20
807 
808 /* MC_CMD_FC_IN_DDR_TEST msgrequest */
809 #define	MC_CMD_FC_IN_DDR_TEST_LEN 8
810 /*            MC_CMD_FC_IN_CMD_OFST 0 */
811 #define	MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4
812 #define	MC_CMD_FC_IN_DDR_TEST_OP_LBN 0
813 #define	MC_CMD_FC_IN_DDR_TEST_OP_WIDTH 8
814 #define	MC_CMD_FC_OP_DDR_TEST_START 0x1 /* enum */
815 #define	MC_CMD_FC_OP_DDR_TEST_POLL 0x2 /* enum */
816 
817 /* MC_CMD_FC_IN_DDR_TEST_START msgrequest */
818 #define	MC_CMD_FC_IN_DDR_TEST_START_LEN 12
819 /*            MC_CMD_FC_IN_CMD_OFST 0 */
820 /*            MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */
821 #define	MC_CMD_FC_IN_DDR_TEST_START_MASK_OFST 8
822 #define	MC_CMD_FC_IN_DDR_TEST_START_T0_LBN 0
823 #define	MC_CMD_FC_IN_DDR_TEST_START_T0_WIDTH 1
824 #define	MC_CMD_FC_IN_DDR_TEST_START_T1_LBN 1
825 #define	MC_CMD_FC_IN_DDR_TEST_START_T1_WIDTH 1
826 #define	MC_CMD_FC_IN_DDR_TEST_START_B0_LBN 2
827 #define	MC_CMD_FC_IN_DDR_TEST_START_B0_WIDTH 1
828 #define	MC_CMD_FC_IN_DDR_TEST_START_B1_LBN 3
829 #define	MC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1
830 
831 /* MC_CMD_FC_IN_DDR_TEST_POLL msgrequest */
832 #define	MC_CMD_FC_IN_DDR_TEST_POLL_LEN 8
833 #define	MC_CMD_FC_IN_DDR_TEST_CMD_OFST 0
834 /*            MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */
835 
836 /* MC_CMD_FC_IN_GET_ASSERT msgrequest */
837 #define	MC_CMD_FC_IN_GET_ASSERT_LEN 4
838 /*            MC_CMD_FC_IN_CMD_OFST 0 */
839 
840 /* MC_CMD_FC_IN_FPGA_BUILD msgrequest */
841 #define	MC_CMD_FC_IN_FPGA_BUILD_LEN 8
842 /*            MC_CMD_FC_IN_CMD_OFST 0 */
843 #define	MC_CMD_FC_IN_FPGA_BUILD_OP_OFST 4
844 #define	MC_CMD_FC_IN_FPGA_BUILD_BUILD 0x1 /* enum */
845 #define	MC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2 /* enum */
846 #define	MC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3 /* enum */
847 
848 /* MC_CMD_FC_IN_READ_MAP msgrequest */
849 #define	MC_CMD_FC_IN_READ_MAP_LEN 8
850 /*            MC_CMD_FC_IN_CMD_OFST 0 */
851 #define	MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4
852 #define	MC_CMD_FC_IN_READ_MAP_OP_LBN 0
853 #define	MC_CMD_FC_IN_READ_MAP_OP_WIDTH 8
854 #define	MC_CMD_FC_OP_READ_MAP_COUNT 0x1 /* enum */
855 #define	MC_CMD_FC_OP_READ_MAP_INDEX 0x2 /* enum */
856 
857 /* MC_CMD_FC_IN_READ_MAP_COUNT msgrequest */
858 #define	MC_CMD_FC_IN_READ_MAP_COUNT_LEN 8
859 /*            MC_CMD_FC_IN_CMD_OFST 0 */
860 /*            MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */
861 
862 /* MC_CMD_FC_IN_READ_MAP_INDEX msgrequest */
863 #define	MC_CMD_FC_IN_READ_MAP_INDEX_LEN 12
864 /*            MC_CMD_FC_IN_CMD_OFST 0 */
865 /*            MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */
866 #define	MC_CMD_FC_IN_MAP_INDEX_OFST 8
867 
868 /* MC_CMD_FC_IN_CAPABILITIES msgrequest */
869 #define	MC_CMD_FC_IN_CAPABILITIES_LEN 4
870 /*            MC_CMD_FC_IN_CMD_OFST 0 */
871 
872 /* MC_CMD_FC_IN_GLOBAL_FLAGS msgrequest */
873 #define	MC_CMD_FC_IN_GLOBAL_FLAGS_LEN 8
874 /*            MC_CMD_FC_IN_CMD_OFST 0 */
875 #define	MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_OFST 4
876 #define	MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_LBN 0
877 #define	MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_WIDTH 1
878 #define	MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_LBN 1
879 #define	MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_WIDTH 1
880 #define	MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_LBN 2
881 #define	MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_WIDTH 1
882 #define	MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_LBN 3
883 #define	MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_WIDTH 1
884 #define	MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_LBN 4
885 #define	MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_WIDTH 1
886 #define	MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_LBN 5
887 #define	MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_WIDTH 1
888 
889 /* MC_CMD_FC_IN_IO_REL msgrequest */
890 #define	MC_CMD_FC_IN_IO_REL_LEN 8
891 /*            MC_CMD_FC_IN_CMD_OFST 0 */
892 #define	MC_CMD_FC_IN_IO_REL_HEADER_OFST 4
893 #define	MC_CMD_FC_IN_IO_REL_OP_LBN 0
894 #define	MC_CMD_FC_IN_IO_REL_OP_WIDTH 8
895 #define	MC_CMD_FC_IN_IO_REL_GET_ADDR 0x1 /* enum */
896 #define	MC_CMD_FC_IN_IO_REL_READ32 0x2 /* enum */
897 #define	MC_CMD_FC_IN_IO_REL_WRITE32 0x3 /* enum */
898 #define	MC_CMD_FC_IN_IO_REL_COMP_TYPE_LBN 8
899 #define	MC_CMD_FC_IN_IO_REL_COMP_TYPE_WIDTH 8
900 #define	MC_CMD_FC_COMP_TYPE_APP_ADDR_SPACE 0x1 /* enum */
901 #define	MC_CMD_FC_COMP_TYPE_FLASH 0x2 /* enum */
902 
903 /* MC_CMD_FC_IN_IO_REL_GET_ADDR msgrequest */
904 #define	MC_CMD_FC_IN_IO_REL_GET_ADDR_LEN 8
905 /*            MC_CMD_FC_IN_CMD_OFST 0 */
906 /*            MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */
907 
908 /* MC_CMD_FC_IN_IO_REL_READ32 msgrequest */
909 #define	MC_CMD_FC_IN_IO_REL_READ32_LEN 20
910 /*            MC_CMD_FC_IN_CMD_OFST 0 */
911 /*            MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */
912 #define	MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_OFST 8
913 #define	MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_OFST 12
914 #define	MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_OFST 16
915 
916 /* MC_CMD_FC_IN_IO_REL_WRITE32 msgrequest */
917 #define	MC_CMD_FC_IN_IO_REL_WRITE32_LENMIN 20
918 #define	MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX 252
919 #define	MC_CMD_FC_IN_IO_REL_WRITE32_LEN(num) (16+4*(num))
920 /*            MC_CMD_FC_IN_CMD_OFST 0 */
921 /*            MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */
922 #define	MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_OFST 8
923 #define	MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_OFST 12
924 #define	MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_OFST 16
925 #define	MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_LEN 4
926 #define	MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MINNUM 1
927 #define	MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM 59
928 
929 /* MC_CMD_FC_IN_UHLINK msgrequest */
930 #define	MC_CMD_FC_IN_UHLINK_LEN 8
931 /*            MC_CMD_FC_IN_CMD_OFST 0 */
932 #define	MC_CMD_FC_IN_UHLINK_HEADER_OFST 4
933 #define	MC_CMD_FC_IN_UHLINK_OP_LBN 0
934 #define	MC_CMD_FC_IN_UHLINK_OP_WIDTH 8
935 #define	MC_CMD_FC_OP_UHLINK_PHY 0x1 /* enum */
936 #define	MC_CMD_FC_OP_UHLINK_MAC 0x2 /* enum */
937 #define	MC_CMD_FC_OP_UHLINK_RX_EYE 0x3 /* enum */
938 #define	MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT 0x4 /* enum */
939 #define	MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT 0x5 /* enum */
940 #define	MC_CMD_FC_OP_UHLINK_RX_TUNE 0x6 /* enum */
941 #define	MC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7 /* enum */
942 #define	MC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8 /* enum */
943 #define	MC_CMD_FC_IN_UHLINK_PORT_TYPE_LBN 8
944 #define	MC_CMD_FC_IN_UHLINK_PORT_TYPE_WIDTH 8
945 #define	MC_CMD_FC_IN_UHLINK_PORT_IDX_LBN 16
946 #define	MC_CMD_FC_IN_UHLINK_PORT_IDX_WIDTH 8
947 #define	MC_CMD_FC_IN_UHLINK_CMD_FORMAT_LBN 24
948 #define	MC_CMD_FC_IN_UHLINK_CMD_FORMAT_WIDTH 8
949 #define	MC_CMD_FC_OP_UHLINK_CMD_FORMAT_DEFAULT 0x0 /* enum */
950 #define	MC_CMD_FC_OP_UHLINK_CMD_FORMAT_PORT_OVERRIDE 0x1 /* enum */
951 
952 /* MC_CMD_FC_OP_UHLINK_PHY msgrequest */
953 #define	MC_CMD_FC_OP_UHLINK_PHY_LEN 8
954 /*            MC_CMD_FC_IN_CMD_OFST 0 */
955 /*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
956 
957 /* MC_CMD_FC_OP_UHLINK_MAC msgrequest */
958 #define	MC_CMD_FC_OP_UHLINK_MAC_LEN 8
959 /*            MC_CMD_FC_IN_CMD_OFST 0 */
960 /*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
961 
962 /* MC_CMD_FC_OP_UHLINK_RX_EYE msgrequest */
963 #define	MC_CMD_FC_OP_UHLINK_RX_EYE_LEN 12
964 /*            MC_CMD_FC_IN_CMD_OFST 0 */
965 /*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
966 #define	MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_OFST 8
967 #define	MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 0x30 /* enum */
968 
969 /* MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT msgrequest */
970 #define	MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT_LEN 8
971 /*            MC_CMD_FC_IN_CMD_OFST 0 */
972 /*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
973 
974 /* MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT msgrequest */
975 #define	MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_LEN 20
976 /*            MC_CMD_FC_IN_CMD_OFST 0 */
977 /*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
978 #define	MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_OFST 8
979 #define	MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_OFST 12
980 #define	MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_OFST 16
981 #define	MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 0x1e /* enum */
982 
983 /* MC_CMD_FC_OP_UHLINK_RX_TUNE msgrequest */
984 #define	MC_CMD_FC_OP_UHLINK_RX_TUNE_LEN 8
985 /*            MC_CMD_FC_IN_CMD_OFST 0 */
986 /*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
987 
988 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_SET msgrequest */
989 #define	MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_LEN 16
990 /*            MC_CMD_FC_IN_CMD_OFST 0 */
991 /*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
992 #define	MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_OFST 8
993 #define	MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PCS_SERIAL 0x0 /* enum */
994 #define	MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_PRE_CDR 0x1 /* enum */
995 #define	MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_POST_CDR 0x2 /* enum */
996 #define	MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_OFST 12
997 #define	MC_CMD_FC_UHLINK_LOOPBACK_STATE_OFF 0x0 /* enum */
998 #define	MC_CMD_FC_UHLINK_LOOPBACK_STATE_ON 0x1 /* enum */
999 
1000 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_GET msgrequest */
1001 #define	MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_LEN 12
1002 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1003 /*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
1004 #define	MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_OFST 8
1005 
1006 /* MC_CMD_FC_IN_SET_LINK msgrequest */
1007 #define	MC_CMD_FC_IN_SET_LINK_LEN 16
1008 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1009 #define	MC_CMD_FC_IN_SET_LINK_MODE_OFST 4
1010 #define	MC_CMD_FC_IN_SET_LINK_SPEED_OFST 8
1011 #define	MC_CMD_FC_IN_SET_LINK_FLAGS_OFST 12
1012 #define	MC_CMD_FC_IN_SET_LINK_LOWPOWER_LBN 0
1013 #define	MC_CMD_FC_IN_SET_LINK_LOWPOWER_WIDTH 1
1014 #define	MC_CMD_FC_IN_SET_LINK_POWEROFF_LBN 1
1015 #define	MC_CMD_FC_IN_SET_LINK_POWEROFF_WIDTH 1
1016 #define	MC_CMD_FC_IN_SET_LINK_TXDIS_LBN 2
1017 #define	MC_CMD_FC_IN_SET_LINK_TXDIS_WIDTH 1
1018 
1019 /* MC_CMD_FC_IN_LICENSE msgrequest */
1020 #define	MC_CMD_FC_IN_LICENSE_LEN 8
1021 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1022 #define	MC_CMD_FC_IN_LICENSE_OP_OFST 4
1023 #define	MC_CMD_FC_IN_LICENSE_UPDATE_LICENSE 0x0 /* enum */
1024 #define	MC_CMD_FC_IN_LICENSE_GET_KEY_STATS 0x1 /* enum */
1025 
1026 /* MC_CMD_FC_IN_STARTUP msgrequest */
1027 #define	MC_CMD_FC_IN_STARTUP_LEN 40
1028 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1029 #define	MC_CMD_FC_IN_STARTUP_BASE_OFST 4
1030 #define	MC_CMD_FC_IN_STARTUP_LENGTH_OFST 8
1031 #define	MC_CMD_FC_IN_STARTUP_IDLENGTH_OFST 12
1032 #define	MC_CMD_FC_IN_STARTUP_ID_OFST 16
1033 #define	MC_CMD_FC_IN_STARTUP_ID_LEN 1
1034 #define	MC_CMD_FC_IN_STARTUP_ID_NUM 24
1035 
1036 /* MC_CMD_FC_IN_DMA msgrequest */
1037 #define	MC_CMD_FC_IN_DMA_LEN 8
1038 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1039 #define	MC_CMD_FC_IN_DMA_OP_OFST 4
1040 #define	MC_CMD_FC_IN_DMA_STOP  0x0 /* enum */
1041 #define	MC_CMD_FC_IN_DMA_READ  0x1 /* enum */
1042 
1043 /* MC_CMD_FC_IN_DMA_STOP msgrequest */
1044 #define	MC_CMD_FC_IN_DMA_STOP_LEN 12
1045 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1046 /*            MC_CMD_FC_IN_DMA_OP_OFST 4 */
1047 #define	MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_OFST 8
1048 
1049 /* MC_CMD_FC_IN_DMA_READ msgrequest */
1050 #define	MC_CMD_FC_IN_DMA_READ_LEN 16
1051 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1052 /*            MC_CMD_FC_IN_DMA_OP_OFST 4 */
1053 #define	MC_CMD_FC_IN_DMA_READ_OFFSET_OFST 8
1054 #define	MC_CMD_FC_IN_DMA_READ_LENGTH_OFST 12
1055 
1056 /* MC_CMD_FC_IN_TIMED_READ msgrequest */
1057 #define	MC_CMD_FC_IN_TIMED_READ_LEN 8
1058 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1059 #define	MC_CMD_FC_IN_TIMED_READ_OP_OFST 4
1060 #define	MC_CMD_FC_IN_TIMED_READ_SET  0x0 /* enum */
1061 #define	MC_CMD_FC_IN_TIMED_READ_GET  0x1 /* enum */
1062 #define	MC_CMD_FC_IN_TIMED_READ_CLEAR  0x2 /* enum */
1063 
1064 /* MC_CMD_FC_IN_TIMED_READ_SET msgrequest */
1065 #define	MC_CMD_FC_IN_TIMED_READ_SET_LEN 52
1066 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1067 /*            MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */
1068 #define	MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_OFST 8
1069 #define	MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12
1070 #define	MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8
1071 #define	MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12
1072 #define	MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16
1073 #define	MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20
1074 #define	MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8
1075 #define	MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20
1076 #define	MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24
1077 #define	MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28
1078 #define	MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_OFST 32
1079 #define	MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_OFST 36
1080 #define	MC_CMD_FC_IN_TIMED_READ_SET_DATA_OFST 40
1081 #define	MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_OFST 44
1082 #define	MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_LBN 0
1083 #define	MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_WIDTH 1
1084 #define	MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_LBN 1
1085 #define	MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_WIDTH 1
1086 #define	MC_CMD_FC_IN_TIMED_READ_SET_EVENT_LBN 2
1087 #define	MC_CMD_FC_IN_TIMED_READ_SET_EVENT_WIDTH 1
1088 #define	MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_LBN 3
1089 #define	MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_WIDTH 2
1090 #define	MC_CMD_FC_IN_TIMED_READ_SET_NONE  0x0 /* enum */
1091 #define	MC_CMD_FC_IN_TIMED_READ_SET_READ  0x1 /* enum */
1092 #define	MC_CMD_FC_IN_TIMED_READ_SET_WRITE  0x2 /* enum */
1093 #define	MC_CMD_FC_IN_TIMED_READ_SET_READWRITE  0x3 /* enum */
1094 #define	MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_OFST 48
1095 
1096 /* MC_CMD_FC_IN_TIMED_READ_GET msgrequest */
1097 #define	MC_CMD_FC_IN_TIMED_READ_GET_LEN 12
1098 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1099 /*            MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */
1100 #define	MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_OFST 8
1101 
1102 /* MC_CMD_FC_IN_TIMED_READ_CLEAR msgrequest */
1103 #define	MC_CMD_FC_IN_TIMED_READ_CLEAR_LEN 12
1104 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1105 /*            MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */
1106 #define	MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_OFST 8
1107 
1108 /* MC_CMD_FC_IN_LOG msgrequest */
1109 #define	MC_CMD_FC_IN_LOG_LEN 8
1110 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1111 #define	MC_CMD_FC_IN_LOG_OP_OFST 4
1112 #define	MC_CMD_FC_IN_LOG_ADDR_RANGE  0x0 /* enum */
1113 #define	MC_CMD_FC_IN_LOG_JTAG_UART  0x1 /* enum */
1114 
1115 /* MC_CMD_FC_IN_LOG_ADDR_RANGE msgrequest */
1116 #define	MC_CMD_FC_IN_LOG_ADDR_RANGE_LEN 20
1117 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1118 /*            MC_CMD_FC_IN_LOG_OP_OFST 4 */
1119 #define	MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_OFST 8
1120 #define	MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_OFST 12
1121 #define	MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_OFST 16
1122 
1123 /* MC_CMD_FC_IN_LOG_JTAG_UART msgrequest */
1124 #define	MC_CMD_FC_IN_LOG_JTAG_UART_LEN 12
1125 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1126 /*            MC_CMD_FC_IN_LOG_OP_OFST 4 */
1127 #define	MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_OFST 8
1128 
1129 /* MC_CMD_FC_IN_CLOCK msgrequest */
1130 #define	MC_CMD_FC_IN_CLOCK_LEN 12
1131 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1132 #define	MC_CMD_FC_IN_CLOCK_OP_OFST 4
1133 #define	MC_CMD_FC_IN_CLOCK_GET_TIME  0x0 /* enum */
1134 #define	MC_CMD_FC_IN_CLOCK_SET_TIME  0x1 /* enum */
1135 #define	MC_CMD_FC_IN_CLOCK_ID_OFST 8
1136 #define	MC_CMD_FC_IN_CLOCK_STATS  0x0 /* enum */
1137 #define	MC_CMD_FC_IN_CLOCK_MAC  0x1 /* enum */
1138 
1139 /* MC_CMD_FC_IN_CLOCK_GET_TIME msgrequest */
1140 #define	MC_CMD_FC_IN_CLOCK_GET_TIME_LEN 12
1141 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1142 /*            MC_CMD_FC_IN_CLOCK_OP_OFST 4 */
1143 /*            MC_CMD_FC_IN_CLOCK_ID_OFST 8 */
1144 
1145 /* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest */
1146 #define	MC_CMD_FC_IN_CLOCK_SET_TIME_LEN 24
1147 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1148 /*            MC_CMD_FC_IN_CLOCK_OP_OFST 4 */
1149 /*            MC_CMD_FC_IN_CLOCK_ID_OFST 8 */
1150 #define	MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12
1151 #define	MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8
1152 #define	MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12
1153 #define	MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16
1154 #define	MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20
1155 
1156 /* MC_CMD_FC_IN_DDR msgrequest */
1157 #define	MC_CMD_FC_IN_DDR_LEN 12
1158 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1159 #define	MC_CMD_FC_IN_DDR_OP_OFST 4
1160 #define	MC_CMD_FC_IN_DDR_SET_SPD  0x0 /* enum */
1161 #define	MC_CMD_FC_IN_DDR_GET_STATUS  0x1 /* enum */
1162 #define	MC_CMD_FC_IN_DDR_BANK_OFST 8
1163 #define	MC_CMD_FC_IN_DDR_BANK_B0  0x0 /* enum */
1164 #define	MC_CMD_FC_IN_DDR_BANK_B1  0x1 /* enum */
1165 #define	MC_CMD_FC_IN_DDR_BANK_T0  0x2 /* enum */
1166 #define	MC_CMD_FC_IN_DDR_BANK_T1  0x3 /* enum */
1167 #define	MC_CMD_FC_IN_DDR_NUM_BANKS  0x4 /* enum */
1168 
1169 /* MC_CMD_FC_IN_DDR_SET_SPD msgrequest */
1170 #define	MC_CMD_FC_IN_DDR_SET_SPD_LEN 148
1171 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1172 /*            MC_CMD_FC_IN_DDR_OP_OFST 4 */
1173 /*            MC_CMD_FC_IN_DDR_BANK_OFST 8 */
1174 #define	MC_CMD_FC_IN_DDR_FLAGS_OFST 12
1175 #define	MC_CMD_FC_IN_DDR_SET_SPD_ACTIVE  0x1 /* enum */
1176 #define	MC_CMD_FC_IN_DDR_SPD_OFST 16
1177 #define	MC_CMD_FC_IN_DDR_SPD_LEN 1
1178 #define	MC_CMD_FC_IN_DDR_SPD_NUM 128
1179 #define	MC_CMD_FC_IN_DDR_SPD_PAGE_ID_OFST 144
1180 
1181 /* MC_CMD_FC_IN_DDR_GET_STATUS msgrequest */
1182 #define	MC_CMD_FC_IN_DDR_GET_STATUS_LEN 12
1183 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1184 /*            MC_CMD_FC_IN_DDR_OP_OFST 4 */
1185 /*            MC_CMD_FC_IN_DDR_BANK_OFST 8 */
1186 
1187 /* MC_CMD_FC_IN_TIMESTAMP msgrequest */
1188 #define	MC_CMD_FC_IN_TIMESTAMP_LEN 8
1189 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1190 #define	MC_CMD_FC_IN_TIMESTAMP_OP_OFST 4
1191 #define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT 0x0 /* enum */
1192 #define	MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT 0x1 /* enum */
1193 #define	MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT 0x2 /* enum */
1194 
1195 /* MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT msgrequest */
1196 #define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LEN 28
1197 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1198 #define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_OFST 4
1199 #define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_OFST 8
1200 #define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LATEST 0x0 /* enum */
1201 #define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_MATCH 0x1 /* enum */
1202 #define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12
1203 #define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8
1204 #define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12
1205 #define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16
1206 #define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20
1207 #define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_OFST 24
1208 
1209 /* MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT msgrequest */
1210 #define	MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_LEN 8
1211 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1212 #define	MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_OFST 4
1213 
1214 /* MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT msgrequest */
1215 #define	MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_LEN 8
1216 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1217 #define	MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_OFST 4
1218 
1219 /* MC_CMD_FC_IN_SPI msgrequest */
1220 #define	MC_CMD_FC_IN_SPI_LEN 8
1221 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1222 #define	MC_CMD_FC_IN_SPI_OP_OFST 4
1223 #define	MC_CMD_FC_IN_SPI_READ 0x0 /* enum */
1224 #define	MC_CMD_FC_IN_SPI_WRITE 0x1 /* enum */
1225 #define	MC_CMD_FC_IN_SPI_ERASE 0x2 /* enum */
1226 
1227 /* MC_CMD_FC_IN_SPI_READ msgrequest */
1228 #define	MC_CMD_FC_IN_SPI_READ_LEN 16
1229 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1230 #define	MC_CMD_FC_IN_SPI_READ_OP_OFST 4
1231 #define	MC_CMD_FC_IN_SPI_READ_ADDR_OFST 8
1232 #define	MC_CMD_FC_IN_SPI_READ_NUMBYTES_OFST 12
1233 
1234 /* MC_CMD_FC_IN_SPI_WRITE msgrequest */
1235 #define	MC_CMD_FC_IN_SPI_WRITE_LENMIN 16
1236 #define	MC_CMD_FC_IN_SPI_WRITE_LENMAX 252
1237 #define	MC_CMD_FC_IN_SPI_WRITE_LEN(num) (12+4*(num))
1238 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1239 #define	MC_CMD_FC_IN_SPI_WRITE_OP_OFST 4
1240 #define	MC_CMD_FC_IN_SPI_WRITE_ADDR_OFST 8
1241 #define	MC_CMD_FC_IN_SPI_WRITE_BUFFER_OFST 12
1242 #define	MC_CMD_FC_IN_SPI_WRITE_BUFFER_LEN 4
1243 #define	MC_CMD_FC_IN_SPI_WRITE_BUFFER_MINNUM 1
1244 #define	MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM 60
1245 
1246 /* MC_CMD_FC_IN_SPI_ERASE msgrequest */
1247 #define	MC_CMD_FC_IN_SPI_ERASE_LEN 16
1248 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1249 #define	MC_CMD_FC_IN_SPI_ERASE_OP_OFST 4
1250 #define	MC_CMD_FC_IN_SPI_ERASE_ADDR_OFST 8
1251 #define	MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_OFST 12
1252 
1253 /* MC_CMD_FC_IN_DIAG msgrequest */
1254 #define	MC_CMD_FC_IN_DIAG_LEN 8
1255 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1256 #define	MC_CMD_FC_IN_DIAG_OP_OFST 4
1257 #define	MC_CMD_FC_IN_DIAG_POWER_NOISE 0x0 /* enum */
1258 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK 0x1 /* enum */
1259 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL 0x2 /* enum */
1260 
1261 /* MC_CMD_FC_IN_DIAG_POWER_NOISE msgrequest */
1262 #define	MC_CMD_FC_IN_DIAG_POWER_NOISE_LEN 12
1263 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1264 #define	MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_OFST 4
1265 #define	MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_OFST 8
1266 #define	MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG 0x0 /* enum */
1267 #define	MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG 0x1 /* enum */
1268 
1269 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG msgrequest */
1270 #define	MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_LEN 12
1271 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1272 #define	MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_OFST 4
1273 #define	MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_OFST 8
1274 
1275 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG msgrequest */
1276 #define	MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 20
1277 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1278 #define	MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_OFST 4
1279 #define	MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_OFST 8
1280 #define	MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_OFST 12
1281 #define	MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_OFST 16
1282 
1283 /* MC_CMD_FC_IN_DIAG_DDR_SOAK msgrequest */
1284 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_LEN 12
1285 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1286 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_OFST 4
1287 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_OFST 8
1288 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_START 0x0 /* enum */
1289 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT 0x1 /* enum */
1290 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP 0x2 /* enum */
1291 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR 0x3 /* enum */
1292 
1293 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_START msgrequest */
1294 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_START_LEN 24
1295 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1296 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_OFST 4
1297 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_OFST 8
1298 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_OFST 12
1299 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_OFST 16
1300 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ZEROS 0x0 /* enum */
1301 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONES 0x1 /* enum */
1302 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_OFST 20
1303 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONGOING_TEST 0x0 /* enum */
1304 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SINGLE_TEST 0x1 /* enum */
1305 
1306 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT msgrequest */
1307 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_LEN 16
1308 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1309 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_OFST 4
1310 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_OFST 8
1311 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_OFST 12
1312 #define	MC_CMD_FC_DDR_BANK0 0x0 /* enum */
1313 #define	MC_CMD_FC_DDR_BANK1 0x1 /* enum */
1314 #define	MC_CMD_FC_DDR_BANK2 0x2 /* enum */
1315 #define	MC_CMD_FC_DDR_BANK3 0x3 /* enum */
1316 #define	MC_CMD_FC_DDR_AOEMEM_MAX_BANKS 0x4 /* enum */
1317 
1318 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP msgrequest */
1319 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_LEN 16
1320 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1321 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_OFST 4
1322 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_OFST 8
1323 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_OFST 12
1324 
1325 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR msgrequest */
1326 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_LEN 20
1327 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1328 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_OFST 4
1329 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_OFST 8
1330 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_OFST 12
1331 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_OFST 16
1332 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_CLEAR 0x0 /* enum */
1333 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SET 0x1 /* enum */
1334 
1335 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL msgrequest */
1336 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_LEN 12
1337 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1338 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_OFST 4
1339 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_OFST 8
1340 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE 0x0 /* enum */
1341 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG 0x1 /* enum */
1342 
1343 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE msgrequest */
1344 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_LEN 16
1345 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1346 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_OFST 4
1347 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_OFST 8
1348 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_OFST 12
1349 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_PASSTHROUGH 0x0 /* enum */
1350 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SNAKE 0x1 /* enum */
1351 
1352 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG msgrequest */
1353 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 24
1354 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1355 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_OFST 4
1356 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_OFST 8
1357 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_OFST 12
1358 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_OFST 16
1359 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_OFST 20
1360 
1361 /* MC_CMD_FC_OUT msgresponse */
1362 #define	MC_CMD_FC_OUT_LEN 0
1363 
1364 /* MC_CMD_FC_OUT_NULL msgresponse */
1365 #define	MC_CMD_FC_OUT_NULL_LEN 0
1366 
1367 /* MC_CMD_FC_OUT_READ32 msgresponse */
1368 #define	MC_CMD_FC_OUT_READ32_LENMIN 4
1369 #define	MC_CMD_FC_OUT_READ32_LENMAX 252
1370 #define	MC_CMD_FC_OUT_READ32_LEN(num) (0+4*(num))
1371 #define	MC_CMD_FC_OUT_READ32_BUFFER_OFST 0
1372 #define	MC_CMD_FC_OUT_READ32_BUFFER_LEN 4
1373 #define	MC_CMD_FC_OUT_READ32_BUFFER_MINNUM 1
1374 #define	MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM 63
1375 
1376 /* MC_CMD_FC_OUT_WRITE32 msgresponse */
1377 #define	MC_CMD_FC_OUT_WRITE32_LEN 0
1378 
1379 /* MC_CMD_FC_OUT_TRC_READ msgresponse */
1380 #define	MC_CMD_FC_OUT_TRC_READ_LEN 16
1381 #define	MC_CMD_FC_OUT_TRC_READ_DATA_OFST 0
1382 #define	MC_CMD_FC_OUT_TRC_READ_DATA_LEN 4
1383 #define	MC_CMD_FC_OUT_TRC_READ_DATA_NUM 4
1384 
1385 /* MC_CMD_FC_OUT_TRC_WRITE msgresponse */
1386 #define	MC_CMD_FC_OUT_TRC_WRITE_LEN 0
1387 
1388 /* MC_CMD_FC_OUT_GET_VERSION msgresponse */
1389 #define	MC_CMD_FC_OUT_GET_VERSION_LEN 12
1390 #define	MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_OFST 0
1391 #define	MC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4
1392 #define	MC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8
1393 #define	MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4
1394 #define	MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8
1395 
1396 /* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */
1397 #define	MC_CMD_FC_OUT_TRC_RX_READ_LEN 8
1398 #define	MC_CMD_FC_OUT_TRC_RX_READ_DATA_OFST 0
1399 #define	MC_CMD_FC_OUT_TRC_RX_READ_DATA_LEN 4
1400 #define	MC_CMD_FC_OUT_TRC_RX_READ_DATA_NUM 2
1401 
1402 /* MC_CMD_FC_OUT_TRC_RX_WRITE msgresponse */
1403 #define	MC_CMD_FC_OUT_TRC_RX_WRITE_LEN 0
1404 
1405 /* MC_CMD_FC_OUT_MAC_RECONFIGURE msgresponse */
1406 #define	MC_CMD_FC_OUT_MAC_RECONFIGURE_LEN 0
1407 
1408 /* MC_CMD_FC_OUT_MAC_SET_LINK msgresponse */
1409 #define	MC_CMD_FC_OUT_MAC_SET_LINK_LEN 0
1410 
1411 /* MC_CMD_FC_OUT_MAC_READ_STATUS msgresponse */
1412 #define	MC_CMD_FC_OUT_MAC_READ_STATUS_LEN 4
1413 #define	MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_OFST 0
1414 
1415 /* MC_CMD_FC_OUT_MAC_GET_RX_STATS msgresponse */
1416 #define	MC_CMD_FC_OUT_MAC_GET_RX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_RX_NSTATS))+1))>>3)
1417 #define	MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0
1418 #define	MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8
1419 #define	MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0
1420 #define	MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4
1421 #define	MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS
1422 #define	MC_CMD_FC_MAC_RX_STATS_OCTETS  0x0 /* enum */
1423 #define	MC_CMD_FC_MAC_RX_OCTETS_OK  0x1 /* enum */
1424 #define	MC_CMD_FC_MAC_RX_ALIGNMENT_ERRORS  0x2 /* enum */
1425 #define	MC_CMD_FC_MAC_RX_PAUSE_MAC_CTRL_FRAMES  0x3 /* enum */
1426 #define	MC_CMD_FC_MAC_RX_FRAMES_OK  0x4 /* enum */
1427 #define	MC_CMD_FC_MAC_RX_CRC_ERRORS  0x5 /* enum */
1428 #define	MC_CMD_FC_MAC_RX_VLAN_OK  0x6 /* enum */
1429 #define	MC_CMD_FC_MAC_RX_ERRORS  0x7 /* enum */
1430 #define	MC_CMD_FC_MAC_RX_UCAST_PKTS  0x8 /* enum */
1431 #define	MC_CMD_FC_MAC_RX_MULTICAST_PKTS  0x9 /* enum */
1432 #define	MC_CMD_FC_MAC_RX_BROADCAST_PKTS  0xa /* enum */
1433 #define	MC_CMD_FC_MAC_RX_STATS_DROP_EVENTS  0xb /* enum */
1434 #define	MC_CMD_FC_MAC_RX_STATS_PKTS  0xc /* enum */
1435 #define	MC_CMD_FC_MAC_RX_STATS_UNDERSIZE_PKTS  0xd /* enum */
1436 #define	MC_CMD_FC_MAC_RX_STATS_PKTS_64  0xe /* enum */
1437 #define	MC_CMD_FC_MAC_RX_STATS_PKTS_65_127  0xf /* enum */
1438 #define	MC_CMD_FC_MAC_RX_STATS_PKTS_128_255  0x10 /* enum */
1439 #define	MC_CMD_FC_MAC_RX_STATS_PKTS_256_511  0x11 /* enum */
1440 #define	MC_CMD_FC_MAC_RX_STATS_PKTS_512_1023  0x12 /* enum */
1441 #define	MC_CMD_FC_MAC_RX_STATS_PKTS_1024_1518  0x13 /* enum */
1442 #define	MC_CMD_FC_MAC_RX_STATS_PKTS_1519_MAX  0x14 /* enum */
1443 #define	MC_CMD_FC_MAC_RX_STATS_OVERSIZE_PKTS  0x15 /* enum */
1444 #define	MC_CMD_FC_MAC_RX_STATS_JABBERS  0x16 /* enum */
1445 #define	MC_CMD_FC_MAC_RX_STATS_FRAGMENTS  0x17 /* enum */
1446 #define	MC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES  0x18 /* enum */
1447 #define	MC_CMD_FC_MAC_RX_NSTATS  0x19 /* enum */
1448 
1449 /* MC_CMD_FC_OUT_MAC_GET_TX_STATS msgresponse */
1450 #define	MC_CMD_FC_OUT_MAC_GET_TX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_TX_NSTATS))+1))>>3)
1451 #define	MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0
1452 #define	MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8
1453 #define	MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0
1454 #define	MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4
1455 #define	MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS
1456 #define	MC_CMD_FC_MAC_TX_STATS_OCTETS  0x0 /* enum */
1457 #define	MC_CMD_FC_MAC_TX_OCTETS_OK  0x1 /* enum */
1458 #define	MC_CMD_FC_MAC_TX_ALIGNMENT_ERRORS  0x2 /* enum */
1459 #define	MC_CMD_FC_MAC_TX_PAUSE_MAC_CTRL_FRAMES  0x3 /* enum */
1460 #define	MC_CMD_FC_MAC_TX_FRAMES_OK  0x4 /* enum */
1461 #define	MC_CMD_FC_MAC_TX_CRC_ERRORS  0x5 /* enum */
1462 #define	MC_CMD_FC_MAC_TX_VLAN_OK  0x6 /* enum */
1463 #define	MC_CMD_FC_MAC_TX_ERRORS  0x7 /* enum */
1464 #define	MC_CMD_FC_MAC_TX_UCAST_PKTS  0x8 /* enum */
1465 #define	MC_CMD_FC_MAC_TX_MULTICAST_PKTS  0x9 /* enum */
1466 #define	MC_CMD_FC_MAC_TX_BROADCAST_PKTS  0xa /* enum */
1467 #define	MC_CMD_FC_MAC_TX_STATS_DROP_EVENTS  0xb /* enum */
1468 #define	MC_CMD_FC_MAC_TX_STATS_PKTS  0xc /* enum */
1469 #define	MC_CMD_FC_MAC_TX_STATS_UNDERSIZE_PKTS  0xd /* enum */
1470 #define	MC_CMD_FC_MAC_TX_STATS_PKTS_64  0xe /* enum */
1471 #define	MC_CMD_FC_MAC_TX_STATS_PKTS_65_127  0xf /* enum */
1472 #define	MC_CMD_FC_MAC_TX_STATS_PKTS_128_255  0x10 /* enum */
1473 #define	MC_CMD_FC_MAC_TX_STATS_PKTS_256_511  0x11 /* enum */
1474 #define	MC_CMD_FC_MAC_TX_STATS_PKTS_512_1023  0x12 /* enum */
1475 #define	MC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518  0x13 /* enum */
1476 #define	MC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU  0x14 /* enum */
1477 #define	MC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES  0x15 /* enum */
1478 #define	MC_CMD_FC_MAC_TX_NSTATS  0x16 /* enum */
1479 
1480 /* MC_CMD_FC_OUT_MAC_GET_STATS msgresponse */
1481 #define	MC_CMD_FC_OUT_MAC_GET_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_NSTATS_PER_BLOCK))+1))>>3)
1482 #define	MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0
1483 #define	MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8
1484 #define	MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0
1485 #define	MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4
1486 #define	MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK
1487 
1488 /* MC_CMD_FC_OUT_MAC msgresponse */
1489 #define	MC_CMD_FC_OUT_MAC_LEN 0
1490 
1491 /* MC_CMD_FC_OUT_SFP msgresponse */
1492 #define	MC_CMD_FC_OUT_SFP_LEN 0
1493 
1494 /* MC_CMD_FC_OUT_DDR_TEST_START msgresponse */
1495 #define	MC_CMD_FC_OUT_DDR_TEST_START_LEN 0
1496 
1497 /* MC_CMD_FC_OUT_DDR_TEST_POLL msgresponse */
1498 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_LEN 8
1499 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_OFST 0
1500 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_LBN 0
1501 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_WIDTH 8
1502 #define	MC_CMD_FC_OP_DDR_TEST_NONE 0x0 /* enum */
1503 #define	MC_CMD_FC_OP_DDR_TEST_INPROGRESS 0x1 /* enum */
1504 #define	MC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2 /* enum */
1505 #define	MC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3 /* enum */
1506 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_LBN 11
1507 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_WIDTH 1
1508 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_LBN 10
1509 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_WIDTH 1
1510 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_LBN 9
1511 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_WIDTH 1
1512 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_LBN 8
1513 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_WIDTH 1
1514 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_OFST 4
1515 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_LBN 31
1516 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_WIDTH 1
1517 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_LBN 30
1518 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_WIDTH 1
1519 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_LBN 29
1520 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_WIDTH 1
1521 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_LBN 28
1522 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_WIDTH 1
1523 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_T0_LBN 15
1524 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_T0_WIDTH 5
1525 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_T1_LBN 10
1526 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_T1_WIDTH 5
1527 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_B0_LBN 5
1528 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_B0_WIDTH 5
1529 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_B1_LBN 0
1530 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_B1_WIDTH 5
1531 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_COMPLETE 0x0 /* enum */
1532 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_FAIL 0x1 /* enum */
1533 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_PASS 0x2 /* enum */
1534 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_FAIL 0x3 /* enum */
1535 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_SUCCESS 0x4 /* enum */
1536 
1537 /* MC_CMD_FC_OUT_DDR_TEST msgresponse */
1538 #define	MC_CMD_FC_OUT_DDR_TEST_LEN 0
1539 
1540 /* MC_CMD_FC_OUT_GET_ASSERT msgresponse */
1541 #define	MC_CMD_FC_OUT_GET_ASSERT_LEN 144
1542 #define	MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_OFST 0
1543 #define	MC_CMD_FC_OUT_GET_ASSERT_STATE_LBN 8
1544 #define	MC_CMD_FC_OUT_GET_ASSERT_STATE_WIDTH 8
1545 #define	MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 /* enum */
1546 #define	MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 /* enum */
1547 #define	MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 /* enum */
1548 #define	MC_CMD_FC_OUT_GET_ASSERT_TYPE_LBN 0
1549 #define	MC_CMD_FC_OUT_GET_ASSERT_TYPE_WIDTH 8
1550 #define	MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 /* enum */
1551 #define	MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 /* enum */
1552 #define	MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 /* enum */
1553 #define	MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_OFST 4
1554 #define	MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_OFST 8
1555 #define	MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_LEN 4
1556 #define	MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_NUM 31
1557 #define	MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_OFST 132
1558 #define	MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_OFST 136
1559 #define	MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_OFST 140
1560 
1561 /* MC_CMD_FC_OUT_FPGA_BUILD msgresponse */
1562 #define	MC_CMD_FC_OUT_FPGA_BUILD_LEN 32
1563 #define	MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_OFST 0
1564 #define	MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_LBN 31
1565 #define	MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_WIDTH 1
1566 #define	MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_LBN 30
1567 #define	MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_WIDTH 1
1568 #define	MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_LBN 16
1569 #define	MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_WIDTH 14
1570 #define	MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_LBN 12
1571 #define	MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_WIDTH 4
1572 #define	MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_LBN 4
1573 #define	MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_WIDTH 8
1574 #define	MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_LBN 0
1575 #define	MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_WIDTH 4
1576 #define	MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_OFST 4
1577 #define	MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_OFST 8
1578 #define	MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_LBN 0
1579 #define	MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_WIDTH 8
1580 #define	MC_CMD_FC_FPGA_TYPE_A7 0xa7 /* enum */
1581 #define	MC_CMD_FC_FPGA_TYPE_A5 0xa5 /* enum */
1582 #define	MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_LBN 8
1583 #define	MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_WIDTH 10
1584 #define	MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_LBN 18
1585 #define	MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_WIDTH 1
1586 #define	MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_LBN 19
1587 #define	MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_WIDTH 1
1588 #define	MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_LBN 20
1589 #define	MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_WIDTH 1
1590 #define	MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_LBN 21
1591 #define	MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_WIDTH 1
1592 #define	MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_LBN 22
1593 #define	MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_WIDTH 1
1594 #define	MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_LBN 23
1595 #define	MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_WIDTH 1
1596 #define	MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_LBN 24
1597 #define	MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_WIDTH 1
1598 #define	MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_LBN 25
1599 #define	MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_WIDTH 1
1600 #define	MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_LBN 26
1601 #define	MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_WIDTH 1
1602 #define	MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_LBN 27
1603 #define	MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_WIDTH 1
1604 #define	MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_LBN 28
1605 #define	MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_WIDTH 1
1606 #define	MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_LBN 29
1607 #define	MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_WIDTH 2
1608 #define	MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_LBN 31
1609 #define	MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_WIDTH 1
1610 #define	MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_OFST 12
1611 #define	MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_LBN 0
1612 #define	MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_WIDTH 16
1613 #define	MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_LBN 16
1614 #define	MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_WIDTH 1
1615 #define	MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 /* enum */
1616 #define	MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 /* enum */
1617 #define	MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_LBN 17
1618 #define	MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_WIDTH 15
1619 #define	MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_OFST 16
1620 #define	MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_LBN 0
1621 #define	MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_WIDTH 16
1622 #define	MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_LBN 16
1623 #define	MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_WIDTH 16
1624 #define	MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_OFST 20
1625 #define	MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_LBN 0
1626 #define	MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_WIDTH 16
1627 #define	MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_LBN 16
1628 #define	MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_WIDTH 16
1629 #define	MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16
1630 #define	MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8
1631 #define	MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16
1632 #define	MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20
1633 #define	MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24
1634 #define	MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28
1635 #define	MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0
1636 #define	MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16
1637 
1638 /* MC_CMD_FC_OUT_FPGA_SERVICES msgresponse */
1639 #define	MC_CMD_FC_OUT_FPGA_SERVICES_LEN 32
1640 #define	MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0
1641 #define	MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_LBN 31
1642 #define	MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_WIDTH 1
1643 #define	MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_LBN 30
1644 #define	MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_WIDTH 1
1645 #define	MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_LBN 16
1646 #define	MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_WIDTH 14
1647 #define	MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_LBN 12
1648 #define	MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_WIDTH 4
1649 #define	MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_LBN 4
1650 #define	MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_WIDTH 8
1651 #define	MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_LBN 0
1652 #define	MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_WIDTH 4
1653 #define	MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_OFST 4
1654 #define	MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_OFST 8
1655 #define	MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_LBN 8
1656 #define	MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_WIDTH 1
1657 #define	MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_LBN 27
1658 #define	MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_WIDTH 1
1659 #define	MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_LBN 28
1660 #define	MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_WIDTH 1
1661 #define	MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_LBN 29
1662 #define	MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_WIDTH 1
1663 #define	MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_LBN 30
1664 #define	MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_WIDTH 1
1665 #define	MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_LBN 31
1666 #define	MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_WIDTH 1
1667 #define	MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_OFST 12
1668 #define	MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_LBN 0
1669 #define	MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_WIDTH 16
1670 #define	MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_LBN 16
1671 #define	MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_WIDTH 1
1672 #define	MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_OFST 16
1673 #define	MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_LBN 0
1674 #define	MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_WIDTH 16
1675 #define	MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_LBN 16
1676 #define	MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_WIDTH 16
1677 #define	MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_OFST 20
1678 #define	MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_LBN 0
1679 #define	MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_WIDTH 16
1680 #define	MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_LBN 16
1681 #define	MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_WIDTH 16
1682 #define	MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_OFST 24
1683 #define	MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_OFST 28
1684 #define	MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0
1685 #define	MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16
1686 
1687 /* MC_CMD_FC_OUT_BSP_VERSION msgresponse */
1688 #define	MC_CMD_FC_OUT_BSP_VERSION_LEN 4
1689 #define	MC_CMD_FC_OUT_BSP_VERSION_SYSID_OFST 0
1690 #define	MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_LBN 12
1691 #define	MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_WIDTH 4
1692 #define	MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_LBN 4
1693 #define	MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_WIDTH 8
1694 #define	MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_LBN 0
1695 #define	MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_WIDTH 4
1696 
1697 /* MC_CMD_FC_OUT_READ_MAP_COUNT msgresponse */
1698 #define	MC_CMD_FC_OUT_READ_MAP_COUNT_LEN 4
1699 #define	MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_OFST 0
1700 
1701 /* MC_CMD_FC_OUT_READ_MAP_INDEX msgresponse */
1702 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_LEN 164
1703 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_OFST 0
1704 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_OFST 4
1705 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8  0x0 /* enum */
1706 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16  0x1 /* enum */
1707 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_32  0x2 /* enum */
1708 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_64  0x3 /* enum */
1709 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_MASK  0x3 /* enum */
1710 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_FC  0x4 /* enum */
1711 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_MEM  0x8 /* enum */
1712 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_READ  0x10 /* enum */
1713 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE  0x20 /* enum */
1714 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE  0x0 /* enum */
1715 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED  0x40 /* enum */
1716 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8
1717 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8
1718 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8
1719 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12
1720 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16
1721 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8
1722 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16
1723 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20
1724 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24
1725 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28
1726 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8
1727 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28
1728 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32
1729 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36
1730 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1
1731 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_NUM 128
1732 
1733 /* MC_CMD_FC_OUT_READ_MAP msgresponse */
1734 #define	MC_CMD_FC_OUT_READ_MAP_LEN 0
1735 
1736 /* MC_CMD_FC_OUT_CAPABILITIES msgresponse */
1737 #define	MC_CMD_FC_OUT_CAPABILITIES_LEN 8
1738 #define	MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_OFST 0
1739 #define	MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_OFST 4
1740 
1741 /* MC_CMD_FC_OUT_GLOBAL_FLAGS msgresponse */
1742 #define	MC_CMD_FC_OUT_GLOBAL_FLAGS_LEN 4
1743 #define	MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_OFST 0
1744 
1745 /* MC_CMD_FC_OUT_IO_REL msgresponse */
1746 #define	MC_CMD_FC_OUT_IO_REL_LEN 0
1747 
1748 /* MC_CMD_FC_OUT_IO_REL_GET_ADDR msgresponse */
1749 #define	MC_CMD_FC_OUT_IO_REL_GET_ADDR_LEN 8
1750 #define	MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_OFST 0
1751 #define	MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_OFST 4
1752 
1753 /* MC_CMD_FC_OUT_IO_REL_READ32 msgresponse */
1754 #define	MC_CMD_FC_OUT_IO_REL_READ32_LENMIN 4
1755 #define	MC_CMD_FC_OUT_IO_REL_READ32_LENMAX 252
1756 #define	MC_CMD_FC_OUT_IO_REL_READ32_LEN(num) (0+4*(num))
1757 #define	MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_OFST 0
1758 #define	MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_LEN 4
1759 #define	MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MINNUM 1
1760 #define	MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM 63
1761 
1762 /* MC_CMD_FC_OUT_IO_REL_WRITE32 msgresponse */
1763 #define	MC_CMD_FC_OUT_IO_REL_WRITE32_LEN 0
1764 
1765 /* MC_CMD_FC_OUT_UHLINK_PHY msgresponse */
1766 #define	MC_CMD_FC_OUT_UHLINK_PHY_LEN 48
1767 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_OFST 0
1768 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_LBN 0
1769 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_WIDTH 16
1770 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_LBN 16
1771 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_WIDTH 16
1772 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_OFST 4
1773 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_LBN 0
1774 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_WIDTH 16
1775 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_LBN 16
1776 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_WIDTH 16
1777 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_OFST 8
1778 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_LBN 0
1779 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_WIDTH 16
1780 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_LBN 16
1781 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_WIDTH 16
1782 #define	MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_OFST 12
1783 #define	MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_LBN 0
1784 #define	MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_WIDTH 16
1785 #define	MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_LBN 16
1786 #define	MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_WIDTH 16
1787 #define	MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_OFST 16
1788 #define	MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_OFST 20
1789 #define	MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_LBN 0
1790 #define	MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WIDTH 1
1791 #define	MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_LBN 1
1792 #define	MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_WIDTH 1
1793 #define	MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_OFST 24
1794 #define	MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_LEN 20
1795 #define	MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_OFST 24
1796 #define	MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_OFST 28
1797 #define	MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_OFST 32
1798 #define	MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_OFST 36
1799 #define	MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_OFST 40
1800 #define	MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_OFST 44
1801 #define	MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_LBN 0
1802 #define	MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_WIDTH 1
1803 #define	MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_LBN 1
1804 #define	MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_WIDTH 1
1805 #define	MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_LBN 2
1806 #define	MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_WIDTH 1
1807 
1808 /* MC_CMD_FC_OUT_UHLINK_MAC msgresponse */
1809 #define	MC_CMD_FC_OUT_UHLINK_MAC_LEN 20
1810 #define	MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_OFST 0
1811 #define	MC_CMD_FC_OUT_UHLINK_MAC_MTU_OFST 4
1812 #define	MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_OFST 8
1813 #define	MC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12
1814 #define	MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8
1815 #define	MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12
1816 #define	MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16
1817 
1818 /* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */
1819 #define	MC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3)
1820 #define	MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_OFST 0
1821 #define	MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_LEN 4
1822 #define	MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_NUM MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK
1823 
1824 /* MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT msgresponse */
1825 #define	MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT_LEN 0
1826 
1827 /* MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT msgresponse */
1828 #define	MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_LEN ((((32-1+(64*MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK))+1))>>3)
1829 #define	MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_OFST 0
1830 #define	MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4
1831 #define	MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8
1832 #define	MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4
1833 #define	MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8
1834 #define	MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK
1835 
1836 /* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */
1837 #define	MC_CMD_FC_OUT_UHLINK_RX_TUNE_LEN 0
1838 
1839 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET msgresponse */
1840 #define	MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET_LEN 0
1841 
1842 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET msgresponse */
1843 #define	MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_LEN 4
1844 #define	MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_OFST 0
1845 
1846 /* MC_CMD_FC_OUT_UHLINK msgresponse */
1847 #define	MC_CMD_FC_OUT_UHLINK_LEN 0
1848 
1849 /* MC_CMD_FC_OUT_SET_LINK msgresponse */
1850 #define	MC_CMD_FC_OUT_SET_LINK_LEN 0
1851 
1852 /* MC_CMD_FC_OUT_LICENSE msgresponse */
1853 #define	MC_CMD_FC_OUT_LICENSE_LEN 12
1854 #define	MC_CMD_FC_OUT_LICENSE_VALID_KEYS_OFST 0
1855 #define	MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_OFST 4
1856 #define	MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_OFST 8
1857 
1858 /* MC_CMD_FC_OUT_STARTUP msgresponse */
1859 #define	MC_CMD_FC_OUT_STARTUP_LEN 4
1860 #define	MC_CMD_FC_OUT_STARTUP_CAPABILITIES_OFST 0
1861 #define	MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_LBN 0
1862 #define	MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_WIDTH 1
1863 
1864 /* MC_CMD_FC_OUT_DMA_READ msgresponse */
1865 #define	MC_CMD_FC_OUT_DMA_READ_LENMIN 1
1866 #define	MC_CMD_FC_OUT_DMA_READ_LENMAX 252
1867 #define	MC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num))
1868 #define	MC_CMD_FC_OUT_DMA_READ_DATA_OFST 0
1869 #define	MC_CMD_FC_OUT_DMA_READ_DATA_LEN 1
1870 #define	MC_CMD_FC_OUT_DMA_READ_DATA_MINNUM 1
1871 #define	MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM 252
1872 
1873 /* MC_CMD_FC_OUT_TIMED_READ_SET msgresponse */
1874 #define	MC_CMD_FC_OUT_TIMED_READ_SET_LEN 4
1875 #define	MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_OFST 0
1876 
1877 /* MC_CMD_FC_OUT_TIMED_READ_GET msgresponse */
1878 #define	MC_CMD_FC_OUT_TIMED_READ_GET_LEN 52
1879 #define	MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_OFST 0
1880 #define	MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4
1881 #define	MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8
1882 #define	MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4
1883 #define	MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8
1884 #define	MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12
1885 #define	MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8
1886 #define	MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12
1887 #define	MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16
1888 #define	MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20
1889 #define	MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_OFST 24
1890 #define	MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_OFST 28
1891 #define	MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_OFST 32
1892 #define	MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36
1893 #define	MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8
1894 #define	MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36
1895 #define	MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40
1896 #define	MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44
1897 #define	MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8
1898 #define	MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44
1899 #define	MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48
1900 
1901 /* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */
1902 #define	MC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0
1903 
1904 /* MC_CMD_FC_OUT_LOG msgresponse */
1905 #define	MC_CMD_FC_OUT_LOG_LEN 0
1906 
1907 /* MC_CMD_FC_OUT_CLOCK_GET_TIME msgresponse */
1908 #define	MC_CMD_FC_OUT_CLOCK_GET_TIME_LEN 24
1909 #define	MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_OFST 0
1910 #define	MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4
1911 #define	MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8
1912 #define	MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4
1913 #define	MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8
1914 #define	MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12
1915 #define	MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16
1916 #define	MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_OFST 20
1917 
1918 /* MC_CMD_FC_OUT_CLOCK_SET_TIME msgresponse */
1919 #define	MC_CMD_FC_OUT_CLOCK_SET_TIME_LEN 0
1920 
1921 /* MC_CMD_FC_OUT_DDR_SET_SPD msgresponse */
1922 #define	MC_CMD_FC_OUT_DDR_SET_SPD_LEN 0
1923 
1924 /* MC_CMD_FC_OUT_DDR_GET_STATUS msgresponse */
1925 #define	MC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4
1926 #define	MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0
1927 #define	MC_CMD_FC_OUT_DDR_GET_STATUS_READY_LBN 0
1928 #define	MC_CMD_FC_OUT_DDR_GET_STATUS_READY_WIDTH 1
1929 #define	MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_LBN 1
1930 #define	MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_WIDTH 1
1931 
1932 /* MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT msgresponse */
1933 #define	MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_LEN 8
1934 #define	MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_OFST 0
1935 #define	MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_OFST 4
1936 
1937 /* MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT msgresponse */
1938 #define	MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMIN 8
1939 #define	MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX 248
1940 #define	MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LEN(num) (0+8*(num))
1941 #define	MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_OFST 0
1942 #define	MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_OFST 4
1943 #define	MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0
1944 #define	MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8
1945 #define	MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0
1946 #define	MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4
1947 #define	MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0
1948 #define	MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31
1949 
1950 /* MC_CMD_FC_OUT_SPI_READ msgresponse */
1951 #define	MC_CMD_FC_OUT_SPI_READ_LENMIN 4
1952 #define	MC_CMD_FC_OUT_SPI_READ_LENMAX 252
1953 #define	MC_CMD_FC_OUT_SPI_READ_LEN(num) (0+4*(num))
1954 #define	MC_CMD_FC_OUT_SPI_READ_BUFFER_OFST 0
1955 #define	MC_CMD_FC_OUT_SPI_READ_BUFFER_LEN 4
1956 #define	MC_CMD_FC_OUT_SPI_READ_BUFFER_MINNUM 1
1957 #define	MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM 63
1958 
1959 /* MC_CMD_FC_OUT_SPI_WRITE msgresponse */
1960 #define	MC_CMD_FC_OUT_SPI_WRITE_LEN 0
1961 
1962 /* MC_CMD_FC_OUT_SPI_ERASE msgresponse */
1963 #define	MC_CMD_FC_OUT_SPI_ERASE_LEN 0
1964 
1965 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG msgresponse */
1966 #define	MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_LEN 8
1967 #define	MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_OFST 0
1968 #define	MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_OFST 4
1969 
1970 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG msgresponse */
1971 #define	MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 0
1972 
1973 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_START msgresponse */
1974 #define	MC_CMD_FC_OUT_DIAG_DDR_SOAK_START_LEN 0
1975 
1976 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT msgresponse */
1977 #define	MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_LEN 8
1978 #define	MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_OFST 0
1979 #define	MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_LBN 0
1980 #define	MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_WIDTH 1
1981 #define	MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_LBN 1
1982 #define	MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_WIDTH 1
1983 #define	MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_LBN 2
1984 #define	MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_WIDTH 1
1985 #define	MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_LBN 3
1986 #define	MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_WIDTH 1
1987 #define	MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_LBN 4
1988 #define	MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_WIDTH 1
1989 #define	MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_OFST 4
1990 
1991 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP msgresponse */
1992 #define	MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP_LEN 0
1993 
1994 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR msgresponse */
1995 #define	MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR_LEN 0
1996 
1997 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE msgresponse */
1998 #define	MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE_LEN 0
1999 
2000 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG msgresponse */
2001 #define	MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 0
2002 
2003 
2004 /***********************************/
2005 /* MC_CMD_AOE
2006  * AOE operations (on MC rather than FC)
2007  */
2008 #define	MC_CMD_AOE  0xa
2009 
2010 /* MC_CMD_AOE_IN msgrequest */
2011 #define	MC_CMD_AOE_IN_LEN 4
2012 #define	MC_CMD_AOE_IN_OP_HDR_OFST 0
2013 #define	MC_CMD_AOE_IN_OP_LBN 0
2014 #define	MC_CMD_AOE_IN_OP_WIDTH 8
2015 #define	MC_CMD_AOE_OP_INFO 0x1 /* enum */
2016 #define	MC_CMD_AOE_OP_CURRENTS 0x2 /* enum */
2017 #define	MC_CMD_AOE_OP_TEMPERATURES 0x3 /* enum */
2018 #define	MC_CMD_AOE_OP_CPLD_IDLE 0x4 /* enum */
2019 #define	MC_CMD_AOE_OP_CPLD_READ 0x5 /* enum */
2020 #define	MC_CMD_AOE_OP_CPLD_WRITE 0x6 /* enum */
2021 #define	MC_CMD_AOE_OP_CPLD_INSTRUCTION 0x7 /* enum */
2022 #define	MC_CMD_AOE_OP_CPLD_REPROGRAM 0x8 /* enum */
2023 #define	MC_CMD_AOE_OP_POWER 0x9 /* enum */
2024 #define	MC_CMD_AOE_OP_LOAD 0xa /* enum */
2025 #define	MC_CMD_AOE_OP_FAN_CONTROL 0xb /* enum */
2026 #define	MC_CMD_AOE_OP_FAN_FAILURES 0xc /* enum */
2027 #define	MC_CMD_AOE_OP_MAC_STATS 0xd /* enum */
2028 #define	MC_CMD_AOE_OP_GET_PHY_MEDIA_INFO 0xe /* enum */
2029 #define	MC_CMD_AOE_OP_JTAG_WRITE 0xf /* enum */
2030 #define	MC_CMD_AOE_OP_FPGA_ACCESS 0x10 /* enum */
2031 #define	MC_CMD_AOE_OP_SET_MTU_OFFSET 0x11 /* enum */
2032 #define	MC_CMD_AOE_OP_LINK_STATE 0x12 /* enum */
2033 #define	MC_CMD_AOE_OP_SIENA_STATS 0x13 /* enum */
2034 #define	MC_CMD_AOE_OP_DDR 0x14 /* enum */
2035 #define	MC_CMD_AOE_OP_FC 0x15 /* enum */
2036 #define	MC_CMD_AOE_OP_DDR_ECC_STATUS 0x16 /* enum */
2037 #define	MC_CMD_AOE_OP_MC_SPI_MASTER 0x17 /* enum */
2038 
2039 /* MC_CMD_AOE_OUT msgresponse */
2040 #define	MC_CMD_AOE_OUT_LEN 0
2041 
2042 /* MC_CMD_AOE_IN_INFO msgrequest */
2043 #define	MC_CMD_AOE_IN_INFO_LEN 4
2044 #define	MC_CMD_AOE_IN_CMD_OFST 0
2045 
2046 /* MC_CMD_AOE_IN_CURRENTS msgrequest */
2047 #define	MC_CMD_AOE_IN_CURRENTS_LEN 4
2048 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2049 
2050 /* MC_CMD_AOE_IN_TEMPERATURES msgrequest */
2051 #define	MC_CMD_AOE_IN_TEMPERATURES_LEN 4
2052 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2053 
2054 /* MC_CMD_AOE_IN_CPLD_IDLE msgrequest */
2055 #define	MC_CMD_AOE_IN_CPLD_IDLE_LEN 4
2056 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2057 
2058 /* MC_CMD_AOE_IN_CPLD_READ msgrequest */
2059 #define	MC_CMD_AOE_IN_CPLD_READ_LEN 12
2060 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2061 #define	MC_CMD_AOE_IN_CPLD_READ_REGISTER_OFST 4
2062 #define	MC_CMD_AOE_IN_CPLD_READ_WIDTH_OFST 8
2063 
2064 /* MC_CMD_AOE_IN_CPLD_WRITE msgrequest */
2065 #define	MC_CMD_AOE_IN_CPLD_WRITE_LEN 16
2066 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2067 #define	MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_OFST 4
2068 #define	MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_OFST 8
2069 #define	MC_CMD_AOE_IN_CPLD_WRITE_VALUE_OFST 12
2070 
2071 /* MC_CMD_AOE_IN_CPLD_INSTRUCTION msgrequest */
2072 #define	MC_CMD_AOE_IN_CPLD_INSTRUCTION_LEN 8
2073 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2074 #define	MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_OFST 4
2075 
2076 /* MC_CMD_AOE_IN_CPLD_REPROGRAM msgrequest */
2077 #define	MC_CMD_AOE_IN_CPLD_REPROGRAM_LEN 8
2078 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2079 #define	MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_OFST 4
2080 #define	MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM 0x1 /* enum */
2081 #define	MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM_EVENT 0x3 /* enum */
2082 #define	MC_CMD_AOE_IN_CPLD_REPROGRAM_STATUS 0x4 /* enum */
2083 
2084 /* MC_CMD_AOE_IN_POWER msgrequest */
2085 #define	MC_CMD_AOE_IN_POWER_LEN 8
2086 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2087 #define	MC_CMD_AOE_IN_POWER_OP_OFST 4
2088 #define	MC_CMD_AOE_IN_POWER_OFF  0x0 /* enum */
2089 #define	MC_CMD_AOE_IN_POWER_ON  0x1 /* enum */
2090 #define	MC_CMD_AOE_IN_POWER_CLEAR  0x2 /* enum */
2091 #define	MC_CMD_AOE_IN_POWER_SHOW_CURRENT  0x3 /* enum */
2092 #define	MC_CMD_AOE_IN_POWER_SHOW_PEAK  0x4 /* enum */
2093 #define	MC_CMD_AOE_IN_POWER_DDR_LAST  0x5 /* enum */
2094 #define	MC_CMD_AOE_IN_POWER_DDR_PEAK  0x6 /* enum */
2095 #define	MC_CMD_AOE_IN_POWER_DDR_CLEAR  0x7 /* enum */
2096 
2097 /* MC_CMD_AOE_IN_LOAD msgrequest */
2098 #define	MC_CMD_AOE_IN_LOAD_LEN 8
2099 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2100 #define	MC_CMD_AOE_IN_LOAD_IMAGE_OFST 4
2101 
2102 /* MC_CMD_AOE_IN_FAN_CONTROL msgrequest */
2103 #define	MC_CMD_AOE_IN_FAN_CONTROL_LEN 8
2104 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2105 #define	MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_OFST 4
2106 
2107 /* MC_CMD_AOE_IN_FAN_FAILURES msgrequest */
2108 #define	MC_CMD_AOE_IN_FAN_FAILURES_LEN 4
2109 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2110 
2111 /* MC_CMD_AOE_IN_MAC_STATS msgrequest */
2112 #define	MC_CMD_AOE_IN_MAC_STATS_LEN 24
2113 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2114 #define	MC_CMD_AOE_IN_MAC_STATS_PORT_OFST 4
2115 #define	MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8
2116 #define	MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8
2117 #define	MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8
2118 #define	MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12
2119 #define	MC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16
2120 #define	MC_CMD_AOE_IN_MAC_STATS_DMA_LBN 0
2121 #define	MC_CMD_AOE_IN_MAC_STATS_DMA_WIDTH 1
2122 #define	MC_CMD_AOE_IN_MAC_STATS_CLEAR_LBN 1
2123 #define	MC_CMD_AOE_IN_MAC_STATS_CLEAR_WIDTH 1
2124 #define	MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_LBN 2
2125 #define	MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_WIDTH 1
2126 #define	MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_LBN 3
2127 #define	MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_WIDTH 1
2128 #define	MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_LBN 4
2129 #define	MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_WIDTH 1
2130 #define	MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_LBN 5
2131 #define	MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_WIDTH 1
2132 #define	MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_LBN 16
2133 #define	MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_WIDTH 16
2134 #define	MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_OFST 20
2135 
2136 /* MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO msgrequest */
2137 #define	MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_LEN 12
2138 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2139 #define	MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_OFST 4
2140 #define	MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_OFST 8
2141 
2142 /* MC_CMD_AOE_IN_JTAG_WRITE msgrequest */
2143 #define	MC_CMD_AOE_IN_JTAG_WRITE_LENMIN 12
2144 #define	MC_CMD_AOE_IN_JTAG_WRITE_LENMAX 252
2145 #define	MC_CMD_AOE_IN_JTAG_WRITE_LEN(num) (8+4*(num))
2146 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2147 #define	MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_OFST 4
2148 #define	MC_CMD_AOE_IN_JTAG_WRITE_DATA_OFST 8
2149 #define	MC_CMD_AOE_IN_JTAG_WRITE_DATA_LEN 4
2150 #define	MC_CMD_AOE_IN_JTAG_WRITE_DATA_MINNUM 1
2151 #define	MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM 61
2152 
2153 /* MC_CMD_AOE_IN_FPGA_ACCESS msgrequest */
2154 #define	MC_CMD_AOE_IN_FPGA_ACCESS_LEN 8
2155 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2156 #define	MC_CMD_AOE_IN_FPGA_ACCESS_OP_OFST 4
2157 #define	MC_CMD_AOE_IN_FPGA_ACCESS_ENABLE 0x1 /* enum */
2158 #define	MC_CMD_AOE_IN_FPGA_ACCESS_DISABLE 0x2 /* enum */
2159 
2160 /* MC_CMD_AOE_IN_SET_MTU_OFFSET msgrequest */
2161 #define	MC_CMD_AOE_IN_SET_MTU_OFFSET_LEN 12
2162 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2163 #define	MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_OFST 4
2164 #define	MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_EXTERNAL 0x8000 /* enum */
2165 #define	MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_INTERNAL 0x4000 /* enum */
2166 #define	MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_OFST 8
2167 
2168 /* MC_CMD_AOE_IN_LINK_STATE msgrequest */
2169 #define	MC_CMD_AOE_IN_LINK_STATE_LEN 8
2170 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2171 #define	MC_CMD_AOE_IN_LINK_STATE_MODE_OFST 4
2172 #define	MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0
2173 #define	MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8
2174 #define	MC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE  0x0 /* enum */
2175 #define	MC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED  0x1 /* enum */
2176 #define	MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC  0x2 /* enum */
2177 #define	MC_CMD_AOE_IN_LINK_STATE_CUSTOM  0x3 /* enum */
2178 #define	MC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8
2179 #define	MC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8
2180 #define	MC_CMD_AOE_IN_LINK_STATE_OP_NONE  0x0 /* enum */
2181 #define	MC_CMD_AOE_IN_LINK_STATE_OP_OR  0x1 /* enum */
2182 #define	MC_CMD_AOE_IN_LINK_STATE_OP_AND  0x2 /* enum */
2183 #define	MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16
2184 #define	MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16
2185 
2186 /* MC_CMD_AOE_IN_SIENA_STATS msgrequest */
2187 #define	MC_CMD_AOE_IN_SIENA_STATS_LEN 8
2188 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2189 #define	MC_CMD_AOE_IN_SIENA_STATS_MODE_OFST 4
2190 #define	MC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA  0x0 /* enum */
2191 #define	MC_CMD_AOE_IN_SIENA_STATS_STATS_AOE  0x1 /* enum */
2192 
2193 /* MC_CMD_AOE_IN_DDR msgrequest */
2194 #define	MC_CMD_AOE_IN_DDR_LEN 12
2195 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2196 #define	MC_CMD_AOE_IN_DDR_BANK_OFST 4
2197 /*            Enum values, see field(s): */
2198 /*               MC_CMD_FC_IN_DDR_BANK */
2199 #define	MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_OFST 8
2200 
2201 /* MC_CMD_AOE_IN_FC msgrequest */
2202 #define	MC_CMD_AOE_IN_FC_LEN 4
2203 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2204 
2205 /* MC_CMD_AOE_IN_DDR_ECC_STATUS msgrequest */
2206 #define	MC_CMD_AOE_IN_DDR_ECC_STATUS_LEN 8
2207 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2208 #define	MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_OFST 4
2209 /*            Enum values, see field(s): */
2210 /*               MC_CMD_FC_IN_DDR_BANK */
2211 
2212 /* MC_CMD_AOE_IN_MC_SPI_MASTER msgrequest */
2213 #define	MC_CMD_AOE_IN_MC_SPI_MASTER_LEN 8
2214 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2215 #define	MC_CMD_AOE_IN_MC_SPI_MASTER_OP_OFST 4
2216 #define	MC_CMD_AOE_IN_MC_SPI_MASTER_READ 0x0 /* enum */
2217 #define	MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE 0x1 /* enum */
2218 
2219 /* MC_CMD_AOE_IN_MC_SPI_MASTER_READ msgrequest */
2220 #define	MC_CMD_AOE_IN_MC_SPI_MASTER_READ_LEN 12
2221 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2222 #define	MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_OFST 4
2223 #define	MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_OFST 8
2224 
2225 /* MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE msgrequest */
2226 #define	MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_LEN 16
2227 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2228 #define	MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_OFST 4
2229 #define	MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_OFST 8
2230 #define	MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_OFST 12
2231 
2232 /* MC_CMD_AOE_OUT_INFO msgresponse */
2233 #define	MC_CMD_AOE_OUT_INFO_LEN 44
2234 #define	MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_OFST 0
2235 #define	MC_CMD_AOE_OUT_INFO_CPLD_VERSION_OFST 4
2236 #define	MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_OFST 8
2237 #define	MC_CMD_AOE_OUT_INFO_FPGA_VERSION_OFST 12
2238 #define	MC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16
2239 #define	MC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20
2240 #define	MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_OFST 24
2241 #define	MC_CMD_AOE_OUT_INFO_FC_STATE_OFST 28
2242 #define	MC_CMD_AOE_OUT_INFO_WATCHDOG 0x1 /* enum */
2243 #define	MC_CMD_AOE_OUT_INFO_COMMS 0x2 /* enum */
2244 #define	MC_CMD_AOE_OUT_INFO_FLAGS_OFST 32
2245 #define	MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1 /* enum */
2246 #define	MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2 /* enum */
2247 #define	MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4 /* enum */
2248 #define	MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8 /* enum */
2249 #define	MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10 /* enum */
2250 #define	MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20 /* enum */
2251 #define	MC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36
2252 #define	MC_CMD_AOE_OUT_INFO_UNKNOWN  0x0 /* enum */
2253 #define	MC_CMD_AOE_OUT_INFO_R1_0  0x10 /* enum */
2254 #define	MC_CMD_AOE_OUT_INFO_R1_1  0x11 /* enum */
2255 #define	MC_CMD_AOE_OUT_INFO_R1_2  0x12 /* enum */
2256 #define	MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40
2257 #define	MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_NO_ERROR 0x0 /* enum */
2258 #define	MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_ADDRESS 0x1 /* enum */
2259 #define	MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_MAGIC 0x2 /* enum */
2260 #define	MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_TEXT 0x3 /* enum */
2261 #define	MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_CHECKSUM 0x4 /* enum */
2262 #define	MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_BSP 0x5 /* enum */
2263 #define	MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_EXECUTE 0x80 /* enum */
2264 #define	MC_CMD_AOE_OUT_INFO_FC_BOOT_NO_BOOTROM 0xff /* enum */
2265 
2266 /* MC_CMD_AOE_OUT_CURRENTS msgresponse */
2267 #define	MC_CMD_AOE_OUT_CURRENTS_LEN 68
2268 #define	MC_CMD_AOE_OUT_CURRENTS_VALUES_OFST 0
2269 #define	MC_CMD_AOE_OUT_CURRENTS_VALUES_LEN 4
2270 #define	MC_CMD_AOE_OUT_CURRENTS_VALUES_NUM 17
2271 #define	MC_CMD_AOE_OUT_CURRENTS_I_2V5 0x0 /* enum */
2272 #define	MC_CMD_AOE_OUT_CURRENTS_I_1V8 0x1 /* enum */
2273 #define	MC_CMD_AOE_OUT_CURRENTS_I_GXB 0x2 /* enum */
2274 #define	MC_CMD_AOE_OUT_CURRENTS_I_PGM 0x3 /* enum */
2275 #define	MC_CMD_AOE_OUT_CURRENTS_I_XCVR 0x4 /* enum */
2276 #define	MC_CMD_AOE_OUT_CURRENTS_I_1V5 0x5 /* enum */
2277 #define	MC_CMD_AOE_OUT_CURRENTS_V_3V3 0x6 /* enum */
2278 #define	MC_CMD_AOE_OUT_CURRENTS_V_1V5 0x7 /* enum */
2279 #define	MC_CMD_AOE_OUT_CURRENTS_I_IN 0x8 /* enum */
2280 #define	MC_CMD_AOE_OUT_CURRENTS_I_OUT 0x9 /* enum */
2281 #define	MC_CMD_AOE_OUT_CURRENTS_V_IN 0xa /* enum */
2282 #define	MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR1 0xb /* enum */
2283 #define	MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR1 0xc /* enum */
2284 #define	MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR2 0xd /* enum */
2285 #define	MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR2 0xe /* enum */
2286 #define	MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR3 0xf /* enum */
2287 #define	MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR3 0x10 /* enum */
2288 
2289 /* MC_CMD_AOE_OUT_TEMPERATURES msgresponse */
2290 #define	MC_CMD_AOE_OUT_TEMPERATURES_LEN 40
2291 #define	MC_CMD_AOE_OUT_TEMPERATURES_VALUES_OFST 0
2292 #define	MC_CMD_AOE_OUT_TEMPERATURES_VALUES_LEN 4
2293 #define	MC_CMD_AOE_OUT_TEMPERATURES_VALUES_NUM 10
2294 #define	MC_CMD_AOE_OUT_TEMPERATURES_MAIN_0 0x0 /* enum */
2295 #define	MC_CMD_AOE_OUT_TEMPERATURES_MAIN_1 0x1 /* enum */
2296 #define	MC_CMD_AOE_OUT_TEMPERATURES_IND_0 0x2 /* enum */
2297 #define	MC_CMD_AOE_OUT_TEMPERATURES_IND_1 0x3 /* enum */
2298 #define	MC_CMD_AOE_OUT_TEMPERATURES_VCCIO1 0x4 /* enum */
2299 #define	MC_CMD_AOE_OUT_TEMPERATURES_VCCIO2 0x5 /* enum */
2300 #define	MC_CMD_AOE_OUT_TEMPERATURES_VCCIO3 0x6 /* enum */
2301 #define	MC_CMD_AOE_OUT_TEMPERATURES_PSU 0x7 /* enum */
2302 #define	MC_CMD_AOE_OUT_TEMPERATURES_FPGA 0x8 /* enum */
2303 #define	MC_CMD_AOE_OUT_TEMPERATURES_SIENA 0x9 /* enum */
2304 
2305 /* MC_CMD_AOE_OUT_CPLD_READ msgresponse */
2306 #define	MC_CMD_AOE_OUT_CPLD_READ_LEN 4
2307 #define	MC_CMD_AOE_OUT_CPLD_READ_VALUE_OFST 0
2308 
2309 /* MC_CMD_AOE_OUT_FAN_FAILURES msgresponse */
2310 #define	MC_CMD_AOE_OUT_FAN_FAILURES_LENMIN 4
2311 #define	MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX 252
2312 #define	MC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num))
2313 #define	MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_OFST 0
2314 #define	MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_LEN 4
2315 #define	MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MINNUM 1
2316 #define	MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM 63
2317 
2318 /* MC_CMD_AOE_OUT_CPLD_REPROGRAM msgresponse */
2319 #define	MC_CMD_AOE_OUT_CPLD_REPROGRAM_LEN 4
2320 #define	MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_OFST 0
2321 
2322 /* MC_CMD_AOE_OUT_MAC_STATS_DMA msgresponse */
2323 #define	MC_CMD_AOE_OUT_MAC_STATS_DMA_LEN 0
2324 
2325 /* MC_CMD_AOE_OUT_MAC_STATS_NO_DMA msgresponse */
2326 #define	MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3)
2327 #define	MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0
2328 #define	MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8
2329 #define	MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0
2330 #define	MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4
2331 #define	MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
2332 
2333 /* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */
2334 #define	MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMIN 5
2335 #define	MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX 252
2336 #define	MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num))
2337 #define	MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_OFST 0
2338 #define	MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_OFST 4
2339 #define	MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_LEN 1
2340 #define	MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MINNUM 1
2341 #define	MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM 248
2342 
2343 /* MC_CMD_AOE_OUT_JTAG_WRITE msgresponse */
2344 #define	MC_CMD_AOE_OUT_JTAG_WRITE_LENMIN 12
2345 #define	MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX 252
2346 #define	MC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num))
2347 #define	MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_OFST 0
2348 #define	MC_CMD_AOE_OUT_JTAG_WRITE_PAD_OFST 4
2349 #define	MC_CMD_AOE_OUT_JTAG_WRITE_DATA_OFST 8
2350 #define	MC_CMD_AOE_OUT_JTAG_WRITE_DATA_LEN 4
2351 #define	MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MINNUM 1
2352 #define	MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM 61
2353 
2354 /* MC_CMD_AOE_OUT_FPGA_ACCESS msgresponse */
2355 #define	MC_CMD_AOE_OUT_FPGA_ACCESS_LEN 0
2356 
2357 /* MC_CMD_AOE_OUT_DDR msgresponse */
2358 #define	MC_CMD_AOE_OUT_DDR_LENMIN 17
2359 #define	MC_CMD_AOE_OUT_DDR_LENMAX 252
2360 #define	MC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num))
2361 #define	MC_CMD_AOE_OUT_DDR_FLAGS_OFST 0
2362 #define	MC_CMD_AOE_OUT_DDR_PRESENT_LBN 0
2363 #define	MC_CMD_AOE_OUT_DDR_PRESENT_WIDTH 1
2364 #define	MC_CMD_AOE_OUT_DDR_POWERED_LBN 1
2365 #define	MC_CMD_AOE_OUT_DDR_POWERED_WIDTH 1
2366 #define	MC_CMD_AOE_OUT_DDR_OPERATIONAL_LBN 2
2367 #define	MC_CMD_AOE_OUT_DDR_OPERATIONAL_WIDTH 1
2368 #define	MC_CMD_AOE_OUT_DDR_CAPACITY_OFST 4
2369 #define	MC_CMD_AOE_OUT_DDR_TYPE_OFST 8
2370 #define	MC_CMD_AOE_OUT_DDR_VOLTAGE_OFST 12
2371 #define	MC_CMD_AOE_OUT_DDR_SPD_OFST 16
2372 #define	MC_CMD_AOE_OUT_DDR_SPD_LEN 1
2373 #define	MC_CMD_AOE_OUT_DDR_SPD_MINNUM 1
2374 #define	MC_CMD_AOE_OUT_DDR_SPD_MAXNUM 236
2375 
2376 /* MC_CMD_AOE_OUT_LINK_STATE msgresponse */
2377 #define	MC_CMD_AOE_OUT_LINK_STATE_LEN 0
2378 
2379 /* MC_CMD_AOE_OUT_FC msgresponse */
2380 #define	MC_CMD_AOE_OUT_FC_LEN 0
2381 
2382 /* MC_CMD_AOE_OUT_DDR_ECC_STATUS msgresponse */
2383 #define	MC_CMD_AOE_OUT_DDR_ECC_STATUS_LEN 8
2384 #define	MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_OFST 0
2385 #define	MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_LBN 0
2386 #define	MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_WIDTH 1
2387 #define	MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_OFST 4
2388 #define	MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_LBN 0
2389 #define	MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_WIDTH 1
2390 #define	MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_LBN 1
2391 #define	MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_WIDTH 1
2392 #define	MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_LBN 2
2393 #define	MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_WIDTH 1
2394 #define	MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_LBN 8
2395 #define	MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_WIDTH 8
2396 #define	MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_LBN 16
2397 #define	MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_WIDTH 8
2398 #define	MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_LBN 24
2399 #define	MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_WIDTH 8
2400 
2401 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_READ msgresponse */
2402 #define	MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_LEN 4
2403 #define	MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_OFST 0
2404 
2405 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE msgresponse */
2406 #define	MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE_LEN 0
2407 
2408 /* MC_CMD_AOE_OUT_MC_SPI_MASTER msgresponse */
2409 #define	MC_CMD_AOE_OUT_MC_SPI_MASTER_LEN 0
2410 
2411 
2412 /***********************************/
2413 /* MC_CMD_PTP
2414  * Perform PTP operation
2415  */
2416 #define	MC_CMD_PTP  0xb
2417 
2418 /* MC_CMD_PTP_IN msgrequest */
2419 #define	MC_CMD_PTP_IN_LEN 1
2420 #define	MC_CMD_PTP_IN_OP_OFST 0
2421 #define	MC_CMD_PTP_IN_OP_LEN 1
2422 #define	MC_CMD_PTP_OP_ENABLE 0x1 /* enum */
2423 #define	MC_CMD_PTP_OP_DISABLE 0x2 /* enum */
2424 #define	MC_CMD_PTP_OP_TRANSMIT 0x3 /* enum */
2425 #define	MC_CMD_PTP_OP_READ_NIC_TIME 0x4 /* enum */
2426 #define	MC_CMD_PTP_OP_STATUS 0x5 /* enum */
2427 #define	MC_CMD_PTP_OP_ADJUST 0x6 /* enum */
2428 #define	MC_CMD_PTP_OP_SYNCHRONIZE 0x7 /* enum */
2429 #define	MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 /* enum */
2430 #define	MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 /* enum */
2431 #define	MC_CMD_PTP_OP_RESET_STATS 0xa /* enum */
2432 #define	MC_CMD_PTP_OP_DEBUG 0xb /* enum */
2433 #define	MC_CMD_PTP_OP_FPGAREAD 0xc /* enum */
2434 #define	MC_CMD_PTP_OP_FPGAWRITE 0xd /* enum */
2435 #define	MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe /* enum */
2436 #define	MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf /* enum */
2437 #define	MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 /* enum */
2438 #define	MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 /* enum */
2439 #define	MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 /* enum */
2440 #define	MC_CMD_PTP_OP_SET_CLK_SRC 0x13 /* enum */
2441 #define	MC_CMD_PTP_OP_RST_CLK 0x14 /* enum */
2442 #define	MC_CMD_PTP_OP_PPS_ENABLE 0x15 /* enum */
2443 #define	MC_CMD_PTP_OP_MAX 0x16 /* enum */
2444 
2445 /* MC_CMD_PTP_IN_ENABLE msgrequest */
2446 #define	MC_CMD_PTP_IN_ENABLE_LEN 16
2447 #define	MC_CMD_PTP_IN_CMD_OFST 0
2448 #define	MC_CMD_PTP_IN_PERIPH_ID_OFST 4
2449 #define	MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8
2450 #define	MC_CMD_PTP_IN_ENABLE_MODE_OFST 12
2451 #define	MC_CMD_PTP_MODE_V1 0x0 /* enum */
2452 #define	MC_CMD_PTP_MODE_V1_VLAN 0x1 /* enum */
2453 #define	MC_CMD_PTP_MODE_V2 0x2 /* enum */
2454 #define	MC_CMD_PTP_MODE_V2_VLAN 0x3 /* enum */
2455 #define	MC_CMD_PTP_MODE_V2_ENHANCED 0x4 /* enum */
2456 
2457 /* MC_CMD_PTP_IN_DISABLE msgrequest */
2458 #define	MC_CMD_PTP_IN_DISABLE_LEN 8
2459 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
2460 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2461 
2462 /* MC_CMD_PTP_IN_TRANSMIT msgrequest */
2463 #define	MC_CMD_PTP_IN_TRANSMIT_LENMIN 13
2464 #define	MC_CMD_PTP_IN_TRANSMIT_LENMAX 252
2465 #define	MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num))
2466 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
2467 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2468 #define	MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8
2469 #define	MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12
2470 #define	MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1
2471 #define	MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1
2472 #define	MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240
2473 
2474 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */
2475 #define	MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8
2476 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
2477 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2478 
2479 /* MC_CMD_PTP_IN_STATUS msgrequest */
2480 #define	MC_CMD_PTP_IN_STATUS_LEN 8
2481 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
2482 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2483 
2484 /* MC_CMD_PTP_IN_ADJUST msgrequest */
2485 #define	MC_CMD_PTP_IN_ADJUST_LEN 24
2486 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
2487 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2488 #define	MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8
2489 #define	MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8
2490 #define	MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8
2491 #define	MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12
2492 #define	MC_CMD_PTP_IN_ADJUST_BITS 0x28 /* enum */
2493 #define	MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16
2494 #define	MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20
2495 
2496 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */
2497 #define	MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20
2498 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
2499 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2500 #define	MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8
2501 #define	MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12
2502 #define	MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8
2503 #define	MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12
2504 #define	MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16
2505 
2506 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */
2507 #define	MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8
2508 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
2509 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2510 
2511 /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */
2512 #define	MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12
2513 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
2514 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2515 #define	MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8
2516 
2517 /* MC_CMD_PTP_IN_RESET_STATS msgrequest */
2518 #define	MC_CMD_PTP_IN_RESET_STATS_LEN 8
2519 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
2520 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2521 
2522 /* MC_CMD_PTP_IN_DEBUG msgrequest */
2523 #define	MC_CMD_PTP_IN_DEBUG_LEN 12
2524 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
2525 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2526 #define	MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8
2527 
2528 /* MC_CMD_PTP_IN_FPGAREAD msgrequest */
2529 #define	MC_CMD_PTP_IN_FPGAREAD_LEN 16
2530 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
2531 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2532 #define	MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8
2533 #define	MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12
2534 
2535 /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */
2536 #define	MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13
2537 #define	MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252
2538 #define	MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num))
2539 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
2540 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2541 #define	MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8
2542 #define	MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12
2543 #define	MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1
2544 #define	MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1
2545 #define	MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240
2546 
2547 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */
2548 #define	MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16
2549 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
2550 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2551 #define	MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8
2552 #define	MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12
2553 
2554 /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */
2555 #define	MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16
2556 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
2557 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2558 #define	MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8
2559 #define	MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8
2560 #define	MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8
2561 #define	MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12
2562 /*               MC_CMD_PTP_IN_ADJUST_BITS 0x28 */
2563 
2564 /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */
2565 #define	MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24
2566 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
2567 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2568 #define	MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8
2569 #define	MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12
2570 #define	MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4
2571 #define	MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3
2572 
2573 /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */
2574 #define	MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20
2575 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
2576 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2577 #define	MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8
2578 #define	MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12
2579 #define	MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8
2580 #define	MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12
2581 #define	MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16
2582 
2583 /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */
2584 #define	MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16
2585 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
2586 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2587 #define	MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8
2588 #define	MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12
2589 
2590 /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */
2591 #define	MC_CMD_PTP_IN_PPS_ENABLE_LEN 12
2592 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
2593 #define	MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4
2594 #define	MC_CMD_PTP_ENABLE_PPS 0x0 /* enum */
2595 #define	MC_CMD_PTP_DISABLE_PPS 0x1 /* enum */
2596 #define	MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8
2597 
2598 /* MC_CMD_PTP_OUT msgresponse */
2599 #define	MC_CMD_PTP_OUT_LEN 0
2600 
2601 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */
2602 #define	MC_CMD_PTP_OUT_TRANSMIT_LEN 8
2603 #define	MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0
2604 #define	MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4
2605 
2606 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */
2607 #define	MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8
2608 #define	MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0
2609 #define	MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4
2610 
2611 /* MC_CMD_PTP_OUT_STATUS msgresponse */
2612 #define	MC_CMD_PTP_OUT_STATUS_LEN 64
2613 #define	MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0
2614 #define	MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4
2615 #define	MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8
2616 #define	MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12
2617 #define	MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16
2618 #define	MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20
2619 #define	MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24
2620 #define	MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28
2621 #define	MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32
2622 #define	MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36
2623 #define	MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40
2624 #define	MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44
2625 #define	MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48
2626 #define	MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52
2627 #define	MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56
2628 #define	MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60
2629 
2630 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */
2631 #define	MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20
2632 #define	MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240
2633 #define	MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num))
2634 #define	MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0
2635 #define	MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20
2636 #define	MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1
2637 #define	MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12
2638 #define	MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0
2639 #define	MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4
2640 #define	MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8
2641 #define	MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12
2642 #define	MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16
2643 
2644 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */
2645 #define	MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8
2646 #define	MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0
2647 #define	MC_CMD_PTP_MANF_SUCCESS 0x0 /* enum */
2648 #define	MC_CMD_PTP_MANF_FPGA_LOAD 0x1 /* enum */
2649 #define	MC_CMD_PTP_MANF_FPGA_VERSION 0x2 /* enum */
2650 #define	MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 /* enum */
2651 #define	MC_CMD_PTP_MANF_OSCILLATOR 0x4 /* enum */
2652 #define	MC_CMD_PTP_MANF_TIMESTAMPS 0x5 /* enum */
2653 #define	MC_CMD_PTP_MANF_PACKET_COUNT 0x6 /* enum */
2654 #define	MC_CMD_PTP_MANF_FILTER_COUNT 0x7 /* enum */
2655 #define	MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 /* enum */
2656 #define	MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 /* enum */
2657 #define	MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4
2658 
2659 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */
2660 #define	MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12
2661 #define	MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0
2662 #define	MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4
2663 #define	MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8
2664 
2665 /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */
2666 #define	MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1
2667 #define	MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252
2668 #define	MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num))
2669 #define	MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0
2670 #define	MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1
2671 #define	MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1
2672 #define	MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252
2673 
2674 
2675 /***********************************/
2676 /* MC_CMD_CSR_READ32
2677  * Read 32bit words from the indirect memory map.
2678  */
2679 #define	MC_CMD_CSR_READ32  0xc
2680 
2681 /* MC_CMD_CSR_READ32_IN msgrequest */
2682 #define	MC_CMD_CSR_READ32_IN_LEN 12
2683 #define	MC_CMD_CSR_READ32_IN_ADDR_OFST 0
2684 #define	MC_CMD_CSR_READ32_IN_STEP_OFST 4
2685 #define	MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8
2686 
2687 /* MC_CMD_CSR_READ32_OUT msgresponse */
2688 #define	MC_CMD_CSR_READ32_OUT_LENMIN 4
2689 #define	MC_CMD_CSR_READ32_OUT_LENMAX 252
2690 #define	MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num))
2691 #define	MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0
2692 #define	MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4
2693 #define	MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1
2694 #define	MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63
2695 
2696 
2697 /***********************************/
2698 /* MC_CMD_CSR_WRITE32
2699  * Write 32bit dwords to the indirect memory map.
2700  */
2701 #define	MC_CMD_CSR_WRITE32  0xd
2702 
2703 /* MC_CMD_CSR_WRITE32_IN msgrequest */
2704 #define	MC_CMD_CSR_WRITE32_IN_LENMIN 12
2705 #define	MC_CMD_CSR_WRITE32_IN_LENMAX 252
2706 #define	MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num))
2707 #define	MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0
2708 #define	MC_CMD_CSR_WRITE32_IN_STEP_OFST 4
2709 #define	MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8
2710 #define	MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4
2711 #define	MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1
2712 #define	MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61
2713 
2714 /* MC_CMD_CSR_WRITE32_OUT msgresponse */
2715 #define	MC_CMD_CSR_WRITE32_OUT_LEN 4
2716 #define	MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0
2717 
2718 
2719 /***********************************/
2720 /* MC_CMD_HP
2721  * HP specific commands.
2722  */
2723 #define	MC_CMD_HP  0x54
2724 
2725 /* MC_CMD_HP_IN msgrequest */
2726 #define	MC_CMD_HP_IN_LEN 16
2727 #define	MC_CMD_HP_IN_SUBCMD_OFST 0
2728 #define	MC_CMD_HP_IN_OCSD_SUBCMD 0x0 /* enum */
2729 #define	MC_CMD_HP_IN_LAST_SUBCMD 0x0 /* enum */
2730 #define	MC_CMD_HP_IN_OCSD_ADDR_OFST 4
2731 #define	MC_CMD_HP_IN_OCSD_ADDR_LEN 8
2732 #define	MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4
2733 #define	MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8
2734 #define	MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12
2735 
2736 /* MC_CMD_HP_OUT msgresponse */
2737 #define	MC_CMD_HP_OUT_LEN 4
2738 #define	MC_CMD_HP_OUT_OCSD_STATUS_OFST 0
2739 #define	MC_CMD_HP_OUT_OCSD_STOPPED 0x1 /* enum */
2740 #define	MC_CMD_HP_OUT_OCSD_STARTED 0x2 /* enum */
2741 #define	MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 /* enum */
2742 
2743 
2744 /***********************************/
2745 /* MC_CMD_STACKINFO
2746  * Get stack information.
2747  */
2748 #define	MC_CMD_STACKINFO  0xf
2749 
2750 /* MC_CMD_STACKINFO_IN msgrequest */
2751 #define	MC_CMD_STACKINFO_IN_LEN 0
2752 
2753 /* MC_CMD_STACKINFO_OUT msgresponse */
2754 #define	MC_CMD_STACKINFO_OUT_LENMIN 12
2755 #define	MC_CMD_STACKINFO_OUT_LENMAX 252
2756 #define	MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num))
2757 #define	MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0
2758 #define	MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12
2759 #define	MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1
2760 #define	MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21
2761 
2762 
2763 /***********************************/
2764 /* MC_CMD_MDIO_READ
2765  * MDIO register read.
2766  */
2767 #define	MC_CMD_MDIO_READ  0x10
2768 
2769 /* MC_CMD_MDIO_READ_IN msgrequest */
2770 #define	MC_CMD_MDIO_READ_IN_LEN 16
2771 #define	MC_CMD_MDIO_READ_IN_BUS_OFST 0
2772 #define	MC_CMD_MDIO_BUS_INTERNAL 0x0 /* enum */
2773 #define	MC_CMD_MDIO_BUS_EXTERNAL 0x1 /* enum */
2774 #define	MC_CMD_MDIO_READ_IN_PRTAD_OFST 4
2775 #define	MC_CMD_MDIO_READ_IN_DEVAD_OFST 8
2776 #define	MC_CMD_MDIO_CLAUSE22 0x20 /* enum */
2777 #define	MC_CMD_MDIO_READ_IN_ADDR_OFST 12
2778 
2779 /* MC_CMD_MDIO_READ_OUT msgresponse */
2780 #define	MC_CMD_MDIO_READ_OUT_LEN 8
2781 #define	MC_CMD_MDIO_READ_OUT_VALUE_OFST 0
2782 #define	MC_CMD_MDIO_READ_OUT_STATUS_OFST 4
2783 #define	MC_CMD_MDIO_STATUS_GOOD 0x8 /* enum */
2784 
2785 
2786 /***********************************/
2787 /* MC_CMD_MDIO_WRITE
2788  * MDIO register write.
2789  */
2790 #define	MC_CMD_MDIO_WRITE  0x11
2791 
2792 /* MC_CMD_MDIO_WRITE_IN msgrequest */
2793 #define	MC_CMD_MDIO_WRITE_IN_LEN 20
2794 #define	MC_CMD_MDIO_WRITE_IN_BUS_OFST 0
2795 /*               MC_CMD_MDIO_BUS_INTERNAL 0x0 */
2796 /*               MC_CMD_MDIO_BUS_EXTERNAL 0x1 */
2797 #define	MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4
2798 #define	MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8
2799 /*               MC_CMD_MDIO_CLAUSE22 0x20 */
2800 #define	MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12
2801 #define	MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16
2802 
2803 /* MC_CMD_MDIO_WRITE_OUT msgresponse */
2804 #define	MC_CMD_MDIO_WRITE_OUT_LEN 4
2805 #define	MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0
2806 /*               MC_CMD_MDIO_STATUS_GOOD 0x8 */
2807 
2808 
2809 /***********************************/
2810 /* MC_CMD_DBI_WRITE
2811  * Write DBI register(s).
2812  */
2813 #define	MC_CMD_DBI_WRITE  0x12
2814 
2815 /* MC_CMD_DBI_WRITE_IN msgrequest */
2816 #define	MC_CMD_DBI_WRITE_IN_LENMIN 12
2817 #define	MC_CMD_DBI_WRITE_IN_LENMAX 252
2818 #define	MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num))
2819 #define	MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0
2820 #define	MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12
2821 #define	MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1
2822 #define	MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21
2823 
2824 /* MC_CMD_DBI_WRITE_OUT msgresponse */
2825 #define	MC_CMD_DBI_WRITE_OUT_LEN 0
2826 
2827 /* MC_CMD_DBIWROP_TYPEDEF structuredef */
2828 #define	MC_CMD_DBIWROP_TYPEDEF_LEN 12
2829 #define	MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0
2830 #define	MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0
2831 #define	MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32
2832 #define	MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST 4
2833 #define	MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_LBN 32
2834 #define	MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_WIDTH 32
2835 #define	MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8
2836 #define	MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64
2837 #define	MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32
2838 
2839 
2840 /***********************************/
2841 /* MC_CMD_PORT_READ32
2842  * Read a 32-bit register from the indirect port register map.
2843  */
2844 #define	MC_CMD_PORT_READ32  0x14
2845 
2846 /* MC_CMD_PORT_READ32_IN msgrequest */
2847 #define	MC_CMD_PORT_READ32_IN_LEN 4
2848 #define	MC_CMD_PORT_READ32_IN_ADDR_OFST 0
2849 
2850 /* MC_CMD_PORT_READ32_OUT msgresponse */
2851 #define	MC_CMD_PORT_READ32_OUT_LEN 8
2852 #define	MC_CMD_PORT_READ32_OUT_VALUE_OFST 0
2853 #define	MC_CMD_PORT_READ32_OUT_STATUS_OFST 4
2854 
2855 
2856 /***********************************/
2857 /* MC_CMD_PORT_WRITE32
2858  * Write a 32-bit register to the indirect port register map.
2859  */
2860 #define	MC_CMD_PORT_WRITE32  0x15
2861 
2862 /* MC_CMD_PORT_WRITE32_IN msgrequest */
2863 #define	MC_CMD_PORT_WRITE32_IN_LEN 8
2864 #define	MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0
2865 #define	MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4
2866 
2867 /* MC_CMD_PORT_WRITE32_OUT msgresponse */
2868 #define	MC_CMD_PORT_WRITE32_OUT_LEN 4
2869 #define	MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0
2870 
2871 
2872 /***********************************/
2873 /* MC_CMD_PORT_READ128
2874  * Read a 128-bit register from the indirect port register map.
2875  */
2876 #define	MC_CMD_PORT_READ128  0x16
2877 
2878 /* MC_CMD_PORT_READ128_IN msgrequest */
2879 #define	MC_CMD_PORT_READ128_IN_LEN 4
2880 #define	MC_CMD_PORT_READ128_IN_ADDR_OFST 0
2881 
2882 /* MC_CMD_PORT_READ128_OUT msgresponse */
2883 #define	MC_CMD_PORT_READ128_OUT_LEN 20
2884 #define	MC_CMD_PORT_READ128_OUT_VALUE_OFST 0
2885 #define	MC_CMD_PORT_READ128_OUT_VALUE_LEN 16
2886 #define	MC_CMD_PORT_READ128_OUT_STATUS_OFST 16
2887 
2888 
2889 /***********************************/
2890 /* MC_CMD_PORT_WRITE128
2891  * Write a 128-bit register to the indirect port register map.
2892  */
2893 #define	MC_CMD_PORT_WRITE128  0x17
2894 
2895 /* MC_CMD_PORT_WRITE128_IN msgrequest */
2896 #define	MC_CMD_PORT_WRITE128_IN_LEN 20
2897 #define	MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0
2898 #define	MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4
2899 #define	MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16
2900 
2901 /* MC_CMD_PORT_WRITE128_OUT msgresponse */
2902 #define	MC_CMD_PORT_WRITE128_OUT_LEN 4
2903 #define	MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0
2904 
2905 
2906 /***********************************/
2907 /* MC_CMD_GET_BOARD_CFG
2908  * Returns the MC firmware configuration structure.
2909  */
2910 #define	MC_CMD_GET_BOARD_CFG  0x18
2911 
2912 /* MC_CMD_GET_BOARD_CFG_IN msgrequest */
2913 #define	MC_CMD_GET_BOARD_CFG_IN_LEN 0
2914 
2915 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */
2916 #define	MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96
2917 #define	MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136
2918 #define	MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num))
2919 #define	MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0
2920 #define	MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4
2921 #define	MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32
2922 #define	MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36
2923 #define	MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0x0 /* enum */
2924 #define	MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 0x1 /* enum */
2925 #define	MC_CMD_CAPABILITIES_TURBO_LBN 0x1 /* enum */
2926 #define	MC_CMD_CAPABILITIES_TURBO_WIDTH 0x1 /* enum */
2927 #define	MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 0x2 /* enum */
2928 #define	MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 0x1 /* enum */
2929 #define	MC_CMD_CAPABILITIES_PTP_LBN 0x3 /* enum */
2930 #define	MC_CMD_CAPABILITIES_PTP_WIDTH 0x1 /* enum */
2931 #define	MC_CMD_CAPABILITIES_AOE_LBN 0x4 /* enum */
2932 #define	MC_CMD_CAPABILITIES_AOE_WIDTH 0x1 /* enum */
2933 #define	MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 0x5 /* enum */
2934 #define	MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 0x1 /* enum */
2935 #define	MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 0x6 /* enum */
2936 #define	MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 0x1 /* enum */
2937 #define	MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40
2938 /*            Enum values, see field(s): */
2939 /*               CAPABILITIES_PORT0 */
2940 #define	MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44
2941 #define	MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6
2942 #define	MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50
2943 #define	MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6
2944 #define	MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56
2945 #define	MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60
2946 #define	MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64
2947 #define	MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68
2948 #define	MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72
2949 #define	MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2
2950 #define	MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12
2951 #define	MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32
2952 
2953 
2954 /***********************************/
2955 /* MC_CMD_DBI_READX
2956  * Read DBI register(s).
2957  */
2958 #define	MC_CMD_DBI_READX  0x19
2959 
2960 /* MC_CMD_DBI_READX_IN msgrequest */
2961 #define	MC_CMD_DBI_READX_IN_LENMIN 8
2962 #define	MC_CMD_DBI_READX_IN_LENMAX 248
2963 #define	MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num))
2964 #define	MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0
2965 #define	MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8
2966 #define	MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0
2967 #define	MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4
2968 #define	MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1
2969 #define	MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31
2970 
2971 /* MC_CMD_DBI_READX_OUT msgresponse */
2972 #define	MC_CMD_DBI_READX_OUT_LENMIN 4
2973 #define	MC_CMD_DBI_READX_OUT_LENMAX 252
2974 #define	MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num))
2975 #define	MC_CMD_DBI_READX_OUT_VALUE_OFST 0
2976 #define	MC_CMD_DBI_READX_OUT_VALUE_LEN 4
2977 #define	MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1
2978 #define	MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63
2979 
2980 
2981 /***********************************/
2982 /* MC_CMD_SET_RAND_SEED
2983  * Set the 16byte seed for the MC pseudo-random generator.
2984  */
2985 #define	MC_CMD_SET_RAND_SEED  0x1a
2986 
2987 /* MC_CMD_SET_RAND_SEED_IN msgrequest */
2988 #define	MC_CMD_SET_RAND_SEED_IN_LEN 16
2989 #define	MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0
2990 #define	MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16
2991 
2992 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */
2993 #define	MC_CMD_SET_RAND_SEED_OUT_LEN 0
2994 
2995 
2996 /***********************************/
2997 /* MC_CMD_LTSSM_HIST
2998  * Retrieve the history of the PCIE LTSSM.
2999  */
3000 #define	MC_CMD_LTSSM_HIST  0x1b
3001 
3002 /* MC_CMD_LTSSM_HIST_IN msgrequest */
3003 #define	MC_CMD_LTSSM_HIST_IN_LEN 0
3004 
3005 /* MC_CMD_LTSSM_HIST_OUT msgresponse */
3006 #define	MC_CMD_LTSSM_HIST_OUT_LENMIN 0
3007 #define	MC_CMD_LTSSM_HIST_OUT_LENMAX 252
3008 #define	MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num))
3009 #define	MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0
3010 #define	MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4
3011 #define	MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0
3012 #define	MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63
3013 
3014 
3015 /***********************************/
3016 /* MC_CMD_DRV_ATTACH
3017  * Inform MCPU that this port is managed on the host.
3018  */
3019 #define	MC_CMD_DRV_ATTACH  0x1c
3020 
3021 /* MC_CMD_DRV_ATTACH_IN msgrequest */
3022 #define	MC_CMD_DRV_ATTACH_IN_LEN 8
3023 #define	MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0
3024 #define	MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
3025 
3026 /* MC_CMD_DRV_ATTACH_OUT msgresponse */
3027 #define	MC_CMD_DRV_ATTACH_OUT_LEN 4
3028 #define	MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0
3029 
3030 
3031 /***********************************/
3032 /* MC_CMD_SHMUART
3033  * Route UART output to circular buffer in shared memory instead.
3034  */
3035 #define	MC_CMD_SHMUART  0x1f
3036 
3037 /* MC_CMD_SHMUART_IN msgrequest */
3038 #define	MC_CMD_SHMUART_IN_LEN 4
3039 #define	MC_CMD_SHMUART_IN_FLAG_OFST 0
3040 
3041 /* MC_CMD_SHMUART_OUT msgresponse */
3042 #define	MC_CMD_SHMUART_OUT_LEN 0
3043 
3044 
3045 /***********************************/
3046 /* MC_CMD_PORT_RESET
3047  * Generic per-port reset.
3048  */
3049 #define	MC_CMD_PORT_RESET  0x20
3050 
3051 /* MC_CMD_PORT_RESET_IN msgrequest */
3052 #define	MC_CMD_PORT_RESET_IN_LEN 0
3053 
3054 /* MC_CMD_PORT_RESET_OUT msgresponse */
3055 #define	MC_CMD_PORT_RESET_OUT_LEN 0
3056 
3057 
3058 /***********************************/
3059 /* MC_CMD_PCIE_CREDITS
3060  * Read instantaneous and minimum flow control thresholds.
3061  */
3062 #define	MC_CMD_PCIE_CREDITS  0x21
3063 
3064 /* MC_CMD_PCIE_CREDITS_IN msgrequest */
3065 #define	MC_CMD_PCIE_CREDITS_IN_LEN 8
3066 #define	MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0
3067 #define	MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4
3068 
3069 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */
3070 #define	MC_CMD_PCIE_CREDITS_OUT_LEN 16
3071 #define	MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0
3072 #define	MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2
3073 #define	MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2
3074 #define	MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2
3075 #define	MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4
3076 #define	MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2
3077 #define	MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6
3078 #define	MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2
3079 #define	MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8
3080 #define	MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2
3081 #define	MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10
3082 #define	MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2
3083 #define	MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12
3084 #define	MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2
3085 #define	MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14
3086 #define	MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2
3087 
3088 
3089 /***********************************/
3090 /* MC_CMD_RXD_MONITOR
3091  * Get histogram of RX queue fill level.
3092  */
3093 #define	MC_CMD_RXD_MONITOR  0x22
3094 
3095 /* MC_CMD_RXD_MONITOR_IN msgrequest */
3096 #define	MC_CMD_RXD_MONITOR_IN_LEN 12
3097 #define	MC_CMD_RXD_MONITOR_IN_QID_OFST 0
3098 #define	MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4
3099 #define	MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8
3100 
3101 /* MC_CMD_RXD_MONITOR_OUT msgresponse */
3102 #define	MC_CMD_RXD_MONITOR_OUT_LEN 80
3103 #define	MC_CMD_RXD_MONITOR_OUT_QID_OFST 0
3104 #define	MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4
3105 #define	MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8
3106 #define	MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12
3107 #define	MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16
3108 #define	MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20
3109 #define	MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24
3110 #define	MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28
3111 #define	MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32
3112 #define	MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36
3113 #define	MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40
3114 #define	MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44
3115 #define	MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48
3116 #define	MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52
3117 #define	MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56
3118 #define	MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60
3119 #define	MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64
3120 #define	MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68
3121 #define	MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72
3122 #define	MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76
3123 
3124 
3125 /***********************************/
3126 /* MC_CMD_PUTS
3127  * puts(3) implementation over MCDI
3128  */
3129 #define	MC_CMD_PUTS  0x23
3130 
3131 /* MC_CMD_PUTS_IN msgrequest */
3132 #define	MC_CMD_PUTS_IN_LENMIN 13
3133 #define	MC_CMD_PUTS_IN_LENMAX 252
3134 #define	MC_CMD_PUTS_IN_LEN(num) (12+1*(num))
3135 #define	MC_CMD_PUTS_IN_DEST_OFST 0
3136 #define	MC_CMD_PUTS_IN_UART_LBN 0
3137 #define	MC_CMD_PUTS_IN_UART_WIDTH 1
3138 #define	MC_CMD_PUTS_IN_PORT_LBN 1
3139 #define	MC_CMD_PUTS_IN_PORT_WIDTH 1
3140 #define	MC_CMD_PUTS_IN_DHOST_OFST 4
3141 #define	MC_CMD_PUTS_IN_DHOST_LEN 6
3142 #define	MC_CMD_PUTS_IN_STRING_OFST 12
3143 #define	MC_CMD_PUTS_IN_STRING_LEN 1
3144 #define	MC_CMD_PUTS_IN_STRING_MINNUM 1
3145 #define	MC_CMD_PUTS_IN_STRING_MAXNUM 240
3146 
3147 /* MC_CMD_PUTS_OUT msgresponse */
3148 #define	MC_CMD_PUTS_OUT_LEN 0
3149 
3150 
3151 /***********************************/
3152 /* MC_CMD_GET_PHY_CFG
3153  * Report PHY configuration.
3154  */
3155 #define	MC_CMD_GET_PHY_CFG  0x24
3156 
3157 /* MC_CMD_GET_PHY_CFG_IN msgrequest */
3158 #define	MC_CMD_GET_PHY_CFG_IN_LEN 0
3159 
3160 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */
3161 #define	MC_CMD_GET_PHY_CFG_OUT_LEN 72
3162 #define	MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0
3163 #define	MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0
3164 #define	MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1
3165 #define	MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1
3166 #define	MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1
3167 #define	MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2
3168 #define	MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1
3169 #define	MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3
3170 #define	MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1
3171 #define	MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4
3172 #define	MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1
3173 #define	MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5
3174 #define	MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1
3175 #define	MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6
3176 #define	MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1
3177 #define	MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4
3178 #define	MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8
3179 #define	MC_CMD_PHY_CAP_10HDX_LBN 1
3180 #define	MC_CMD_PHY_CAP_10HDX_WIDTH 1
3181 #define	MC_CMD_PHY_CAP_10FDX_LBN 2
3182 #define	MC_CMD_PHY_CAP_10FDX_WIDTH 1
3183 #define	MC_CMD_PHY_CAP_100HDX_LBN 3
3184 #define	MC_CMD_PHY_CAP_100HDX_WIDTH 1
3185 #define	MC_CMD_PHY_CAP_100FDX_LBN 4
3186 #define	MC_CMD_PHY_CAP_100FDX_WIDTH 1
3187 #define	MC_CMD_PHY_CAP_1000HDX_LBN 5
3188 #define	MC_CMD_PHY_CAP_1000HDX_WIDTH 1
3189 #define	MC_CMD_PHY_CAP_1000FDX_LBN 6
3190 #define	MC_CMD_PHY_CAP_1000FDX_WIDTH 1
3191 #define	MC_CMD_PHY_CAP_10000FDX_LBN 7
3192 #define	MC_CMD_PHY_CAP_10000FDX_WIDTH 1
3193 #define	MC_CMD_PHY_CAP_PAUSE_LBN 8
3194 #define	MC_CMD_PHY_CAP_PAUSE_WIDTH 1
3195 #define	MC_CMD_PHY_CAP_ASYM_LBN 9
3196 #define	MC_CMD_PHY_CAP_ASYM_WIDTH 1
3197 #define	MC_CMD_PHY_CAP_AN_LBN 10
3198 #define	MC_CMD_PHY_CAP_AN_WIDTH 1
3199 #define	MC_CMD_PHY_CAP_DDM_LBN 12
3200 #define	MC_CMD_PHY_CAP_DDM_WIDTH 1
3201 #define	MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12
3202 #define	MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16
3203 #define	MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20
3204 #define	MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24
3205 #define	MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20
3206 #define	MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44
3207 #define	MC_CMD_MEDIA_XAUI 0x1 /* enum */
3208 #define	MC_CMD_MEDIA_CX4 0x2 /* enum */
3209 #define	MC_CMD_MEDIA_KX4 0x3 /* enum */
3210 #define	MC_CMD_MEDIA_XFP 0x4 /* enum */
3211 #define	MC_CMD_MEDIA_SFP_PLUS 0x5 /* enum */
3212 #define	MC_CMD_MEDIA_BASE_T 0x6 /* enum */
3213 #define	MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48
3214 #define	MC_CMD_MMD_CLAUSE22 0x0 /* enum */
3215 #define	MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */
3216 #define	MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */
3217 #define	MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */
3218 #define	MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */
3219 #define	MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */
3220 #define	MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */
3221 #define	MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */
3222 #define	MC_CMD_MMD_CLAUSE45_C22EXT 0x1d /* enum */
3223 #define	MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */
3224 #define	MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */
3225 #define	MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52
3226 #define	MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20
3227 
3228 
3229 /***********************************/
3230 /* MC_CMD_START_BIST
3231  * Start a BIST test on the PHY.
3232  */
3233 #define	MC_CMD_START_BIST  0x25
3234 
3235 /* MC_CMD_START_BIST_IN msgrequest */
3236 #define	MC_CMD_START_BIST_IN_LEN 4
3237 #define	MC_CMD_START_BIST_IN_TYPE_OFST 0
3238 #define	MC_CMD_PHY_BIST_CABLE_SHORT 0x1 /* enum */
3239 #define	MC_CMD_PHY_BIST_CABLE_LONG 0x2 /* enum */
3240 #define	MC_CMD_BPX_SERDES_BIST 0x3 /* enum */
3241 #define	MC_CMD_MC_LOOPBACK_BIST 0x4 /* enum */
3242 #define	MC_CMD_PHY_BIST 0x5 /* enum */
3243 
3244 /* MC_CMD_START_BIST_OUT msgresponse */
3245 #define	MC_CMD_START_BIST_OUT_LEN 0
3246 
3247 
3248 /***********************************/
3249 /* MC_CMD_POLL_BIST
3250  * Poll for BIST completion.
3251  */
3252 #define	MC_CMD_POLL_BIST  0x26
3253 
3254 /* MC_CMD_POLL_BIST_IN msgrequest */
3255 #define	MC_CMD_POLL_BIST_IN_LEN 0
3256 
3257 /* MC_CMD_POLL_BIST_OUT msgresponse */
3258 #define	MC_CMD_POLL_BIST_OUT_LEN 8
3259 #define	MC_CMD_POLL_BIST_OUT_RESULT_OFST 0
3260 #define	MC_CMD_POLL_BIST_RUNNING 0x1 /* enum */
3261 #define	MC_CMD_POLL_BIST_PASSED 0x2 /* enum */
3262 #define	MC_CMD_POLL_BIST_FAILED 0x3 /* enum */
3263 #define	MC_CMD_POLL_BIST_TIMEOUT 0x4 /* enum */
3264 #define	MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4
3265 
3266 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */
3267 #define	MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36
3268 /*            MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
3269 /*            Enum values, see field(s): */
3270 /*               MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
3271 #define	MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4
3272 #define	MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8
3273 #define	MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12
3274 #define	MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16
3275 #define	MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20
3276 #define	MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 /* enum */
3277 #define	MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 /* enum */
3278 #define	MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 /* enum */
3279 #define	MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 /* enum */
3280 #define	MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 /* enum */
3281 #define	MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24
3282 /*            Enum values, see field(s): */
3283 /*               CABLE_STATUS_A */
3284 #define	MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28
3285 /*            Enum values, see field(s): */
3286 /*               CABLE_STATUS_A */
3287 #define	MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32
3288 /*            Enum values, see field(s): */
3289 /*               CABLE_STATUS_A */
3290 
3291 /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */
3292 #define	MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8
3293 /*            MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
3294 /*            Enum values, see field(s): */
3295 /*               MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
3296 #define	MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4
3297 #define	MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 /* enum */
3298 #define	MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 /* enum */
3299 #define	MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 /* enum */
3300 #define	MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 /* enum */
3301 #define	MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 /* enum */
3302 #define	MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 /* enum */
3303 #define	MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 /* enum */
3304 #define	MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 /* enum */
3305 #define	MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 /* enum */
3306 
3307 
3308 /***********************************/
3309 /* MC_CMD_FLUSH_RX_QUEUES
3310  * Flush receive queue(s).
3311  */
3312 #define	MC_CMD_FLUSH_RX_QUEUES  0x27
3313 
3314 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */
3315 #define	MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4
3316 #define	MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252
3317 #define	MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num))
3318 #define	MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0
3319 #define	MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4
3320 #define	MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1
3321 #define	MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63
3322 
3323 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */
3324 #define	MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0
3325 
3326 
3327 /***********************************/
3328 /* MC_CMD_GET_LOOPBACK_MODES
3329  * Get port's loopback modes.
3330  */
3331 #define	MC_CMD_GET_LOOPBACK_MODES  0x28
3332 
3333 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */
3334 #define	MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0
3335 
3336 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */
3337 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 32
3338 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0
3339 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8
3340 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0
3341 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4
3342 #define	MC_CMD_LOOPBACK_NONE  0x0 /* enum */
3343 #define	MC_CMD_LOOPBACK_DATA  0x1 /* enum */
3344 #define	MC_CMD_LOOPBACK_GMAC  0x2 /* enum */
3345 #define	MC_CMD_LOOPBACK_XGMII 0x3 /* enum */
3346 #define	MC_CMD_LOOPBACK_XGXS  0x4 /* enum */
3347 #define	MC_CMD_LOOPBACK_XAUI  0x5 /* enum */
3348 #define	MC_CMD_LOOPBACK_GMII  0x6 /* enum */
3349 #define	MC_CMD_LOOPBACK_SGMII  0x7 /* enum */
3350 #define	MC_CMD_LOOPBACK_XGBR  0x8 /* enum */
3351 #define	MC_CMD_LOOPBACK_XFI  0x9 /* enum */
3352 #define	MC_CMD_LOOPBACK_XAUI_FAR  0xa /* enum */
3353 #define	MC_CMD_LOOPBACK_GMII_FAR  0xb /* enum */
3354 #define	MC_CMD_LOOPBACK_SGMII_FAR  0xc /* enum */
3355 #define	MC_CMD_LOOPBACK_XFI_FAR  0xd /* enum */
3356 #define	MC_CMD_LOOPBACK_GPHY  0xe /* enum */
3357 #define	MC_CMD_LOOPBACK_PHYXS  0xf /* enum */
3358 #define	MC_CMD_LOOPBACK_PCS  0x10 /* enum */
3359 #define	MC_CMD_LOOPBACK_PMAPMD  0x11 /* enum */
3360 #define	MC_CMD_LOOPBACK_XPORT  0x12 /* enum */
3361 #define	MC_CMD_LOOPBACK_XGMII_WS  0x13 /* enum */
3362 #define	MC_CMD_LOOPBACK_XAUI_WS  0x14 /* enum */
3363 #define	MC_CMD_LOOPBACK_XAUI_WS_FAR  0x15 /* enum */
3364 #define	MC_CMD_LOOPBACK_XAUI_WS_NEAR  0x16 /* enum */
3365 #define	MC_CMD_LOOPBACK_GMII_WS  0x17 /* enum */
3366 #define	MC_CMD_LOOPBACK_XFI_WS  0x18 /* enum */
3367 #define	MC_CMD_LOOPBACK_XFI_WS_FAR  0x19 /* enum */
3368 #define	MC_CMD_LOOPBACK_PHYXS_WS  0x1a /* enum */
3369 #define	MC_CMD_LOOPBACK_AOE_INT_NEAR  0x23 /* enum */
3370 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8
3371 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8
3372 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8
3373 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12
3374 /*            Enum values, see field(s): */
3375 /*               100M */
3376 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16
3377 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8
3378 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16
3379 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20
3380 /*            Enum values, see field(s): */
3381 /*               100M */
3382 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24
3383 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8
3384 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24
3385 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28
3386 /*            Enum values, see field(s): */
3387 /*               100M */
3388 
3389 
3390 /***********************************/
3391 /* MC_CMD_GET_LINK
3392  * Read the unified MAC/PHY link state.
3393  */
3394 #define	MC_CMD_GET_LINK  0x29
3395 
3396 /* MC_CMD_GET_LINK_IN msgrequest */
3397 #define	MC_CMD_GET_LINK_IN_LEN 0
3398 
3399 /* MC_CMD_GET_LINK_OUT msgresponse */
3400 #define	MC_CMD_GET_LINK_OUT_LEN 28
3401 #define	MC_CMD_GET_LINK_OUT_CAP_OFST 0
3402 #define	MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4
3403 #define	MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8
3404 #define	MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12
3405 /*            Enum values, see field(s): */
3406 /*               MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
3407 #define	MC_CMD_GET_LINK_OUT_FLAGS_OFST 16
3408 #define	MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0
3409 #define	MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1
3410 #define	MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1
3411 #define	MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1
3412 #define	MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2
3413 #define	MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1
3414 #define	MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3
3415 #define	MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1
3416 #define	MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6
3417 #define	MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1
3418 #define	MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7
3419 #define	MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1
3420 #define	MC_CMD_GET_LINK_OUT_FCNTL_OFST 20
3421 #define	MC_CMD_FCNTL_OFF 0x0 /* enum */
3422 #define	MC_CMD_FCNTL_RESPOND 0x1 /* enum */
3423 #define	MC_CMD_FCNTL_BIDIR 0x2 /* enum */
3424 #define	MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24
3425 #define	MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0
3426 #define	MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1
3427 #define	MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1
3428 #define	MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1
3429 #define	MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2
3430 #define	MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1
3431 #define	MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3
3432 #define	MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1
3433 
3434 
3435 /***********************************/
3436 /* MC_CMD_SET_LINK
3437  * Write the unified MAC/PHY link configuration.
3438  */
3439 #define	MC_CMD_SET_LINK  0x2a
3440 
3441 /* MC_CMD_SET_LINK_IN msgrequest */
3442 #define	MC_CMD_SET_LINK_IN_LEN 16
3443 #define	MC_CMD_SET_LINK_IN_CAP_OFST 0
3444 #define	MC_CMD_SET_LINK_IN_FLAGS_OFST 4
3445 #define	MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0
3446 #define	MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1
3447 #define	MC_CMD_SET_LINK_IN_POWEROFF_LBN 1
3448 #define	MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1
3449 #define	MC_CMD_SET_LINK_IN_TXDIS_LBN 2
3450 #define	MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1
3451 #define	MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8
3452 /*            Enum values, see field(s): */
3453 /*               MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
3454 #define	MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12
3455 
3456 /* MC_CMD_SET_LINK_OUT msgresponse */
3457 #define	MC_CMD_SET_LINK_OUT_LEN 0
3458 
3459 
3460 /***********************************/
3461 /* MC_CMD_SET_ID_LED
3462  * Set indentification LED state.
3463  */
3464 #define	MC_CMD_SET_ID_LED  0x2b
3465 
3466 /* MC_CMD_SET_ID_LED_IN msgrequest */
3467 #define	MC_CMD_SET_ID_LED_IN_LEN 4
3468 #define	MC_CMD_SET_ID_LED_IN_STATE_OFST 0
3469 #define	MC_CMD_LED_OFF  0x0 /* enum */
3470 #define	MC_CMD_LED_ON  0x1 /* enum */
3471 #define	MC_CMD_LED_DEFAULT  0x2 /* enum */
3472 
3473 /* MC_CMD_SET_ID_LED_OUT msgresponse */
3474 #define	MC_CMD_SET_ID_LED_OUT_LEN 0
3475 
3476 
3477 /***********************************/
3478 /* MC_CMD_SET_MAC
3479  * Set MAC configuration.
3480  */
3481 #define	MC_CMD_SET_MAC  0x2c
3482 
3483 /* MC_CMD_SET_MAC_IN msgrequest */
3484 #define	MC_CMD_SET_MAC_IN_LEN 24
3485 #define	MC_CMD_SET_MAC_IN_MTU_OFST 0
3486 #define	MC_CMD_SET_MAC_IN_DRAIN_OFST 4
3487 #define	MC_CMD_SET_MAC_IN_ADDR_OFST 8
3488 #define	MC_CMD_SET_MAC_IN_ADDR_LEN 8
3489 #define	MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8
3490 #define	MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12
3491 #define	MC_CMD_SET_MAC_IN_REJECT_OFST 16
3492 #define	MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0
3493 #define	MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1
3494 #define	MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1
3495 #define	MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1
3496 #define	MC_CMD_SET_MAC_IN_FCNTL_OFST 20
3497 /*               MC_CMD_FCNTL_OFF 0x0 */
3498 /*               MC_CMD_FCNTL_RESPOND 0x1 */
3499 /*               MC_CMD_FCNTL_BIDIR 0x2 */
3500 #define	MC_CMD_FCNTL_AUTO 0x3 /* enum */
3501 
3502 /* MC_CMD_SET_MAC_OUT msgresponse */
3503 #define	MC_CMD_SET_MAC_OUT_LEN 0
3504 
3505 
3506 /***********************************/
3507 /* MC_CMD_PHY_STATS
3508  * Get generic PHY statistics.
3509  */
3510 #define	MC_CMD_PHY_STATS  0x2d
3511 
3512 /* MC_CMD_PHY_STATS_IN msgrequest */
3513 #define	MC_CMD_PHY_STATS_IN_LEN 8
3514 #define	MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0
3515 #define	MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8
3516 #define	MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0
3517 #define	MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4
3518 
3519 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */
3520 #define	MC_CMD_PHY_STATS_OUT_DMA_LEN 0
3521 
3522 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */
3523 #define	MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3)
3524 #define	MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0
3525 #define	MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4
3526 #define	MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS
3527 #define	MC_CMD_OUI  0x0 /* enum */
3528 #define	MC_CMD_PMA_PMD_LINK_UP  0x1 /* enum */
3529 #define	MC_CMD_PMA_PMD_RX_FAULT  0x2 /* enum */
3530 #define	MC_CMD_PMA_PMD_TX_FAULT  0x3 /* enum */
3531 #define	MC_CMD_PMA_PMD_SIGNAL  0x4 /* enum */
3532 #define	MC_CMD_PMA_PMD_SNR_A  0x5 /* enum */
3533 #define	MC_CMD_PMA_PMD_SNR_B  0x6 /* enum */
3534 #define	MC_CMD_PMA_PMD_SNR_C  0x7 /* enum */
3535 #define	MC_CMD_PMA_PMD_SNR_D  0x8 /* enum */
3536 #define	MC_CMD_PCS_LINK_UP  0x9 /* enum */
3537 #define	MC_CMD_PCS_RX_FAULT  0xa /* enum */
3538 #define	MC_CMD_PCS_TX_FAULT  0xb /* enum */
3539 #define	MC_CMD_PCS_BER  0xc /* enum */
3540 #define	MC_CMD_PCS_BLOCK_ERRORS  0xd /* enum */
3541 #define	MC_CMD_PHYXS_LINK_UP  0xe /* enum */
3542 #define	MC_CMD_PHYXS_RX_FAULT  0xf /* enum */
3543 #define	MC_CMD_PHYXS_TX_FAULT  0x10 /* enum */
3544 #define	MC_CMD_PHYXS_ALIGN  0x11 /* enum */
3545 #define	MC_CMD_PHYXS_SYNC  0x12 /* enum */
3546 #define	MC_CMD_AN_LINK_UP  0x13 /* enum */
3547 #define	MC_CMD_AN_COMPLETE  0x14 /* enum */
3548 #define	MC_CMD_AN_10GBT_STATUS  0x15 /* enum */
3549 #define	MC_CMD_CL22_LINK_UP  0x16 /* enum */
3550 #define	MC_CMD_PHY_NSTATS  0x17 /* enum */
3551 
3552 
3553 /***********************************/
3554 /* MC_CMD_MAC_STATS
3555  * Get generic MAC statistics.
3556  */
3557 #define	MC_CMD_MAC_STATS  0x2e
3558 
3559 /* MC_CMD_MAC_STATS_IN msgrequest */
3560 #define	MC_CMD_MAC_STATS_IN_LEN 16
3561 #define	MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0
3562 #define	MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8
3563 #define	MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0
3564 #define	MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4
3565 #define	MC_CMD_MAC_STATS_IN_CMD_OFST 8
3566 #define	MC_CMD_MAC_STATS_IN_DMA_LBN 0
3567 #define	MC_CMD_MAC_STATS_IN_DMA_WIDTH 1
3568 #define	MC_CMD_MAC_STATS_IN_CLEAR_LBN 1
3569 #define	MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1
3570 #define	MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2
3571 #define	MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1
3572 #define	MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3
3573 #define	MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1
3574 #define	MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4
3575 #define	MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1
3576 #define	MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5
3577 #define	MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1
3578 #define	MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16
3579 #define	MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16
3580 #define	MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12
3581 
3582 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */
3583 #define	MC_CMD_MAC_STATS_OUT_DMA_LEN 0
3584 
3585 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */
3586 #define	MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3)
3587 #define	MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0
3588 #define	MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8
3589 #define	MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0
3590 #define	MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4
3591 #define	MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
3592 #define	MC_CMD_MAC_GENERATION_START  0x0 /* enum */
3593 #define	MC_CMD_MAC_TX_PKTS  0x1 /* enum */
3594 #define	MC_CMD_MAC_TX_PAUSE_PKTS  0x2 /* enum */
3595 #define	MC_CMD_MAC_TX_CONTROL_PKTS  0x3 /* enum */
3596 #define	MC_CMD_MAC_TX_UNICAST_PKTS  0x4 /* enum */
3597 #define	MC_CMD_MAC_TX_MULTICAST_PKTS  0x5 /* enum */
3598 #define	MC_CMD_MAC_TX_BROADCAST_PKTS  0x6 /* enum */
3599 #define	MC_CMD_MAC_TX_BYTES  0x7 /* enum */
3600 #define	MC_CMD_MAC_TX_BAD_BYTES  0x8 /* enum */
3601 #define	MC_CMD_MAC_TX_LT64_PKTS  0x9 /* enum */
3602 #define	MC_CMD_MAC_TX_64_PKTS  0xa /* enum */
3603 #define	MC_CMD_MAC_TX_65_TO_127_PKTS  0xb /* enum */
3604 #define	MC_CMD_MAC_TX_128_TO_255_PKTS  0xc /* enum */
3605 #define	MC_CMD_MAC_TX_256_TO_511_PKTS  0xd /* enum */
3606 #define	MC_CMD_MAC_TX_512_TO_1023_PKTS  0xe /* enum */
3607 #define	MC_CMD_MAC_TX_1024_TO_15XX_PKTS  0xf /* enum */
3608 #define	MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS  0x10 /* enum */
3609 #define	MC_CMD_MAC_TX_GTJUMBO_PKTS  0x11 /* enum */
3610 #define	MC_CMD_MAC_TX_BAD_FCS_PKTS  0x12 /* enum */
3611 #define	MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS  0x13 /* enum */
3612 #define	MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS  0x14 /* enum */
3613 #define	MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS  0x15 /* enum */
3614 #define	MC_CMD_MAC_TX_LATE_COLLISION_PKTS  0x16 /* enum */
3615 #define	MC_CMD_MAC_TX_DEFERRED_PKTS  0x17 /* enum */
3616 #define	MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS  0x18 /* enum */
3617 #define	MC_CMD_MAC_TX_NON_TCPUDP_PKTS  0x19 /* enum */
3618 #define	MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS  0x1a /* enum */
3619 #define	MC_CMD_MAC_TX_IP_SRC_ERR_PKTS  0x1b /* enum */
3620 #define	MC_CMD_MAC_RX_PKTS  0x1c /* enum */
3621 #define	MC_CMD_MAC_RX_PAUSE_PKTS  0x1d /* enum */
3622 #define	MC_CMD_MAC_RX_GOOD_PKTS  0x1e /* enum */
3623 #define	MC_CMD_MAC_RX_CONTROL_PKTS  0x1f /* enum */
3624 #define	MC_CMD_MAC_RX_UNICAST_PKTS  0x20 /* enum */
3625 #define	MC_CMD_MAC_RX_MULTICAST_PKTS  0x21 /* enum */
3626 #define	MC_CMD_MAC_RX_BROADCAST_PKTS  0x22 /* enum */
3627 #define	MC_CMD_MAC_RX_BYTES  0x23 /* enum */
3628 #define	MC_CMD_MAC_RX_BAD_BYTES  0x24 /* enum */
3629 #define	MC_CMD_MAC_RX_64_PKTS  0x25 /* enum */
3630 #define	MC_CMD_MAC_RX_65_TO_127_PKTS  0x26 /* enum */
3631 #define	MC_CMD_MAC_RX_128_TO_255_PKTS  0x27 /* enum */
3632 #define	MC_CMD_MAC_RX_256_TO_511_PKTS  0x28 /* enum */
3633 #define	MC_CMD_MAC_RX_512_TO_1023_PKTS  0x29 /* enum */
3634 #define	MC_CMD_MAC_RX_1024_TO_15XX_PKTS  0x2a /* enum */
3635 #define	MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS  0x2b /* enum */
3636 #define	MC_CMD_MAC_RX_GTJUMBO_PKTS  0x2c /* enum */
3637 #define	MC_CMD_MAC_RX_UNDERSIZE_PKTS  0x2d /* enum */
3638 #define	MC_CMD_MAC_RX_BAD_FCS_PKTS  0x2e /* enum */
3639 #define	MC_CMD_MAC_RX_OVERFLOW_PKTS  0x2f /* enum */
3640 #define	MC_CMD_MAC_RX_FALSE_CARRIER_PKTS  0x30 /* enum */
3641 #define	MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS  0x31 /* enum */
3642 #define	MC_CMD_MAC_RX_ALIGN_ERROR_PKTS  0x32 /* enum */
3643 #define	MC_CMD_MAC_RX_LENGTH_ERROR_PKTS  0x33 /* enum */
3644 #define	MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS  0x34 /* enum */
3645 #define	MC_CMD_MAC_RX_JABBER_PKTS  0x35 /* enum */
3646 #define	MC_CMD_MAC_RX_NODESC_DROPS  0x36 /* enum */
3647 #define	MC_CMD_MAC_RX_LANES01_CHAR_ERR  0x37 /* enum */
3648 #define	MC_CMD_MAC_RX_LANES23_CHAR_ERR  0x38 /* enum */
3649 #define	MC_CMD_MAC_RX_LANES01_DISP_ERR  0x39 /* enum */
3650 #define	MC_CMD_MAC_RX_LANES23_DISP_ERR  0x3a /* enum */
3651 #define	MC_CMD_MAC_RX_MATCH_FAULT  0x3b /* enum */
3652 #define	MC_CMD_GMAC_DMABUF_START  0x40 /* enum */
3653 #define	MC_CMD_GMAC_DMABUF_END    0x5f /* enum */
3654 #define	MC_CMD_MAC_GENERATION_END 0x60 /* enum */
3655 #define	MC_CMD_MAC_NSTATS  0x61 /* enum */
3656 
3657 
3658 /***********************************/
3659 /* MC_CMD_SRIOV
3660  * to be documented
3661  */
3662 #define	MC_CMD_SRIOV  0x30
3663 
3664 /* MC_CMD_SRIOV_IN msgrequest */
3665 #define	MC_CMD_SRIOV_IN_LEN 12
3666 #define	MC_CMD_SRIOV_IN_ENABLE_OFST 0
3667 #define	MC_CMD_SRIOV_IN_VI_BASE_OFST 4
3668 #define	MC_CMD_SRIOV_IN_VF_COUNT_OFST 8
3669 
3670 /* MC_CMD_SRIOV_OUT msgresponse */
3671 #define	MC_CMD_SRIOV_OUT_LEN 8
3672 #define	MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0
3673 #define	MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4
3674 
3675 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */
3676 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32
3677 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0
3678 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0
3679 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32
3680 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4
3681 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32
3682 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32
3683 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8
3684 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8
3685 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8
3686 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12
3687 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64
3688 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64
3689 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16
3690 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */
3691 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128
3692 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32
3693 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20
3694 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8
3695 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20
3696 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24
3697 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160
3698 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64
3699 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28
3700 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224
3701 #define	MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32
3702 
3703 
3704 /***********************************/
3705 /* MC_CMD_MEMCPY
3706  * Perform memory copy operation.
3707  */
3708 #define	MC_CMD_MEMCPY  0x31
3709 
3710 /* MC_CMD_MEMCPY_IN msgrequest */
3711 #define	MC_CMD_MEMCPY_IN_LENMIN 32
3712 #define	MC_CMD_MEMCPY_IN_LENMAX 224
3713 #define	MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num))
3714 #define	MC_CMD_MEMCPY_IN_RECORD_OFST 0
3715 #define	MC_CMD_MEMCPY_IN_RECORD_LEN 32
3716 #define	MC_CMD_MEMCPY_IN_RECORD_MINNUM 1
3717 #define	MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7
3718 
3719 /* MC_CMD_MEMCPY_OUT msgresponse */
3720 #define	MC_CMD_MEMCPY_OUT_LEN 0
3721 
3722 
3723 /***********************************/
3724 /* MC_CMD_WOL_FILTER_SET
3725  * Set a WoL filter.
3726  */
3727 #define	MC_CMD_WOL_FILTER_SET  0x32
3728 
3729 /* MC_CMD_WOL_FILTER_SET_IN msgrequest */
3730 #define	MC_CMD_WOL_FILTER_SET_IN_LEN 192
3731 #define	MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0
3732 #define	MC_CMD_FILTER_MODE_SIMPLE    0x0 /* enum */
3733 #define	MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */
3734 #define	MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4
3735 #define	MC_CMD_WOL_TYPE_MAGIC      0x0 /* enum */
3736 #define	MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 /* enum */
3737 #define	MC_CMD_WOL_TYPE_IPV4_SYN   0x3 /* enum */
3738 #define	MC_CMD_WOL_TYPE_IPV6_SYN   0x4 /* enum */
3739 #define	MC_CMD_WOL_TYPE_BITMAP     0x5 /* enum */
3740 #define	MC_CMD_WOL_TYPE_LINK       0x6 /* enum */
3741 #define	MC_CMD_WOL_TYPE_MAX        0x7 /* enum */
3742 #define	MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8
3743 #define	MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4
3744 #define	MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46
3745 
3746 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */
3747 #define	MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16
3748 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
3749 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
3750 #define	MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8
3751 #define	MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8
3752 #define	MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8
3753 #define	MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12
3754 
3755 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */
3756 #define	MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20
3757 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
3758 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
3759 #define	MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8
3760 #define	MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12
3761 #define	MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16
3762 #define	MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2
3763 #define	MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18
3764 #define	MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2
3765 
3766 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */
3767 #define	MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44
3768 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
3769 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
3770 #define	MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8
3771 #define	MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16
3772 #define	MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24
3773 #define	MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16
3774 #define	MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40
3775 #define	MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2
3776 #define	MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42
3777 #define	MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2
3778 
3779 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */
3780 #define	MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187
3781 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
3782 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
3783 #define	MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8
3784 #define	MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48
3785 #define	MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56
3786 #define	MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128
3787 #define	MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184
3788 #define	MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1
3789 #define	MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185
3790 #define	MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1
3791 #define	MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186
3792 #define	MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1
3793 
3794 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */
3795 #define	MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12
3796 /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
3797 /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
3798 #define	MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8
3799 #define	MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0
3800 #define	MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1
3801 #define	MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1
3802 #define	MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1
3803 
3804 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */
3805 #define	MC_CMD_WOL_FILTER_SET_OUT_LEN 4
3806 #define	MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0
3807 
3808 
3809 /***********************************/
3810 /* MC_CMD_WOL_FILTER_REMOVE
3811  * Remove a WoL filter.
3812  */
3813 #define	MC_CMD_WOL_FILTER_REMOVE  0x33
3814 
3815 /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */
3816 #define	MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4
3817 #define	MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0
3818 
3819 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */
3820 #define	MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0
3821 
3822 
3823 /***********************************/
3824 /* MC_CMD_WOL_FILTER_RESET
3825  * Reset (i.e. remove all) WoL filters.
3826  */
3827 #define	MC_CMD_WOL_FILTER_RESET  0x34
3828 
3829 /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */
3830 #define	MC_CMD_WOL_FILTER_RESET_IN_LEN 4
3831 #define	MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0
3832 #define	MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */
3833 #define	MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */
3834 
3835 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */
3836 #define	MC_CMD_WOL_FILTER_RESET_OUT_LEN 0
3837 
3838 
3839 /***********************************/
3840 /* MC_CMD_SET_MCAST_HASH
3841  * Set the MCASH hash value.
3842  */
3843 #define	MC_CMD_SET_MCAST_HASH  0x35
3844 
3845 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */
3846 #define	MC_CMD_SET_MCAST_HASH_IN_LEN 32
3847 #define	MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0
3848 #define	MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16
3849 #define	MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16
3850 #define	MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16
3851 
3852 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */
3853 #define	MC_CMD_SET_MCAST_HASH_OUT_LEN 0
3854 
3855 
3856 /***********************************/
3857 /* MC_CMD_NVRAM_TYPES
3858  * Get virtual NVRAM partitions information.
3859  */
3860 #define	MC_CMD_NVRAM_TYPES  0x36
3861 
3862 /* MC_CMD_NVRAM_TYPES_IN msgrequest */
3863 #define	MC_CMD_NVRAM_TYPES_IN_LEN 0
3864 
3865 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */
3866 #define	MC_CMD_NVRAM_TYPES_OUT_LEN 4
3867 #define	MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0
3868 #define	MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 /* enum */
3869 #define	MC_CMD_NVRAM_TYPE_MC_FW 0x1 /* enum */
3870 #define	MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 /* enum */
3871 #define	MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 /* enum */
3872 #define	MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 /* enum */
3873 #define	MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 /* enum */
3874 #define	MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 /* enum */
3875 #define	MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 /* enum */
3876 #define	MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 /* enum */
3877 #define	MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 /* enum */
3878 #define	MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa /* enum */
3879 #define	MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb /* enum */
3880 #define	MC_CMD_NVRAM_TYPE_LOG 0xc /* enum */
3881 #define	MC_CMD_NVRAM_TYPE_FPGA 0xd /* enum */
3882 #define	MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe /* enum */
3883 #define	MC_CMD_NVRAM_TYPE_FC_FW 0xf /* enum */
3884 #define	MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10 /* enum */
3885 #define	MC_CMD_NVRAM_TYPE_CPLD 0x11 /* enum */
3886 #define	MC_CMD_NVRAM_TYPE_LICENSE 0x12 /* enum */
3887 #define	MC_CMD_NVRAM_TYPE_FC_LOG 0x13 /* enum */
3888 #define	MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14 /* enum */
3889 
3890 
3891 /***********************************/
3892 /* MC_CMD_NVRAM_INFO
3893  * Read info about a virtual NVRAM partition.
3894  */
3895 #define	MC_CMD_NVRAM_INFO  0x37
3896 
3897 /* MC_CMD_NVRAM_INFO_IN msgrequest */
3898 #define	MC_CMD_NVRAM_INFO_IN_LEN 4
3899 #define	MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0
3900 /*            Enum values, see field(s): */
3901 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
3902 
3903 /* MC_CMD_NVRAM_INFO_OUT msgresponse */
3904 #define	MC_CMD_NVRAM_INFO_OUT_LEN 24
3905 #define	MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0
3906 /*            Enum values, see field(s): */
3907 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
3908 #define	MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4
3909 #define	MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8
3910 #define	MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12
3911 #define	MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0
3912 #define	MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1
3913 #define	MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16
3914 #define	MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20
3915 
3916 
3917 /***********************************/
3918 /* MC_CMD_NVRAM_UPDATE_START
3919  * Start a group of update operations on a virtual NVRAM partition.
3920  */
3921 #define	MC_CMD_NVRAM_UPDATE_START  0x38
3922 
3923 /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest */
3924 #define	MC_CMD_NVRAM_UPDATE_START_IN_LEN 4
3925 #define	MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0
3926 /*            Enum values, see field(s): */
3927 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
3928 
3929 /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */
3930 #define	MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0
3931 
3932 
3933 /***********************************/
3934 /* MC_CMD_NVRAM_READ
3935  * Read data from a virtual NVRAM partition.
3936  */
3937 #define	MC_CMD_NVRAM_READ  0x39
3938 
3939 /* MC_CMD_NVRAM_READ_IN msgrequest */
3940 #define	MC_CMD_NVRAM_READ_IN_LEN 12
3941 #define	MC_CMD_NVRAM_READ_IN_TYPE_OFST 0
3942 /*            Enum values, see field(s): */
3943 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
3944 #define	MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4
3945 #define	MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8
3946 
3947 /* MC_CMD_NVRAM_READ_OUT msgresponse */
3948 #define	MC_CMD_NVRAM_READ_OUT_LENMIN 1
3949 #define	MC_CMD_NVRAM_READ_OUT_LENMAX 252
3950 #define	MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))
3951 #define	MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0
3952 #define	MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1
3953 #define	MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1
3954 #define	MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252
3955 
3956 
3957 /***********************************/
3958 /* MC_CMD_NVRAM_WRITE
3959  * Write data to a virtual NVRAM partition.
3960  */
3961 #define	MC_CMD_NVRAM_WRITE  0x3a
3962 
3963 /* MC_CMD_NVRAM_WRITE_IN msgrequest */
3964 #define	MC_CMD_NVRAM_WRITE_IN_LENMIN 13
3965 #define	MC_CMD_NVRAM_WRITE_IN_LENMAX 252
3966 #define	MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num))
3967 #define	MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0
3968 /*            Enum values, see field(s): */
3969 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
3970 #define	MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4
3971 #define	MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8
3972 #define	MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12
3973 #define	MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1
3974 #define	MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1
3975 #define	MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240
3976 
3977 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */
3978 #define	MC_CMD_NVRAM_WRITE_OUT_LEN 0
3979 
3980 
3981 /***********************************/
3982 /* MC_CMD_NVRAM_ERASE
3983  * Erase sector(s) from a virtual NVRAM partition.
3984  */
3985 #define	MC_CMD_NVRAM_ERASE  0x3b
3986 
3987 /* MC_CMD_NVRAM_ERASE_IN msgrequest */
3988 #define	MC_CMD_NVRAM_ERASE_IN_LEN 12
3989 #define	MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0
3990 /*            Enum values, see field(s): */
3991 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
3992 #define	MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4
3993 #define	MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8
3994 
3995 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */
3996 #define	MC_CMD_NVRAM_ERASE_OUT_LEN 0
3997 
3998 
3999 /***********************************/
4000 /* MC_CMD_NVRAM_UPDATE_FINISH
4001  * Finish a group of update operations on a virtual NVRAM partition.
4002  */
4003 #define	MC_CMD_NVRAM_UPDATE_FINISH  0x3c
4004 
4005 /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest */
4006 #define	MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8
4007 #define	MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0
4008 /*            Enum values, see field(s): */
4009 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4010 #define	MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4
4011 
4012 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse */
4013 #define	MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0
4014 
4015 
4016 /***********************************/
4017 /* MC_CMD_REBOOT
4018  * Reboot the MC.
4019  */
4020 #define	MC_CMD_REBOOT  0x3d
4021 
4022 /* MC_CMD_REBOOT_IN msgrequest */
4023 #define	MC_CMD_REBOOT_IN_LEN 4
4024 #define	MC_CMD_REBOOT_IN_FLAGS_OFST 0
4025 #define	MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */
4026 
4027 /* MC_CMD_REBOOT_OUT msgresponse */
4028 #define	MC_CMD_REBOOT_OUT_LEN 0
4029 
4030 
4031 /***********************************/
4032 /* MC_CMD_SCHEDINFO
4033  * Request scheduler info.
4034  */
4035 #define	MC_CMD_SCHEDINFO  0x3e
4036 
4037 /* MC_CMD_SCHEDINFO_IN msgrequest */
4038 #define	MC_CMD_SCHEDINFO_IN_LEN 0
4039 
4040 /* MC_CMD_SCHEDINFO_OUT msgresponse */
4041 #define	MC_CMD_SCHEDINFO_OUT_LENMIN 4
4042 #define	MC_CMD_SCHEDINFO_OUT_LENMAX 252
4043 #define	MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num))
4044 #define	MC_CMD_SCHEDINFO_OUT_DATA_OFST 0
4045 #define	MC_CMD_SCHEDINFO_OUT_DATA_LEN 4
4046 #define	MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1
4047 #define	MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63
4048 
4049 
4050 /***********************************/
4051 /* MC_CMD_REBOOT_MODE
4052  */
4053 #define	MC_CMD_REBOOT_MODE  0x3f
4054 
4055 /* MC_CMD_REBOOT_MODE_IN msgrequest */
4056 #define	MC_CMD_REBOOT_MODE_IN_LEN 4
4057 #define	MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0
4058 #define	MC_CMD_REBOOT_MODE_NORMAL 0x0 /* enum */
4059 #define	MC_CMD_REBOOT_MODE_SNAPPER 0x3 /* enum */
4060 
4061 /* MC_CMD_REBOOT_MODE_OUT msgresponse */
4062 #define	MC_CMD_REBOOT_MODE_OUT_LEN 4
4063 #define	MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0
4064 
4065 
4066 /***********************************/
4067 /* MC_CMD_SENSOR_INFO
4068  * Returns information about every available sensor.
4069  */
4070 #define	MC_CMD_SENSOR_INFO  0x41
4071 
4072 /* MC_CMD_SENSOR_INFO_IN msgrequest */
4073 #define	MC_CMD_SENSOR_INFO_IN_LEN 0
4074 
4075 /* MC_CMD_SENSOR_INFO_OUT msgresponse */
4076 #define	MC_CMD_SENSOR_INFO_OUT_LENMIN 12
4077 #define	MC_CMD_SENSOR_INFO_OUT_LENMAX 252
4078 #define	MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num))
4079 #define	MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0
4080 #define	MC_CMD_SENSOR_CONTROLLER_TEMP  0x0 /* enum */
4081 #define	MC_CMD_SENSOR_PHY_COMMON_TEMP  0x1 /* enum */
4082 #define	MC_CMD_SENSOR_CONTROLLER_COOLING  0x2 /* enum */
4083 #define	MC_CMD_SENSOR_PHY0_TEMP  0x3 /* enum */
4084 #define	MC_CMD_SENSOR_PHY0_COOLING  0x4 /* enum */
4085 #define	MC_CMD_SENSOR_PHY1_TEMP  0x5 /* enum */
4086 #define	MC_CMD_SENSOR_PHY1_COOLING  0x6 /* enum */
4087 #define	MC_CMD_SENSOR_IN_1V0  0x7 /* enum */
4088 #define	MC_CMD_SENSOR_IN_1V2  0x8 /* enum */
4089 #define	MC_CMD_SENSOR_IN_1V8  0x9 /* enum */
4090 #define	MC_CMD_SENSOR_IN_2V5  0xa /* enum */
4091 #define	MC_CMD_SENSOR_IN_3V3  0xb /* enum */
4092 #define	MC_CMD_SENSOR_IN_12V0  0xc /* enum */
4093 #define	MC_CMD_SENSOR_IN_1V2A  0xd /* enum */
4094 #define	MC_CMD_SENSOR_IN_VREF  0xe /* enum */
4095 #define	MC_CMD_SENSOR_OUT_VAOE  0xf /* enum */
4096 #define	MC_CMD_SENSOR_AOE_TEMP  0x10 /* enum */
4097 #define	MC_CMD_SENSOR_PSU_AOE_TEMP  0x11 /* enum */
4098 #define	MC_CMD_SENSOR_PSU_TEMP  0x12 /* enum */
4099 #define	MC_CMD_SENSOR_FAN_0  0x13 /* enum */
4100 #define	MC_CMD_SENSOR_FAN_1  0x14 /* enum */
4101 #define	MC_CMD_SENSOR_FAN_2  0x15 /* enum */
4102 #define	MC_CMD_SENSOR_FAN_3  0x16 /* enum */
4103 #define	MC_CMD_SENSOR_FAN_4  0x17 /* enum */
4104 #define	MC_CMD_SENSOR_IN_VAOE  0x18 /* enum */
4105 #define	MC_CMD_SENSOR_OUT_IAOE  0x19 /* enum */
4106 #define	MC_CMD_SENSOR_IN_IAOE  0x1a /* enum */
4107 #define	MC_CMD_SENSOR_NIC_POWER  0x1b /* enum */
4108 #define	MC_CMD_SENSOR_ENTRY_OFST 4
4109 #define	MC_CMD_SENSOR_ENTRY_LEN 8
4110 #define	MC_CMD_SENSOR_ENTRY_LO_OFST 4
4111 #define	MC_CMD_SENSOR_ENTRY_HI_OFST 8
4112 #define	MC_CMD_SENSOR_ENTRY_MINNUM 1
4113 #define	MC_CMD_SENSOR_ENTRY_MAXNUM 31
4114 
4115 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */
4116 #define	MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8
4117 #define	MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0
4118 #define	MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2
4119 #define	MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0
4120 #define	MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16
4121 #define	MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2
4122 #define	MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2
4123 #define	MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16
4124 #define	MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16
4125 #define	MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4
4126 #define	MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2
4127 #define	MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32
4128 #define	MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16
4129 #define	MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6
4130 #define	MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2
4131 #define	MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48
4132 #define	MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16
4133 
4134 
4135 /***********************************/
4136 /* MC_CMD_READ_SENSORS
4137  * Returns the current reading from each sensor.
4138  */
4139 #define	MC_CMD_READ_SENSORS  0x42
4140 
4141 /* MC_CMD_READ_SENSORS_IN msgrequest */
4142 #define	MC_CMD_READ_SENSORS_IN_LEN 8
4143 #define	MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0
4144 #define	MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8
4145 #define	MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0
4146 #define	MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4
4147 
4148 /* MC_CMD_READ_SENSORS_OUT msgresponse */
4149 #define	MC_CMD_READ_SENSORS_OUT_LEN 0
4150 
4151 /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */
4152 #define	MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 3
4153 #define	MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0
4154 #define	MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2
4155 #define	MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0
4156 #define	MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16
4157 #define	MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2
4158 #define	MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1
4159 #define	MC_CMD_SENSOR_STATE_OK  0x0 /* enum */
4160 #define	MC_CMD_SENSOR_STATE_WARNING  0x1 /* enum */
4161 #define	MC_CMD_SENSOR_STATE_FATAL  0x2 /* enum */
4162 #define	MC_CMD_SENSOR_STATE_BROKEN  0x3 /* enum */
4163 #define	MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16
4164 #define	MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8
4165 
4166 
4167 /***********************************/
4168 /* MC_CMD_GET_PHY_STATE
4169  * Report current state of PHY.
4170  */
4171 #define	MC_CMD_GET_PHY_STATE  0x43
4172 
4173 /* MC_CMD_GET_PHY_STATE_IN msgrequest */
4174 #define	MC_CMD_GET_PHY_STATE_IN_LEN 0
4175 
4176 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */
4177 #define	MC_CMD_GET_PHY_STATE_OUT_LEN 4
4178 #define	MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0
4179 #define	MC_CMD_PHY_STATE_OK 0x1 /* enum */
4180 #define	MC_CMD_PHY_STATE_ZOMBIE 0x2 /* enum */
4181 
4182 
4183 /***********************************/
4184 /* MC_CMD_SETUP_8021QBB
4185  * 802.1Qbb control.
4186  */
4187 #define	MC_CMD_SETUP_8021QBB  0x44
4188 
4189 /* MC_CMD_SETUP_8021QBB_IN msgrequest */
4190 #define	MC_CMD_SETUP_8021QBB_IN_LEN 32
4191 #define	MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0
4192 #define	MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32
4193 
4194 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */
4195 #define	MC_CMD_SETUP_8021QBB_OUT_LEN 0
4196 
4197 
4198 /***********************************/
4199 /* MC_CMD_WOL_FILTER_GET
4200  * Retrieve ID of any WoL filters.
4201  */
4202 #define	MC_CMD_WOL_FILTER_GET  0x45
4203 
4204 /* MC_CMD_WOL_FILTER_GET_IN msgrequest */
4205 #define	MC_CMD_WOL_FILTER_GET_IN_LEN 0
4206 
4207 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */
4208 #define	MC_CMD_WOL_FILTER_GET_OUT_LEN 4
4209 #define	MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0
4210 
4211 
4212 /***********************************/
4213 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD
4214  * Add a protocol offload to NIC for lights-out state.
4215  */
4216 #define	MC_CMD_ADD_LIGHTSOUT_OFFLOAD  0x46
4217 
4218 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */
4219 #define	MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8
4220 #define	MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252
4221 #define	MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num))
4222 #define	MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
4223 #define	MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */
4224 #define	MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS  0x2 /* enum */
4225 #define	MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4
4226 #define	MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4
4227 #define	MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1
4228 #define	MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62
4229 
4230 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */
4231 #define	MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14
4232 /*            MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
4233 #define	MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4
4234 #define	MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6
4235 #define	MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10
4236 
4237 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */
4238 #define	MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42
4239 /*            MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
4240 #define	MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4
4241 #define	MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6
4242 #define	MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10
4243 #define	MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16
4244 #define	MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26
4245 #define	MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16
4246 
4247 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */
4248 #define	MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4
4249 #define	MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0
4250 
4251 
4252 /***********************************/
4253 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD
4254  * Remove a protocol offload from NIC for lights-out state.
4255  */
4256 #define	MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD  0x47
4257 
4258 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */
4259 #define	MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8
4260 #define	MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
4261 #define	MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4
4262 
4263 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */
4264 #define	MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0
4265 
4266 
4267 /***********************************/
4268 /* MC_CMD_MAC_RESET_RESTORE
4269  * Restore MAC after block reset.
4270  */
4271 #define	MC_CMD_MAC_RESET_RESTORE  0x48
4272 
4273 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */
4274 #define	MC_CMD_MAC_RESET_RESTORE_IN_LEN 0
4275 
4276 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */
4277 #define	MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0
4278 
4279 
4280 /***********************************/
4281 /* MC_CMD_TESTASSERT
4282  */
4283 #define	MC_CMD_TESTASSERT   0x49
4284 
4285 /* MC_CMD_TESTASSERT_IN msgrequest */
4286 #define	MC_CMD_TESTASSERT_IN_LEN 0
4287 
4288 /* MC_CMD_TESTASSERT_OUT msgresponse */
4289 #define	MC_CMD_TESTASSERT_OUT_LEN 0
4290 
4291 
4292 /***********************************/
4293 /* MC_CMD_WORKAROUND
4294  * Enable/Disable a given workaround.
4295  */
4296 #define	MC_CMD_WORKAROUND  0x4a
4297 
4298 /* MC_CMD_WORKAROUND_IN msgrequest */
4299 #define	MC_CMD_WORKAROUND_IN_LEN 8
4300 #define	MC_CMD_WORKAROUND_IN_TYPE_OFST 0
4301 #define	MC_CMD_WORKAROUND_BUG17230 0x1 /* enum */
4302 #define	MC_CMD_WORKAROUND_IN_ENABLED_OFST 4
4303 
4304 /* MC_CMD_WORKAROUND_OUT msgresponse */
4305 #define	MC_CMD_WORKAROUND_OUT_LEN 0
4306 
4307 
4308 /***********************************/
4309 /* MC_CMD_GET_PHY_MEDIA_INFO
4310  * Read media-specific data from PHY.
4311  */
4312 #define	MC_CMD_GET_PHY_MEDIA_INFO  0x4b
4313 
4314 /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */
4315 #define	MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4
4316 #define	MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0
4317 
4318 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */
4319 #define	MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5
4320 #define	MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252
4321 #define	MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num))
4322 #define	MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0
4323 #define	MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4
4324 #define	MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1
4325 #define	MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1
4326 #define	MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248
4327 
4328 
4329 /***********************************/
4330 /* MC_CMD_NVRAM_TEST
4331  * Test a particular NVRAM partition.
4332  */
4333 #define	MC_CMD_NVRAM_TEST  0x4c
4334 
4335 /* MC_CMD_NVRAM_TEST_IN msgrequest */
4336 #define	MC_CMD_NVRAM_TEST_IN_LEN 4
4337 #define	MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0
4338 /*            Enum values, see field(s): */
4339 /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4340 
4341 /* MC_CMD_NVRAM_TEST_OUT msgresponse */
4342 #define	MC_CMD_NVRAM_TEST_OUT_LEN 4
4343 #define	MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0
4344 #define	MC_CMD_NVRAM_TEST_PASS 0x0 /* enum */
4345 #define	MC_CMD_NVRAM_TEST_FAIL 0x1 /* enum */
4346 #define	MC_CMD_NVRAM_TEST_NOTSUPP 0x2 /* enum */
4347 
4348 
4349 /***********************************/
4350 /* MC_CMD_MRSFP_TWEAK
4351  * Read status and/or set parameters for the 'mrsfp' driver.
4352  */
4353 #define	MC_CMD_MRSFP_TWEAK  0x4d
4354 
4355 /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */
4356 #define	MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16
4357 #define	MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0
4358 #define	MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4
4359 #define	MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8
4360 #define	MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12
4361 
4362 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */
4363 #define	MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0
4364 
4365 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */
4366 #define	MC_CMD_MRSFP_TWEAK_OUT_LEN 12
4367 #define	MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0
4368 #define	MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4
4369 #define	MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8
4370 #define	MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 /* enum */
4371 #define	MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 /* enum */
4372 
4373 
4374 /***********************************/
4375 /* MC_CMD_SENSOR_SET_LIMS
4376  * Adjusts the sensor limits.
4377  */
4378 #define	MC_CMD_SENSOR_SET_LIMS  0x4e
4379 
4380 /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */
4381 #define	MC_CMD_SENSOR_SET_LIMS_IN_LEN 20
4382 #define	MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0
4383 /*            Enum values, see field(s): */
4384 /*               MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
4385 #define	MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4
4386 #define	MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8
4387 #define	MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12
4388 #define	MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16
4389 
4390 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */
4391 #define	MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0
4392 
4393 
4394 /***********************************/
4395 /* MC_CMD_GET_RESOURCE_LIMITS
4396  */
4397 #define	MC_CMD_GET_RESOURCE_LIMITS  0x4f
4398 
4399 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */
4400 #define	MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0
4401 
4402 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */
4403 #define	MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16
4404 #define	MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0
4405 #define	MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4
4406 #define	MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8
4407 #define	MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12
4408 
4409 
4410 /***********************************/
4411 /* MC_CMD_CLP
4412  * CLP support operations
4413  */
4414 #define	MC_CMD_CLP  0x56
4415 
4416 /* MC_CMD_CLP_IN msgrequest */
4417 #define	MC_CMD_CLP_IN_LEN 4
4418 #define	MC_CMD_CLP_IN_OP_OFST 0
4419 #define	MC_CMD_CLP_OP_DEFAULT 0x1 /* enum */
4420 #define	MC_CMD_CLP_OP_SET_MAC 0x2 /* enum */
4421 #define	MC_CMD_CLP_OP_GET_MAC 0x3 /* enum */
4422 #define	MC_CMD_CLP_OP_SET_BOOT 0x4 /* enum */
4423 #define	MC_CMD_CLP_OP_GET_BOOT 0x5 /* enum */
4424 
4425 /* MC_CMD_CLP_OUT msgresponse */
4426 #define	MC_CMD_CLP_OUT_LEN 0
4427 
4428 /* MC_CMD_CLP_IN_DEFAULT msgrequest */
4429 #define	MC_CMD_CLP_IN_DEFAULT_LEN 4
4430 /*            MC_CMD_CLP_IN_OP_OFST 0 */
4431 
4432 /* MC_CMD_CLP_OUT_DEFAULT msgresponse */
4433 #define	MC_CMD_CLP_OUT_DEFAULT_LEN 0
4434 
4435 /* MC_CMD_CLP_IN_SET_MAC msgrequest */
4436 #define	MC_CMD_CLP_IN_SET_MAC_LEN 12
4437 /*            MC_CMD_CLP_IN_OP_OFST 0 */
4438 #define	MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4
4439 #define	MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6
4440 #define	MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10
4441 #define	MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2
4442 
4443 /* MC_CMD_CLP_OUT_SET_MAC msgresponse */
4444 #define	MC_CMD_CLP_OUT_SET_MAC_LEN 0
4445 
4446 /* MC_CMD_CLP_IN_GET_MAC msgrequest */
4447 #define	MC_CMD_CLP_IN_GET_MAC_LEN 4
4448 /*            MC_CMD_CLP_IN_OP_OFST 0 */
4449 
4450 /* MC_CMD_CLP_OUT_GET_MAC msgresponse */
4451 #define	MC_CMD_CLP_OUT_GET_MAC_LEN 8
4452 #define	MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0
4453 #define	MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6
4454 #define	MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6
4455 #define	MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2
4456 
4457 /* MC_CMD_CLP_IN_SET_BOOT msgrequest */
4458 #define	MC_CMD_CLP_IN_SET_BOOT_LEN 5
4459 /*            MC_CMD_CLP_IN_OP_OFST 0 */
4460 #define	MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4
4461 #define	MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1
4462 
4463 /* MC_CMD_CLP_OUT_SET_BOOT msgresponse */
4464 #define	MC_CMD_CLP_OUT_SET_BOOT_LEN 0
4465 
4466 /* MC_CMD_CLP_IN_GET_BOOT msgrequest */
4467 #define	MC_CMD_CLP_IN_GET_BOOT_LEN 4
4468 /*            MC_CMD_CLP_IN_OP_OFST 0 */
4469 
4470 /* MC_CMD_CLP_OUT_GET_BOOT msgresponse */
4471 #define	MC_CMD_CLP_OUT_GET_BOOT_LEN 4
4472 #define	MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0
4473 #define	MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1
4474 #define	MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1
4475 #define	MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3
4476 
4477 /* MC_CMD_RESOURCE_SPECIFIER enum */
4478 #define	MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff /* enum */
4479 #define	MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe /* enum */
4480 
4481 
4482 /***********************************/
4483 /* MC_CMD_INIT_EVQ
4484  */
4485 #define	MC_CMD_INIT_EVQ  0x50
4486 
4487 /* MC_CMD_INIT_EVQ_IN msgrequest */
4488 #define	MC_CMD_INIT_EVQ_IN_LENMIN 36
4489 #define	MC_CMD_INIT_EVQ_IN_LENMAX 540
4490 #define	MC_CMD_INIT_EVQ_IN_LEN(num) (28+8*(num))
4491 #define	MC_CMD_INIT_EVQ_IN_SIZE_OFST 0
4492 #define	MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4
4493 #define	MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8
4494 #define	MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12
4495 #define	MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16
4496 #define	MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0
4497 #define	MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1
4498 #define	MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1
4499 #define	MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1
4500 #define	MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20
4501 #define	MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0 /* enum */
4502 #define	MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1 /* enum */
4503 #define	MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2 /* enum */
4504 #define	MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3 /* enum */
4505 #define	MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24
4506 #define	MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24
4507 #define	MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 28
4508 #define	MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8
4509 #define	MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 28
4510 #define	MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 32
4511 #define	MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1
4512 #define	MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64
4513 
4514 /* MC_CMD_INIT_EVQ_OUT msgresponse */
4515 #define	MC_CMD_INIT_EVQ_OUT_LEN 4
4516 #define	MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0
4517 
4518 /* QUEUE_CRC_MODE structuredef */
4519 #define	QUEUE_CRC_MODE_LEN 1
4520 #define	QUEUE_CRC_MODE_MODE_LBN 0
4521 #define	QUEUE_CRC_MODE_MODE_WIDTH 4
4522 #define	QUEUE_CRC_MODE_NONE  0x0 /* enum */
4523 #define	QUEUE_CRC_MODE_FCOE  0x1 /* enum */
4524 #define	QUEUE_CRC_MODE_ISCSI_HDR  0x2 /* enum */
4525 #define	QUEUE_CRC_MODE_ISCSI  0x3 /* enum */
4526 #define	QUEUE_CRC_MODE_FCOIPOE  0x4 /* enum */
4527 #define	QUEUE_CRC_MODE_MPA  0x5 /* enum */
4528 #define	QUEUE_CRC_MODE_SPARE_LBN 4
4529 #define	QUEUE_CRC_MODE_SPARE_WIDTH 4
4530 
4531 
4532 /***********************************/
4533 /* MC_CMD_INIT_RXQ
4534  */
4535 #define	MC_CMD_INIT_RXQ  0x51
4536 
4537 /* MC_CMD_INIT_RXQ_IN msgrequest */
4538 #define	MC_CMD_INIT_RXQ_IN_LENMIN 32
4539 #define	MC_CMD_INIT_RXQ_IN_LENMAX 248
4540 #define	MC_CMD_INIT_RXQ_IN_LEN(num) (24+8*(num))
4541 #define	MC_CMD_INIT_RXQ_IN_SIZE_OFST 0
4542 #define	MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4
4543 #define	MC_CMD_INIT_RXQ_IN_LABEL_OFST 8
4544 #define	MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12
4545 #define	MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16
4546 #define	MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0
4547 #define	MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1
4548 #define	MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1
4549 #define	MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1
4550 #define	MC_CMD_INIT_RXQ_IN_FLAG_PKT_EDIT_LBN 2
4551 #define	MC_CMD_INIT_RXQ_IN_FLAG_PKT_EDIT_WIDTH 1
4552 #define	MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3
4553 #define	MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4
4554 #define	MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20
4555 #define	MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 24
4556 #define	MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8
4557 #define	MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 24
4558 #define	MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 28
4559 #define	MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1
4560 #define	MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28
4561 
4562 /* MC_CMD_INIT_RXQ_OUT msgresponse */
4563 #define	MC_CMD_INIT_RXQ_OUT_LEN 0
4564 
4565 
4566 /***********************************/
4567 /* MC_CMD_INIT_TXQ
4568  */
4569 #define	MC_CMD_INIT_TXQ  0x52
4570 
4571 /* MC_CMD_INIT_TXQ_IN msgrequest */
4572 #define	MC_CMD_INIT_TXQ_IN_LENMIN 32
4573 #define	MC_CMD_INIT_TXQ_IN_LENMAX 248
4574 #define	MC_CMD_INIT_TXQ_IN_LEN(num) (24+8*(num))
4575 #define	MC_CMD_INIT_TXQ_IN_SIZE_OFST 0
4576 #define	MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4
4577 #define	MC_CMD_INIT_TXQ_IN_LABEL_OFST 8
4578 #define	MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12
4579 #define	MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16
4580 #define	MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0
4581 #define	MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1
4582 #define	MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1
4583 #define	MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1
4584 #define	MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2
4585 #define	MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
4586 #define	MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3
4587 #define	MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
4588 #define	MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4
4589 #define	MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4
4590 #define	MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20
4591 #define	MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 24
4592 #define	MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8
4593 #define	MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 24
4594 #define	MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 28
4595 #define	MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1
4596 #define	MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28
4597 
4598 /* MC_CMD_INIT_TXQ_OUT msgresponse */
4599 #define	MC_CMD_INIT_TXQ_OUT_LEN 0
4600 
4601 
4602 /***********************************/
4603 /* MC_CMD_FINI_EVQ
4604  */
4605 #define	MC_CMD_FINI_EVQ  0x55
4606 
4607 /* MC_CMD_FINI_EVQ_IN msgrequest */
4608 #define	MC_CMD_FINI_EVQ_IN_LEN 4
4609 #define	MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0
4610 
4611 /* MC_CMD_FINI_EVQ_OUT msgresponse */
4612 #define	MC_CMD_FINI_EVQ_OUT_LEN 0
4613 
4614 
4615 /***********************************/
4616 /* MC_CMD_FINI_RXQ
4617  */
4618 #define	MC_CMD_FINI_RXQ  0x56
4619 
4620 /* MC_CMD_FINI_RXQ_IN msgrequest */
4621 #define	MC_CMD_FINI_RXQ_IN_LEN 4
4622 #define	MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0
4623 
4624 /* MC_CMD_FINI_RXQ_OUT msgresponse */
4625 #define	MC_CMD_FINI_RXQ_OUT_LEN 0
4626 
4627 
4628 /***********************************/
4629 /* MC_CMD_FINI_TXQ
4630  */
4631 #define	MC_CMD_FINI_TXQ  0x57
4632 
4633 /* MC_CMD_FINI_TXQ_IN msgrequest */
4634 #define	MC_CMD_FINI_TXQ_IN_LEN 4
4635 #define	MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0
4636 
4637 /* MC_CMD_FINI_TXQ_OUT msgresponse */
4638 #define	MC_CMD_FINI_TXQ_OUT_LEN 0
4639 
4640 
4641 /***********************************/
4642 /* MC_CMD_DRIVER_EVENT
4643  */
4644 #define	MC_CMD_DRIVER_EVENT  0x5a
4645 
4646 /* MC_CMD_DRIVER_EVENT_IN msgrequest */
4647 #define	MC_CMD_DRIVER_EVENT_IN_LEN 12
4648 #define	MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0
4649 #define	MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4
4650 #define	MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8
4651 #define	MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4
4652 #define	MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8
4653 
4654 
4655 /***********************************/
4656 /* MC_CMD_PROXY_CMD
4657  */
4658 #define	MC_CMD_PROXY_CMD  0x5b
4659 
4660 /* MC_CMD_PROXY_CMD_IN msgrequest */
4661 #define	MC_CMD_PROXY_CMD_IN_LEN 4
4662 #define	MC_CMD_PROXY_CMD_IN_TARGET_OFST 0
4663 
4664 
4665 /***********************************/
4666 /* MC_CMD_ALLOC_OWNER_IDS
4667  */
4668 #define	MC_CMD_ALLOC_OWNER_IDS  0x54
4669 
4670 /* MC_CMD_ALLOC_OWNER_IDS_IN msgrequest */
4671 #define	MC_CMD_ALLOC_OWNER_IDS_IN_LEN 4
4672 #define	MC_CMD_ALLOC_OWNER_IDS_IN_NIDS_OFST 0
4673 
4674 /* MC_CMD_ALLOC_OWNER_IDS_OUT msgresponse */
4675 #define	MC_CMD_ALLOC_OWNER_IDS_OUT_LEN 12
4676 #define	MC_CMD_ALLOC_OWNER_IDS_OUT_HANDLE_OFST 0
4677 #define	MC_CMD_ALLOC_OWNER_IDS_OUT_NIDS_OFST 4
4678 #define	MC_CMD_ALLOC_OWNER_IDS_OUT_BASE_OFST 8
4679 
4680 
4681 /***********************************/
4682 /* MC_CMD_FREE_OWNER_IDS
4683  */
4684 #define	MC_CMD_FREE_OWNER_IDS  0x59
4685 
4686 /* MC_CMD_FREE_OWNER_IDS_IN msgrequest */
4687 #define	MC_CMD_FREE_OWNER_IDS_IN_LEN 4
4688 #define	MC_CMD_FREE_OWNER_IDS_IN_HANDLE_OFST 0
4689 
4690 /* MC_CMD_FREE_OWNER_IDS_OUT msgresponse */
4691 #define	MC_CMD_FREE_OWNER_IDS_OUT_LEN 0
4692 
4693 
4694 /***********************************/
4695 /* MC_CMD_ALLOC_BUFTBL_CHUNK
4696  */
4697 #define	MC_CMD_ALLOC_BUFTBL_CHUNK  0x5c
4698 
4699 /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */
4700 #define	MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8
4701 #define	MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0
4702 #define	MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4
4703 
4704 /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */
4705 #define	MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12
4706 #define	MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0
4707 #define	MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4
4708 #define	MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8
4709 
4710 
4711 /***********************************/
4712 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES
4713  */
4714 #define	MC_CMD_PROGRAM_BUFTBL_ENTRIES  0x5d
4715 
4716 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */
4717 #define	MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20
4718 #define	MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 252
4719 #define	MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num))
4720 #define	MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0
4721 #define	MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4
4722 #define	MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8
4723 #define	MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12
4724 #define	MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8
4725 #define	MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12
4726 #define	MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16
4727 #define	MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1
4728 #define	MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 30
4729 
4730 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */
4731 #define	MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0
4732 
4733 
4734 /***********************************/
4735 /* MC_CMD_FREE_BUFTBL_CHUNK
4736  */
4737 #define	MC_CMD_FREE_BUFTBL_CHUNK  0x5e
4738 
4739 /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */
4740 #define	MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4
4741 #define	MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0
4742 
4743 /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */
4744 #define	MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0
4745 
4746 
4747 /***********************************/
4748 /* MC_CMD_GET_PF_COUNT
4749  */
4750 #define	MC_CMD_GET_PF_COUNT  0x60
4751 
4752 /* MC_CMD_GET_PF_COUNT_IN msgrequest */
4753 #define	MC_CMD_GET_PF_COUNT_IN_LEN 0
4754 
4755 /* MC_CMD_GET_PF_COUNT_OUT msgresponse */
4756 #define	MC_CMD_GET_PF_COUNT_OUT_LEN 1
4757 #define	MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0
4758 #define	MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1
4759 
4760 
4761 /***********************************/
4762 /* MC_CMD_FILTER_OP
4763  */
4764 #define	MC_CMD_FILTER_OP  0x61
4765 
4766 /* MC_CMD_FILTER_OP_IN msgrequest */
4767 #define	MC_CMD_FILTER_OP_IN_LEN 100
4768 #define	MC_CMD_FILTER_OP_IN_OP_OFST 0
4769 #define	MC_CMD_FILTER_OP_IN_OP_INSERT  0x0 /* enum */
4770 #define	MC_CMD_FILTER_OP_IN_OP_REMOVE  0x1 /* enum */
4771 #define	MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE  0x2 /* enum */
4772 #define	MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE  0x3 /* enum */
4773 #define	MC_CMD_FILTER_OP_IN_HANDLE_OFST 4
4774 #define	MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 8
4775 #define	MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0
4776 #define	MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1
4777 #define	MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1
4778 #define	MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1
4779 #define	MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2
4780 #define	MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1
4781 #define	MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3
4782 #define	MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1
4783 #define	MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4
4784 #define	MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1
4785 #define	MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5
4786 #define	MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1
4787 #define	MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6
4788 #define	MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1
4789 #define	MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7
4790 #define	MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1
4791 #define	MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8
4792 #define	MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1
4793 #define	MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9
4794 #define	MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1
4795 #define	MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10
4796 #define	MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1
4797 #define	MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11
4798 #define	MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1
4799 #define	MC_CMD_FILTER_OP_IN_RX_DEST_OFST 12
4800 #define	MC_CMD_FILTER_OP_IN_RX_DEST_DROP  0x0 /* enum */
4801 #define	MC_CMD_FILTER_OP_IN_RX_DEST_HOST  0x1 /* enum */
4802 #define	MC_CMD_FILTER_OP_IN_RX_DEST_MC  0x2 /* enum */
4803 #define	MC_CMD_FILTER_OP_IN_RX_DEST_TX0  0x3 /* enum */
4804 #define	MC_CMD_FILTER_OP_IN_RX_DEST_TX1  0x4 /* enum */
4805 #define	MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 16
4806 #define	MC_CMD_FILTER_OP_IN_RX_FLAGS_OFST 20
4807 #define	MC_CMD_FILTER_OP_IN_RX_FLAG_RSS_LBN 0
4808 #define	MC_CMD_FILTER_OP_IN_RX_FLAG_RSS_WIDTH 1
4809 #define	MC_CMD_FILTER_OP_IN_RSS_CONTEXT_OFST 24
4810 #define	MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 28
4811 #define	MC_CMD_FILTER_OP_IN_TX_DEST_OFST 32
4812 #define	MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0
4813 #define	MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1
4814 #define	MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1
4815 #define	MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1
4816 #define	MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 36
4817 #define	MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6
4818 #define	MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 42
4819 #define	MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2
4820 #define	MC_CMD_FILTER_OP_IN_DST_MAC_OFST 44
4821 #define	MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6
4822 #define	MC_CMD_FILTER_OP_IN_DST_PORT_OFST 50
4823 #define	MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2
4824 #define	MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 52
4825 #define	MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2
4826 #define	MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 54
4827 #define	MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2
4828 #define	MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 56
4829 #define	MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2
4830 #define	MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 58
4831 #define	MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2
4832 #define	MC_CMD_FILTER_OP_IN_FWDEF0_OFST 60
4833 #define	MC_CMD_FILTER_OP_IN_FWDEF1_OFST 64
4834 #define	MC_CMD_FILTER_OP_IN_SRC_IP_OFST 68
4835 #define	MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16
4836 #define	MC_CMD_FILTER_OP_IN_DST_IP_OFST 84
4837 #define	MC_CMD_FILTER_OP_IN_DST_IP_LEN 16
4838 
4839 /* MC_CMD_FILTER_OP_OUT msgresponse */
4840 #define	MC_CMD_FILTER_OP_OUT_LEN 8
4841 #define	MC_CMD_FILTER_OP_OUT_OP_OFST 0
4842 #define	MC_CMD_FILTER_OP_OUT_OP_INSERT  0x0 /* enum */
4843 #define	MC_CMD_FILTER_OP_OUT_OP_REMOVE  0x1 /* enum */
4844 #define	MC_CMD_FILTER_OP_OUT_OP_SUBSCRIBE  0x2 /* enum */
4845 #define	MC_CMD_FILTER_OP_OUT_OP_UNSUBSCRIBE  0x3 /* enum */
4846 #define	MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4
4847 
4848 
4849 /***********************************/
4850 /* MC_CMD_SET_PF_COUNT
4851  */
4852 #define	MC_CMD_SET_PF_COUNT  0x62
4853 
4854 /* MC_CMD_SET_PF_COUNT_IN msgrequest */
4855 #define	MC_CMD_SET_PF_COUNT_IN_LEN 4
4856 #define	MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0
4857 
4858 /* MC_CMD_SET_PF_COUNT_OUT msgresponse */
4859 #define	MC_CMD_SET_PF_COUNT_OUT_LEN 0
4860 
4861 
4862 /***********************************/
4863 /* MC_CMD_GET_PORT_ASSIGNMENT
4864  */
4865 #define	MC_CMD_GET_PORT_ASSIGNMENT  0x63
4866 
4867 /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */
4868 #define	MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0
4869 
4870 /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */
4871 #define	MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4
4872 #define	MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0
4873 
4874 
4875 /***********************************/
4876 /* MC_CMD_SET_PORT_ASSIGNMENT
4877  */
4878 #define	MC_CMD_SET_PORT_ASSIGNMENT  0x64
4879 
4880 /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */
4881 #define	MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4
4882 #define	MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0
4883 
4884 /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */
4885 #define	MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0
4886 
4887 
4888 /***********************************/
4889 /* MC_CMD_ALLOC_VIS
4890  */
4891 #define	MC_CMD_ALLOC_VIS  0x65
4892 
4893 /* MC_CMD_ALLOC_VIS_IN msgrequest */
4894 #define	MC_CMD_ALLOC_VIS_IN_LEN 4
4895 #define	MC_CMD_ALLOC_VIS_IN_VI_COUNT_OFST 0
4896 
4897 /* MC_CMD_ALLOC_VIS_OUT msgresponse */
4898 #define	MC_CMD_ALLOC_VIS_OUT_LEN 0
4899 
4900 
4901 /***********************************/
4902 /* MC_CMD_FREE_VIS
4903  */
4904 #define	MC_CMD_FREE_VIS  0x66
4905 
4906 /* MC_CMD_FREE_VIS_IN msgrequest */
4907 #define	MC_CMD_FREE_VIS_IN_LEN 0
4908 
4909 /* MC_CMD_FREE_VIS_OUT msgresponse */
4910 #define	MC_CMD_FREE_VIS_OUT_LEN 0
4911 
4912 
4913 /***********************************/
4914 /* MC_CMD_GET_SRIOV_CFG
4915  */
4916 #define	MC_CMD_GET_SRIOV_CFG  0x67
4917 
4918 /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */
4919 #define	MC_CMD_GET_SRIOV_CFG_IN_LEN 0
4920 
4921 /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */
4922 #define	MC_CMD_GET_SRIOV_CFG_OUT_LEN 20
4923 #define	MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0
4924 #define	MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4
4925 #define	MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8
4926 #define	MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0
4927 #define	MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1
4928 #define	MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12
4929 #define	MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16
4930 
4931 
4932 /***********************************/
4933 /* MC_CMD_SET_SRIOV_CFG
4934  */
4935 #define	MC_CMD_SET_SRIOV_CFG  0x68
4936 
4937 /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */
4938 #define	MC_CMD_SET_SRIOV_CFG_IN_LEN 20
4939 #define	MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0
4940 #define	MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4
4941 #define	MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8
4942 #define	MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0
4943 #define	MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1
4944 #define	MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12
4945 #define	MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16
4946 
4947 /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */
4948 #define	MC_CMD_SET_SRIOV_CFG_OUT_LEN 0
4949 
4950 
4951 /***********************************/
4952 /* MC_CMD_GET_VI_COUNT
4953  */
4954 #define	MC_CMD_GET_VI_COUNT  0x69
4955 
4956 /* MC_CMD_GET_VI_COUNT_IN msgrequest */
4957 #define	MC_CMD_GET_VI_COUNT_IN_LEN 0
4958 
4959 /* MC_CMD_GET_VI_COUNT_OUT msgresponse */
4960 #define	MC_CMD_GET_VI_COUNT_OUT_LEN 4
4961 #define	MC_CMD_GET_VI_COUNT_OUT_VI_COUNT_OFST 0
4962 
4963 
4964 /***********************************/
4965 /* MC_CMD_GET_VECTOR_CFG
4966  */
4967 #define	MC_CMD_GET_VECTOR_CFG  0x70
4968 
4969 /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */
4970 #define	MC_CMD_GET_VECTOR_CFG_IN_LEN 0
4971 
4972 /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */
4973 #define	MC_CMD_GET_VECTOR_CFG_OUT_LEN 12
4974 #define	MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0
4975 #define	MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4
4976 #define	MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8
4977 
4978 
4979 /***********************************/
4980 /* MC_CMD_SET_VECTOR_CFG
4981  */
4982 #define	MC_CMD_SET_VECTOR_CFG  0x71
4983 
4984 /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */
4985 #define	MC_CMD_SET_VECTOR_CFG_IN_LEN 12
4986 #define	MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0
4987 #define	MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4
4988 #define	MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8
4989 
4990 /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */
4991 #define	MC_CMD_SET_VECTOR_CFG_OUT_LEN 0
4992 
4993 
4994 /***********************************/
4995 /* MC_CMD_ALLOC_PIOBUF
4996  */
4997 #define	MC_CMD_ALLOC_PIOBUF  0x72
4998 
4999 /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */
5000 #define	MC_CMD_ALLOC_PIOBUF_IN_LEN 0
5001 
5002 /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */
5003 #define	MC_CMD_ALLOC_PIOBUF_OUT_LEN 4
5004 #define	MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0
5005 
5006 
5007 /***********************************/
5008 /* MC_CMD_FREE_PIOBUF
5009  */
5010 #define	MC_CMD_FREE_PIOBUF  0x73
5011 
5012 /* MC_CMD_FREE_PIOBUF_IN msgrequest */
5013 #define	MC_CMD_FREE_PIOBUF_IN_LEN 4
5014 #define	MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
5015 
5016 /* MC_CMD_FREE_PIOBUF_OUT msgresponse */
5017 #define	MC_CMD_FREE_PIOBUF_OUT_LEN 0
5018 
5019 
5020 /***********************************/
5021 /* MC_CMD_V2_EXTN
5022  */
5023 #define	MC_CMD_V2_EXTN  0x7f
5024 
5025 /* MC_CMD_V2_EXTN_IN msgrequest */
5026 #define	MC_CMD_V2_EXTN_IN_LEN 4
5027 #define	MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0
5028 #define	MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15
5029 #define	MC_CMD_V2_EXTN_IN_UNUSED_LBN 15
5030 #define	MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1
5031 #define	MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16
5032 #define	MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10
5033 #define	MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26
5034 #define	MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 6
5035 
5036 
5037 /***********************************/
5038 /* MC_CMD_TCM_BUCKET_ALLOC
5039  */
5040 #define	MC_CMD_TCM_BUCKET_ALLOC  0x80
5041 
5042 /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */
5043 #define	MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0
5044 
5045 /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */
5046 #define	MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4
5047 #define	MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0
5048 
5049 
5050 /***********************************/
5051 /* MC_CMD_TCM_BUCKET_FREE
5052  */
5053 #define	MC_CMD_TCM_BUCKET_FREE  0x81
5054 
5055 /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */
5056 #define	MC_CMD_TCM_BUCKET_FREE_IN_LEN 4
5057 #define	MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0
5058 
5059 /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */
5060 #define	MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0
5061 
5062 
5063 /***********************************/
5064 /* MC_CMD_TCM_BUCKET_INIT
5065  */
5066 #define	MC_CMD_TCM_BUCKET_INIT  0x82
5067 
5068 /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */
5069 #define	MC_CMD_TCM_BUCKET_INIT_IN_LEN 8
5070 #define	MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0
5071 #define	MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4
5072 
5073 /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */
5074 #define	MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0
5075 
5076 
5077 /***********************************/
5078 /* MC_CMD_TCM_TXQ_INIT
5079  */
5080 #define	MC_CMD_TCM_TXQ_INIT  0x83
5081 
5082 /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */
5083 #define	MC_CMD_TCM_TXQ_INIT_IN_LEN 28
5084 #define	MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0
5085 #define	MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4
5086 #define	MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8
5087 #define	MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12
5088 #define	MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16
5089 #define	MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20
5090 #define	MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24
5091 
5092 /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */
5093 #define	MC_CMD_TCM_TXQ_INIT_OUT_LEN 0
5094 
5095 #endif /* _SIENA_MC_DRIVER_PCOL_H */
5096