1 /*- 2 * Copyright (c) 2015-2016 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 */ 30 31 #include <sys/cdefs.h> 32 #include "efx.h" 33 #include "efx_impl.h" 34 35 #if EFSYS_OPT_MEDFORD 36 37 static __checkReturn efx_rc_t 38 medford_nic_get_required_pcie_bandwidth( 39 __in efx_nic_t *enp, 40 __out uint32_t *bandwidth_mbpsp) 41 { 42 uint32_t bandwidth; 43 efx_rc_t rc; 44 45 if ((rc = ef10_nic_get_port_mode_bandwidth(enp, 46 &bandwidth)) != 0) 47 goto fail1; 48 49 *bandwidth_mbpsp = bandwidth; 50 51 return (0); 52 53 fail1: 54 EFSYS_PROBE1(fail1, efx_rc_t, rc); 55 56 return (rc); 57 } 58 59 __checkReturn efx_rc_t 60 medford_board_cfg( 61 __in efx_nic_t *enp) 62 { 63 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 64 uint32_t sysclk, dpcpu_clk; 65 uint32_t end_padding; 66 uint32_t bandwidth; 67 efx_rc_t rc; 68 69 /* 70 * Enable firmware workarounds for hardware errata. 71 * Expected responses are: 72 * - 0 (zero): 73 * Success: workaround enabled or disabled as requested. 74 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP): 75 * Firmware does not support the MC_CMD_WORKAROUND request. 76 * (assume that the workaround is not supported). 77 * - MC_CMD_ERR_ENOENT (reported as ENOENT): 78 * Firmware does not support the requested workaround. 79 * - MC_CMD_ERR_EPERM (reported as EACCES): 80 * Unprivileged function cannot enable/disable workarounds. 81 * 82 * See efx_mcdi_request_errcode() for MCDI error translations. 83 */ 84 85 if (EFX_PCI_FUNCTION_IS_VF(encp)) { 86 /* 87 * Interrupt testing does not work for VFs. See bug50084 and 88 * bug71432 comment 21. 89 */ 90 encp->enc_bug41750_workaround = B_TRUE; 91 } 92 93 /* Chained multicast is always enabled on Medford */ 94 encp->enc_bug26807_workaround = B_TRUE; 95 96 /* 97 * If the bug61265 workaround is enabled, then interrupt holdoff timers 98 * cannot be controlled by timer table writes, so MCDI must be used 99 * (timer table writes can still be used for wakeup timers). 100 */ 101 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE, 102 NULL); 103 if ((rc == 0) || (rc == EACCES)) 104 encp->enc_bug61265_workaround = B_TRUE; 105 else if ((rc == ENOTSUP) || (rc == ENOENT)) 106 encp->enc_bug61265_workaround = B_FALSE; 107 else 108 goto fail1; 109 110 /* Checksums for TSO sends can be incorrect on Medford. */ 111 encp->enc_bug61297_workaround = B_TRUE; 112 113 /* Get clock frequencies (in MHz). */ 114 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0) 115 goto fail2; 116 117 /* 118 * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for 119 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units. 120 */ 121 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */ 122 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << 123 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000; 124 125 /* Alignment for receive packet DMA buffers */ 126 encp->enc_rx_buf_align_start = 1; 127 128 /* Get the RX DMA end padding alignment configuration */ 129 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) { 130 if (rc != EACCES) 131 goto fail3; 132 133 /* Assume largest tail padding size supported by hardware */ 134 end_padding = 256; 135 } 136 encp->enc_rx_buf_align_end = end_padding; 137 138 /* 139 * The maximum supported transmit queue size is 2048. TXQs with 4096 140 * descriptors are not supported as the top bit is used for vfifo 141 * stuffing. 142 */ 143 encp->enc_txq_max_ndescs = 2048; 144 145 EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS); 146 encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS; 147 encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE; 148 encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE; 149 150 /* 151 * Medford stores a single global copy of VPD, not per-PF as on 152 * Huntington. 153 */ 154 encp->enc_vpd_is_global = B_TRUE; 155 156 rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth); 157 if (rc != 0) 158 goto fail4; 159 encp->enc_required_pcie_bandwidth_mbps = bandwidth; 160 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3; 161 162 return (0); 163 164 fail4: 165 EFSYS_PROBE(fail4); 166 fail3: 167 EFSYS_PROBE(fail3); 168 fail2: 169 EFSYS_PROBE(fail2); 170 fail1: 171 EFSYS_PROBE1(fail1, efx_rc_t, rc); 172 173 return (rc); 174 } 175 176 #endif /* EFSYS_OPT_MEDFORD */ 177