1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2009-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 */ 32 33 #include <sys/cdefs.h> 34 #include "efx.h" 35 #include "efx_impl.h" 36 37 #if EFSYS_OPT_SIENA 38 39 static void 40 siena_phy_decode_cap( 41 __in uint32_t mcdi_cap, 42 __out uint32_t *maskp) 43 { 44 uint32_t mask; 45 46 mask = 0; 47 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10HDX_LBN)) 48 mask |= (1 << EFX_PHY_CAP_10HDX); 49 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10FDX_LBN)) 50 mask |= (1 << EFX_PHY_CAP_10FDX); 51 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100HDX_LBN)) 52 mask |= (1 << EFX_PHY_CAP_100HDX); 53 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100FDX_LBN)) 54 mask |= (1 << EFX_PHY_CAP_100FDX); 55 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000HDX_LBN)) 56 mask |= (1 << EFX_PHY_CAP_1000HDX); 57 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000FDX_LBN)) 58 mask |= (1 << EFX_PHY_CAP_1000FDX); 59 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10000FDX_LBN)) 60 mask |= (1 << EFX_PHY_CAP_10000FDX); 61 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_PAUSE_LBN)) 62 mask |= (1 << EFX_PHY_CAP_PAUSE); 63 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_ASYM_LBN)) 64 mask |= (1 << EFX_PHY_CAP_ASYM); 65 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_AN_LBN)) 66 mask |= (1 << EFX_PHY_CAP_AN); 67 68 *maskp = mask; 69 } 70 71 static void 72 siena_phy_decode_link_mode( 73 __in efx_nic_t *enp, 74 __in uint32_t link_flags, 75 __in unsigned int speed, 76 __in unsigned int fcntl, 77 __out efx_link_mode_t *link_modep, 78 __out unsigned int *fcntlp) 79 { 80 boolean_t fd = !!(link_flags & 81 (1 << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN)); 82 boolean_t up = !!(link_flags & 83 (1 << MC_CMD_GET_LINK_OUT_LINK_UP_LBN)); 84 85 _NOTE(ARGUNUSED(enp)) 86 87 if (!up) 88 *link_modep = EFX_LINK_DOWN; 89 else if (speed == 10000 && fd) 90 *link_modep = EFX_LINK_10000FDX; 91 else if (speed == 1000) 92 *link_modep = fd ? EFX_LINK_1000FDX : EFX_LINK_1000HDX; 93 else if (speed == 100) 94 *link_modep = fd ? EFX_LINK_100FDX : EFX_LINK_100HDX; 95 else if (speed == 10) 96 *link_modep = fd ? EFX_LINK_10FDX : EFX_LINK_10HDX; 97 else 98 *link_modep = EFX_LINK_UNKNOWN; 99 100 if (fcntl == MC_CMD_FCNTL_OFF) 101 *fcntlp = 0; 102 else if (fcntl == MC_CMD_FCNTL_RESPOND) 103 *fcntlp = EFX_FCNTL_RESPOND; 104 else if (fcntl == MC_CMD_FCNTL_BIDIR) 105 *fcntlp = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE; 106 else { 107 EFSYS_PROBE1(mc_pcol_error, int, fcntl); 108 *fcntlp = 0; 109 } 110 } 111 112 void 113 siena_phy_link_ev( 114 __in efx_nic_t *enp, 115 __in efx_qword_t *eqp, 116 __out efx_link_mode_t *link_modep) 117 { 118 efx_port_t *epp = &(enp->en_port); 119 unsigned int link_flags; 120 unsigned int speed; 121 unsigned int fcntl; 122 efx_link_mode_t link_mode; 123 uint32_t lp_cap_mask; 124 125 /* 126 * Convert the LINKCHANGE speed enumeration into mbit/s, in the 127 * same way as GET_LINK encodes the speed 128 */ 129 switch (MCDI_EV_FIELD(eqp, LINKCHANGE_SPEED)) { 130 case MCDI_EVENT_LINKCHANGE_SPEED_100M: 131 speed = 100; 132 break; 133 case MCDI_EVENT_LINKCHANGE_SPEED_1G: 134 speed = 1000; 135 break; 136 case MCDI_EVENT_LINKCHANGE_SPEED_10G: 137 speed = 10000; 138 break; 139 default: 140 speed = 0; 141 break; 142 } 143 144 link_flags = MCDI_EV_FIELD(eqp, LINKCHANGE_LINK_FLAGS); 145 siena_phy_decode_link_mode(enp, link_flags, speed, 146 MCDI_EV_FIELD(eqp, LINKCHANGE_FCNTL), 147 &link_mode, &fcntl); 148 siena_phy_decode_cap(MCDI_EV_FIELD(eqp, LINKCHANGE_LP_CAP), 149 &lp_cap_mask); 150 151 /* 152 * It's safe to update ep_lp_cap_mask without the driver's port lock 153 * because presumably any concurrently running efx_port_poll() is 154 * only going to arrive at the same value. 155 * 156 * ep_fcntl has two meanings. It's either the link common fcntl 157 * (if the PHY supports AN), or it's the forced link state. If 158 * the former, it's safe to update the value for the same reason as 159 * for ep_lp_cap_mask. If the latter, then just ignore the value, 160 * because we can race with efx_mac_fcntl_set(). 161 */ 162 epp->ep_lp_cap_mask = lp_cap_mask; 163 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN)) 164 epp->ep_fcntl = fcntl; 165 166 *link_modep = link_mode; 167 } 168 169 __checkReturn efx_rc_t 170 siena_phy_power( 171 __in efx_nic_t *enp, 172 __in boolean_t power) 173 { 174 efx_rc_t rc; 175 176 if (!power) 177 return (0); 178 179 /* Check if the PHY is a zombie */ 180 if ((rc = siena_phy_verify(enp)) != 0) 181 goto fail1; 182 183 enp->en_reset_flags |= EFX_RESET_PHY; 184 185 return (0); 186 187 fail1: 188 EFSYS_PROBE1(fail1, efx_rc_t, rc); 189 190 return (rc); 191 } 192 193 __checkReturn efx_rc_t 194 siena_phy_get_link( 195 __in efx_nic_t *enp, 196 __out siena_link_state_t *slsp) 197 { 198 efx_mcdi_req_t req; 199 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_LINK_IN_LEN, 200 MC_CMD_GET_LINK_OUT_LEN); 201 efx_rc_t rc; 202 203 req.emr_cmd = MC_CMD_GET_LINK; 204 req.emr_in_buf = payload; 205 req.emr_in_length = MC_CMD_GET_LINK_IN_LEN; 206 req.emr_out_buf = payload; 207 req.emr_out_length = MC_CMD_GET_LINK_OUT_LEN; 208 209 efx_mcdi_execute(enp, &req); 210 211 if (req.emr_rc != 0) { 212 rc = req.emr_rc; 213 goto fail1; 214 } 215 216 if (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_LEN) { 217 rc = EMSGSIZE; 218 goto fail2; 219 } 220 221 siena_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_CAP), 222 &slsp->sls_adv_cap_mask); 223 siena_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_LP_CAP), 224 &slsp->sls_lp_cap_mask); 225 226 siena_phy_decode_link_mode(enp, MCDI_OUT_DWORD(req, GET_LINK_OUT_FLAGS), 227 MCDI_OUT_DWORD(req, GET_LINK_OUT_LINK_SPEED), 228 MCDI_OUT_DWORD(req, GET_LINK_OUT_FCNTL), 229 &slsp->sls_link_mode, &slsp->sls_fcntl); 230 231 #if EFSYS_OPT_LOOPBACK 232 /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespace agree */ 233 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_NONE == EFX_LOOPBACK_OFF); 234 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_DATA == EFX_LOOPBACK_DATA); 235 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMAC == EFX_LOOPBACK_GMAC); 236 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII == EFX_LOOPBACK_XGMII); 237 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGXS == EFX_LOOPBACK_XGXS); 238 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI == EFX_LOOPBACK_XAUI); 239 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII == EFX_LOOPBACK_GMII); 240 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII == EFX_LOOPBACK_SGMII); 241 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGBR == EFX_LOOPBACK_XGBR); 242 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI == EFX_LOOPBACK_XFI); 243 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_FAR == EFX_LOOPBACK_XAUI_FAR); 244 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_FAR == EFX_LOOPBACK_GMII_FAR); 245 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII_FAR == EFX_LOOPBACK_SGMII_FAR); 246 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_FAR == EFX_LOOPBACK_XFI_FAR); 247 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GPHY == EFX_LOOPBACK_GPHY); 248 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS == EFX_LOOPBACK_PHY_XS); 249 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PCS == EFX_LOOPBACK_PCS); 250 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMAPMD == EFX_LOOPBACK_PMA_PMD); 251 252 slsp->sls_loopback = MCDI_OUT_DWORD(req, GET_LINK_OUT_LOOPBACK_MODE); 253 #endif /* EFSYS_OPT_LOOPBACK */ 254 255 slsp->sls_mac_up = MCDI_OUT_DWORD(req, GET_LINK_OUT_MAC_FAULT) == 0; 256 257 return (0); 258 259 fail2: 260 EFSYS_PROBE(fail2); 261 fail1: 262 EFSYS_PROBE1(fail1, efx_rc_t, rc); 263 264 return (rc); 265 } 266 267 __checkReturn efx_rc_t 268 siena_phy_reconfigure( 269 __in efx_nic_t *enp) 270 { 271 efx_port_t *epp = &(enp->en_port); 272 efx_mcdi_req_t req; 273 EFX_MCDI_DECLARE_BUF(payload, 274 MAX(MC_CMD_SET_ID_LED_IN_LEN, MC_CMD_SET_LINK_IN_LEN), 275 MAX(MC_CMD_SET_ID_LED_OUT_LEN, MC_CMD_SET_LINK_OUT_LEN)); 276 uint32_t cap_mask; 277 #if EFSYS_OPT_PHY_LED_CONTROL 278 unsigned int led_mode; 279 #endif 280 unsigned int speed; 281 efx_rc_t rc; 282 283 req.emr_cmd = MC_CMD_SET_LINK; 284 req.emr_in_buf = payload; 285 req.emr_in_length = MC_CMD_SET_LINK_IN_LEN; 286 req.emr_out_buf = payload; 287 req.emr_out_length = MC_CMD_SET_LINK_OUT_LEN; 288 289 cap_mask = epp->ep_adv_cap_mask; 290 MCDI_IN_POPULATE_DWORD_10(req, SET_LINK_IN_CAP, 291 PHY_CAP_10HDX, (cap_mask >> EFX_PHY_CAP_10HDX) & 0x1, 292 PHY_CAP_10FDX, (cap_mask >> EFX_PHY_CAP_10FDX) & 0x1, 293 PHY_CAP_100HDX, (cap_mask >> EFX_PHY_CAP_100HDX) & 0x1, 294 PHY_CAP_100FDX, (cap_mask >> EFX_PHY_CAP_100FDX) & 0x1, 295 PHY_CAP_1000HDX, (cap_mask >> EFX_PHY_CAP_1000HDX) & 0x1, 296 PHY_CAP_1000FDX, (cap_mask >> EFX_PHY_CAP_1000FDX) & 0x1, 297 PHY_CAP_10000FDX, (cap_mask >> EFX_PHY_CAP_10000FDX) & 0x1, 298 PHY_CAP_PAUSE, (cap_mask >> EFX_PHY_CAP_PAUSE) & 0x1, 299 PHY_CAP_ASYM, (cap_mask >> EFX_PHY_CAP_ASYM) & 0x1, 300 PHY_CAP_AN, (cap_mask >> EFX_PHY_CAP_AN) & 0x1); 301 302 #if EFSYS_OPT_LOOPBACK 303 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE, 304 epp->ep_loopback_type); 305 switch (epp->ep_loopback_link_mode) { 306 case EFX_LINK_100FDX: 307 speed = 100; 308 break; 309 case EFX_LINK_1000FDX: 310 speed = 1000; 311 break; 312 case EFX_LINK_10000FDX: 313 speed = 10000; 314 break; 315 default: 316 speed = 0; 317 } 318 #else 319 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE, MC_CMD_LOOPBACK_NONE); 320 speed = 0; 321 #endif /* EFSYS_OPT_LOOPBACK */ 322 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_SPEED, speed); 323 324 #if EFSYS_OPT_PHY_FLAGS 325 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, epp->ep_phy_flags); 326 #else 327 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, 0); 328 #endif /* EFSYS_OPT_PHY_FLAGS */ 329 330 efx_mcdi_execute(enp, &req); 331 332 if (req.emr_rc != 0) { 333 rc = req.emr_rc; 334 goto fail1; 335 } 336 337 /* And set the blink mode */ 338 (void) memset(payload, 0, sizeof (payload)); 339 req.emr_cmd = MC_CMD_SET_ID_LED; 340 req.emr_in_buf = payload; 341 req.emr_in_length = MC_CMD_SET_ID_LED_IN_LEN; 342 req.emr_out_buf = payload; 343 req.emr_out_length = MC_CMD_SET_ID_LED_OUT_LEN; 344 345 #if EFSYS_OPT_PHY_LED_CONTROL 346 switch (epp->ep_phy_led_mode) { 347 case EFX_PHY_LED_DEFAULT: 348 led_mode = MC_CMD_LED_DEFAULT; 349 break; 350 case EFX_PHY_LED_OFF: 351 led_mode = MC_CMD_LED_OFF; 352 break; 353 case EFX_PHY_LED_ON: 354 led_mode = MC_CMD_LED_ON; 355 break; 356 default: 357 EFSYS_ASSERT(0); 358 led_mode = MC_CMD_LED_DEFAULT; 359 } 360 361 MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, led_mode); 362 #else 363 MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, MC_CMD_LED_DEFAULT); 364 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 365 366 efx_mcdi_execute(enp, &req); 367 368 if (req.emr_rc != 0) { 369 rc = req.emr_rc; 370 goto fail2; 371 } 372 373 return (0); 374 375 fail2: 376 EFSYS_PROBE(fail2); 377 fail1: 378 EFSYS_PROBE1(fail1, efx_rc_t, rc); 379 380 return (rc); 381 } 382 383 __checkReturn efx_rc_t 384 siena_phy_verify( 385 __in efx_nic_t *enp) 386 { 387 efx_mcdi_req_t req; 388 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PHY_STATE_IN_LEN, 389 MC_CMD_GET_PHY_STATE_OUT_LEN); 390 uint32_t state; 391 efx_rc_t rc; 392 393 req.emr_cmd = MC_CMD_GET_PHY_STATE; 394 req.emr_in_buf = payload; 395 req.emr_in_length = MC_CMD_GET_PHY_STATE_IN_LEN; 396 req.emr_out_buf = payload; 397 req.emr_out_length = MC_CMD_GET_PHY_STATE_OUT_LEN; 398 399 efx_mcdi_execute(enp, &req); 400 401 if (req.emr_rc != 0) { 402 rc = req.emr_rc; 403 goto fail1; 404 } 405 406 if (req.emr_out_length_used < MC_CMD_GET_PHY_STATE_OUT_LEN) { 407 rc = EMSGSIZE; 408 goto fail2; 409 } 410 411 state = MCDI_OUT_DWORD(req, GET_PHY_STATE_OUT_STATE); 412 if (state != MC_CMD_PHY_STATE_OK) { 413 if (state != MC_CMD_PHY_STATE_ZOMBIE) 414 EFSYS_PROBE1(mc_pcol_error, int, state); 415 rc = ENOTACTIVE; 416 goto fail3; 417 } 418 419 return (0); 420 421 fail3: 422 EFSYS_PROBE(fail3); 423 fail2: 424 EFSYS_PROBE(fail2); 425 fail1: 426 EFSYS_PROBE1(fail1, efx_rc_t, rc); 427 428 return (rc); 429 } 430 431 __checkReturn efx_rc_t 432 siena_phy_oui_get( 433 __in efx_nic_t *enp, 434 __out uint32_t *ouip) 435 { 436 _NOTE(ARGUNUSED(enp, ouip)) 437 438 return (ENOTSUP); 439 } 440 441 #if EFSYS_OPT_PHY_STATS 442 443 #define SIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat, \ 444 _mc_record, _efx_record) \ 445 if ((_vmask) & (1ULL << (_mc_record))) { \ 446 (_smask) |= (1ULL << (_efx_record)); \ 447 if ((_stat) != NULL && !EFSYS_MEM_IS_NULL(_esmp)) { \ 448 efx_dword_t dword; \ 449 EFSYS_MEM_READD(_esmp, (_mc_record) * 4, &dword);\ 450 (_stat)[_efx_record] = \ 451 EFX_DWORD_FIELD(dword, EFX_DWORD_0); \ 452 } \ 453 } 454 455 #define SIENA_SIMPLE_STAT_SET2(_vmask, _esmp, _smask, _stat, _record) \ 456 SIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat, \ 457 MC_CMD_ ## _record, \ 458 EFX_PHY_STAT_ ## _record) 459 460 void 461 siena_phy_decode_stats( 462 __in efx_nic_t *enp, 463 __in uint32_t vmask, 464 __in_opt efsys_mem_t *esmp, 465 __out_opt uint64_t *smaskp, 466 __inout_ecount_opt(EFX_PHY_NSTATS) uint32_t *stat) 467 { 468 uint64_t smask = 0; 469 470 _NOTE(ARGUNUSED(enp)) 471 472 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, OUI); 473 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_LINK_UP); 474 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_RX_FAULT); 475 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_TX_FAULT); 476 477 if (vmask & (1 << MC_CMD_PMA_PMD_SIGNAL)) { 478 smask |= ((1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_A) | 479 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_B) | 480 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_C) | 481 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_D)); 482 if (stat != NULL && esmp != NULL && !EFSYS_MEM_IS_NULL(esmp)) { 483 efx_dword_t dword; 484 uint32_t sig; 485 EFSYS_MEM_READD(esmp, 4 * MC_CMD_PMA_PMD_SIGNAL, 486 &dword); 487 sig = EFX_DWORD_FIELD(dword, EFX_DWORD_0); 488 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_A] = (sig >> 1) & 1; 489 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_B] = (sig >> 2) & 1; 490 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_C] = (sig >> 3) & 1; 491 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_D] = (sig >> 4) & 1; 492 } 493 } 494 495 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_A, 496 EFX_PHY_STAT_SNR_A); 497 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_B, 498 EFX_PHY_STAT_SNR_B); 499 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_C, 500 EFX_PHY_STAT_SNR_C); 501 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_D, 502 EFX_PHY_STAT_SNR_D); 503 504 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_LINK_UP); 505 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_RX_FAULT); 506 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_TX_FAULT); 507 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BER); 508 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BLOCK_ERRORS); 509 510 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_LINK_UP, 511 EFX_PHY_STAT_PHY_XS_LINK_UP); 512 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_RX_FAULT, 513 EFX_PHY_STAT_PHY_XS_RX_FAULT); 514 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_TX_FAULT, 515 EFX_PHY_STAT_PHY_XS_TX_FAULT); 516 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_ALIGN, 517 EFX_PHY_STAT_PHY_XS_ALIGN); 518 519 if (vmask & (1 << MC_CMD_PHYXS_SYNC)) { 520 smask |= ((1 << EFX_PHY_STAT_PHY_XS_SYNC_A) | 521 (1 << EFX_PHY_STAT_PHY_XS_SYNC_B) | 522 (1 << EFX_PHY_STAT_PHY_XS_SYNC_C) | 523 (1 << EFX_PHY_STAT_PHY_XS_SYNC_D)); 524 if (stat != NULL && !EFSYS_MEM_IS_NULL(esmp)) { 525 efx_dword_t dword; 526 uint32_t sync; 527 EFSYS_MEM_READD(esmp, 4 * MC_CMD_PHYXS_SYNC, &dword); 528 sync = EFX_DWORD_FIELD(dword, EFX_DWORD_0); 529 stat[EFX_PHY_STAT_PHY_XS_SYNC_A] = (sync >> 0) & 1; 530 stat[EFX_PHY_STAT_PHY_XS_SYNC_B] = (sync >> 1) & 1; 531 stat[EFX_PHY_STAT_PHY_XS_SYNC_C] = (sync >> 2) & 1; 532 stat[EFX_PHY_STAT_PHY_XS_SYNC_D] = (sync >> 3) & 1; 533 } 534 } 535 536 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_LINK_UP); 537 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_COMPLETE); 538 539 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_CL22_LINK_UP, 540 EFX_PHY_STAT_CL22EXT_LINK_UP); 541 542 if (smaskp != NULL) 543 *smaskp = smask; 544 } 545 546 __checkReturn efx_rc_t 547 siena_phy_stats_update( 548 __in efx_nic_t *enp, 549 __in efsys_mem_t *esmp, 550 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat) 551 { 552 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 553 uint32_t vmask = encp->enc_mcdi_phy_stat_mask; 554 uint64_t smask; 555 efx_mcdi_req_t req; 556 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_PHY_STATS_IN_LEN, 557 MC_CMD_PHY_STATS_OUT_DMA_LEN); 558 efx_rc_t rc; 559 560 if ((esmp == NULL) || (EFSYS_MEM_SIZE(esmp) < EFX_PHY_STATS_SIZE)) { 561 rc = EINVAL; 562 goto fail1; 563 } 564 565 req.emr_cmd = MC_CMD_PHY_STATS; 566 req.emr_in_buf = payload; 567 req.emr_in_length = MC_CMD_PHY_STATS_IN_LEN; 568 req.emr_out_buf = payload; 569 req.emr_out_length = MC_CMD_PHY_STATS_OUT_DMA_LEN; 570 571 MCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_LO, 572 EFSYS_MEM_ADDR(esmp) & 0xffffffff); 573 MCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_HI, 574 EFSYS_MEM_ADDR(esmp) >> 32); 575 576 efx_mcdi_execute(enp, &req); 577 578 if (req.emr_rc != 0) { 579 rc = req.emr_rc; 580 goto fail2; 581 } 582 EFSYS_ASSERT3U(req.emr_out_length, ==, MC_CMD_PHY_STATS_OUT_DMA_LEN); 583 584 siena_phy_decode_stats(enp, vmask, esmp, &smask, stat); 585 EFSYS_ASSERT(smask == encp->enc_phy_stat_mask); 586 587 (void)rc; /* XXX? */ 588 return (0); 589 590 fail2: 591 EFSYS_PROBE(fail2); 592 fail1: 593 EFSYS_PROBE1(fail1, efx_rc_t, rc); 594 595 return (0); 596 } 597 598 #endif /* EFSYS_OPT_PHY_STATS */ 599 600 #if EFSYS_OPT_BIST 601 602 __checkReturn efx_rc_t 603 siena_phy_bist_start( 604 __in efx_nic_t *enp, 605 __in efx_bist_type_t type) 606 { 607 efx_rc_t rc; 608 609 if ((rc = efx_mcdi_bist_start(enp, type)) != 0) 610 goto fail1; 611 612 return (0); 613 614 fail1: 615 EFSYS_PROBE1(fail1, efx_rc_t, rc); 616 617 return (rc); 618 } 619 620 static __checkReturn unsigned long 621 siena_phy_sft9001_bist_status( 622 __in uint16_t code) 623 { 624 switch (code) { 625 case MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY: 626 return (EFX_PHY_CABLE_STATUS_BUSY); 627 case MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT: 628 return (EFX_PHY_CABLE_STATUS_INTERPAIRSHORT); 629 case MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT: 630 return (EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT); 631 case MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN: 632 return (EFX_PHY_CABLE_STATUS_OPEN); 633 case MC_CMD_POLL_BIST_SFT9001_PAIR_OK: 634 return (EFX_PHY_CABLE_STATUS_OK); 635 default: 636 return (EFX_PHY_CABLE_STATUS_INVALID); 637 } 638 } 639 640 __checkReturn efx_rc_t 641 siena_phy_bist_poll( 642 __in efx_nic_t *enp, 643 __in efx_bist_type_t type, 644 __out efx_bist_result_t *resultp, 645 __out_opt __drv_when(count > 0, __notnull) 646 uint32_t *value_maskp, 647 __out_ecount_opt(count) __drv_when(count > 0, __notnull) 648 unsigned long *valuesp, 649 __in size_t count) 650 { 651 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 652 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_POLL_BIST_IN_LEN, 653 MCDI_CTL_SDU_LEN_MAX); 654 uint32_t value_mask = 0; 655 efx_mcdi_req_t req; 656 uint32_t result; 657 efx_rc_t rc; 658 659 req.emr_cmd = MC_CMD_POLL_BIST; 660 req.emr_in_buf = payload; 661 req.emr_in_length = MC_CMD_POLL_BIST_IN_LEN; 662 req.emr_out_buf = payload; 663 req.emr_out_length = MCDI_CTL_SDU_LEN_MAX; 664 665 efx_mcdi_execute(enp, &req); 666 667 if (req.emr_rc != 0) { 668 rc = req.emr_rc; 669 goto fail1; 670 } 671 672 if (req.emr_out_length_used < MC_CMD_POLL_BIST_OUT_RESULT_OFST + 4) { 673 rc = EMSGSIZE; 674 goto fail2; 675 } 676 677 if (count > 0) 678 (void) memset(valuesp, '\0', count * sizeof (unsigned long)); 679 680 result = MCDI_OUT_DWORD(req, POLL_BIST_OUT_RESULT); 681 682 /* Extract PHY specific results */ 683 if (result == MC_CMD_POLL_BIST_PASSED && 684 encp->enc_phy_type == EFX_PHY_SFT9001B && 685 req.emr_out_length_used >= MC_CMD_POLL_BIST_OUT_SFT9001_LEN && 686 (type == EFX_BIST_TYPE_PHY_CABLE_SHORT || 687 type == EFX_BIST_TYPE_PHY_CABLE_LONG)) { 688 uint16_t word; 689 690 if (count > EFX_BIST_PHY_CABLE_LENGTH_A) { 691 if (valuesp != NULL) 692 valuesp[EFX_BIST_PHY_CABLE_LENGTH_A] = 693 MCDI_OUT_DWORD(req, 694 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A); 695 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_A); 696 } 697 698 if (count > EFX_BIST_PHY_CABLE_LENGTH_B) { 699 if (valuesp != NULL) 700 valuesp[EFX_BIST_PHY_CABLE_LENGTH_B] = 701 MCDI_OUT_DWORD(req, 702 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B); 703 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_B); 704 } 705 706 if (count > EFX_BIST_PHY_CABLE_LENGTH_C) { 707 if (valuesp != NULL) 708 valuesp[EFX_BIST_PHY_CABLE_LENGTH_C] = 709 MCDI_OUT_DWORD(req, 710 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C); 711 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_C); 712 } 713 714 if (count > EFX_BIST_PHY_CABLE_LENGTH_D) { 715 if (valuesp != NULL) 716 valuesp[EFX_BIST_PHY_CABLE_LENGTH_D] = 717 MCDI_OUT_DWORD(req, 718 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D); 719 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_D); 720 } 721 722 if (count > EFX_BIST_PHY_CABLE_STATUS_A) { 723 if (valuesp != NULL) { 724 word = MCDI_OUT_WORD(req, 725 POLL_BIST_OUT_SFT9001_CABLE_STATUS_A); 726 valuesp[EFX_BIST_PHY_CABLE_STATUS_A] = 727 siena_phy_sft9001_bist_status(word); 728 } 729 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_A); 730 } 731 732 if (count > EFX_BIST_PHY_CABLE_STATUS_B) { 733 if (valuesp != NULL) { 734 word = MCDI_OUT_WORD(req, 735 POLL_BIST_OUT_SFT9001_CABLE_STATUS_B); 736 valuesp[EFX_BIST_PHY_CABLE_STATUS_B] = 737 siena_phy_sft9001_bist_status(word); 738 } 739 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_B); 740 } 741 742 if (count > EFX_BIST_PHY_CABLE_STATUS_C) { 743 if (valuesp != NULL) { 744 word = MCDI_OUT_WORD(req, 745 POLL_BIST_OUT_SFT9001_CABLE_STATUS_C); 746 valuesp[EFX_BIST_PHY_CABLE_STATUS_C] = 747 siena_phy_sft9001_bist_status(word); 748 } 749 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_C); 750 } 751 752 if (count > EFX_BIST_PHY_CABLE_STATUS_D) { 753 if (valuesp != NULL) { 754 word = MCDI_OUT_WORD(req, 755 POLL_BIST_OUT_SFT9001_CABLE_STATUS_D); 756 valuesp[EFX_BIST_PHY_CABLE_STATUS_D] = 757 siena_phy_sft9001_bist_status(word); 758 } 759 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_D); 760 } 761 762 } else if (result == MC_CMD_POLL_BIST_FAILED && 763 encp->enc_phy_type == EFX_PHY_QLX111V && 764 req.emr_out_length >= MC_CMD_POLL_BIST_OUT_MRSFP_LEN && 765 count > EFX_BIST_FAULT_CODE) { 766 if (valuesp != NULL) 767 valuesp[EFX_BIST_FAULT_CODE] = 768 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MRSFP_TEST); 769 value_mask |= 1 << EFX_BIST_FAULT_CODE; 770 } 771 772 if (value_maskp != NULL) 773 *value_maskp = value_mask; 774 775 EFSYS_ASSERT(resultp != NULL); 776 if (result == MC_CMD_POLL_BIST_RUNNING) 777 *resultp = EFX_BIST_RESULT_RUNNING; 778 else if (result == MC_CMD_POLL_BIST_PASSED) 779 *resultp = EFX_BIST_RESULT_PASSED; 780 else 781 *resultp = EFX_BIST_RESULT_FAILED; 782 783 return (0); 784 785 fail2: 786 EFSYS_PROBE(fail2); 787 fail1: 788 EFSYS_PROBE1(fail1, efx_rc_t, rc); 789 790 return (rc); 791 } 792 793 void 794 siena_phy_bist_stop( 795 __in efx_nic_t *enp, 796 __in efx_bist_type_t type) 797 { 798 /* There is no way to stop BIST on Siena */ 799 _NOTE(ARGUNUSED(enp, type)) 800 } 801 802 #endif /* EFSYS_OPT_BIST */ 803 804 #endif /* EFSYS_OPT_SIENA */ 805