1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org> 5 * Copyright (c) 1997, 1998, 1999 6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 /* 40 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 41 * available from http://www.sis.com.tw. 42 * 43 * This driver also supports the NatSemi DP83815. Datasheets are 44 * available from http://www.national.com. 45 * 46 * Written by Bill Paul <wpaul@ee.columbia.edu> 47 * Electrical Engineering Department 48 * Columbia University, New York City 49 */ 50 /* 51 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 52 * simple TX and RX descriptors of 3 longwords in size. The receiver 53 * has a single perfect filter entry for the station address and a 54 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 55 * transceiver while the 7016 requires an external transceiver chip. 56 * Both chips offer the standard bit-bang MII interface as well as 57 * an enchanced PHY interface which simplifies accessing MII registers. 58 * 59 * The only downside to this chipset is that RX descriptors must be 60 * longword aligned. 61 */ 62 63 #ifdef HAVE_KERNEL_OPTION_HEADERS 64 #include "opt_device_polling.h" 65 #endif 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/bus.h> 70 #include <sys/endian.h> 71 #include <sys/kernel.h> 72 #include <sys/lock.h> 73 #include <sys/malloc.h> 74 #include <sys/mbuf.h> 75 #include <sys/module.h> 76 #include <sys/socket.h> 77 #include <sys/sockio.h> 78 #include <sys/sysctl.h> 79 80 #include <net/if.h> 81 #include <net/if_var.h> 82 #include <net/if_arp.h> 83 #include <net/ethernet.h> 84 #include <net/if_dl.h> 85 #include <net/if_media.h> 86 #include <net/if_types.h> 87 #include <net/if_vlan_var.h> 88 89 #include <net/bpf.h> 90 91 #include <machine/bus.h> 92 #include <machine/resource.h> 93 #include <sys/rman.h> 94 95 #include <dev/mii/mii.h> 96 #include <dev/mii/mii_bitbang.h> 97 #include <dev/mii/miivar.h> 98 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcivar.h> 101 102 #define SIS_USEIOSPACE 103 104 #include <dev/sis/if_sisreg.h> 105 106 MODULE_DEPEND(sis, pci, 1, 1, 1); 107 MODULE_DEPEND(sis, ether, 1, 1, 1); 108 MODULE_DEPEND(sis, miibus, 1, 1, 1); 109 110 /* "device miibus" required. See GENERIC if you get errors here. */ 111 #include "miibus_if.h" 112 113 #define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx) 114 #define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx) 115 #define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED) 116 117 /* 118 * register space access macros 119 */ 120 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val) 121 122 #define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg) 123 124 #define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg) 125 126 #define CSR_BARRIER(sc, reg, length, flags) \ 127 bus_barrier(sc->sis_res[0], reg, length, flags) 128 129 /* 130 * Various supported device vendors/types and their names. 131 */ 132 static const struct sis_type sis_devs[] = { 133 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 134 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 135 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 136 { 0, 0, NULL } 137 }; 138 139 static int sis_detach(device_t); 140 static __inline void sis_discard_rxbuf(struct sis_rxdesc *); 141 static int sis_dma_alloc(struct sis_softc *); 142 static void sis_dma_free(struct sis_softc *); 143 static int sis_dma_ring_alloc(struct sis_softc *, bus_size_t, bus_size_t, 144 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 145 static void sis_dmamap_cb(void *, bus_dma_segment_t *, int, int); 146 #ifndef __NO_STRICT_ALIGNMENT 147 static __inline void sis_fixup_rx(struct mbuf *); 148 #endif 149 static void sis_ifmedia_sts(if_t, struct ifmediareq *); 150 static int sis_ifmedia_upd(if_t); 151 static void sis_init(void *); 152 static void sis_initl(struct sis_softc *); 153 static void sis_intr(void *); 154 static int sis_ioctl(if_t, u_long, caddr_t); 155 static uint32_t sis_mii_bitbang_read(device_t); 156 static void sis_mii_bitbang_write(device_t, uint32_t); 157 static int sis_newbuf(struct sis_softc *, struct sis_rxdesc *); 158 static int sis_resume(device_t); 159 static int sis_rxeof(struct sis_softc *); 160 static void sis_rxfilter(struct sis_softc *); 161 static void sis_rxfilter_ns(struct sis_softc *); 162 static void sis_rxfilter_sis(struct sis_softc *); 163 static void sis_start(if_t); 164 static void sis_startl(if_t); 165 static void sis_stop(struct sis_softc *); 166 static int sis_suspend(device_t); 167 static void sis_add_sysctls(struct sis_softc *); 168 static void sis_watchdog(struct sis_softc *); 169 static void sis_wol(struct sis_softc *); 170 171 /* 172 * MII bit-bang glue 173 */ 174 static const struct mii_bitbang_ops sis_mii_bitbang_ops = { 175 sis_mii_bitbang_read, 176 sis_mii_bitbang_write, 177 { 178 SIS_MII_DATA, /* MII_BIT_MDO */ 179 SIS_MII_DATA, /* MII_BIT_MDI */ 180 SIS_MII_CLK, /* MII_BIT_MDC */ 181 SIS_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 182 0, /* MII_BIT_DIR_PHY_HOST */ 183 } 184 }; 185 186 static struct resource_spec sis_res_spec[] = { 187 #ifdef SIS_USEIOSPACE 188 { SYS_RES_IOPORT, SIS_PCI_LOIO, RF_ACTIVE}, 189 #else 190 { SYS_RES_MEMORY, SIS_PCI_LOMEM, RF_ACTIVE}, 191 #endif 192 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE}, 193 { -1, 0 } 194 }; 195 196 #define SIS_SETBIT(sc, reg, x) \ 197 CSR_WRITE_4(sc, reg, \ 198 CSR_READ_4(sc, reg) | (x)) 199 200 #define SIS_CLRBIT(sc, reg, x) \ 201 CSR_WRITE_4(sc, reg, \ 202 CSR_READ_4(sc, reg) & ~(x)) 203 204 #define SIO_SET(x) \ 205 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 206 207 #define SIO_CLR(x) \ 208 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 209 210 /* 211 * Routine to reverse the bits in a word. Stolen almost 212 * verbatim from /usr/games/fortune. 213 */ 214 static uint16_t 215 sis_reverse(uint16_t n) 216 { 217 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 218 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 219 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 220 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 221 222 return (n); 223 } 224 225 static void 226 sis_delay(struct sis_softc *sc) 227 { 228 int idx; 229 230 for (idx = (300 / 33) + 1; idx > 0; idx--) 231 CSR_READ_4(sc, SIS_CSR); 232 } 233 234 static void 235 sis_eeprom_idle(struct sis_softc *sc) 236 { 237 int i; 238 239 SIO_SET(SIS_EECTL_CSEL); 240 sis_delay(sc); 241 SIO_SET(SIS_EECTL_CLK); 242 sis_delay(sc); 243 244 for (i = 0; i < 25; i++) { 245 SIO_CLR(SIS_EECTL_CLK); 246 sis_delay(sc); 247 SIO_SET(SIS_EECTL_CLK); 248 sis_delay(sc); 249 } 250 251 SIO_CLR(SIS_EECTL_CLK); 252 sis_delay(sc); 253 SIO_CLR(SIS_EECTL_CSEL); 254 sis_delay(sc); 255 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 256 } 257 258 /* 259 * Send a read command and address to the EEPROM, check for ACK. 260 */ 261 static void 262 sis_eeprom_putbyte(struct sis_softc *sc, int addr) 263 { 264 int d, i; 265 266 d = addr | SIS_EECMD_READ; 267 268 /* 269 * Feed in each bit and stobe the clock. 270 */ 271 for (i = 0x400; i; i >>= 1) { 272 if (d & i) { 273 SIO_SET(SIS_EECTL_DIN); 274 } else { 275 SIO_CLR(SIS_EECTL_DIN); 276 } 277 sis_delay(sc); 278 SIO_SET(SIS_EECTL_CLK); 279 sis_delay(sc); 280 SIO_CLR(SIS_EECTL_CLK); 281 sis_delay(sc); 282 } 283 } 284 285 /* 286 * Read a word of data stored in the EEPROM at address 'addr.' 287 */ 288 static void 289 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 290 { 291 int i; 292 uint16_t word = 0; 293 294 /* Force EEPROM to idle state. */ 295 sis_eeprom_idle(sc); 296 297 /* Enter EEPROM access mode. */ 298 sis_delay(sc); 299 SIO_CLR(SIS_EECTL_CLK); 300 sis_delay(sc); 301 SIO_SET(SIS_EECTL_CSEL); 302 sis_delay(sc); 303 304 /* 305 * Send address of word we want to read. 306 */ 307 sis_eeprom_putbyte(sc, addr); 308 309 /* 310 * Start reading bits from EEPROM. 311 */ 312 for (i = 0x8000; i; i >>= 1) { 313 SIO_SET(SIS_EECTL_CLK); 314 sis_delay(sc); 315 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 316 word |= i; 317 sis_delay(sc); 318 SIO_CLR(SIS_EECTL_CLK); 319 sis_delay(sc); 320 } 321 322 /* Turn off EEPROM access mode. */ 323 sis_eeprom_idle(sc); 324 325 *dest = word; 326 } 327 328 /* 329 * Read a sequence of words from the EEPROM. 330 */ 331 static void 332 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 333 { 334 int i; 335 uint16_t word = 0, *ptr; 336 337 for (i = 0; i < cnt; i++) { 338 sis_eeprom_getword(sc, off + i, &word); 339 ptr = (uint16_t *)(dest + (i * 2)); 340 if (swap) 341 *ptr = ntohs(word); 342 else 343 *ptr = word; 344 } 345 } 346 347 #if defined(__i386__) || defined(__amd64__) 348 static device_t 349 sis_find_bridge(device_t dev) 350 { 351 devclass_t pci_devclass; 352 device_t *pci_devices; 353 int pci_count = 0; 354 device_t *pci_children; 355 int pci_childcount = 0; 356 device_t *busp, *childp; 357 device_t child = NULL; 358 int i, j; 359 360 if ((pci_devclass = devclass_find("pci")) == NULL) 361 return (NULL); 362 363 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 364 365 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 366 if (device_get_children(*busp, &pci_children, &pci_childcount)) 367 continue; 368 for (j = 0, childp = pci_children; 369 j < pci_childcount; j++, childp++) { 370 if (pci_get_vendor(*childp) == SIS_VENDORID && 371 pci_get_device(*childp) == 0x0008) { 372 child = *childp; 373 free(pci_children, M_TEMP); 374 goto done; 375 } 376 } 377 free(pci_children, M_TEMP); 378 } 379 380 done: 381 free(pci_devices, M_TEMP); 382 return (child); 383 } 384 385 static void 386 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt) 387 { 388 device_t bridge; 389 uint8_t reg; 390 int i; 391 bus_space_tag_t btag; 392 393 bridge = sis_find_bridge(dev); 394 if (bridge == NULL) 395 return; 396 reg = pci_read_config(bridge, 0x48, 1); 397 pci_write_config(bridge, 0x48, reg|0x40, 1); 398 399 /* XXX */ 400 #if defined(__amd64__) || defined(__i386__) 401 btag = X86_BUS_SPACE_IO; 402 #endif 403 404 for (i = 0; i < cnt; i++) { 405 bus_space_write_1(btag, 0x0, 0x70, i + off); 406 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 407 } 408 409 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 410 } 411 412 static void 413 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 414 { 415 uint32_t filtsave, csrsave; 416 417 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 418 csrsave = CSR_READ_4(sc, SIS_CSR); 419 420 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 421 CSR_WRITE_4(sc, SIS_CSR, 0); 422 423 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 424 425 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 426 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 427 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 428 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 429 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 430 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 431 432 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 433 CSR_WRITE_4(sc, SIS_CSR, csrsave); 434 } 435 #endif 436 437 /* 438 * Read the MII serial port for the MII bit-bang module. 439 */ 440 static uint32_t 441 sis_mii_bitbang_read(device_t dev) 442 { 443 struct sis_softc *sc; 444 uint32_t val; 445 446 sc = device_get_softc(dev); 447 448 val = CSR_READ_4(sc, SIS_EECTL); 449 CSR_BARRIER(sc, SIS_EECTL, 4, 450 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 451 return (val); 452 } 453 454 /* 455 * Write the MII serial port for the MII bit-bang module. 456 */ 457 static void 458 sis_mii_bitbang_write(device_t dev, uint32_t val) 459 { 460 struct sis_softc *sc; 461 462 sc = device_get_softc(dev); 463 464 CSR_WRITE_4(sc, SIS_EECTL, val); 465 CSR_BARRIER(sc, SIS_EECTL, 4, 466 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 467 } 468 469 static int 470 sis_miibus_readreg(device_t dev, int phy, int reg) 471 { 472 struct sis_softc *sc; 473 474 sc = device_get_softc(dev); 475 476 if (sc->sis_type == SIS_TYPE_83815) { 477 if (phy != 0) 478 return (0); 479 /* 480 * The NatSemi chip can take a while after 481 * a reset to come ready, during which the BMSR 482 * returns a value of 0. This is *never* supposed 483 * to happen: some of the BMSR bits are meant to 484 * be hardwired in the on position, and this can 485 * confuse the miibus code a bit during the probe 486 * and attach phase. So we make an effort to check 487 * for this condition and wait for it to clear. 488 */ 489 if (!CSR_READ_4(sc, NS_BMSR)) 490 DELAY(1000); 491 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 492 } 493 494 /* 495 * Chipsets < SIS_635 seem not to be able to read/write 496 * through mdio. Use the enhanced PHY access register 497 * again for them. 498 */ 499 if (sc->sis_type == SIS_TYPE_900 && 500 sc->sis_rev < SIS_REV_635) { 501 int i, val = 0; 502 503 if (phy != 0) 504 return (0); 505 506 CSR_WRITE_4(sc, SIS_PHYCTL, 507 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 508 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 509 510 for (i = 0; i < SIS_TIMEOUT; i++) { 511 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 512 break; 513 } 514 515 if (i == SIS_TIMEOUT) { 516 device_printf(sc->sis_dev, 517 "PHY failed to come ready\n"); 518 return (0); 519 } 520 521 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 522 523 if (val == 0xFFFF) 524 return (0); 525 526 return (val); 527 } else 528 return (mii_bitbang_readreg(dev, &sis_mii_bitbang_ops, phy, 529 reg)); 530 } 531 532 static int 533 sis_miibus_writereg(device_t dev, int phy, int reg, int data) 534 { 535 struct sis_softc *sc; 536 537 sc = device_get_softc(dev); 538 539 if (sc->sis_type == SIS_TYPE_83815) { 540 if (phy != 0) 541 return (0); 542 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 543 return (0); 544 } 545 546 /* 547 * Chipsets < SIS_635 seem not to be able to read/write 548 * through mdio. Use the enhanced PHY access register 549 * again for them. 550 */ 551 if (sc->sis_type == SIS_TYPE_900 && 552 sc->sis_rev < SIS_REV_635) { 553 int i; 554 555 if (phy != 0) 556 return (0); 557 558 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 559 (reg << 6) | SIS_PHYOP_WRITE); 560 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 561 562 for (i = 0; i < SIS_TIMEOUT; i++) { 563 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 564 break; 565 } 566 567 if (i == SIS_TIMEOUT) 568 device_printf(sc->sis_dev, 569 "PHY failed to come ready\n"); 570 } else 571 mii_bitbang_writereg(dev, &sis_mii_bitbang_ops, phy, reg, 572 data); 573 return (0); 574 } 575 576 static void 577 sis_miibus_statchg(device_t dev) 578 { 579 struct sis_softc *sc; 580 struct mii_data *mii; 581 if_t ifp; 582 uint32_t reg; 583 584 sc = device_get_softc(dev); 585 SIS_LOCK_ASSERT(sc); 586 587 mii = device_get_softc(sc->sis_miibus); 588 ifp = sc->sis_ifp; 589 if (mii == NULL || ifp == NULL || 590 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 591 return; 592 593 sc->sis_flags &= ~SIS_FLAG_LINK; 594 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 595 (IFM_ACTIVE | IFM_AVALID)) { 596 switch (IFM_SUBTYPE(mii->mii_media_active)) { 597 case IFM_10_T: 598 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 599 sc->sis_flags |= SIS_FLAG_LINK; 600 break; 601 case IFM_100_TX: 602 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 603 sc->sis_flags |= SIS_FLAG_LINK; 604 break; 605 default: 606 break; 607 } 608 } 609 610 if ((sc->sis_flags & SIS_FLAG_LINK) == 0) { 611 /* 612 * Stopping MACs seem to reset SIS_TX_LISTPTR and 613 * SIS_RX_LISTPTR which in turn requires resetting 614 * TX/RX buffers. So just don't do anything for 615 * lost link. 616 */ 617 return; 618 } 619 620 /* Set full/half duplex mode. */ 621 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 622 SIS_SETBIT(sc, SIS_TX_CFG, 623 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR)); 624 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 625 } else { 626 SIS_CLRBIT(sc, SIS_TX_CFG, 627 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR)); 628 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 629 } 630 631 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 632 /* 633 * MPII03.D: Half Duplex Excessive Collisions. 634 * Also page 49 in 83816 manual 635 */ 636 SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D); 637 } 638 639 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && 640 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 641 /* 642 * Short Cable Receive Errors (MP21.E) 643 */ 644 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 645 reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff; 646 CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000); 647 DELAY(100); 648 reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff; 649 if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) { 650 device_printf(sc->sis_dev, 651 "Applying short cable fix (reg=%x)\n", reg); 652 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); 653 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20); 654 } 655 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 656 } 657 /* Enable TX/RX MACs. */ 658 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE); 659 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE | SIS_CSR_RX_ENABLE); 660 } 661 662 static uint32_t 663 sis_mchash(struct sis_softc *sc, const uint8_t *addr) 664 { 665 uint32_t crc; 666 667 /* Compute CRC for the address value. */ 668 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 669 670 /* 671 * return the filter bit position 672 * 673 * The NatSemi chip has a 512-bit filter, which is 674 * different than the SiS, so we special-case it. 675 */ 676 if (sc->sis_type == SIS_TYPE_83815) 677 return (crc >> 23); 678 else if (sc->sis_rev >= SIS_REV_635 || 679 sc->sis_rev == SIS_REV_900B) 680 return (crc >> 24); 681 else 682 return (crc >> 25); 683 } 684 685 static void 686 sis_rxfilter(struct sis_softc *sc) 687 { 688 689 SIS_LOCK_ASSERT(sc); 690 691 if (sc->sis_type == SIS_TYPE_83815) 692 sis_rxfilter_ns(sc); 693 else 694 sis_rxfilter_sis(sc); 695 } 696 697 static u_int 698 sis_write_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 699 { 700 struct sis_softc *sc = arg; 701 uint32_t h; 702 int bit, index; 703 704 h = sis_mchash(sc, LLADDR(sdl)); 705 index = h >> 3; 706 bit = h & 0x1F; 707 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 708 if (bit > 0xF) 709 bit -= 0x10; 710 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 711 712 return (1); 713 } 714 715 static void 716 sis_rxfilter_ns(struct sis_softc *sc) 717 { 718 if_t ifp; 719 uint32_t i, filter; 720 721 ifp = sc->sis_ifp; 722 filter = CSR_READ_4(sc, SIS_RXFILT_CTL); 723 if (filter & SIS_RXFILTCTL_ENABLE) { 724 /* 725 * Filter should be disabled to program other bits. 726 */ 727 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE); 728 CSR_READ_4(sc, SIS_RXFILT_CTL); 729 } 730 filter &= ~(NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT | 731 NS_RXFILTCTL_MCHASH | SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD | 732 SIS_RXFILTCTL_ALLMULTI); 733 734 if (if_getflags(ifp) & IFF_BROADCAST) 735 filter |= SIS_RXFILTCTL_BROAD; 736 /* 737 * For the NatSemi chip, we have to explicitly enable the 738 * reception of ARP frames, as well as turn on the 'perfect 739 * match' filter where we store the station address, otherwise 740 * we won't receive unicasts meant for this host. 741 */ 742 filter |= NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT; 743 744 if (if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) { 745 filter |= SIS_RXFILTCTL_ALLMULTI; 746 if (if_getflags(ifp) & IFF_PROMISC) 747 filter |= SIS_RXFILTCTL_ALLPHYS; 748 } else { 749 /* 750 * We have to explicitly enable the multicast hash table 751 * on the NatSemi chip if we want to use it, which we do. 752 */ 753 filter |= NS_RXFILTCTL_MCHASH; 754 755 /* first, zot all the existing hash bits */ 756 for (i = 0; i < 32; i++) { 757 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + 758 (i * 2)); 759 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 760 } 761 762 if_foreach_llmaddr(ifp, sis_write_maddr, sc); 763 } 764 765 /* Turn the receive filter on */ 766 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter | SIS_RXFILTCTL_ENABLE); 767 CSR_READ_4(sc, SIS_RXFILT_CTL); 768 } 769 770 struct sis_hash_maddr_ctx { 771 struct sis_softc *sc; 772 uint16_t hashes[16]; 773 }; 774 775 static u_int 776 sis_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 777 { 778 struct sis_hash_maddr_ctx *ctx = arg; 779 uint32_t h; 780 781 h = sis_mchash(ctx->sc, LLADDR(sdl)); 782 ctx->hashes[h >> 4] |= 1 << (h & 0xf); 783 784 return (1); 785 } 786 787 static void 788 sis_rxfilter_sis(struct sis_softc *sc) 789 { 790 if_t ifp; 791 struct sis_hash_maddr_ctx ctx; 792 uint32_t filter, i, n; 793 794 ifp = sc->sis_ifp; 795 796 /* hash table size */ 797 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 798 n = 16; 799 else 800 n = 8; 801 802 filter = CSR_READ_4(sc, SIS_RXFILT_CTL); 803 if (filter & SIS_RXFILTCTL_ENABLE) { 804 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE); 805 CSR_READ_4(sc, SIS_RXFILT_CTL); 806 } 807 filter &= ~(SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD | 808 SIS_RXFILTCTL_ALLMULTI); 809 if (if_getflags(ifp) & IFF_BROADCAST) 810 filter |= SIS_RXFILTCTL_BROAD; 811 812 if (if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) { 813 filter |= SIS_RXFILTCTL_ALLMULTI; 814 if (if_getflags(ifp) & IFF_PROMISC) 815 filter |= SIS_RXFILTCTL_ALLPHYS; 816 for (i = 0; i < n; i++) 817 ctx.hashes[i] = ~0; 818 } else { 819 for (i = 0; i < n; i++) 820 ctx.hashes[i] = 0; 821 ctx.sc = sc; 822 if (if_foreach_llmaddr(ifp, sis_hash_maddr, &ctx) > n) { 823 filter |= SIS_RXFILTCTL_ALLMULTI; 824 for (i = 0; i < n; i++) 825 ctx.hashes[i] = ~0; 826 } 827 } 828 829 for (i = 0; i < n; i++) { 830 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 831 CSR_WRITE_4(sc, SIS_RXFILT_DATA, ctx.hashes[i]); 832 } 833 834 /* Turn the receive filter on */ 835 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter | SIS_RXFILTCTL_ENABLE); 836 CSR_READ_4(sc, SIS_RXFILT_CTL); 837 } 838 839 static void 840 sis_reset(struct sis_softc *sc) 841 { 842 int i; 843 844 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 845 846 for (i = 0; i < SIS_TIMEOUT; i++) { 847 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 848 break; 849 } 850 851 if (i == SIS_TIMEOUT) 852 device_printf(sc->sis_dev, "reset never completed\n"); 853 854 /* Wait a little while for the chip to get its brains in order. */ 855 DELAY(1000); 856 857 /* 858 * If this is a NetSemi chip, make sure to clear 859 * PME mode. 860 */ 861 if (sc->sis_type == SIS_TYPE_83815) { 862 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 863 CSR_WRITE_4(sc, NS_CLKRUN, 0); 864 } else { 865 /* Disable WOL functions. */ 866 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, 0); 867 } 868 } 869 870 /* 871 * Probe for an SiS chip. Check the PCI vendor and device 872 * IDs against our list and return a device name if we find a match. 873 */ 874 static int 875 sis_probe(device_t dev) 876 { 877 const struct sis_type *t; 878 879 t = sis_devs; 880 881 while (t->sis_name != NULL) { 882 if ((pci_get_vendor(dev) == t->sis_vid) && 883 (pci_get_device(dev) == t->sis_did)) { 884 device_set_desc(dev, t->sis_name); 885 return (BUS_PROBE_DEFAULT); 886 } 887 t++; 888 } 889 890 return (ENXIO); 891 } 892 893 /* 894 * Attach the interface. Allocate softc structures, do ifmedia 895 * setup and ethernet/BPF attach. 896 */ 897 static int 898 sis_attach(device_t dev) 899 { 900 u_char eaddr[ETHER_ADDR_LEN]; 901 struct sis_softc *sc; 902 if_t ifp; 903 int error = 0, pmc; 904 905 sc = device_get_softc(dev); 906 907 sc->sis_dev = dev; 908 909 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 910 MTX_DEF); 911 callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0); 912 913 if (pci_get_device(dev) == SIS_DEVICEID_900) 914 sc->sis_type = SIS_TYPE_900; 915 if (pci_get_device(dev) == SIS_DEVICEID_7016) 916 sc->sis_type = SIS_TYPE_7016; 917 if (pci_get_vendor(dev) == NS_VENDORID) 918 sc->sis_type = SIS_TYPE_83815; 919 920 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 921 /* 922 * Map control/status registers. 923 */ 924 pci_enable_busmaster(dev); 925 926 error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res); 927 if (error) { 928 device_printf(dev, "couldn't allocate resources\n"); 929 goto fail; 930 } 931 932 /* Reset the adapter. */ 933 sis_reset(sc); 934 935 if (sc->sis_type == SIS_TYPE_900 && 936 (sc->sis_rev == SIS_REV_635 || 937 sc->sis_rev == SIS_REV_900B)) { 938 SIO_SET(SIS_CFG_RND_CNT); 939 SIO_SET(SIS_CFG_PERR_DETECT); 940 } 941 942 /* 943 * Get station address from the EEPROM. 944 */ 945 switch (pci_get_vendor(dev)) { 946 case NS_VENDORID: 947 sc->sis_srr = CSR_READ_4(sc, NS_SRR); 948 949 /* We can't update the device description, so spew */ 950 if (sc->sis_srr == NS_SRR_15C) 951 device_printf(dev, "Silicon Revision: DP83815C\n"); 952 else if (sc->sis_srr == NS_SRR_15D) 953 device_printf(dev, "Silicon Revision: DP83815D\n"); 954 else if (sc->sis_srr == NS_SRR_16A) 955 device_printf(dev, "Silicon Revision: DP83816A\n"); 956 else 957 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); 958 959 /* 960 * Reading the MAC address out of the EEPROM on 961 * the NatSemi chip takes a bit more work than 962 * you'd expect. The address spans 4 16-bit words, 963 * with the first word containing only a single bit. 964 * You have to shift everything over one bit to 965 * get it aligned properly. Also, the bits are 966 * stored backwards (the LSB is really the MSB, 967 * and so on) so you have to reverse them in order 968 * to get the MAC address into the form we want. 969 * Why? Who the hell knows. 970 */ 971 { 972 uint16_t tmp[4]; 973 974 sis_read_eeprom(sc, (caddr_t)&tmp, 975 NS_EE_NODEADDR, 4, 0); 976 977 /* Shift everything over one bit. */ 978 tmp[3] = tmp[3] >> 1; 979 tmp[3] |= tmp[2] << 15; 980 tmp[2] = tmp[2] >> 1; 981 tmp[2] |= tmp[1] << 15; 982 tmp[1] = tmp[1] >> 1; 983 tmp[1] |= tmp[0] << 15; 984 985 /* Now reverse all the bits. */ 986 tmp[3] = sis_reverse(tmp[3]); 987 tmp[2] = sis_reverse(tmp[2]); 988 tmp[1] = sis_reverse(tmp[1]); 989 990 eaddr[0] = (tmp[1] >> 0) & 0xFF; 991 eaddr[1] = (tmp[1] >> 8) & 0xFF; 992 eaddr[2] = (tmp[2] >> 0) & 0xFF; 993 eaddr[3] = (tmp[2] >> 8) & 0xFF; 994 eaddr[4] = (tmp[3] >> 0) & 0xFF; 995 eaddr[5] = (tmp[3] >> 8) & 0xFF; 996 } 997 break; 998 case SIS_VENDORID: 999 default: 1000 #if defined(__i386__) || defined(__amd64__) 1001 /* 1002 * If this is a SiS 630E chipset with an embedded 1003 * SiS 900 controller, we have to read the MAC address 1004 * from the APC CMOS RAM. Our method for doing this 1005 * is very ugly since we have to reach out and grab 1006 * ahold of hardware for which we cannot properly 1007 * allocate resources. This code is only compiled on 1008 * the i386 architecture since the SiS 630E chipset 1009 * is for x86 motherboards only. Note that there are 1010 * a lot of magic numbers in this hack. These are 1011 * taken from SiS's Linux driver. I'd like to replace 1012 * them with proper symbolic definitions, but that 1013 * requires some datasheets that I don't have access 1014 * to at the moment. 1015 */ 1016 if (sc->sis_rev == SIS_REV_630S || 1017 sc->sis_rev == SIS_REV_630E || 1018 sc->sis_rev == SIS_REV_630EA1) 1019 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1020 1021 else if (sc->sis_rev == SIS_REV_635 || 1022 sc->sis_rev == SIS_REV_630ET) 1023 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1024 else if (sc->sis_rev == SIS_REV_96x) { 1025 /* Allow to read EEPROM from LAN. It is shared 1026 * between a 1394 controller and the NIC and each 1027 * time we access it, we need to set SIS_EECMD_REQ. 1028 */ 1029 SIO_SET(SIS_EECMD_REQ); 1030 for (int waittime = 0; waittime < SIS_TIMEOUT; 1031 waittime++) { 1032 /* Force EEPROM to idle state. */ 1033 sis_eeprom_idle(sc); 1034 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1035 sis_read_eeprom(sc, (caddr_t)&eaddr, 1036 SIS_EE_NODEADDR, 3, 0); 1037 break; 1038 } 1039 DELAY(1); 1040 } 1041 /* 1042 * Set SIS_EECTL_CLK to high, so a other master 1043 * can operate on the i2c bus. 1044 */ 1045 SIO_SET(SIS_EECTL_CLK); 1046 /* Refuse EEPROM access by LAN */ 1047 SIO_SET(SIS_EECMD_DONE); 1048 } else 1049 #endif 1050 sis_read_eeprom(sc, (caddr_t)&eaddr, 1051 SIS_EE_NODEADDR, 3, 0); 1052 break; 1053 } 1054 1055 sis_add_sysctls(sc); 1056 1057 /* Allocate DMA'able memory. */ 1058 if ((error = sis_dma_alloc(sc)) != 0) 1059 goto fail; 1060 1061 ifp = sc->sis_ifp = if_alloc(IFT_ETHER); 1062 if (ifp == NULL) { 1063 device_printf(dev, "can not if_alloc()\n"); 1064 error = ENOSPC; 1065 goto fail; 1066 } 1067 if_setsoftc(ifp, sc); 1068 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1069 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1070 if_setioctlfn(ifp, sis_ioctl); 1071 if_setstartfn(ifp, sis_start); 1072 if_setinitfn(ifp, sis_init); 1073 if_setsendqlen(ifp, SIS_TX_LIST_CNT - 1); 1074 if_setsendqready(ifp); 1075 1076 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) == 0) { 1077 if (sc->sis_type == SIS_TYPE_83815) 1078 if_setcapabilitiesbit(ifp, IFCAP_WOL, 0); 1079 else 1080 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 1081 if_setcapenable(ifp, if_getcapabilities(ifp)); 1082 } 1083 1084 /* 1085 * Do MII setup. 1086 */ 1087 error = mii_attach(dev, &sc->sis_miibus, ifp, sis_ifmedia_upd, 1088 sis_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 1089 if (error != 0) { 1090 device_printf(dev, "attaching PHYs failed\n"); 1091 goto fail; 1092 } 1093 1094 /* 1095 * Call MI attach routine. 1096 */ 1097 ether_ifattach(ifp, eaddr); 1098 1099 /* 1100 * Tell the upper layer(s) we support long frames. 1101 */ 1102 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1103 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 1104 if_setcapenable(ifp, if_getcapabilities(ifp)); 1105 #ifdef DEVICE_POLLING 1106 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 1107 #endif 1108 1109 /* Hook interrupt last to avoid having to lock softc */ 1110 error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE, 1111 NULL, sis_intr, sc, &sc->sis_intrhand); 1112 1113 if (error) { 1114 device_printf(dev, "couldn't set up irq\n"); 1115 ether_ifdetach(ifp); 1116 goto fail; 1117 } 1118 1119 fail: 1120 if (error) 1121 sis_detach(dev); 1122 1123 return (error); 1124 } 1125 1126 /* 1127 * Shutdown hardware and free up resources. This can be called any 1128 * time after the mutex has been initialized. It is called in both 1129 * the error case in attach and the normal detach case so it needs 1130 * to be careful about only freeing resources that have actually been 1131 * allocated. 1132 */ 1133 static int 1134 sis_detach(device_t dev) 1135 { 1136 struct sis_softc *sc; 1137 if_t ifp; 1138 1139 sc = device_get_softc(dev); 1140 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 1141 ifp = sc->sis_ifp; 1142 1143 #ifdef DEVICE_POLLING 1144 if (if_getcapenable(ifp) & IFCAP_POLLING) 1145 ether_poll_deregister(ifp); 1146 #endif 1147 1148 /* These should only be active if attach succeeded. */ 1149 if (device_is_attached(dev)) { 1150 SIS_LOCK(sc); 1151 sis_stop(sc); 1152 SIS_UNLOCK(sc); 1153 callout_drain(&sc->sis_stat_ch); 1154 ether_ifdetach(ifp); 1155 } 1156 if (sc->sis_miibus) 1157 device_delete_child(dev, sc->sis_miibus); 1158 bus_generic_detach(dev); 1159 1160 if (sc->sis_intrhand) 1161 bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand); 1162 bus_release_resources(dev, sis_res_spec, sc->sis_res); 1163 1164 if (ifp) 1165 if_free(ifp); 1166 1167 sis_dma_free(sc); 1168 1169 mtx_destroy(&sc->sis_mtx); 1170 1171 return (0); 1172 } 1173 1174 struct sis_dmamap_arg { 1175 bus_addr_t sis_busaddr; 1176 }; 1177 1178 static void 1179 sis_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1180 { 1181 struct sis_dmamap_arg *ctx; 1182 1183 if (error != 0) 1184 return; 1185 1186 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1187 1188 ctx = (struct sis_dmamap_arg *)arg; 1189 ctx->sis_busaddr = segs[0].ds_addr; 1190 } 1191 1192 static int 1193 sis_dma_ring_alloc(struct sis_softc *sc, bus_size_t alignment, 1194 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 1195 bus_addr_t *paddr, const char *msg) 1196 { 1197 struct sis_dmamap_arg ctx; 1198 int error; 1199 1200 error = bus_dma_tag_create(sc->sis_parent_tag, alignment, 0, 1201 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1, 1202 maxsize, 0, NULL, NULL, tag); 1203 if (error != 0) { 1204 device_printf(sc->sis_dev, 1205 "could not create %s dma tag\n", msg); 1206 return (ENOMEM); 1207 } 1208 /* Allocate DMA'able memory for ring. */ 1209 error = bus_dmamem_alloc(*tag, (void **)ring, 1210 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 1211 if (error != 0) { 1212 device_printf(sc->sis_dev, 1213 "could not allocate DMA'able memory for %s\n", msg); 1214 return (ENOMEM); 1215 } 1216 /* Load the address of the ring. */ 1217 ctx.sis_busaddr = 0; 1218 error = bus_dmamap_load(*tag, *map, *ring, maxsize, sis_dmamap_cb, 1219 &ctx, BUS_DMA_NOWAIT); 1220 if (error != 0) { 1221 device_printf(sc->sis_dev, 1222 "could not load DMA'able memory for %s\n", msg); 1223 return (ENOMEM); 1224 } 1225 *paddr = ctx.sis_busaddr; 1226 return (0); 1227 } 1228 1229 static int 1230 sis_dma_alloc(struct sis_softc *sc) 1231 { 1232 struct sis_rxdesc *rxd; 1233 struct sis_txdesc *txd; 1234 int error, i; 1235 1236 /* Allocate the parent bus DMA tag appropriate for PCI. */ 1237 error = bus_dma_tag_create(bus_get_dma_tag(sc->sis_dev), 1238 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1239 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 1240 0, NULL, NULL, &sc->sis_parent_tag); 1241 if (error != 0) { 1242 device_printf(sc->sis_dev, 1243 "could not allocate parent dma tag\n"); 1244 return (ENOMEM); 1245 } 1246 1247 /* Create RX ring. */ 1248 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_RX_LIST_SZ, 1249 &sc->sis_rx_list_tag, (uint8_t **)&sc->sis_rx_list, 1250 &sc->sis_rx_list_map, &sc->sis_rx_paddr, "RX ring"); 1251 if (error) 1252 return (error); 1253 1254 /* Create TX ring. */ 1255 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_TX_LIST_SZ, 1256 &sc->sis_tx_list_tag, (uint8_t **)&sc->sis_tx_list, 1257 &sc->sis_tx_list_map, &sc->sis_tx_paddr, "TX ring"); 1258 if (error) 1259 return (error); 1260 1261 /* Create tag for RX mbufs. */ 1262 error = bus_dma_tag_create(sc->sis_parent_tag, SIS_RX_BUF_ALIGN, 0, 1263 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 1264 MCLBYTES, 0, NULL, NULL, &sc->sis_rx_tag); 1265 if (error) { 1266 device_printf(sc->sis_dev, "could not allocate RX dma tag\n"); 1267 return (error); 1268 } 1269 1270 /* Create tag for TX mbufs. */ 1271 error = bus_dma_tag_create(sc->sis_parent_tag, 1, 0, 1272 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1273 MCLBYTES * SIS_MAXTXSEGS, SIS_MAXTXSEGS, MCLBYTES, 0, NULL, NULL, 1274 &sc->sis_tx_tag); 1275 if (error) { 1276 device_printf(sc->sis_dev, "could not allocate TX dma tag\n"); 1277 return (error); 1278 } 1279 1280 /* Create DMA maps for RX buffers. */ 1281 error = bus_dmamap_create(sc->sis_rx_tag, 0, &sc->sis_rx_sparemap); 1282 if (error) { 1283 device_printf(sc->sis_dev, 1284 "can't create spare DMA map for RX\n"); 1285 return (error); 1286 } 1287 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1288 rxd = &sc->sis_rxdesc[i]; 1289 rxd->rx_m = NULL; 1290 error = bus_dmamap_create(sc->sis_rx_tag, 0, &rxd->rx_dmamap); 1291 if (error) { 1292 device_printf(sc->sis_dev, 1293 "can't create DMA map for RX\n"); 1294 return (error); 1295 } 1296 } 1297 1298 /* Create DMA maps for TX buffers. */ 1299 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1300 txd = &sc->sis_txdesc[i]; 1301 txd->tx_m = NULL; 1302 error = bus_dmamap_create(sc->sis_tx_tag, 0, &txd->tx_dmamap); 1303 if (error) { 1304 device_printf(sc->sis_dev, 1305 "can't create DMA map for TX\n"); 1306 return (error); 1307 } 1308 } 1309 1310 return (0); 1311 } 1312 1313 static void 1314 sis_dma_free(struct sis_softc *sc) 1315 { 1316 struct sis_rxdesc *rxd; 1317 struct sis_txdesc *txd; 1318 int i; 1319 1320 /* Destroy DMA maps for RX buffers. */ 1321 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1322 rxd = &sc->sis_rxdesc[i]; 1323 if (rxd->rx_dmamap) 1324 bus_dmamap_destroy(sc->sis_rx_tag, rxd->rx_dmamap); 1325 } 1326 if (sc->sis_rx_sparemap) 1327 bus_dmamap_destroy(sc->sis_rx_tag, sc->sis_rx_sparemap); 1328 1329 /* Destroy DMA maps for TX buffers. */ 1330 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1331 txd = &sc->sis_txdesc[i]; 1332 if (txd->tx_dmamap) 1333 bus_dmamap_destroy(sc->sis_tx_tag, txd->tx_dmamap); 1334 } 1335 1336 if (sc->sis_rx_tag) 1337 bus_dma_tag_destroy(sc->sis_rx_tag); 1338 if (sc->sis_tx_tag) 1339 bus_dma_tag_destroy(sc->sis_tx_tag); 1340 1341 /* Destroy RX ring. */ 1342 if (sc->sis_rx_paddr) 1343 bus_dmamap_unload(sc->sis_rx_list_tag, sc->sis_rx_list_map); 1344 if (sc->sis_rx_list) 1345 bus_dmamem_free(sc->sis_rx_list_tag, sc->sis_rx_list, 1346 sc->sis_rx_list_map); 1347 1348 if (sc->sis_rx_list_tag) 1349 bus_dma_tag_destroy(sc->sis_rx_list_tag); 1350 1351 /* Destroy TX ring. */ 1352 if (sc->sis_tx_paddr) 1353 bus_dmamap_unload(sc->sis_tx_list_tag, sc->sis_tx_list_map); 1354 1355 if (sc->sis_tx_list) 1356 bus_dmamem_free(sc->sis_tx_list_tag, sc->sis_tx_list, 1357 sc->sis_tx_list_map); 1358 1359 if (sc->sis_tx_list_tag) 1360 bus_dma_tag_destroy(sc->sis_tx_list_tag); 1361 1362 /* Destroy the parent tag. */ 1363 if (sc->sis_parent_tag) 1364 bus_dma_tag_destroy(sc->sis_parent_tag); 1365 } 1366 1367 /* 1368 * Initialize the TX and RX descriptors and allocate mbufs for them. Note that 1369 * we arrange the descriptors in a closed ring, so that the last descriptor 1370 * points back to the first. 1371 */ 1372 static int 1373 sis_ring_init(struct sis_softc *sc) 1374 { 1375 struct sis_rxdesc *rxd; 1376 struct sis_txdesc *txd; 1377 bus_addr_t next; 1378 int error, i; 1379 1380 bzero(&sc->sis_tx_list[0], SIS_TX_LIST_SZ); 1381 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1382 txd = &sc->sis_txdesc[i]; 1383 txd->tx_m = NULL; 1384 if (i == SIS_TX_LIST_CNT - 1) 1385 next = SIS_TX_RING_ADDR(sc, 0); 1386 else 1387 next = SIS_TX_RING_ADDR(sc, i + 1); 1388 sc->sis_tx_list[i].sis_next = htole32(SIS_ADDR_LO(next)); 1389 } 1390 sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0; 1391 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, 1392 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1393 1394 sc->sis_rx_cons = 0; 1395 bzero(&sc->sis_rx_list[0], SIS_RX_LIST_SZ); 1396 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1397 rxd = &sc->sis_rxdesc[i]; 1398 rxd->rx_desc = &sc->sis_rx_list[i]; 1399 if (i == SIS_RX_LIST_CNT - 1) 1400 next = SIS_RX_RING_ADDR(sc, 0); 1401 else 1402 next = SIS_RX_RING_ADDR(sc, i + 1); 1403 rxd->rx_desc->sis_next = htole32(SIS_ADDR_LO(next)); 1404 error = sis_newbuf(sc, rxd); 1405 if (error) 1406 return (error); 1407 } 1408 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, 1409 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1410 1411 return (0); 1412 } 1413 1414 /* 1415 * Initialize an RX descriptor and attach an MBUF cluster. 1416 */ 1417 static int 1418 sis_newbuf(struct sis_softc *sc, struct sis_rxdesc *rxd) 1419 { 1420 struct mbuf *m; 1421 bus_dma_segment_t segs[1]; 1422 bus_dmamap_t map; 1423 int nsegs; 1424 1425 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1426 if (m == NULL) 1427 return (ENOBUFS); 1428 m->m_len = m->m_pkthdr.len = SIS_RXLEN; 1429 #ifndef __NO_STRICT_ALIGNMENT 1430 m_adj(m, SIS_RX_BUF_ALIGN); 1431 #endif 1432 1433 if (bus_dmamap_load_mbuf_sg(sc->sis_rx_tag, sc->sis_rx_sparemap, m, 1434 segs, &nsegs, 0) != 0) { 1435 m_freem(m); 1436 return (ENOBUFS); 1437 } 1438 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1439 1440 if (rxd->rx_m != NULL) { 1441 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, 1442 BUS_DMASYNC_POSTREAD); 1443 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap); 1444 } 1445 map = rxd->rx_dmamap; 1446 rxd->rx_dmamap = sc->sis_rx_sparemap; 1447 sc->sis_rx_sparemap = map; 1448 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_PREREAD); 1449 rxd->rx_m = m; 1450 rxd->rx_desc->sis_ptr = htole32(SIS_ADDR_LO(segs[0].ds_addr)); 1451 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN); 1452 return (0); 1453 } 1454 1455 static __inline void 1456 sis_discard_rxbuf(struct sis_rxdesc *rxd) 1457 { 1458 1459 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN); 1460 } 1461 1462 #ifndef __NO_STRICT_ALIGNMENT 1463 static __inline void 1464 sis_fixup_rx(struct mbuf *m) 1465 { 1466 uint16_t *src, *dst; 1467 int i; 1468 1469 src = mtod(m, uint16_t *); 1470 dst = src - (SIS_RX_BUF_ALIGN - ETHER_ALIGN) / sizeof(*src); 1471 1472 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1473 *dst++ = *src++; 1474 1475 m->m_data -= SIS_RX_BUF_ALIGN - ETHER_ALIGN; 1476 } 1477 #endif 1478 1479 /* 1480 * A frame has been uploaded: pass the resulting mbuf chain up to 1481 * the higher level protocols. 1482 */ 1483 static int 1484 sis_rxeof(struct sis_softc *sc) 1485 { 1486 struct mbuf *m; 1487 if_t ifp; 1488 struct sis_rxdesc *rxd; 1489 struct sis_desc *cur_rx; 1490 int prog, rx_cons, rx_npkts = 0, total_len; 1491 uint32_t rxstat; 1492 1493 SIS_LOCK_ASSERT(sc); 1494 1495 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, 1496 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1497 1498 rx_cons = sc->sis_rx_cons; 1499 ifp = sc->sis_ifp; 1500 1501 for (prog = 0; (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0; 1502 SIS_INC(rx_cons, SIS_RX_LIST_CNT), prog++) { 1503 #ifdef DEVICE_POLLING 1504 if (if_getcapenable(ifp) & IFCAP_POLLING) { 1505 if (sc->rxcycles <= 0) 1506 break; 1507 sc->rxcycles--; 1508 } 1509 #endif 1510 cur_rx = &sc->sis_rx_list[rx_cons]; 1511 rxstat = le32toh(cur_rx->sis_cmdsts); 1512 if ((rxstat & SIS_CMDSTS_OWN) == 0) 1513 break; 1514 rxd = &sc->sis_rxdesc[rx_cons]; 1515 1516 total_len = (rxstat & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN; 1517 if ((if_getcapenable(ifp) & IFCAP_VLAN_MTU) != 0 && 1518 total_len <= (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - 1519 ETHER_CRC_LEN)) 1520 rxstat &= ~SIS_RXSTAT_GIANT; 1521 if (SIS_RXSTAT_ERROR(rxstat) != 0) { 1522 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1523 if (rxstat & SIS_RXSTAT_COLL) 1524 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 1525 sis_discard_rxbuf(rxd); 1526 continue; 1527 } 1528 1529 /* Add a new receive buffer to the ring. */ 1530 m = rxd->rx_m; 1531 if (sis_newbuf(sc, rxd) != 0) { 1532 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1533 sis_discard_rxbuf(rxd); 1534 continue; 1535 } 1536 1537 /* No errors; receive the packet. */ 1538 m->m_pkthdr.len = m->m_len = total_len; 1539 #ifndef __NO_STRICT_ALIGNMENT 1540 /* 1541 * On architectures without alignment problems we try to 1542 * allocate a new buffer for the receive ring, and pass up 1543 * the one where the packet is already, saving the expensive 1544 * copy operation. 1545 */ 1546 sis_fixup_rx(m); 1547 #endif 1548 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1549 m->m_pkthdr.rcvif = ifp; 1550 1551 SIS_UNLOCK(sc); 1552 if_input(ifp, m); 1553 SIS_LOCK(sc); 1554 rx_npkts++; 1555 } 1556 1557 if (prog > 0) { 1558 sc->sis_rx_cons = rx_cons; 1559 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, 1560 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1561 } 1562 1563 return (rx_npkts); 1564 } 1565 1566 /* 1567 * A frame was downloaded to the chip. It's safe for us to clean up 1568 * the list buffers. 1569 */ 1570 1571 static void 1572 sis_txeof(struct sis_softc *sc) 1573 { 1574 if_t ifp; 1575 struct sis_desc *cur_tx; 1576 struct sis_txdesc *txd; 1577 uint32_t cons, txstat; 1578 1579 SIS_LOCK_ASSERT(sc); 1580 1581 cons = sc->sis_tx_cons; 1582 if (cons == sc->sis_tx_prod) 1583 return; 1584 1585 ifp = sc->sis_ifp; 1586 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, 1587 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1588 1589 /* 1590 * Go through our tx list and free mbufs for those 1591 * frames that have been transmitted. 1592 */ 1593 for (; cons != sc->sis_tx_prod; SIS_INC(cons, SIS_TX_LIST_CNT)) { 1594 cur_tx = &sc->sis_tx_list[cons]; 1595 txstat = le32toh(cur_tx->sis_cmdsts); 1596 if ((txstat & SIS_CMDSTS_OWN) != 0) 1597 break; 1598 txd = &sc->sis_txdesc[cons]; 1599 if (txd->tx_m != NULL) { 1600 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, 1601 BUS_DMASYNC_POSTWRITE); 1602 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); 1603 m_freem(txd->tx_m); 1604 txd->tx_m = NULL; 1605 if ((txstat & SIS_CMDSTS_PKT_OK) != 0) { 1606 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1607 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1608 (txstat & SIS_TXSTAT_COLLCNT) >> 16); 1609 } else { 1610 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1611 if (txstat & SIS_TXSTAT_EXCESSCOLLS) 1612 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 1613 if (txstat & SIS_TXSTAT_OUTOFWINCOLL) 1614 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 1615 } 1616 } 1617 sc->sis_tx_cnt--; 1618 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1619 } 1620 sc->sis_tx_cons = cons; 1621 if (sc->sis_tx_cnt == 0) 1622 sc->sis_watchdog_timer = 0; 1623 } 1624 1625 static void 1626 sis_tick(void *xsc) 1627 { 1628 struct sis_softc *sc; 1629 struct mii_data *mii; 1630 1631 sc = xsc; 1632 SIS_LOCK_ASSERT(sc); 1633 1634 mii = device_get_softc(sc->sis_miibus); 1635 mii_tick(mii); 1636 sis_watchdog(sc); 1637 if ((sc->sis_flags & SIS_FLAG_LINK) == 0) 1638 sis_miibus_statchg(sc->sis_dev); 1639 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 1640 } 1641 1642 #ifdef DEVICE_POLLING 1643 static poll_handler_t sis_poll; 1644 1645 static int 1646 sis_poll(if_t ifp, enum poll_cmd cmd, int count) 1647 { 1648 struct sis_softc *sc = if_getsoftc(ifp); 1649 int rx_npkts = 0; 1650 1651 SIS_LOCK(sc); 1652 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 1653 SIS_UNLOCK(sc); 1654 return (rx_npkts); 1655 } 1656 1657 /* 1658 * On the sis, reading the status register also clears it. 1659 * So before returning to intr mode we must make sure that all 1660 * possible pending sources of interrupts have been served. 1661 * In practice this means run to completion the *eof routines, 1662 * and then call the interrupt routine 1663 */ 1664 sc->rxcycles = count; 1665 rx_npkts = sis_rxeof(sc); 1666 sis_txeof(sc); 1667 if (!if_sendq_empty(ifp)) 1668 sis_startl(ifp); 1669 1670 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1671 uint32_t status; 1672 1673 /* Reading the ISR register clears all interrupts. */ 1674 status = CSR_READ_4(sc, SIS_ISR); 1675 1676 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1677 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1678 1679 if (status & (SIS_ISR_RX_IDLE)) 1680 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1681 1682 if (status & SIS_ISR_SYSERR) { 1683 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1684 sis_initl(sc); 1685 } 1686 } 1687 1688 SIS_UNLOCK(sc); 1689 return (rx_npkts); 1690 } 1691 #endif /* DEVICE_POLLING */ 1692 1693 static void 1694 sis_intr(void *arg) 1695 { 1696 struct sis_softc *sc; 1697 if_t ifp; 1698 uint32_t status; 1699 1700 sc = arg; 1701 ifp = sc->sis_ifp; 1702 1703 SIS_LOCK(sc); 1704 #ifdef DEVICE_POLLING 1705 if (if_getcapenable(ifp) & IFCAP_POLLING) { 1706 SIS_UNLOCK(sc); 1707 return; 1708 } 1709 #endif 1710 1711 /* Reading the ISR register clears all interrupts. */ 1712 status = CSR_READ_4(sc, SIS_ISR); 1713 if ((status & SIS_INTRS) == 0) { 1714 /* Not ours. */ 1715 SIS_UNLOCK(sc); 1716 return; 1717 } 1718 1719 /* Disable interrupts. */ 1720 CSR_WRITE_4(sc, SIS_IER, 0); 1721 1722 for (;(status & SIS_INTRS) != 0;) { 1723 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 1724 break; 1725 if (status & 1726 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1727 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1728 sis_txeof(sc); 1729 1730 if (status & (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | 1731 SIS_ISR_RX_ERR | SIS_ISR_RX_IDLE)) 1732 sis_rxeof(sc); 1733 1734 if (status & SIS_ISR_RX_OFLOW) 1735 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1736 1737 if (status & (SIS_ISR_RX_IDLE)) 1738 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1739 1740 if (status & SIS_ISR_SYSERR) { 1741 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1742 sis_initl(sc); 1743 SIS_UNLOCK(sc); 1744 return; 1745 } 1746 status = CSR_READ_4(sc, SIS_ISR); 1747 } 1748 1749 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1750 /* Re-enable interrupts. */ 1751 CSR_WRITE_4(sc, SIS_IER, 1); 1752 1753 if (!if_sendq_empty(ifp)) 1754 sis_startl(ifp); 1755 } 1756 1757 SIS_UNLOCK(sc); 1758 } 1759 1760 /* 1761 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1762 * pointers to the fragment pointers. 1763 */ 1764 static int 1765 sis_encap(struct sis_softc *sc, struct mbuf **m_head) 1766 { 1767 struct mbuf *m; 1768 struct sis_txdesc *txd; 1769 struct sis_desc *f; 1770 bus_dma_segment_t segs[SIS_MAXTXSEGS]; 1771 bus_dmamap_t map; 1772 int error, i, frag, nsegs, prod; 1773 int padlen; 1774 1775 prod = sc->sis_tx_prod; 1776 txd = &sc->sis_txdesc[prod]; 1777 if ((sc->sis_flags & SIS_FLAG_MANUAL_PAD) != 0 && 1778 (*m_head)->m_pkthdr.len < SIS_MIN_FRAMELEN) { 1779 m = *m_head; 1780 padlen = SIS_MIN_FRAMELEN - m->m_pkthdr.len; 1781 if (M_WRITABLE(m) == 0) { 1782 /* Get a writable copy. */ 1783 m = m_dup(*m_head, M_NOWAIT); 1784 m_freem(*m_head); 1785 if (m == NULL) { 1786 *m_head = NULL; 1787 return (ENOBUFS); 1788 } 1789 *m_head = m; 1790 } 1791 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) { 1792 m = m_defrag(m, M_NOWAIT); 1793 if (m == NULL) { 1794 m_freem(*m_head); 1795 *m_head = NULL; 1796 return (ENOBUFS); 1797 } 1798 } 1799 /* 1800 * Manually pad short frames, and zero the pad space 1801 * to avoid leaking data. 1802 */ 1803 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1804 m->m_pkthdr.len += padlen; 1805 m->m_len = m->m_pkthdr.len; 1806 *m_head = m; 1807 } 1808 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap, 1809 *m_head, segs, &nsegs, 0); 1810 if (error == EFBIG) { 1811 m = m_collapse(*m_head, M_NOWAIT, SIS_MAXTXSEGS); 1812 if (m == NULL) { 1813 m_freem(*m_head); 1814 *m_head = NULL; 1815 return (ENOBUFS); 1816 } 1817 *m_head = m; 1818 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap, 1819 *m_head, segs, &nsegs, 0); 1820 if (error != 0) { 1821 m_freem(*m_head); 1822 *m_head = NULL; 1823 return (error); 1824 } 1825 } else if (error != 0) 1826 return (error); 1827 1828 /* Check for descriptor overruns. */ 1829 if (sc->sis_tx_cnt + nsegs > SIS_TX_LIST_CNT - 1) { 1830 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); 1831 return (ENOBUFS); 1832 } 1833 1834 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, BUS_DMASYNC_PREWRITE); 1835 1836 frag = prod; 1837 for (i = 0; i < nsegs; i++) { 1838 f = &sc->sis_tx_list[prod]; 1839 if (i == 0) 1840 f->sis_cmdsts = htole32(segs[i].ds_len | 1841 SIS_CMDSTS_MORE); 1842 else 1843 f->sis_cmdsts = htole32(segs[i].ds_len | 1844 SIS_CMDSTS_OWN | SIS_CMDSTS_MORE); 1845 f->sis_ptr = htole32(SIS_ADDR_LO(segs[i].ds_addr)); 1846 SIS_INC(prod, SIS_TX_LIST_CNT); 1847 sc->sis_tx_cnt++; 1848 } 1849 1850 /* Update producer index. */ 1851 sc->sis_tx_prod = prod; 1852 1853 /* Remove MORE flag on the last descriptor. */ 1854 prod = (prod - 1) & (SIS_TX_LIST_CNT - 1); 1855 f = &sc->sis_tx_list[prod]; 1856 f->sis_cmdsts &= ~htole32(SIS_CMDSTS_MORE); 1857 1858 /* Lastly transfer ownership of packet to the controller. */ 1859 f = &sc->sis_tx_list[frag]; 1860 f->sis_cmdsts |= htole32(SIS_CMDSTS_OWN); 1861 1862 /* Swap the last and the first dmamaps. */ 1863 map = txd->tx_dmamap; 1864 txd->tx_dmamap = sc->sis_txdesc[prod].tx_dmamap; 1865 sc->sis_txdesc[prod].tx_dmamap = map; 1866 sc->sis_txdesc[prod].tx_m = *m_head; 1867 1868 return (0); 1869 } 1870 1871 static void 1872 sis_start(if_t ifp) 1873 { 1874 struct sis_softc *sc; 1875 1876 sc = if_getsoftc(ifp); 1877 SIS_LOCK(sc); 1878 sis_startl(ifp); 1879 SIS_UNLOCK(sc); 1880 } 1881 1882 static void 1883 sis_startl(if_t ifp) 1884 { 1885 struct sis_softc *sc; 1886 struct mbuf *m_head; 1887 int queued; 1888 1889 sc = if_getsoftc(ifp); 1890 1891 SIS_LOCK_ASSERT(sc); 1892 1893 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1894 IFF_DRV_RUNNING || (sc->sis_flags & SIS_FLAG_LINK) == 0) 1895 return; 1896 1897 for (queued = 0; !if_sendq_empty(ifp) && 1898 sc->sis_tx_cnt < SIS_TX_LIST_CNT - 4;) { 1899 m_head = if_dequeue(ifp); 1900 if (m_head == NULL) 1901 break; 1902 1903 if (sis_encap(sc, &m_head) != 0) { 1904 if (m_head == NULL) 1905 break; 1906 if_sendq_prepend(ifp, m_head); 1907 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1908 break; 1909 } 1910 1911 queued++; 1912 1913 /* 1914 * If there's a BPF listener, bounce a copy of this frame 1915 * to him. 1916 */ 1917 BPF_MTAP(ifp, m_head); 1918 } 1919 1920 if (queued) { 1921 /* Transmit */ 1922 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, 1923 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1924 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1925 1926 /* 1927 * Set a timeout in case the chip goes out to lunch. 1928 */ 1929 sc->sis_watchdog_timer = 5; 1930 } 1931 } 1932 1933 static void 1934 sis_init(void *xsc) 1935 { 1936 struct sis_softc *sc = xsc; 1937 1938 SIS_LOCK(sc); 1939 sis_initl(sc); 1940 SIS_UNLOCK(sc); 1941 } 1942 1943 static void 1944 sis_initl(struct sis_softc *sc) 1945 { 1946 if_t ifp = sc->sis_ifp; 1947 struct mii_data *mii; 1948 uint8_t *eaddr; 1949 1950 SIS_LOCK_ASSERT(sc); 1951 1952 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1953 return; 1954 1955 /* 1956 * Cancel pending I/O and free all RX/TX buffers. 1957 */ 1958 sis_stop(sc); 1959 /* 1960 * Reset the chip to a known state. 1961 */ 1962 sis_reset(sc); 1963 #ifdef notyet 1964 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 1965 /* 1966 * Configure 400usec of interrupt holdoff. This is based 1967 * on empirical tests on a Soekris 4801. 1968 */ 1969 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); 1970 } 1971 #endif 1972 1973 mii = device_get_softc(sc->sis_miibus); 1974 1975 /* Set MAC address */ 1976 eaddr = if_getlladdr(sc->sis_ifp); 1977 if (sc->sis_type == SIS_TYPE_83815) { 1978 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1979 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8); 1980 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1981 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8); 1982 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1983 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8); 1984 } else { 1985 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1986 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8); 1987 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1988 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8); 1989 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1990 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8); 1991 } 1992 1993 /* Init circular TX/RX lists. */ 1994 if (sis_ring_init(sc) != 0) { 1995 device_printf(sc->sis_dev, 1996 "initialization failed: no memory for rx buffers\n"); 1997 sis_stop(sc); 1998 return; 1999 } 2000 2001 if (sc->sis_type == SIS_TYPE_83815) { 2002 if (sc->sis_manual_pad != 0) 2003 sc->sis_flags |= SIS_FLAG_MANUAL_PAD; 2004 else 2005 sc->sis_flags &= ~SIS_FLAG_MANUAL_PAD; 2006 } 2007 2008 /* 2009 * Short Cable Receive Errors (MP21.E) 2010 * also: Page 78 of the DP83815 data sheet (september 2002 version) 2011 * recommends the following register settings "for optimum 2012 * performance." for rev 15C. Set this also for 15D parts as 2013 * they require it in practice. 2014 */ 2015 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) { 2016 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2017 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2018 /* set val for c2 */ 2019 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2020 /* load/kill c2 */ 2021 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2022 /* rais SD off, from 4 to c */ 2023 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2024 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2025 } 2026 2027 sis_rxfilter(sc); 2028 2029 /* 2030 * Load the address of the RX and TX lists. 2031 */ 2032 CSR_WRITE_4(sc, SIS_RX_LISTPTR, SIS_ADDR_LO(sc->sis_rx_paddr)); 2033 CSR_WRITE_4(sc, SIS_TX_LISTPTR, SIS_ADDR_LO(sc->sis_tx_paddr)); 2034 2035 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 2036 * the PCI bus. When this bit is set, the Max DMA Burst Size 2037 * for TX/RX DMA should be no larger than 16 double words. 2038 */ 2039 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 2040 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 2041 } else { 2042 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 2043 } 2044 2045 /* Accept Long Packets for VLAN support */ 2046 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 2047 2048 /* 2049 * Assume 100Mbps link, actual MAC configuration is done 2050 * after getting a valid link. 2051 */ 2052 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 2053 2054 /* 2055 * Enable interrupts. 2056 */ 2057 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2058 #ifdef DEVICE_POLLING 2059 /* 2060 * ... only enable interrupts if we are not polling, make sure 2061 * they are off otherwise. 2062 */ 2063 if (if_getcapenable(ifp) & IFCAP_POLLING) 2064 CSR_WRITE_4(sc, SIS_IER, 0); 2065 else 2066 #endif 2067 CSR_WRITE_4(sc, SIS_IER, 1); 2068 2069 /* Clear MAC disable. */ 2070 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE); 2071 2072 sc->sis_flags &= ~SIS_FLAG_LINK; 2073 mii_mediachg(mii); 2074 2075 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2076 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2077 2078 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 2079 } 2080 2081 /* 2082 * Set media options. 2083 */ 2084 static int 2085 sis_ifmedia_upd(if_t ifp) 2086 { 2087 struct sis_softc *sc; 2088 struct mii_data *mii; 2089 struct mii_softc *miisc; 2090 int error; 2091 2092 sc = if_getsoftc(ifp); 2093 2094 SIS_LOCK(sc); 2095 mii = device_get_softc(sc->sis_miibus); 2096 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2097 PHY_RESET(miisc); 2098 error = mii_mediachg(mii); 2099 SIS_UNLOCK(sc); 2100 2101 return (error); 2102 } 2103 2104 /* 2105 * Report current media status. 2106 */ 2107 static void 2108 sis_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 2109 { 2110 struct sis_softc *sc; 2111 struct mii_data *mii; 2112 2113 sc = if_getsoftc(ifp); 2114 2115 SIS_LOCK(sc); 2116 mii = device_get_softc(sc->sis_miibus); 2117 mii_pollstat(mii); 2118 ifmr->ifm_active = mii->mii_media_active; 2119 ifmr->ifm_status = mii->mii_media_status; 2120 SIS_UNLOCK(sc); 2121 } 2122 2123 static int 2124 sis_ioctl(if_t ifp, u_long command, caddr_t data) 2125 { 2126 struct sis_softc *sc = if_getsoftc(ifp); 2127 struct ifreq *ifr = (struct ifreq *) data; 2128 struct mii_data *mii; 2129 int error = 0, mask; 2130 2131 switch (command) { 2132 case SIOCSIFFLAGS: 2133 SIS_LOCK(sc); 2134 if (if_getflags(ifp) & IFF_UP) { 2135 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 2136 ((if_getflags(ifp) ^ sc->sis_if_flags) & 2137 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2138 sis_rxfilter(sc); 2139 else 2140 sis_initl(sc); 2141 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2142 sis_stop(sc); 2143 sc->sis_if_flags = if_getflags(ifp); 2144 SIS_UNLOCK(sc); 2145 break; 2146 case SIOCADDMULTI: 2147 case SIOCDELMULTI: 2148 SIS_LOCK(sc); 2149 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2150 sis_rxfilter(sc); 2151 SIS_UNLOCK(sc); 2152 break; 2153 case SIOCGIFMEDIA: 2154 case SIOCSIFMEDIA: 2155 mii = device_get_softc(sc->sis_miibus); 2156 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2157 break; 2158 case SIOCSIFCAP: 2159 SIS_LOCK(sc); 2160 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 2161 #ifdef DEVICE_POLLING 2162 if ((mask & IFCAP_POLLING) != 0 && 2163 (IFCAP_POLLING & if_getcapabilities(ifp)) != 0) { 2164 if_togglecapenable(ifp, IFCAP_POLLING); 2165 if ((IFCAP_POLLING & if_getcapenable(ifp)) != 0) { 2166 error = ether_poll_register(sis_poll, ifp); 2167 if (error != 0) { 2168 SIS_UNLOCK(sc); 2169 break; 2170 } 2171 /* Disable interrupts. */ 2172 CSR_WRITE_4(sc, SIS_IER, 0); 2173 } else { 2174 error = ether_poll_deregister(ifp); 2175 /* Enable interrupts. */ 2176 CSR_WRITE_4(sc, SIS_IER, 1); 2177 } 2178 } 2179 #endif /* DEVICE_POLLING */ 2180 if ((mask & IFCAP_WOL) != 0 && 2181 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) { 2182 if ((mask & IFCAP_WOL_UCAST) != 0) 2183 if_togglecapenable(ifp, IFCAP_WOL_UCAST); 2184 if ((mask & IFCAP_WOL_MCAST) != 0) 2185 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 2186 if ((mask & IFCAP_WOL_MAGIC) != 0) 2187 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 2188 } 2189 SIS_UNLOCK(sc); 2190 break; 2191 default: 2192 error = ether_ioctl(ifp, command, data); 2193 break; 2194 } 2195 2196 return (error); 2197 } 2198 2199 static void 2200 sis_watchdog(struct sis_softc *sc) 2201 { 2202 2203 SIS_LOCK_ASSERT(sc); 2204 2205 if (sc->sis_watchdog_timer == 0 || --sc->sis_watchdog_timer >0) 2206 return; 2207 2208 device_printf(sc->sis_dev, "watchdog timeout\n"); 2209 if_inc_counter(sc->sis_ifp, IFCOUNTER_OERRORS, 1); 2210 2211 if_setdrvflagbits(sc->sis_ifp, 0, IFF_DRV_RUNNING); 2212 sis_initl(sc); 2213 2214 if (!if_sendq_empty(sc->sis_ifp)) 2215 sis_startl(sc->sis_ifp); 2216 } 2217 2218 /* 2219 * Stop the adapter and free any mbufs allocated to the 2220 * RX and TX lists. 2221 */ 2222 static void 2223 sis_stop(struct sis_softc *sc) 2224 { 2225 if_t ifp; 2226 struct sis_rxdesc *rxd; 2227 struct sis_txdesc *txd; 2228 int i; 2229 2230 SIS_LOCK_ASSERT(sc); 2231 2232 ifp = sc->sis_ifp; 2233 sc->sis_watchdog_timer = 0; 2234 2235 callout_stop(&sc->sis_stat_ch); 2236 2237 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2238 CSR_WRITE_4(sc, SIS_IER, 0); 2239 CSR_WRITE_4(sc, SIS_IMR, 0); 2240 CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */ 2241 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2242 DELAY(1000); 2243 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2244 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2245 2246 sc->sis_flags &= ~SIS_FLAG_LINK; 2247 2248 /* 2249 * Free data in the RX lists. 2250 */ 2251 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2252 rxd = &sc->sis_rxdesc[i]; 2253 if (rxd->rx_m != NULL) { 2254 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, 2255 BUS_DMASYNC_POSTREAD); 2256 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap); 2257 m_freem(rxd->rx_m); 2258 rxd->rx_m = NULL; 2259 } 2260 } 2261 2262 /* 2263 * Free the TX list buffers. 2264 */ 2265 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2266 txd = &sc->sis_txdesc[i]; 2267 if (txd->tx_m != NULL) { 2268 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, 2269 BUS_DMASYNC_POSTWRITE); 2270 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); 2271 m_freem(txd->tx_m); 2272 txd->tx_m = NULL; 2273 } 2274 } 2275 } 2276 2277 /* 2278 * Stop all chip I/O so that the kernel's probe routines don't 2279 * get confused by errant DMAs when rebooting. 2280 */ 2281 static int 2282 sis_shutdown(device_t dev) 2283 { 2284 2285 return (sis_suspend(dev)); 2286 } 2287 2288 static int 2289 sis_suspend(device_t dev) 2290 { 2291 struct sis_softc *sc; 2292 2293 sc = device_get_softc(dev); 2294 SIS_LOCK(sc); 2295 sis_stop(sc); 2296 sis_wol(sc); 2297 SIS_UNLOCK(sc); 2298 return (0); 2299 } 2300 2301 static int 2302 sis_resume(device_t dev) 2303 { 2304 struct sis_softc *sc; 2305 if_t ifp; 2306 2307 sc = device_get_softc(dev); 2308 SIS_LOCK(sc); 2309 ifp = sc->sis_ifp; 2310 if ((if_getflags(ifp) & IFF_UP) != 0) { 2311 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2312 sis_initl(sc); 2313 } 2314 SIS_UNLOCK(sc); 2315 return (0); 2316 } 2317 2318 static void 2319 sis_wol(struct sis_softc *sc) 2320 { 2321 if_t ifp; 2322 uint32_t val; 2323 uint16_t pmstat; 2324 int pmc; 2325 2326 ifp = sc->sis_ifp; 2327 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) 2328 return; 2329 2330 if (sc->sis_type == SIS_TYPE_83815) { 2331 /* Reset RXDP. */ 2332 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2333 2334 /* Configure WOL events. */ 2335 CSR_READ_4(sc, NS_WCSR); 2336 val = 0; 2337 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) != 0) 2338 val |= NS_WCSR_WAKE_UCAST; 2339 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 2340 val |= NS_WCSR_WAKE_MCAST; 2341 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2342 val |= NS_WCSR_WAKE_MAGIC; 2343 CSR_WRITE_4(sc, NS_WCSR, val); 2344 /* Enable PME and clear PMESTS. */ 2345 val = CSR_READ_4(sc, NS_CLKRUN); 2346 val |= NS_CLKRUN_PMEENB | NS_CLKRUN_PMESTS; 2347 CSR_WRITE_4(sc, NS_CLKRUN, val); 2348 /* Enable silent RX mode. */ 2349 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2350 } else { 2351 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) != 0) 2352 return; 2353 val = 0; 2354 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2355 val |= SIS_PWRMAN_WOL_MAGIC; 2356 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, val); 2357 /* Request PME. */ 2358 pmstat = pci_read_config(sc->sis_dev, 2359 pmc + PCIR_POWER_STATUS, 2); 2360 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2361 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2362 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2363 pci_write_config(sc->sis_dev, 2364 pmc + PCIR_POWER_STATUS, pmstat, 2); 2365 } 2366 } 2367 2368 static void 2369 sis_add_sysctls(struct sis_softc *sc) 2370 { 2371 struct sysctl_ctx_list *ctx; 2372 struct sysctl_oid_list *children; 2373 2374 ctx = device_get_sysctl_ctx(sc->sis_dev); 2375 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sis_dev)); 2376 2377 /* 2378 * Unlike most other controllers, NS DP83815/DP83816 controllers 2379 * seem to pad with 0xFF when it encounter short frames. According 2380 * to RFC 1042 the pad bytes should be 0x00. Turning this tunable 2381 * on will have driver pad manully but it's disabled by default 2382 * because it will consume extra CPU cycles for short frames. 2383 */ 2384 sc->sis_manual_pad = 0; 2385 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "manual_pad", 2386 CTLFLAG_RWTUN, &sc->sis_manual_pad, 0, "Manually pad short frames"); 2387 } 2388 2389 static device_method_t sis_methods[] = { 2390 /* Device interface */ 2391 DEVMETHOD(device_probe, sis_probe), 2392 DEVMETHOD(device_attach, sis_attach), 2393 DEVMETHOD(device_detach, sis_detach), 2394 DEVMETHOD(device_shutdown, sis_shutdown), 2395 DEVMETHOD(device_suspend, sis_suspend), 2396 DEVMETHOD(device_resume, sis_resume), 2397 2398 /* MII interface */ 2399 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 2400 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 2401 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 2402 2403 DEVMETHOD_END 2404 }; 2405 2406 static driver_t sis_driver = { 2407 "sis", 2408 sis_methods, 2409 sizeof(struct sis_softc) 2410 }; 2411 2412 DRIVER_MODULE(sis, pci, sis_driver, 0, 0); 2413 DRIVER_MODULE(miibus, sis, miibus_driver, 0, 0); 2414