1 /*- 2 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org> 3 * Copyright (c) 1997, 1998, 1999 4 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 39 * available from http://www.sis.com.tw. 40 * 41 * This driver also supports the NatSemi DP83815. Datasheets are 42 * available from http://www.national.com. 43 * 44 * Written by Bill Paul <wpaul@ee.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 /* 49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 50 * simple TX and RX descriptors of 3 longwords in size. The receiver 51 * has a single perfect filter entry for the station address and a 52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 53 * transceiver while the 7016 requires an external transceiver chip. 54 * Both chips offer the standard bit-bang MII interface as well as 55 * an enchanced PHY interface which simplifies accessing MII registers. 56 * 57 * The only downside to this chipset is that RX descriptors must be 58 * longword aligned. 59 */ 60 61 #ifdef HAVE_KERNEL_OPTION_HEADERS 62 #include "opt_device_polling.h" 63 #endif 64 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/bus.h> 68 #include <sys/endian.h> 69 #include <sys/kernel.h> 70 #include <sys/lock.h> 71 #include <sys/malloc.h> 72 #include <sys/mbuf.h> 73 #include <sys/module.h> 74 #include <sys/socket.h> 75 #include <sys/sockio.h> 76 #include <sys/sysctl.h> 77 78 #include <net/if.h> 79 #include <net/if_arp.h> 80 #include <net/ethernet.h> 81 #include <net/if_dl.h> 82 #include <net/if_media.h> 83 #include <net/if_types.h> 84 #include <net/if_vlan_var.h> 85 86 #include <net/bpf.h> 87 88 #include <machine/bus.h> 89 #include <machine/resource.h> 90 #include <sys/bus.h> 91 #include <sys/rman.h> 92 93 #include <dev/mii/mii.h> 94 #include <dev/mii/miivar.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 99 #define SIS_USEIOSPACE 100 101 #include <dev/sis/if_sisreg.h> 102 103 MODULE_DEPEND(sis, pci, 1, 1, 1); 104 MODULE_DEPEND(sis, ether, 1, 1, 1); 105 MODULE_DEPEND(sis, miibus, 1, 1, 1); 106 107 /* "device miibus" required. See GENERIC if you get errors here. */ 108 #include "miibus_if.h" 109 110 #define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx) 111 #define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx) 112 #define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED) 113 114 /* 115 * register space access macros 116 */ 117 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val) 118 119 #define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg) 120 121 #define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg) 122 123 /* 124 * Various supported device vendors/types and their names. 125 */ 126 static struct sis_type sis_devs[] = { 127 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 128 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 129 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 130 { 0, 0, NULL } 131 }; 132 133 static int sis_detach(device_t); 134 static __inline void sis_discard_rxbuf(struct sis_rxdesc *); 135 static int sis_dma_alloc(struct sis_softc *); 136 static void sis_dma_free(struct sis_softc *); 137 static int sis_dma_ring_alloc(struct sis_softc *, bus_size_t, bus_size_t, 138 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 139 static void sis_dmamap_cb(void *, bus_dma_segment_t *, int, int); 140 #ifndef __NO_STRICT_ALIGNMENT 141 static __inline void sis_fixup_rx(struct mbuf *); 142 #endif 143 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *); 144 static int sis_ifmedia_upd(struct ifnet *); 145 static void sis_init(void *); 146 static void sis_initl(struct sis_softc *); 147 static void sis_intr(void *); 148 static int sis_ioctl(struct ifnet *, u_long, caddr_t); 149 static int sis_newbuf(struct sis_softc *, struct sis_rxdesc *); 150 static int sis_resume(device_t); 151 static int sis_rxeof(struct sis_softc *); 152 static void sis_rxfilter(struct sis_softc *); 153 static void sis_rxfilter_ns(struct sis_softc *); 154 static void sis_rxfilter_sis(struct sis_softc *); 155 static void sis_start(struct ifnet *); 156 static void sis_startl(struct ifnet *); 157 static void sis_stop(struct sis_softc *); 158 static int sis_suspend(device_t); 159 static void sis_add_sysctls(struct sis_softc *); 160 static void sis_watchdog(struct sis_softc *); 161 static void sis_wol(struct sis_softc *); 162 163 164 static struct resource_spec sis_res_spec[] = { 165 #ifdef SIS_USEIOSPACE 166 { SYS_RES_IOPORT, SIS_PCI_LOIO, RF_ACTIVE}, 167 #else 168 { SYS_RES_MEMORY, SIS_PCI_LOMEM, RF_ACTIVE}, 169 #endif 170 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE}, 171 { -1, 0 } 172 }; 173 174 #define SIS_SETBIT(sc, reg, x) \ 175 CSR_WRITE_4(sc, reg, \ 176 CSR_READ_4(sc, reg) | (x)) 177 178 #define SIS_CLRBIT(sc, reg, x) \ 179 CSR_WRITE_4(sc, reg, \ 180 CSR_READ_4(sc, reg) & ~(x)) 181 182 #define SIO_SET(x) \ 183 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 184 185 #define SIO_CLR(x) \ 186 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 187 188 /* 189 * Routine to reverse the bits in a word. Stolen almost 190 * verbatim from /usr/games/fortune. 191 */ 192 static uint16_t 193 sis_reverse(uint16_t n) 194 { 195 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 196 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 197 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 198 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 199 200 return (n); 201 } 202 203 static void 204 sis_delay(struct sis_softc *sc) 205 { 206 int idx; 207 208 for (idx = (300 / 33) + 1; idx > 0; idx--) 209 CSR_READ_4(sc, SIS_CSR); 210 } 211 212 static void 213 sis_eeprom_idle(struct sis_softc *sc) 214 { 215 int i; 216 217 SIO_SET(SIS_EECTL_CSEL); 218 sis_delay(sc); 219 SIO_SET(SIS_EECTL_CLK); 220 sis_delay(sc); 221 222 for (i = 0; i < 25; i++) { 223 SIO_CLR(SIS_EECTL_CLK); 224 sis_delay(sc); 225 SIO_SET(SIS_EECTL_CLK); 226 sis_delay(sc); 227 } 228 229 SIO_CLR(SIS_EECTL_CLK); 230 sis_delay(sc); 231 SIO_CLR(SIS_EECTL_CSEL); 232 sis_delay(sc); 233 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 234 } 235 236 /* 237 * Send a read command and address to the EEPROM, check for ACK. 238 */ 239 static void 240 sis_eeprom_putbyte(struct sis_softc *sc, int addr) 241 { 242 int d, i; 243 244 d = addr | SIS_EECMD_READ; 245 246 /* 247 * Feed in each bit and stobe the clock. 248 */ 249 for (i = 0x400; i; i >>= 1) { 250 if (d & i) { 251 SIO_SET(SIS_EECTL_DIN); 252 } else { 253 SIO_CLR(SIS_EECTL_DIN); 254 } 255 sis_delay(sc); 256 SIO_SET(SIS_EECTL_CLK); 257 sis_delay(sc); 258 SIO_CLR(SIS_EECTL_CLK); 259 sis_delay(sc); 260 } 261 } 262 263 /* 264 * Read a word of data stored in the EEPROM at address 'addr.' 265 */ 266 static void 267 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 268 { 269 int i; 270 uint16_t word = 0; 271 272 /* Force EEPROM to idle state. */ 273 sis_eeprom_idle(sc); 274 275 /* Enter EEPROM access mode. */ 276 sis_delay(sc); 277 SIO_CLR(SIS_EECTL_CLK); 278 sis_delay(sc); 279 SIO_SET(SIS_EECTL_CSEL); 280 sis_delay(sc); 281 282 /* 283 * Send address of word we want to read. 284 */ 285 sis_eeprom_putbyte(sc, addr); 286 287 /* 288 * Start reading bits from EEPROM. 289 */ 290 for (i = 0x8000; i; i >>= 1) { 291 SIO_SET(SIS_EECTL_CLK); 292 sis_delay(sc); 293 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 294 word |= i; 295 sis_delay(sc); 296 SIO_CLR(SIS_EECTL_CLK); 297 sis_delay(sc); 298 } 299 300 /* Turn off EEPROM access mode. */ 301 sis_eeprom_idle(sc); 302 303 *dest = word; 304 } 305 306 /* 307 * Read a sequence of words from the EEPROM. 308 */ 309 static void 310 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 311 { 312 int i; 313 uint16_t word = 0, *ptr; 314 315 for (i = 0; i < cnt; i++) { 316 sis_eeprom_getword(sc, off + i, &word); 317 ptr = (uint16_t *)(dest + (i * 2)); 318 if (swap) 319 *ptr = ntohs(word); 320 else 321 *ptr = word; 322 } 323 } 324 325 #if defined(__i386__) || defined(__amd64__) 326 static device_t 327 sis_find_bridge(device_t dev) 328 { 329 devclass_t pci_devclass; 330 device_t *pci_devices; 331 int pci_count = 0; 332 device_t *pci_children; 333 int pci_childcount = 0; 334 device_t *busp, *childp; 335 device_t child = NULL; 336 int i, j; 337 338 if ((pci_devclass = devclass_find("pci")) == NULL) 339 return (NULL); 340 341 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 342 343 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 344 if (device_get_children(*busp, &pci_children, &pci_childcount)) 345 continue; 346 for (j = 0, childp = pci_children; 347 j < pci_childcount; j++, childp++) { 348 if (pci_get_vendor(*childp) == SIS_VENDORID && 349 pci_get_device(*childp) == 0x0008) { 350 child = *childp; 351 free(pci_children, M_TEMP); 352 goto done; 353 } 354 } 355 free(pci_children, M_TEMP); 356 } 357 358 done: 359 free(pci_devices, M_TEMP); 360 return (child); 361 } 362 363 static void 364 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt) 365 { 366 device_t bridge; 367 uint8_t reg; 368 int i; 369 bus_space_tag_t btag; 370 371 bridge = sis_find_bridge(dev); 372 if (bridge == NULL) 373 return; 374 reg = pci_read_config(bridge, 0x48, 1); 375 pci_write_config(bridge, 0x48, reg|0x40, 1); 376 377 /* XXX */ 378 #if defined(__amd64__) || defined(__i386__) 379 btag = X86_BUS_SPACE_IO; 380 #endif 381 382 for (i = 0; i < cnt; i++) { 383 bus_space_write_1(btag, 0x0, 0x70, i + off); 384 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 385 } 386 387 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 388 } 389 390 static void 391 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 392 { 393 uint32_t filtsave, csrsave; 394 395 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 396 csrsave = CSR_READ_4(sc, SIS_CSR); 397 398 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 399 CSR_WRITE_4(sc, SIS_CSR, 0); 400 401 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 402 403 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 404 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 405 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 406 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 407 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 408 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 409 410 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 411 CSR_WRITE_4(sc, SIS_CSR, csrsave); 412 } 413 #endif 414 415 /* 416 * Sync the PHYs by setting data bit and strobing the clock 32 times. 417 */ 418 static void 419 sis_mii_sync(struct sis_softc *sc) 420 { 421 int i; 422 423 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 424 425 for (i = 0; i < 32; i++) { 426 SIO_SET(SIS_MII_CLK); 427 DELAY(1); 428 SIO_CLR(SIS_MII_CLK); 429 DELAY(1); 430 } 431 } 432 433 /* 434 * Clock a series of bits through the MII. 435 */ 436 static void 437 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt) 438 { 439 int i; 440 441 SIO_CLR(SIS_MII_CLK); 442 443 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 444 if (bits & i) { 445 SIO_SET(SIS_MII_DATA); 446 } else { 447 SIO_CLR(SIS_MII_DATA); 448 } 449 DELAY(1); 450 SIO_CLR(SIS_MII_CLK); 451 DELAY(1); 452 SIO_SET(SIS_MII_CLK); 453 } 454 } 455 456 /* 457 * Read an PHY register through the MII. 458 */ 459 static int 460 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) 461 { 462 int i, ack; 463 464 /* 465 * Set up frame for RX. 466 */ 467 frame->mii_stdelim = SIS_MII_STARTDELIM; 468 frame->mii_opcode = SIS_MII_READOP; 469 frame->mii_turnaround = 0; 470 frame->mii_data = 0; 471 472 /* 473 * Turn on data xmit. 474 */ 475 SIO_SET(SIS_MII_DIR); 476 477 sis_mii_sync(sc); 478 479 /* 480 * Send command/address info. 481 */ 482 sis_mii_send(sc, frame->mii_stdelim, 2); 483 sis_mii_send(sc, frame->mii_opcode, 2); 484 sis_mii_send(sc, frame->mii_phyaddr, 5); 485 sis_mii_send(sc, frame->mii_regaddr, 5); 486 487 /* Idle bit */ 488 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 489 DELAY(1); 490 SIO_SET(SIS_MII_CLK); 491 DELAY(1); 492 493 /* Turn off xmit. */ 494 SIO_CLR(SIS_MII_DIR); 495 496 /* Check for ack */ 497 SIO_CLR(SIS_MII_CLK); 498 DELAY(1); 499 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 500 SIO_SET(SIS_MII_CLK); 501 DELAY(1); 502 503 /* 504 * Now try reading data bits. If the ack failed, we still 505 * need to clock through 16 cycles to keep the PHY(s) in sync. 506 */ 507 if (ack) { 508 for (i = 0; i < 16; i++) { 509 SIO_CLR(SIS_MII_CLK); 510 DELAY(1); 511 SIO_SET(SIS_MII_CLK); 512 DELAY(1); 513 } 514 goto fail; 515 } 516 517 for (i = 0x8000; i; i >>= 1) { 518 SIO_CLR(SIS_MII_CLK); 519 DELAY(1); 520 if (!ack) { 521 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 522 frame->mii_data |= i; 523 DELAY(1); 524 } 525 SIO_SET(SIS_MII_CLK); 526 DELAY(1); 527 } 528 529 fail: 530 531 SIO_CLR(SIS_MII_CLK); 532 DELAY(1); 533 SIO_SET(SIS_MII_CLK); 534 DELAY(1); 535 536 if (ack) 537 return (1); 538 return (0); 539 } 540 541 /* 542 * Write to a PHY register through the MII. 543 */ 544 static int 545 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame) 546 { 547 548 /* 549 * Set up frame for TX. 550 */ 551 552 frame->mii_stdelim = SIS_MII_STARTDELIM; 553 frame->mii_opcode = SIS_MII_WRITEOP; 554 frame->mii_turnaround = SIS_MII_TURNAROUND; 555 556 /* 557 * Turn on data output. 558 */ 559 SIO_SET(SIS_MII_DIR); 560 561 sis_mii_sync(sc); 562 563 sis_mii_send(sc, frame->mii_stdelim, 2); 564 sis_mii_send(sc, frame->mii_opcode, 2); 565 sis_mii_send(sc, frame->mii_phyaddr, 5); 566 sis_mii_send(sc, frame->mii_regaddr, 5); 567 sis_mii_send(sc, frame->mii_turnaround, 2); 568 sis_mii_send(sc, frame->mii_data, 16); 569 570 /* Idle bit. */ 571 SIO_SET(SIS_MII_CLK); 572 DELAY(1); 573 SIO_CLR(SIS_MII_CLK); 574 DELAY(1); 575 576 /* 577 * Turn off xmit. 578 */ 579 SIO_CLR(SIS_MII_DIR); 580 581 return (0); 582 } 583 584 static int 585 sis_miibus_readreg(device_t dev, int phy, int reg) 586 { 587 struct sis_softc *sc; 588 struct sis_mii_frame frame; 589 590 sc = device_get_softc(dev); 591 592 if (sc->sis_type == SIS_TYPE_83815) { 593 if (phy != 0) 594 return (0); 595 /* 596 * The NatSemi chip can take a while after 597 * a reset to come ready, during which the BMSR 598 * returns a value of 0. This is *never* supposed 599 * to happen: some of the BMSR bits are meant to 600 * be hardwired in the on position, and this can 601 * confuse the miibus code a bit during the probe 602 * and attach phase. So we make an effort to check 603 * for this condition and wait for it to clear. 604 */ 605 if (!CSR_READ_4(sc, NS_BMSR)) 606 DELAY(1000); 607 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 608 } 609 610 /* 611 * Chipsets < SIS_635 seem not to be able to read/write 612 * through mdio. Use the enhanced PHY access register 613 * again for them. 614 */ 615 if (sc->sis_type == SIS_TYPE_900 && 616 sc->sis_rev < SIS_REV_635) { 617 int i, val = 0; 618 619 if (phy != 0) 620 return (0); 621 622 CSR_WRITE_4(sc, SIS_PHYCTL, 623 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 624 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 625 626 for (i = 0; i < SIS_TIMEOUT; i++) { 627 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 628 break; 629 } 630 631 if (i == SIS_TIMEOUT) { 632 device_printf(sc->sis_dev, "PHY failed to come ready\n"); 633 return (0); 634 } 635 636 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 637 638 if (val == 0xFFFF) 639 return (0); 640 641 return (val); 642 } else { 643 bzero((char *)&frame, sizeof(frame)); 644 645 frame.mii_phyaddr = phy; 646 frame.mii_regaddr = reg; 647 sis_mii_readreg(sc, &frame); 648 649 return (frame.mii_data); 650 } 651 } 652 653 static int 654 sis_miibus_writereg(device_t dev, int phy, int reg, int data) 655 { 656 struct sis_softc *sc; 657 struct sis_mii_frame frame; 658 659 sc = device_get_softc(dev); 660 661 if (sc->sis_type == SIS_TYPE_83815) { 662 if (phy != 0) 663 return (0); 664 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 665 return (0); 666 } 667 668 /* 669 * Chipsets < SIS_635 seem not to be able to read/write 670 * through mdio. Use the enhanced PHY access register 671 * again for them. 672 */ 673 if (sc->sis_type == SIS_TYPE_900 && 674 sc->sis_rev < SIS_REV_635) { 675 int i; 676 677 if (phy != 0) 678 return (0); 679 680 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 681 (reg << 6) | SIS_PHYOP_WRITE); 682 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 683 684 for (i = 0; i < SIS_TIMEOUT; i++) { 685 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 686 break; 687 } 688 689 if (i == SIS_TIMEOUT) 690 device_printf(sc->sis_dev, "PHY failed to come ready\n"); 691 } else { 692 bzero((char *)&frame, sizeof(frame)); 693 694 frame.mii_phyaddr = phy; 695 frame.mii_regaddr = reg; 696 frame.mii_data = data; 697 sis_mii_writereg(sc, &frame); 698 } 699 return (0); 700 } 701 702 static void 703 sis_miibus_statchg(device_t dev) 704 { 705 struct sis_softc *sc; 706 struct mii_data *mii; 707 struct ifnet *ifp; 708 uint32_t reg; 709 710 sc = device_get_softc(dev); 711 SIS_LOCK_ASSERT(sc); 712 713 mii = device_get_softc(sc->sis_miibus); 714 ifp = sc->sis_ifp; 715 if (mii == NULL || ifp == NULL || 716 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 717 return; 718 719 sc->sis_flags &= ~SIS_FLAG_LINK; 720 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 721 (IFM_ACTIVE | IFM_AVALID)) { 722 switch (IFM_SUBTYPE(mii->mii_media_active)) { 723 case IFM_10_T: 724 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 725 sc->sis_flags |= SIS_FLAG_LINK; 726 break; 727 case IFM_100_TX: 728 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 729 sc->sis_flags |= SIS_FLAG_LINK; 730 break; 731 default: 732 break; 733 } 734 } 735 736 if ((sc->sis_flags & SIS_FLAG_LINK) == 0) { 737 /* 738 * Stopping MACs seem to reset SIS_TX_LISTPTR and 739 * SIS_RX_LISTPTR which in turn requires resetting 740 * TX/RX buffers. So just don't do anything for 741 * lost link. 742 */ 743 return; 744 } 745 746 /* Set full/half duplex mode. */ 747 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 748 SIS_SETBIT(sc, SIS_TX_CFG, 749 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR)); 750 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 751 } else { 752 SIS_CLRBIT(sc, SIS_TX_CFG, 753 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR)); 754 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 755 } 756 757 if (sc->sis_type == SIS_TYPE_83816) { 758 /* 759 * MPII03.D: Half Duplex Excessive Collisions. 760 * Also page 49 in 83816 manual 761 */ 762 SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D); 763 } 764 765 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && 766 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 767 /* 768 * Short Cable Receive Errors (MP21.E) 769 */ 770 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 771 reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff; 772 CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000); 773 DELAY(100); 774 reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff; 775 if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) { 776 device_printf(sc->sis_dev, 777 "Applying short cable fix (reg=%x)\n", reg); 778 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); 779 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20); 780 } 781 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 782 } 783 /* Enable TX/RX MACs. */ 784 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE); 785 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE | SIS_CSR_RX_ENABLE); 786 } 787 788 static uint32_t 789 sis_mchash(struct sis_softc *sc, const uint8_t *addr) 790 { 791 uint32_t crc; 792 793 /* Compute CRC for the address value. */ 794 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 795 796 /* 797 * return the filter bit position 798 * 799 * The NatSemi chip has a 512-bit filter, which is 800 * different than the SiS, so we special-case it. 801 */ 802 if (sc->sis_type == SIS_TYPE_83815) 803 return (crc >> 23); 804 else if (sc->sis_rev >= SIS_REV_635 || 805 sc->sis_rev == SIS_REV_900B) 806 return (crc >> 24); 807 else 808 return (crc >> 25); 809 } 810 811 static void 812 sis_rxfilter(struct sis_softc *sc) 813 { 814 815 SIS_LOCK_ASSERT(sc); 816 817 if (sc->sis_type == SIS_TYPE_83815) 818 sis_rxfilter_ns(sc); 819 else 820 sis_rxfilter_sis(sc); 821 } 822 823 static void 824 sis_rxfilter_ns(struct sis_softc *sc) 825 { 826 struct ifnet *ifp; 827 struct ifmultiaddr *ifma; 828 uint32_t h, i, filter; 829 int bit, index; 830 831 ifp = sc->sis_ifp; 832 filter = CSR_READ_4(sc, SIS_RXFILT_CTL); 833 if (filter & SIS_RXFILTCTL_ENABLE) { 834 /* 835 * Filter should be disabled to program other bits. 836 */ 837 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE); 838 CSR_READ_4(sc, SIS_RXFILT_CTL); 839 } 840 filter &= ~(NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT | 841 NS_RXFILTCTL_MCHASH | SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD | 842 SIS_RXFILTCTL_ALLMULTI); 843 844 if (ifp->if_flags & IFF_BROADCAST) 845 filter |= SIS_RXFILTCTL_BROAD; 846 /* 847 * For the NatSemi chip, we have to explicitly enable the 848 * reception of ARP frames, as well as turn on the 'perfect 849 * match' filter where we store the station address, otherwise 850 * we won't receive unicasts meant for this host. 851 */ 852 filter |= NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT; 853 854 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 855 filter |= SIS_RXFILTCTL_ALLMULTI; 856 if (ifp->if_flags & IFF_PROMISC) 857 filter |= SIS_RXFILTCTL_ALLPHYS; 858 } else { 859 /* 860 * We have to explicitly enable the multicast hash table 861 * on the NatSemi chip if we want to use it, which we do. 862 */ 863 filter |= NS_RXFILTCTL_MCHASH; 864 865 /* first, zot all the existing hash bits */ 866 for (i = 0; i < 32; i++) { 867 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + 868 (i * 2)); 869 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 870 } 871 872 if_maddr_rlock(ifp); 873 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 874 if (ifma->ifma_addr->sa_family != AF_LINK) 875 continue; 876 h = sis_mchash(sc, 877 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 878 index = h >> 3; 879 bit = h & 0x1F; 880 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + 881 index); 882 if (bit > 0xF) 883 bit -= 0x10; 884 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 885 } 886 if_maddr_runlock(ifp); 887 } 888 889 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter); 890 CSR_READ_4(sc, SIS_RXFILT_CTL); 891 } 892 893 static void 894 sis_rxfilter_sis(struct sis_softc *sc) 895 { 896 struct ifnet *ifp; 897 struct ifmultiaddr *ifma; 898 uint32_t filter, h, i, n; 899 uint16_t hashes[16]; 900 901 ifp = sc->sis_ifp; 902 903 /* hash table size */ 904 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 905 n = 16; 906 else 907 n = 8; 908 909 filter = CSR_READ_4(sc, SIS_RXFILT_CTL); 910 if (filter & SIS_RXFILTCTL_ENABLE) { 911 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILT_CTL); 912 CSR_READ_4(sc, SIS_RXFILT_CTL); 913 } 914 filter &= ~(SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD | 915 SIS_RXFILTCTL_ALLMULTI); 916 if (ifp->if_flags & IFF_BROADCAST) 917 filter |= SIS_RXFILTCTL_BROAD; 918 919 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 920 filter |= SIS_RXFILTCTL_ALLMULTI; 921 if (ifp->if_flags & IFF_PROMISC) 922 filter |= SIS_RXFILTCTL_ALLPHYS; 923 for (i = 0; i < n; i++) 924 hashes[i] = ~0; 925 } else { 926 for (i = 0; i < n; i++) 927 hashes[i] = 0; 928 i = 0; 929 if_maddr_rlock(ifp); 930 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 931 if (ifma->ifma_addr->sa_family != AF_LINK) 932 continue; 933 h = sis_mchash(sc, 934 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 935 hashes[h >> 4] |= 1 << (h & 0xf); 936 i++; 937 } 938 if_maddr_runlock(ifp); 939 if (i > n) { 940 filter |= SIS_RXFILTCTL_ALLMULTI; 941 for (i = 0; i < n; i++) 942 hashes[i] = ~0; 943 } 944 } 945 946 for (i = 0; i < n; i++) { 947 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 948 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 949 } 950 951 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter); 952 CSR_READ_4(sc, SIS_RXFILT_CTL); 953 } 954 955 static void 956 sis_reset(struct sis_softc *sc) 957 { 958 int i; 959 960 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 961 962 for (i = 0; i < SIS_TIMEOUT; i++) { 963 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 964 break; 965 } 966 967 if (i == SIS_TIMEOUT) 968 device_printf(sc->sis_dev, "reset never completed\n"); 969 970 /* Wait a little while for the chip to get its brains in order. */ 971 DELAY(1000); 972 973 /* 974 * If this is a NetSemi chip, make sure to clear 975 * PME mode. 976 */ 977 if (sc->sis_type == SIS_TYPE_83815) { 978 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 979 CSR_WRITE_4(sc, NS_CLKRUN, 0); 980 } else { 981 /* Disable WOL functions. */ 982 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, 0); 983 } 984 } 985 986 /* 987 * Probe for an SiS chip. Check the PCI vendor and device 988 * IDs against our list and return a device name if we find a match. 989 */ 990 static int 991 sis_probe(device_t dev) 992 { 993 struct sis_type *t; 994 995 t = sis_devs; 996 997 while (t->sis_name != NULL) { 998 if ((pci_get_vendor(dev) == t->sis_vid) && 999 (pci_get_device(dev) == t->sis_did)) { 1000 device_set_desc(dev, t->sis_name); 1001 return (BUS_PROBE_DEFAULT); 1002 } 1003 t++; 1004 } 1005 1006 return (ENXIO); 1007 } 1008 1009 /* 1010 * Attach the interface. Allocate softc structures, do ifmedia 1011 * setup and ethernet/BPF attach. 1012 */ 1013 static int 1014 sis_attach(device_t dev) 1015 { 1016 u_char eaddr[ETHER_ADDR_LEN]; 1017 struct sis_softc *sc; 1018 struct ifnet *ifp; 1019 int error = 0, pmc, waittime = 0; 1020 1021 waittime = 0; 1022 sc = device_get_softc(dev); 1023 1024 sc->sis_dev = dev; 1025 1026 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1027 MTX_DEF); 1028 callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0); 1029 1030 if (pci_get_device(dev) == SIS_DEVICEID_900) 1031 sc->sis_type = SIS_TYPE_900; 1032 if (pci_get_device(dev) == SIS_DEVICEID_7016) 1033 sc->sis_type = SIS_TYPE_7016; 1034 if (pci_get_vendor(dev) == NS_VENDORID) 1035 sc->sis_type = SIS_TYPE_83815; 1036 1037 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 1038 /* 1039 * Map control/status registers. 1040 */ 1041 pci_enable_busmaster(dev); 1042 1043 error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res); 1044 if (error) { 1045 device_printf(dev, "couldn't allocate resources\n"); 1046 goto fail; 1047 } 1048 1049 /* Reset the adapter. */ 1050 sis_reset(sc); 1051 1052 if (sc->sis_type == SIS_TYPE_900 && 1053 (sc->sis_rev == SIS_REV_635 || 1054 sc->sis_rev == SIS_REV_900B)) { 1055 SIO_SET(SIS_CFG_RND_CNT); 1056 SIO_SET(SIS_CFG_PERR_DETECT); 1057 } 1058 1059 /* 1060 * Get station address from the EEPROM. 1061 */ 1062 switch (pci_get_vendor(dev)) { 1063 case NS_VENDORID: 1064 sc->sis_srr = CSR_READ_4(sc, NS_SRR); 1065 1066 /* We can't update the device description, so spew */ 1067 if (sc->sis_srr == NS_SRR_15C) 1068 device_printf(dev, "Silicon Revision: DP83815C\n"); 1069 else if (sc->sis_srr == NS_SRR_15D) 1070 device_printf(dev, "Silicon Revision: DP83815D\n"); 1071 else if (sc->sis_srr == NS_SRR_16A) 1072 device_printf(dev, "Silicon Revision: DP83816A\n"); 1073 else 1074 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); 1075 1076 /* 1077 * Reading the MAC address out of the EEPROM on 1078 * the NatSemi chip takes a bit more work than 1079 * you'd expect. The address spans 4 16-bit words, 1080 * with the first word containing only a single bit. 1081 * You have to shift everything over one bit to 1082 * get it aligned properly. Also, the bits are 1083 * stored backwards (the LSB is really the MSB, 1084 * and so on) so you have to reverse them in order 1085 * to get the MAC address into the form we want. 1086 * Why? Who the hell knows. 1087 */ 1088 { 1089 uint16_t tmp[4]; 1090 1091 sis_read_eeprom(sc, (caddr_t)&tmp, 1092 NS_EE_NODEADDR, 4, 0); 1093 1094 /* Shift everything over one bit. */ 1095 tmp[3] = tmp[3] >> 1; 1096 tmp[3] |= tmp[2] << 15; 1097 tmp[2] = tmp[2] >> 1; 1098 tmp[2] |= tmp[1] << 15; 1099 tmp[1] = tmp[1] >> 1; 1100 tmp[1] |= tmp[0] << 15; 1101 1102 /* Now reverse all the bits. */ 1103 tmp[3] = sis_reverse(tmp[3]); 1104 tmp[2] = sis_reverse(tmp[2]); 1105 tmp[1] = sis_reverse(tmp[1]); 1106 1107 eaddr[0] = (tmp[1] >> 0) & 0xFF; 1108 eaddr[1] = (tmp[1] >> 8) & 0xFF; 1109 eaddr[2] = (tmp[2] >> 0) & 0xFF; 1110 eaddr[3] = (tmp[2] >> 8) & 0xFF; 1111 eaddr[4] = (tmp[3] >> 0) & 0xFF; 1112 eaddr[5] = (tmp[3] >> 8) & 0xFF; 1113 } 1114 break; 1115 case SIS_VENDORID: 1116 default: 1117 #if defined(__i386__) || defined(__amd64__) 1118 /* 1119 * If this is a SiS 630E chipset with an embedded 1120 * SiS 900 controller, we have to read the MAC address 1121 * from the APC CMOS RAM. Our method for doing this 1122 * is very ugly since we have to reach out and grab 1123 * ahold of hardware for which we cannot properly 1124 * allocate resources. This code is only compiled on 1125 * the i386 architecture since the SiS 630E chipset 1126 * is for x86 motherboards only. Note that there are 1127 * a lot of magic numbers in this hack. These are 1128 * taken from SiS's Linux driver. I'd like to replace 1129 * them with proper symbolic definitions, but that 1130 * requires some datasheets that I don't have access 1131 * to at the moment. 1132 */ 1133 if (sc->sis_rev == SIS_REV_630S || 1134 sc->sis_rev == SIS_REV_630E || 1135 sc->sis_rev == SIS_REV_630EA1) 1136 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1137 1138 else if (sc->sis_rev == SIS_REV_635 || 1139 sc->sis_rev == SIS_REV_630ET) 1140 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1141 else if (sc->sis_rev == SIS_REV_96x) { 1142 /* Allow to read EEPROM from LAN. It is shared 1143 * between a 1394 controller and the NIC and each 1144 * time we access it, we need to set SIS_EECMD_REQ. 1145 */ 1146 SIO_SET(SIS_EECMD_REQ); 1147 for (waittime = 0; waittime < SIS_TIMEOUT; 1148 waittime++) { 1149 /* Force EEPROM to idle state. */ 1150 sis_eeprom_idle(sc); 1151 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1152 sis_read_eeprom(sc, (caddr_t)&eaddr, 1153 SIS_EE_NODEADDR, 3, 0); 1154 break; 1155 } 1156 DELAY(1); 1157 } 1158 /* 1159 * Set SIS_EECTL_CLK to high, so a other master 1160 * can operate on the i2c bus. 1161 */ 1162 SIO_SET(SIS_EECTL_CLK); 1163 /* Refuse EEPROM access by LAN */ 1164 SIO_SET(SIS_EECMD_DONE); 1165 } else 1166 #endif 1167 sis_read_eeprom(sc, (caddr_t)&eaddr, 1168 SIS_EE_NODEADDR, 3, 0); 1169 break; 1170 } 1171 1172 sis_add_sysctls(sc); 1173 1174 /* Allocate DMA'able memory. */ 1175 if ((error = sis_dma_alloc(sc)) != 0) 1176 goto fail; 1177 1178 ifp = sc->sis_ifp = if_alloc(IFT_ETHER); 1179 if (ifp == NULL) { 1180 device_printf(dev, "can not if_alloc()\n"); 1181 error = ENOSPC; 1182 goto fail; 1183 } 1184 ifp->if_softc = sc; 1185 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1186 ifp->if_mtu = ETHERMTU; 1187 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1188 ifp->if_ioctl = sis_ioctl; 1189 ifp->if_start = sis_start; 1190 ifp->if_init = sis_init; 1191 IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1192 ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1; 1193 IFQ_SET_READY(&ifp->if_snd); 1194 1195 if (pci_find_extcap(sc->sis_dev, PCIY_PMG, &pmc) == 0) { 1196 if (sc->sis_type == SIS_TYPE_83815) 1197 ifp->if_capabilities |= IFCAP_WOL; 1198 else 1199 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 1200 ifp->if_capenable = ifp->if_capabilities; 1201 } 1202 1203 /* 1204 * Do MII setup. 1205 */ 1206 error = mii_attach(dev, &sc->sis_miibus, ifp, sis_ifmedia_upd, 1207 sis_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 1208 if (error != 0) { 1209 device_printf(dev, "attaching PHYs failed\n"); 1210 goto fail; 1211 } 1212 1213 /* 1214 * Call MI attach routine. 1215 */ 1216 ether_ifattach(ifp, eaddr); 1217 1218 /* 1219 * Tell the upper layer(s) we support long frames. 1220 */ 1221 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1222 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1223 ifp->if_capenable = ifp->if_capabilities; 1224 #ifdef DEVICE_POLLING 1225 ifp->if_capabilities |= IFCAP_POLLING; 1226 #endif 1227 1228 /* Hook interrupt last to avoid having to lock softc */ 1229 error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE, 1230 NULL, sis_intr, sc, &sc->sis_intrhand); 1231 1232 if (error) { 1233 device_printf(dev, "couldn't set up irq\n"); 1234 ether_ifdetach(ifp); 1235 goto fail; 1236 } 1237 1238 fail: 1239 if (error) 1240 sis_detach(dev); 1241 1242 return (error); 1243 } 1244 1245 /* 1246 * Shutdown hardware and free up resources. This can be called any 1247 * time after the mutex has been initialized. It is called in both 1248 * the error case in attach and the normal detach case so it needs 1249 * to be careful about only freeing resources that have actually been 1250 * allocated. 1251 */ 1252 static int 1253 sis_detach(device_t dev) 1254 { 1255 struct sis_softc *sc; 1256 struct ifnet *ifp; 1257 1258 sc = device_get_softc(dev); 1259 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 1260 ifp = sc->sis_ifp; 1261 1262 #ifdef DEVICE_POLLING 1263 if (ifp->if_capenable & IFCAP_POLLING) 1264 ether_poll_deregister(ifp); 1265 #endif 1266 1267 /* These should only be active if attach succeeded. */ 1268 if (device_is_attached(dev)) { 1269 SIS_LOCK(sc); 1270 sis_stop(sc); 1271 SIS_UNLOCK(sc); 1272 callout_drain(&sc->sis_stat_ch); 1273 ether_ifdetach(ifp); 1274 } 1275 if (sc->sis_miibus) 1276 device_delete_child(dev, sc->sis_miibus); 1277 bus_generic_detach(dev); 1278 1279 if (sc->sis_intrhand) 1280 bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand); 1281 bus_release_resources(dev, sis_res_spec, sc->sis_res); 1282 1283 if (ifp) 1284 if_free(ifp); 1285 1286 sis_dma_free(sc); 1287 1288 mtx_destroy(&sc->sis_mtx); 1289 1290 return (0); 1291 } 1292 1293 struct sis_dmamap_arg { 1294 bus_addr_t sis_busaddr; 1295 }; 1296 1297 static void 1298 sis_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1299 { 1300 struct sis_dmamap_arg *ctx; 1301 1302 if (error != 0) 1303 return; 1304 1305 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1306 1307 ctx = (struct sis_dmamap_arg *)arg; 1308 ctx->sis_busaddr = segs[0].ds_addr; 1309 } 1310 1311 static int 1312 sis_dma_ring_alloc(struct sis_softc *sc, bus_size_t alignment, 1313 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 1314 bus_addr_t *paddr, const char *msg) 1315 { 1316 struct sis_dmamap_arg ctx; 1317 int error; 1318 1319 error = bus_dma_tag_create(sc->sis_parent_tag, alignment, 0, 1320 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1, 1321 maxsize, 0, NULL, NULL, tag); 1322 if (error != 0) { 1323 device_printf(sc->sis_dev, 1324 "could not create %s dma tag\n", msg); 1325 return (ENOMEM); 1326 } 1327 /* Allocate DMA'able memory for ring. */ 1328 error = bus_dmamem_alloc(*tag, (void **)ring, 1329 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 1330 if (error != 0) { 1331 device_printf(sc->sis_dev, 1332 "could not allocate DMA'able memory for %s\n", msg); 1333 return (ENOMEM); 1334 } 1335 /* Load the address of the ring. */ 1336 ctx.sis_busaddr = 0; 1337 error = bus_dmamap_load(*tag, *map, *ring, maxsize, sis_dmamap_cb, 1338 &ctx, BUS_DMA_NOWAIT); 1339 if (error != 0) { 1340 device_printf(sc->sis_dev, 1341 "could not load DMA'able memory for %s\n", msg); 1342 return (ENOMEM); 1343 } 1344 *paddr = ctx.sis_busaddr; 1345 return (0); 1346 } 1347 1348 static int 1349 sis_dma_alloc(struct sis_softc *sc) 1350 { 1351 struct sis_rxdesc *rxd; 1352 struct sis_txdesc *txd; 1353 int error, i; 1354 1355 /* Allocate the parent bus DMA tag appropriate for PCI. */ 1356 error = bus_dma_tag_create(bus_get_dma_tag(sc->sis_dev), 1357 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1358 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 1359 0, NULL, NULL, &sc->sis_parent_tag); 1360 if (error != 0) { 1361 device_printf(sc->sis_dev, 1362 "could not allocate parent dma tag\n"); 1363 return (ENOMEM); 1364 } 1365 1366 /* Create RX ring. */ 1367 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_RX_LIST_SZ, 1368 &sc->sis_rx_list_tag, (uint8_t **)&sc->sis_rx_list, 1369 &sc->sis_rx_list_map, &sc->sis_rx_paddr, "RX ring"); 1370 if (error) 1371 return (error); 1372 1373 /* Create TX ring. */ 1374 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_TX_LIST_SZ, 1375 &sc->sis_tx_list_tag, (uint8_t **)&sc->sis_tx_list, 1376 &sc->sis_tx_list_map, &sc->sis_tx_paddr, "TX ring"); 1377 if (error) 1378 return (error); 1379 1380 /* Create tag for RX mbufs. */ 1381 error = bus_dma_tag_create(sc->sis_parent_tag, SIS_RX_BUF_ALIGN, 0, 1382 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 1383 MCLBYTES, 0, NULL, NULL, &sc->sis_rx_tag); 1384 if (error) { 1385 device_printf(sc->sis_dev, "could not allocate RX dma tag\n"); 1386 return (error); 1387 } 1388 1389 /* Create tag for TX mbufs. */ 1390 error = bus_dma_tag_create(sc->sis_parent_tag, 1, 0, 1391 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1392 MCLBYTES * SIS_MAXTXSEGS, SIS_MAXTXSEGS, MCLBYTES, 0, NULL, NULL, 1393 &sc->sis_tx_tag); 1394 if (error) { 1395 device_printf(sc->sis_dev, "could not allocate TX dma tag\n"); 1396 return (error); 1397 } 1398 1399 /* Create DMA maps for RX buffers. */ 1400 error = bus_dmamap_create(sc->sis_rx_tag, 0, &sc->sis_rx_sparemap); 1401 if (error) { 1402 device_printf(sc->sis_dev, 1403 "can't create spare DMA map for RX\n"); 1404 return (error); 1405 } 1406 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1407 rxd = &sc->sis_rxdesc[i]; 1408 rxd->rx_m = NULL; 1409 error = bus_dmamap_create(sc->sis_rx_tag, 0, &rxd->rx_dmamap); 1410 if (error) { 1411 device_printf(sc->sis_dev, 1412 "can't create DMA map for RX\n"); 1413 return (error); 1414 } 1415 } 1416 1417 /* Create DMA maps for TX buffers. */ 1418 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1419 txd = &sc->sis_txdesc[i]; 1420 txd->tx_m = NULL; 1421 error = bus_dmamap_create(sc->sis_tx_tag, 0, &txd->tx_dmamap); 1422 if (error) { 1423 device_printf(sc->sis_dev, 1424 "can't create DMA map for TX\n"); 1425 return (error); 1426 } 1427 } 1428 1429 return (0); 1430 } 1431 1432 static void 1433 sis_dma_free(struct sis_softc *sc) 1434 { 1435 struct sis_rxdesc *rxd; 1436 struct sis_txdesc *txd; 1437 int i; 1438 1439 /* Destroy DMA maps for RX buffers. */ 1440 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1441 rxd = &sc->sis_rxdesc[i]; 1442 if (rxd->rx_dmamap) 1443 bus_dmamap_destroy(sc->sis_rx_tag, rxd->rx_dmamap); 1444 } 1445 if (sc->sis_rx_sparemap) 1446 bus_dmamap_destroy(sc->sis_rx_tag, sc->sis_rx_sparemap); 1447 1448 /* Destroy DMA maps for TX buffers. */ 1449 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1450 txd = &sc->sis_txdesc[i]; 1451 if (txd->tx_dmamap) 1452 bus_dmamap_destroy(sc->sis_tx_tag, txd->tx_dmamap); 1453 } 1454 1455 if (sc->sis_rx_tag) 1456 bus_dma_tag_destroy(sc->sis_rx_tag); 1457 if (sc->sis_tx_tag) 1458 bus_dma_tag_destroy(sc->sis_tx_tag); 1459 1460 /* Destroy RX ring. */ 1461 if (sc->sis_rx_list_map) 1462 bus_dmamap_unload(sc->sis_rx_list_tag, sc->sis_rx_list_map); 1463 if (sc->sis_rx_list_map && sc->sis_rx_list) 1464 bus_dmamem_free(sc->sis_rx_list_tag, sc->sis_rx_list, 1465 sc->sis_rx_list_map); 1466 1467 if (sc->sis_rx_list_tag) 1468 bus_dma_tag_destroy(sc->sis_rx_list_tag); 1469 1470 /* Destroy TX ring. */ 1471 if (sc->sis_tx_list_map) 1472 bus_dmamap_unload(sc->sis_tx_list_tag, sc->sis_tx_list_map); 1473 1474 if (sc->sis_tx_list_map && sc->sis_tx_list) 1475 bus_dmamem_free(sc->sis_tx_list_tag, sc->sis_tx_list, 1476 sc->sis_tx_list_map); 1477 1478 if (sc->sis_tx_list_tag) 1479 bus_dma_tag_destroy(sc->sis_tx_list_tag); 1480 1481 /* Destroy the parent tag. */ 1482 if (sc->sis_parent_tag) 1483 bus_dma_tag_destroy(sc->sis_parent_tag); 1484 } 1485 1486 /* 1487 * Initialize the TX and RX descriptors and allocate mbufs for them. Note that 1488 * we arrange the descriptors in a closed ring, so that the last descriptor 1489 * points back to the first. 1490 */ 1491 static int 1492 sis_ring_init(struct sis_softc *sc) 1493 { 1494 struct sis_rxdesc *rxd; 1495 struct sis_txdesc *txd; 1496 bus_addr_t next; 1497 int error, i; 1498 1499 bzero(&sc->sis_tx_list[0], SIS_TX_LIST_SZ); 1500 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1501 txd = &sc->sis_txdesc[i]; 1502 txd->tx_m = NULL; 1503 if (i == SIS_TX_LIST_CNT - 1) 1504 next = SIS_TX_RING_ADDR(sc, 0); 1505 else 1506 next = SIS_TX_RING_ADDR(sc, i + 1); 1507 sc->sis_tx_list[i].sis_next = htole32(SIS_ADDR_LO(next)); 1508 } 1509 sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0; 1510 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, 1511 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1512 1513 sc->sis_rx_cons = 0; 1514 bzero(&sc->sis_rx_list[0], SIS_RX_LIST_SZ); 1515 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1516 rxd = &sc->sis_rxdesc[i]; 1517 rxd->rx_desc = &sc->sis_rx_list[i]; 1518 if (i == SIS_RX_LIST_CNT - 1) 1519 next = SIS_RX_RING_ADDR(sc, 0); 1520 else 1521 next = SIS_RX_RING_ADDR(sc, i + 1); 1522 rxd->rx_desc->sis_next = htole32(SIS_ADDR_LO(next)); 1523 error = sis_newbuf(sc, rxd); 1524 if (error) 1525 return (error); 1526 } 1527 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, 1528 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1529 1530 return (0); 1531 } 1532 1533 /* 1534 * Initialize an RX descriptor and attach an MBUF cluster. 1535 */ 1536 static int 1537 sis_newbuf(struct sis_softc *sc, struct sis_rxdesc *rxd) 1538 { 1539 struct mbuf *m; 1540 bus_dma_segment_t segs[1]; 1541 bus_dmamap_t map; 1542 int nsegs; 1543 1544 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1545 if (m == NULL) 1546 return (ENOBUFS); 1547 m->m_len = m->m_pkthdr.len = SIS_RXLEN; 1548 #ifndef __NO_STRICT_ALIGNMENT 1549 m_adj(m, SIS_RX_BUF_ALIGN); 1550 #endif 1551 1552 if (bus_dmamap_load_mbuf_sg(sc->sis_rx_tag, sc->sis_rx_sparemap, m, 1553 segs, &nsegs, 0) != 0) { 1554 m_freem(m); 1555 return (ENOBUFS); 1556 } 1557 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1558 1559 if (rxd->rx_m != NULL) { 1560 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, 1561 BUS_DMASYNC_POSTREAD); 1562 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap); 1563 } 1564 map = rxd->rx_dmamap; 1565 rxd->rx_dmamap = sc->sis_rx_sparemap; 1566 sc->sis_rx_sparemap = map; 1567 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_PREREAD); 1568 rxd->rx_m = m; 1569 rxd->rx_desc->sis_ptr = htole32(SIS_ADDR_LO(segs[0].ds_addr)); 1570 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN); 1571 return (0); 1572 } 1573 1574 static __inline void 1575 sis_discard_rxbuf(struct sis_rxdesc *rxd) 1576 { 1577 1578 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN); 1579 } 1580 1581 #ifndef __NO_STRICT_ALIGNMENT 1582 static __inline void 1583 sis_fixup_rx(struct mbuf *m) 1584 { 1585 uint16_t *src, *dst; 1586 int i; 1587 1588 src = mtod(m, uint16_t *); 1589 dst = src - (SIS_RX_BUF_ALIGN - ETHER_ALIGN) / sizeof(*src); 1590 1591 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1592 *dst++ = *src++; 1593 1594 m->m_data -= SIS_RX_BUF_ALIGN - ETHER_ALIGN; 1595 } 1596 #endif 1597 1598 /* 1599 * A frame has been uploaded: pass the resulting mbuf chain up to 1600 * the higher level protocols. 1601 */ 1602 static int 1603 sis_rxeof(struct sis_softc *sc) 1604 { 1605 struct mbuf *m; 1606 struct ifnet *ifp; 1607 struct sis_rxdesc *rxd; 1608 struct sis_desc *cur_rx; 1609 int prog, rx_cons, rx_npkts = 0, total_len; 1610 uint32_t rxstat; 1611 1612 SIS_LOCK_ASSERT(sc); 1613 1614 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, 1615 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1616 1617 rx_cons = sc->sis_rx_cons; 1618 ifp = sc->sis_ifp; 1619 1620 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 1621 SIS_INC(rx_cons, SIS_RX_LIST_CNT), prog++) { 1622 #ifdef DEVICE_POLLING 1623 if (ifp->if_capenable & IFCAP_POLLING) { 1624 if (sc->rxcycles <= 0) 1625 break; 1626 sc->rxcycles--; 1627 } 1628 #endif 1629 cur_rx = &sc->sis_rx_list[rx_cons]; 1630 rxstat = le32toh(cur_rx->sis_cmdsts); 1631 if ((rxstat & SIS_CMDSTS_OWN) == 0) 1632 break; 1633 rxd = &sc->sis_rxdesc[rx_cons]; 1634 1635 total_len = (rxstat & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN; 1636 if ((ifp->if_capenable & IFCAP_VLAN_MTU) != 0 && 1637 total_len <= (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - 1638 ETHER_CRC_LEN)) 1639 rxstat &= ~SIS_RXSTAT_GIANT; 1640 if (SIS_RXSTAT_ERROR(rxstat) != 0) { 1641 ifp->if_ierrors++; 1642 if (rxstat & SIS_RXSTAT_COLL) 1643 ifp->if_collisions++; 1644 sis_discard_rxbuf(rxd); 1645 continue; 1646 } 1647 1648 /* Add a new receive buffer to the ring. */ 1649 m = rxd->rx_m; 1650 if (sis_newbuf(sc, rxd) != 0) { 1651 ifp->if_iqdrops++; 1652 sis_discard_rxbuf(rxd); 1653 continue; 1654 } 1655 1656 /* No errors; receive the packet. */ 1657 m->m_pkthdr.len = m->m_len = total_len; 1658 #ifndef __NO_STRICT_ALIGNMENT 1659 /* 1660 * On architectures without alignment problems we try to 1661 * allocate a new buffer for the receive ring, and pass up 1662 * the one where the packet is already, saving the expensive 1663 * copy operation. 1664 */ 1665 sis_fixup_rx(m); 1666 #endif 1667 ifp->if_ipackets++; 1668 m->m_pkthdr.rcvif = ifp; 1669 1670 SIS_UNLOCK(sc); 1671 (*ifp->if_input)(ifp, m); 1672 SIS_LOCK(sc); 1673 rx_npkts++; 1674 } 1675 1676 if (prog > 0) { 1677 sc->sis_rx_cons = rx_cons; 1678 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, 1679 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1680 } 1681 1682 return (rx_npkts); 1683 } 1684 1685 /* 1686 * A frame was downloaded to the chip. It's safe for us to clean up 1687 * the list buffers. 1688 */ 1689 1690 static void 1691 sis_txeof(struct sis_softc *sc) 1692 { 1693 struct ifnet *ifp; 1694 struct sis_desc *cur_tx; 1695 struct sis_txdesc *txd; 1696 uint32_t cons, txstat; 1697 1698 SIS_LOCK_ASSERT(sc); 1699 1700 cons = sc->sis_tx_cons; 1701 if (cons == sc->sis_tx_prod) 1702 return; 1703 1704 ifp = sc->sis_ifp; 1705 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, 1706 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1707 1708 /* 1709 * Go through our tx list and free mbufs for those 1710 * frames that have been transmitted. 1711 */ 1712 for (; cons != sc->sis_tx_prod; SIS_INC(cons, SIS_TX_LIST_CNT)) { 1713 cur_tx = &sc->sis_tx_list[cons]; 1714 txstat = le32toh(cur_tx->sis_cmdsts); 1715 if ((txstat & SIS_CMDSTS_OWN) != 0) 1716 break; 1717 txd = &sc->sis_txdesc[cons]; 1718 if (txd->tx_m != NULL) { 1719 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, 1720 BUS_DMASYNC_POSTWRITE); 1721 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); 1722 m_freem(txd->tx_m); 1723 txd->tx_m = NULL; 1724 if ((txstat & SIS_CMDSTS_PKT_OK) != 0) { 1725 ifp->if_opackets++; 1726 ifp->if_collisions += 1727 (txstat & SIS_TXSTAT_COLLCNT) >> 16; 1728 } else { 1729 ifp->if_oerrors++; 1730 if (txstat & SIS_TXSTAT_EXCESSCOLLS) 1731 ifp->if_collisions++; 1732 if (txstat & SIS_TXSTAT_OUTOFWINCOLL) 1733 ifp->if_collisions++; 1734 } 1735 } 1736 sc->sis_tx_cnt--; 1737 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1738 } 1739 sc->sis_tx_cons = cons; 1740 if (sc->sis_tx_cnt == 0) 1741 sc->sis_watchdog_timer = 0; 1742 } 1743 1744 static void 1745 sis_tick(void *xsc) 1746 { 1747 struct sis_softc *sc; 1748 struct mii_data *mii; 1749 struct ifnet *ifp; 1750 1751 sc = xsc; 1752 SIS_LOCK_ASSERT(sc); 1753 ifp = sc->sis_ifp; 1754 1755 mii = device_get_softc(sc->sis_miibus); 1756 mii_tick(mii); 1757 sis_watchdog(sc); 1758 if ((sc->sis_flags & SIS_FLAG_LINK) == 0) 1759 sis_miibus_statchg(sc->sis_dev); 1760 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 1761 } 1762 1763 #ifdef DEVICE_POLLING 1764 static poll_handler_t sis_poll; 1765 1766 static int 1767 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1768 { 1769 struct sis_softc *sc = ifp->if_softc; 1770 int rx_npkts = 0; 1771 1772 SIS_LOCK(sc); 1773 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1774 SIS_UNLOCK(sc); 1775 return (rx_npkts); 1776 } 1777 1778 /* 1779 * On the sis, reading the status register also clears it. 1780 * So before returning to intr mode we must make sure that all 1781 * possible pending sources of interrupts have been served. 1782 * In practice this means run to completion the *eof routines, 1783 * and then call the interrupt routine 1784 */ 1785 sc->rxcycles = count; 1786 rx_npkts = sis_rxeof(sc); 1787 sis_txeof(sc); 1788 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1789 sis_startl(ifp); 1790 1791 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1792 uint32_t status; 1793 1794 /* Reading the ISR register clears all interrupts. */ 1795 status = CSR_READ_4(sc, SIS_ISR); 1796 1797 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1798 ifp->if_ierrors++; 1799 1800 if (status & (SIS_ISR_RX_IDLE)) 1801 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1802 1803 if (status & SIS_ISR_SYSERR) { 1804 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1805 sis_initl(sc); 1806 } 1807 } 1808 1809 SIS_UNLOCK(sc); 1810 return (rx_npkts); 1811 } 1812 #endif /* DEVICE_POLLING */ 1813 1814 static void 1815 sis_intr(void *arg) 1816 { 1817 struct sis_softc *sc; 1818 struct ifnet *ifp; 1819 uint32_t status; 1820 1821 sc = arg; 1822 ifp = sc->sis_ifp; 1823 1824 SIS_LOCK(sc); 1825 #ifdef DEVICE_POLLING 1826 if (ifp->if_capenable & IFCAP_POLLING) { 1827 SIS_UNLOCK(sc); 1828 return; 1829 } 1830 #endif 1831 1832 /* Reading the ISR register clears all interrupts. */ 1833 status = CSR_READ_4(sc, SIS_ISR); 1834 if ((status & SIS_INTRS) == 0) { 1835 /* Not ours. */ 1836 SIS_UNLOCK(sc); 1837 return; 1838 } 1839 1840 /* Disable interrupts. */ 1841 CSR_WRITE_4(sc, SIS_IER, 0); 1842 1843 for (;(status & SIS_INTRS) != 0;) { 1844 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1845 break; 1846 if (status & 1847 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1848 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1849 sis_txeof(sc); 1850 1851 if (status & (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | 1852 SIS_ISR_RX_ERR | SIS_ISR_RX_IDLE)) 1853 sis_rxeof(sc); 1854 1855 if (status & SIS_ISR_RX_OFLOW) 1856 ifp->if_ierrors++; 1857 1858 if (status & (SIS_ISR_RX_IDLE)) 1859 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1860 1861 if (status & SIS_ISR_SYSERR) { 1862 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1863 sis_initl(sc); 1864 SIS_UNLOCK(sc); 1865 return; 1866 } 1867 status = CSR_READ_4(sc, SIS_ISR); 1868 } 1869 1870 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1871 /* Re-enable interrupts. */ 1872 CSR_WRITE_4(sc, SIS_IER, 1); 1873 1874 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1875 sis_startl(ifp); 1876 } 1877 1878 SIS_UNLOCK(sc); 1879 } 1880 1881 /* 1882 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1883 * pointers to the fragment pointers. 1884 */ 1885 static int 1886 sis_encap(struct sis_softc *sc, struct mbuf **m_head) 1887 { 1888 struct mbuf *m; 1889 struct sis_txdesc *txd; 1890 struct sis_desc *f; 1891 bus_dma_segment_t segs[SIS_MAXTXSEGS]; 1892 bus_dmamap_t map; 1893 int error, i, frag, nsegs, prod; 1894 int padlen; 1895 1896 prod = sc->sis_tx_prod; 1897 txd = &sc->sis_txdesc[prod]; 1898 if ((sc->sis_flags & SIS_FLAG_MANUAL_PAD) != 0 && 1899 (*m_head)->m_pkthdr.len < SIS_MIN_FRAMELEN) { 1900 m = *m_head; 1901 padlen = SIS_MIN_FRAMELEN - m->m_pkthdr.len; 1902 if (M_WRITABLE(m) == 0) { 1903 /* Get a writable copy. */ 1904 m = m_dup(*m_head, M_DONTWAIT); 1905 m_freem(*m_head); 1906 if (m == NULL) { 1907 *m_head = NULL; 1908 return (ENOBUFS); 1909 } 1910 *m_head = m; 1911 } 1912 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) { 1913 m = m_defrag(m, M_DONTWAIT); 1914 if (m == NULL) { 1915 m_freem(*m_head); 1916 *m_head = NULL; 1917 return (ENOBUFS); 1918 } 1919 } 1920 /* 1921 * Manually pad short frames, and zero the pad space 1922 * to avoid leaking data. 1923 */ 1924 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1925 m->m_pkthdr.len += padlen; 1926 m->m_len = m->m_pkthdr.len; 1927 *m_head = m; 1928 } 1929 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap, 1930 *m_head, segs, &nsegs, 0); 1931 if (error == EFBIG) { 1932 m = m_collapse(*m_head, M_DONTWAIT, SIS_MAXTXSEGS); 1933 if (m == NULL) { 1934 m_freem(*m_head); 1935 *m_head = NULL; 1936 return (ENOBUFS); 1937 } 1938 *m_head = m; 1939 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap, 1940 *m_head, segs, &nsegs, 0); 1941 if (error != 0) { 1942 m_freem(*m_head); 1943 *m_head = NULL; 1944 return (error); 1945 } 1946 } else if (error != 0) 1947 return (error); 1948 1949 /* Check for descriptor overruns. */ 1950 if (sc->sis_tx_cnt + nsegs > SIS_TX_LIST_CNT - 1) { 1951 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); 1952 return (ENOBUFS); 1953 } 1954 1955 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, BUS_DMASYNC_PREWRITE); 1956 1957 frag = prod; 1958 for (i = 0; i < nsegs; i++) { 1959 f = &sc->sis_tx_list[prod]; 1960 if (i == 0) 1961 f->sis_cmdsts = htole32(segs[i].ds_len | 1962 SIS_CMDSTS_MORE); 1963 else 1964 f->sis_cmdsts = htole32(segs[i].ds_len | 1965 SIS_CMDSTS_OWN | SIS_CMDSTS_MORE); 1966 f->sis_ptr = htole32(SIS_ADDR_LO(segs[i].ds_addr)); 1967 SIS_INC(prod, SIS_TX_LIST_CNT); 1968 sc->sis_tx_cnt++; 1969 } 1970 1971 /* Update producer index. */ 1972 sc->sis_tx_prod = prod; 1973 1974 /* Remove MORE flag on the last descriptor. */ 1975 prod = (prod - 1) & (SIS_TX_LIST_CNT - 1); 1976 f = &sc->sis_tx_list[prod]; 1977 f->sis_cmdsts &= ~htole32(SIS_CMDSTS_MORE); 1978 1979 /* Lastly transfer ownership of packet to the controller. */ 1980 f = &sc->sis_tx_list[frag]; 1981 f->sis_cmdsts |= htole32(SIS_CMDSTS_OWN); 1982 1983 /* Swap the last and the first dmamaps. */ 1984 map = txd->tx_dmamap; 1985 txd->tx_dmamap = sc->sis_txdesc[prod].tx_dmamap; 1986 sc->sis_txdesc[prod].tx_dmamap = map; 1987 sc->sis_txdesc[prod].tx_m = *m_head; 1988 1989 return (0); 1990 } 1991 1992 static void 1993 sis_start(struct ifnet *ifp) 1994 { 1995 struct sis_softc *sc; 1996 1997 sc = ifp->if_softc; 1998 SIS_LOCK(sc); 1999 sis_startl(ifp); 2000 SIS_UNLOCK(sc); 2001 } 2002 2003 static void 2004 sis_startl(struct ifnet *ifp) 2005 { 2006 struct sis_softc *sc; 2007 struct mbuf *m_head; 2008 int queued; 2009 2010 sc = ifp->if_softc; 2011 2012 SIS_LOCK_ASSERT(sc); 2013 2014 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2015 IFF_DRV_RUNNING || (sc->sis_flags & SIS_FLAG_LINK) == 0) 2016 return; 2017 2018 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2019 sc->sis_tx_cnt < SIS_TX_LIST_CNT - 4;) { 2020 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2021 if (m_head == NULL) 2022 break; 2023 2024 if (sis_encap(sc, &m_head) != 0) { 2025 if (m_head == NULL) 2026 break; 2027 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2028 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2029 break; 2030 } 2031 2032 queued++; 2033 2034 /* 2035 * If there's a BPF listener, bounce a copy of this frame 2036 * to him. 2037 */ 2038 BPF_MTAP(ifp, m_head); 2039 } 2040 2041 if (queued) { 2042 /* Transmit */ 2043 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, 2044 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2045 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 2046 2047 /* 2048 * Set a timeout in case the chip goes out to lunch. 2049 */ 2050 sc->sis_watchdog_timer = 5; 2051 } 2052 } 2053 2054 static void 2055 sis_init(void *xsc) 2056 { 2057 struct sis_softc *sc = xsc; 2058 2059 SIS_LOCK(sc); 2060 sis_initl(sc); 2061 SIS_UNLOCK(sc); 2062 } 2063 2064 static void 2065 sis_initl(struct sis_softc *sc) 2066 { 2067 struct ifnet *ifp = sc->sis_ifp; 2068 struct mii_data *mii; 2069 uint8_t *eaddr; 2070 2071 SIS_LOCK_ASSERT(sc); 2072 2073 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2074 return; 2075 2076 /* 2077 * Cancel pending I/O and free all RX/TX buffers. 2078 */ 2079 sis_stop(sc); 2080 /* 2081 * Reset the chip to a known state. 2082 */ 2083 sis_reset(sc); 2084 #ifdef notyet 2085 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 2086 /* 2087 * Configure 400usec of interrupt holdoff. This is based 2088 * on emperical tests on a Soekris 4801. 2089 */ 2090 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); 2091 } 2092 #endif 2093 2094 mii = device_get_softc(sc->sis_miibus); 2095 2096 /* Set MAC address */ 2097 eaddr = IF_LLADDR(sc->sis_ifp); 2098 if (sc->sis_type == SIS_TYPE_83815) { 2099 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 2100 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8); 2101 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 2102 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8); 2103 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 2104 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8); 2105 } else { 2106 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 2107 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8); 2108 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 2109 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8); 2110 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 2111 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8); 2112 } 2113 2114 /* Init circular TX/RX lists. */ 2115 if (sis_ring_init(sc) != 0) { 2116 device_printf(sc->sis_dev, 2117 "initialization failed: no memory for rx buffers\n"); 2118 sis_stop(sc); 2119 return; 2120 } 2121 2122 if (sc->sis_type == SIS_TYPE_83815 || sc->sis_type == SIS_TYPE_83816) { 2123 if (sc->sis_manual_pad != 0) 2124 sc->sis_flags |= SIS_FLAG_MANUAL_PAD; 2125 else 2126 sc->sis_flags &= ~SIS_FLAG_MANUAL_PAD; 2127 } 2128 2129 /* 2130 * Short Cable Receive Errors (MP21.E) 2131 * also: Page 78 of the DP83815 data sheet (september 2002 version) 2132 * recommends the following register settings "for optimum 2133 * performance." for rev 15C. Set this also for 15D parts as 2134 * they require it in practice. 2135 */ 2136 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) { 2137 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2138 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2139 /* set val for c2 */ 2140 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2141 /* load/kill c2 */ 2142 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2143 /* rais SD off, from 4 to c */ 2144 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2145 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2146 } 2147 2148 sis_rxfilter(sc); 2149 /* Turn the receive filter on */ 2150 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 2151 2152 /* 2153 * Load the address of the RX and TX lists. 2154 */ 2155 CSR_WRITE_4(sc, SIS_RX_LISTPTR, SIS_ADDR_LO(sc->sis_rx_paddr)); 2156 CSR_WRITE_4(sc, SIS_TX_LISTPTR, SIS_ADDR_LO(sc->sis_tx_paddr)); 2157 2158 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 2159 * the PCI bus. When this bit is set, the Max DMA Burst Size 2160 * for TX/RX DMA should be no larger than 16 double words. 2161 */ 2162 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 2163 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 2164 } else { 2165 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 2166 } 2167 2168 /* Accept Long Packets for VLAN support */ 2169 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 2170 2171 /* 2172 * Assume 100Mbps link, actual MAC configuration is done 2173 * after getting a valid link. 2174 */ 2175 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 2176 2177 /* 2178 * Enable interrupts. 2179 */ 2180 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2181 #ifdef DEVICE_POLLING 2182 /* 2183 * ... only enable interrupts if we are not polling, make sure 2184 * they are off otherwise. 2185 */ 2186 if (ifp->if_capenable & IFCAP_POLLING) 2187 CSR_WRITE_4(sc, SIS_IER, 0); 2188 else 2189 #endif 2190 CSR_WRITE_4(sc, SIS_IER, 1); 2191 2192 /* Clear MAC disable. */ 2193 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE); 2194 2195 sc->sis_flags &= ~SIS_FLAG_LINK; 2196 mii_mediachg(mii); 2197 2198 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2199 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2200 2201 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 2202 } 2203 2204 /* 2205 * Set media options. 2206 */ 2207 static int 2208 sis_ifmedia_upd(struct ifnet *ifp) 2209 { 2210 struct sis_softc *sc; 2211 struct mii_data *mii; 2212 int error; 2213 2214 sc = ifp->if_softc; 2215 2216 SIS_LOCK(sc); 2217 mii = device_get_softc(sc->sis_miibus); 2218 if (mii->mii_instance) { 2219 struct mii_softc *miisc; 2220 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2221 mii_phy_reset(miisc); 2222 } 2223 error = mii_mediachg(mii); 2224 SIS_UNLOCK(sc); 2225 2226 return (error); 2227 } 2228 2229 /* 2230 * Report current media status. 2231 */ 2232 static void 2233 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2234 { 2235 struct sis_softc *sc; 2236 struct mii_data *mii; 2237 2238 sc = ifp->if_softc; 2239 2240 SIS_LOCK(sc); 2241 mii = device_get_softc(sc->sis_miibus); 2242 mii_pollstat(mii); 2243 SIS_UNLOCK(sc); 2244 ifmr->ifm_active = mii->mii_media_active; 2245 ifmr->ifm_status = mii->mii_media_status; 2246 } 2247 2248 static int 2249 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2250 { 2251 struct sis_softc *sc = ifp->if_softc; 2252 struct ifreq *ifr = (struct ifreq *) data; 2253 struct mii_data *mii; 2254 int error = 0, mask; 2255 2256 switch (command) { 2257 case SIOCSIFFLAGS: 2258 SIS_LOCK(sc); 2259 if (ifp->if_flags & IFF_UP) { 2260 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2261 ((ifp->if_flags ^ sc->sis_if_flags) & 2262 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2263 sis_rxfilter(sc); 2264 else 2265 sis_initl(sc); 2266 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2267 sis_stop(sc); 2268 sc->sis_if_flags = ifp->if_flags; 2269 SIS_UNLOCK(sc); 2270 break; 2271 case SIOCADDMULTI: 2272 case SIOCDELMULTI: 2273 SIS_LOCK(sc); 2274 sis_rxfilter(sc); 2275 SIS_UNLOCK(sc); 2276 break; 2277 case SIOCGIFMEDIA: 2278 case SIOCSIFMEDIA: 2279 mii = device_get_softc(sc->sis_miibus); 2280 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2281 break; 2282 case SIOCSIFCAP: 2283 SIS_LOCK(sc); 2284 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2285 #ifdef DEVICE_POLLING 2286 if ((mask & IFCAP_POLLING) != 0 && 2287 (IFCAP_POLLING & ifp->if_capabilities) != 0) { 2288 ifp->if_capenable ^= IFCAP_POLLING; 2289 if ((IFCAP_POLLING & ifp->if_capenable) != 0) { 2290 error = ether_poll_register(sis_poll, ifp); 2291 if (error != 0) { 2292 SIS_UNLOCK(sc); 2293 break; 2294 } 2295 /* Disable interrupts. */ 2296 CSR_WRITE_4(sc, SIS_IER, 0); 2297 } else { 2298 error = ether_poll_deregister(ifp); 2299 /* Enable interrupts. */ 2300 CSR_WRITE_4(sc, SIS_IER, 1); 2301 } 2302 } 2303 #endif /* DEVICE_POLLING */ 2304 if ((mask & IFCAP_WOL) != 0 && 2305 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2306 if ((mask & IFCAP_WOL_UCAST) != 0) 2307 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2308 if ((mask & IFCAP_WOL_MCAST) != 0) 2309 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2310 if ((mask & IFCAP_WOL_MAGIC) != 0) 2311 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2312 } 2313 SIS_UNLOCK(sc); 2314 break; 2315 default: 2316 error = ether_ioctl(ifp, command, data); 2317 break; 2318 } 2319 2320 return (error); 2321 } 2322 2323 static void 2324 sis_watchdog(struct sis_softc *sc) 2325 { 2326 2327 SIS_LOCK_ASSERT(sc); 2328 2329 if (sc->sis_watchdog_timer == 0 || --sc->sis_watchdog_timer >0) 2330 return; 2331 2332 device_printf(sc->sis_dev, "watchdog timeout\n"); 2333 sc->sis_ifp->if_oerrors++; 2334 2335 sc->sis_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2336 sis_initl(sc); 2337 2338 if (!IFQ_DRV_IS_EMPTY(&sc->sis_ifp->if_snd)) 2339 sis_startl(sc->sis_ifp); 2340 } 2341 2342 /* 2343 * Stop the adapter and free any mbufs allocated to the 2344 * RX and TX lists. 2345 */ 2346 static void 2347 sis_stop(struct sis_softc *sc) 2348 { 2349 struct ifnet *ifp; 2350 struct sis_rxdesc *rxd; 2351 struct sis_txdesc *txd; 2352 int i; 2353 2354 SIS_LOCK_ASSERT(sc); 2355 2356 ifp = sc->sis_ifp; 2357 sc->sis_watchdog_timer = 0; 2358 2359 callout_stop(&sc->sis_stat_ch); 2360 2361 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2362 CSR_WRITE_4(sc, SIS_IER, 0); 2363 CSR_WRITE_4(sc, SIS_IMR, 0); 2364 CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */ 2365 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2366 DELAY(1000); 2367 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2368 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2369 2370 sc->sis_flags &= ~SIS_FLAG_LINK; 2371 2372 /* 2373 * Free data in the RX lists. 2374 */ 2375 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2376 rxd = &sc->sis_rxdesc[i]; 2377 if (rxd->rx_m != NULL) { 2378 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, 2379 BUS_DMASYNC_POSTREAD); 2380 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap); 2381 m_freem(rxd->rx_m); 2382 rxd->rx_m = NULL; 2383 } 2384 } 2385 2386 /* 2387 * Free the TX list buffers. 2388 */ 2389 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2390 txd = &sc->sis_txdesc[i]; 2391 if (txd->tx_m != NULL) { 2392 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, 2393 BUS_DMASYNC_POSTWRITE); 2394 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); 2395 m_freem(txd->tx_m); 2396 txd->tx_m = NULL; 2397 } 2398 } 2399 } 2400 2401 /* 2402 * Stop all chip I/O so that the kernel's probe routines don't 2403 * get confused by errant DMAs when rebooting. 2404 */ 2405 static int 2406 sis_shutdown(device_t dev) 2407 { 2408 2409 return (sis_suspend(dev)); 2410 } 2411 2412 static int 2413 sis_suspend(device_t dev) 2414 { 2415 struct sis_softc *sc; 2416 2417 sc = device_get_softc(dev); 2418 SIS_LOCK(sc); 2419 sis_stop(sc); 2420 sis_wol(sc); 2421 SIS_UNLOCK(sc); 2422 return (0); 2423 } 2424 2425 static int 2426 sis_resume(device_t dev) 2427 { 2428 struct sis_softc *sc; 2429 struct ifnet *ifp; 2430 2431 sc = device_get_softc(dev); 2432 SIS_LOCK(sc); 2433 ifp = sc->sis_ifp; 2434 if ((ifp->if_flags & IFF_UP) != 0) { 2435 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2436 sis_initl(sc); 2437 } 2438 SIS_UNLOCK(sc); 2439 return (0); 2440 } 2441 2442 static void 2443 sis_wol(struct sis_softc *sc) 2444 { 2445 struct ifnet *ifp; 2446 uint32_t val; 2447 uint16_t pmstat; 2448 int pmc; 2449 2450 ifp = sc->sis_ifp; 2451 if ((ifp->if_capenable & IFCAP_WOL) == 0) 2452 return; 2453 2454 if (sc->sis_type == SIS_TYPE_83815) { 2455 /* Reset RXDP. */ 2456 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2457 2458 /* Configure WOL events. */ 2459 CSR_READ_4(sc, NS_WCSR); 2460 val = 0; 2461 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2462 val |= NS_WCSR_WAKE_UCAST; 2463 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2464 val |= NS_WCSR_WAKE_MCAST; 2465 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2466 val |= NS_WCSR_WAKE_MAGIC; 2467 CSR_WRITE_4(sc, NS_WCSR, val); 2468 /* Enable PME and clear PMESTS. */ 2469 val = CSR_READ_4(sc, NS_CLKRUN); 2470 val |= NS_CLKRUN_PMEENB | NS_CLKRUN_PMESTS; 2471 CSR_WRITE_4(sc, NS_CLKRUN, val); 2472 /* Enable silent RX mode. */ 2473 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2474 } else { 2475 if (pci_find_extcap(sc->sis_dev, PCIY_PMG, &pmc) != 0) 2476 return; 2477 val = 0; 2478 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2479 val |= SIS_PWRMAN_WOL_MAGIC; 2480 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, val); 2481 /* Request PME. */ 2482 pmstat = pci_read_config(sc->sis_dev, 2483 pmc + PCIR_POWER_STATUS, 2); 2484 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2485 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2486 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2487 pci_write_config(sc->sis_dev, 2488 pmc + PCIR_POWER_STATUS, pmstat, 2); 2489 } 2490 } 2491 2492 static void 2493 sis_add_sysctls(struct sis_softc *sc) 2494 { 2495 struct sysctl_ctx_list *ctx; 2496 struct sysctl_oid_list *children; 2497 char tn[32]; 2498 int unit; 2499 2500 ctx = device_get_sysctl_ctx(sc->sis_dev); 2501 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sis_dev)); 2502 2503 unit = device_get_unit(sc->sis_dev); 2504 /* 2505 * Unlike most other controllers, NS DP83815/DP83816 controllers 2506 * seem to pad with 0xFF when it encounter short frames. According 2507 * to RFC 1042 the pad bytes should be 0x00. Turning this tunable 2508 * on will have driver pad manully but it's disabled by default 2509 * because it will consume extra CPU cycles for short frames. 2510 */ 2511 sc->sis_manual_pad = 0; 2512 snprintf(tn, sizeof(tn), "dev.sis.%d.manual_pad", unit); 2513 TUNABLE_INT_FETCH(tn, &sc->sis_manual_pad); 2514 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "manual_pad", 2515 CTLFLAG_RW, &sc->sis_manual_pad, 0, "Manually pad short frames"); 2516 } 2517 2518 static device_method_t sis_methods[] = { 2519 /* Device interface */ 2520 DEVMETHOD(device_probe, sis_probe), 2521 DEVMETHOD(device_attach, sis_attach), 2522 DEVMETHOD(device_detach, sis_detach), 2523 DEVMETHOD(device_shutdown, sis_shutdown), 2524 DEVMETHOD(device_suspend, sis_suspend), 2525 DEVMETHOD(device_resume, sis_resume), 2526 2527 /* bus interface */ 2528 DEVMETHOD(bus_print_child, bus_generic_print_child), 2529 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 2530 2531 /* MII interface */ 2532 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 2533 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 2534 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 2535 2536 { 0, 0 } 2537 }; 2538 2539 static driver_t sis_driver = { 2540 "sis", 2541 sis_methods, 2542 sizeof(struct sis_softc) 2543 }; 2544 2545 static devclass_t sis_devclass; 2546 2547 DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0); 2548 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 2549