1 /*- 2 * Copyright 2016-2021 Microchip Technology, Inc. and/or its subsidiaries. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 27 #ifndef _PQI_DEFINES_H 28 #define _PQI_DEFINES_H 29 30 #define PQI_STATUS_FAILURE -1 31 #define PQI_STATUS_TIMEOUT -2 32 #define PQI_STATUS_QFULL -3 33 #define PQI_STATUS_SUCCESS 0 34 35 /* Maximum timeout for internal command completion */ 36 #define TIMEOUT_INFINITE ((uint32_t) (-1)) 37 #define PQISRC_CMD_TIMEOUT TIMEOUT_INFINITE 38 #define PQISRC_PASSTHROUGH_CMD_TIMEOUT PQISRC_CMD_TIMEOUT 39 /* Delay in milli seconds */ 40 #define PQISRC_TMF_TIMEOUT (OS_TMF_TIMEOUT_SEC * 1000) 41 /* Delay in micro seconds */ 42 #define PQISRC_PENDING_IO_TIMEOUT_USEC 30000000 /* 30 seconds */ 43 44 /* If want to disable atomic operations on device active io, then set to zero */ 45 #define PQISRC_DEVICE_IO_COUNTER 1 46 47 #define INVALID_ELEM 0xffff 48 #ifndef MIN 49 #define MIN(a,b) ((a) < (b) ? (a) : (b)) 50 #endif 51 52 #ifndef MAX 53 #define MAX(a,b) ((a) > (b) ? (a) : (b)) 54 #endif 55 56 #define PQISRC_ROUNDUP(x, y) (((x) + (y) - 1) / (y) * (y)) 57 #define PQISRC_DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) 58 59 #define ALIGN_BOUNDARY(a, n) { \ 60 if (a % n) \ 61 a = a + (n - a % n); \ 62 } 63 64 /* Busy wait timeout on a condition */ 65 #define COND_BUSYWAIT(cond, timeout /* in millisecond */) { \ 66 if (!(cond)) { \ 67 while (timeout) { \ 68 OS_BUSYWAIT(1000); \ 69 if (cond) \ 70 break; \ 71 timeout--; \ 72 } \ 73 } \ 74 } 75 76 /* Wait timeout on a condition*/ 77 #define COND_WAIT(cond, timeout /* in millisecond */) { \ 78 if (!(cond)) { \ 79 while (timeout) { \ 80 OS_SLEEP(1000); \ 81 if (cond) \ 82 break; \ 83 timeout--; \ 84 } \ 85 } \ 86 } 87 88 #define FILL_QUEUE_ARRAY_ADDR(q,virt,dma) { \ 89 q->array_virt_addr = virt; \ 90 q->array_dma_addr = dma; \ 91 } 92 93 #define true 1 94 #define false 0 95 96 enum INTR_TYPE { 97 LOCK_INTR, 98 LOCK_SLEEP 99 }; 100 101 #define LOCKNAME_SIZE 32 102 103 #define INTR_TYPE_NONE 0x0 104 #define INTR_TYPE_FIXED 0x1 105 #define INTR_TYPE_MSI 0x2 106 #define INTR_TYPE_MSIX 0x4 107 #define SIS_ENABLE_MSIX 0x40 108 #define SIS_ENABLE_INTX 0x80 109 #define PQISRC_LEGACY_INTX_MASK 0x1 110 111 #define DMA_TO_VIRT(mem) ((mem)->virt_addr) 112 #define DMA_PHYS_LOW(mem) (((mem)->dma_addr) & 0x00000000ffffffff) 113 #define DMA_PHYS_HIGH(mem) ((((mem)->dma_addr) & 0xffffffff00000000) >> 32) 114 115 116 typedef enum REQUEST_STATUS { 117 REQUEST_SUCCESS = 0, 118 REQUEST_PENDING = -1, 119 REQUEST_FAILED = -2, 120 }REQUEST_STATUS_T; 121 typedef enum IO_PATH { 122 AIO_PATH, 123 RAID_PATH 124 }IO_PATH_T; 125 126 typedef enum device_type 127 { 128 DISK_DEVICE, 129 TAPE_DEVICE, 130 ROM_DEVICE = 5, 131 SES_DEVICE, 132 CONTROLLER_DEVICE, 133 MEDIUM_CHANGER_DEVICE, 134 RAID_DEVICE = 0x0c, 135 ENCLOSURE_DEVICE, 136 ZBC_DEVICE = 0x14 137 } device_type_t; 138 139 typedef enum controller_state { 140 PQI_UP_RUNNING, 141 PQI_BUS_RESET, 142 }controller_state_t; 143 144 145 #define PQISRC_MAX_MSIX_SUPPORTED 64 146 147 /* SIS Specific */ 148 #define PQISRC_INIT_STRUCT_REVISION 9 149 #define PQISRC_SECTOR_SIZE 512 150 #define PQISRC_BLK_SIZE PQISRC_SECTOR_SIZE 151 #define PQISRC_DEFAULT_DMA_ALIGN 4 152 #define PQISRC_DMA_ALIGN_MASK (PQISRC_DEFAULT_DMA_ALIGN - 1) 153 #define PQISRC_ERR_BUF_DMA_ALIGN 32 154 #define PQISRC_ERR_BUF_ELEM_SIZE MAX(sizeof(raid_path_error_info_elem_t),sizeof(aio_path_error_info_elem_t)) 155 #define PQISRC_INIT_STRUCT_DMA_ALIGN 16 156 157 #define SIS_CMD_GET_ADAPTER_PROPERTIES 0x19 158 #define SIS_CMD_GET_COMM_PREFERRED_SETTINGS 0x26 159 #define SIS_CMD_GET_PQI_CAPABILITIES 0x3000 160 #define SIS_CMD_INIT_BASE_STRUCT_ADDRESS 0x1b 161 162 #define SIS_SUPPORT_EXT_OPT 0x00800000 163 #define SIS_SUPPORT_PQI 0x00000004 164 #define SIS_SUPPORT_PQI_RESET_QUIESCE 0x00000008 165 166 #define SIS_PQI_RESET_QUIESCE 0x1000000 167 168 #define SIS_STATUS_OK_TIMEOUT 120000 /* in milli sec, 5 sec */ 169 170 #define SIS_CMD_COMPLETE_TIMEOUT 30000 /* in milli sec, 30 secs */ 171 #define SIS_POLL_START_WAIT_TIME 20000 /* in micro sec, 20 milli sec */ 172 #define SIS_DB_BIT_CLEAR_TIMEOUT_CNT 120000 /* 500usec * 120000 = 60 sec */ 173 174 #define SIS_ENABLE_TIMEOUT 3000 175 #define REENABLE_SIS 0x1 176 #define TRIGGER_NMI_SIS 0x800000 177 /*SIS Register status defines */ 178 179 #define PQI_CTRL_KERNEL_UP_AND_RUNNING 0x80 180 #define PQI_CTRL_KERNEL_PANIC 0x100 181 182 #define SIS_CTL_TO_HOST_DB_DISABLE_ALL 0xFFFFFFFF 183 #define SIS_CTL_TO_HOST_DB_CLEAR 0x00001000 184 #define SIS_CMD_SUBMIT 0x00000200 /* Bit 9 */ 185 #define SIS_CMD_COMPLETE 0x00001000 /* Bit 12 */ 186 #define SIS_CMD_STATUS_SUCCESS 0x1 187 188 /* PQI specific */ 189 190 /* defines */ 191 #define PQISRC_PQI_REG_OFFSET 0x4000 192 #define PQISRC_MAX_OUTSTANDING_REQ 4096 193 #define PQISRC_MAX_ADMIN_IB_QUEUE_ELEM_NUM 16 194 #define PQISRC_MAX_ADMIN_OB_QUEUE_ELEM_NUM 16 195 196 197 198 #define PQI_MIN_OP_IB_QUEUE_ID 1 199 #define PQI_OP_EVENT_QUEUE_ID 1 200 #define PQI_MIN_OP_OB_QUEUE_ID 2 201 202 #define PQISRC_MAX_SUPPORTED_OP_IB_Q 128 203 #define PQISRC_MAX_SUPPORTED_OP_RAID_IB_Q (PQISRC_MAX_SUPPORTED_OP_IB_Q / 2) 204 #define PQISRC_MAX_SUPPORTED_OP_AIO_IB_Q (PQISRC_MAX_SUPPORTED_OP_RAID_IB_Q) 205 #define PQISRC_MAX_OP_IB_QUEUE_ELEM_NUM (PQISRC_MAX_OUTSTANDING_REQ / PQISRC_MAX_SUPPORTED_OP_IB_Q) 206 #define PQISRC_MAX_OP_OB_QUEUE_ELEM_NUM PQISRC_MAX_OUTSTANDING_REQ 207 #define PQISRC_MIN_OP_OB_QUEUE_ELEM_NUM 2 208 #define PQISRC_MAX_SUPPORTED_OP_OB_Q 64 209 #define PQISRC_OP_MAX_IBQ_ELEM_SIZE 8 /* 8 * 16 = 128 bytes */ 210 #define PQISRC_OP_MIN_IBQ_ELEM_SIZE 2 /* 2 * 16 = 32 bytes */ 211 #define PQISRC_OP_OBQ_ELEM_SIZE 1 /* 16 bytes */ 212 #define PQISRC_ADMIN_IBQ_ELEM_SIZE 2 /* 2 * 16 = 32 bytes */ 213 #define PQISRC_INTR_COALSC_GRAN 0 214 #define PQISRC_PROTO_BIT_MASK 0 215 #define PQISRC_SGL_SUPPORTED_BIT_MASK 0 216 217 #define PQISRC_NUM_EVENT_Q_ELEM 32 218 #define PQISRC_EVENT_Q_ELEM_SIZE 32 219 220 /* PQI Registers state status */ 221 222 #define PQI_RESET_ACTION_RESET 0x1 223 #define PQI_RESET_ACTION_COMPLETED 0x2 224 #define PQI_RESET_TYPE_NO_RESET 0x0 225 #define PQI_RESET_TYPE_SOFT_RESET 0x1 226 #define PQI_RESET_TYPE_FIRM_RESET 0x2 227 #define PQI_RESET_TYPE_HARD_RESET 0x3 228 229 #define PQI_RESET_POLL_INTERVAL 100000 /*100 msec*/ 230 231 enum pqisrc_ctrl_mode{ 232 CTRL_SIS_MODE = 0, 233 CTRL_PQI_MODE 234 }; 235 236 /* PQI device performing internal initialization (e.g., POST). */ 237 #define PQI_DEV_STATE_POWER_ON_AND_RESET 0x0 238 /* Upon entry to this state PQI device initialization begins. */ 239 #define PQI_DEV_STATE_PQI_STATUS_AVAILABLE 0x1 240 /* PQI device Standard registers are available to the driver. */ 241 #define PQI_DEV_STATE_ALL_REGISTERS_READY 0x2 242 /* PQI device is initialized and ready to process any PCI transactions. */ 243 #define PQI_DEV_STATE_ADMIN_QUEUE_PAIR_READY 0x3 244 /* The PQI Device Error register indicates the error. */ 245 #define PQI_DEV_STATE_ERROR 0x4 246 247 #define PQI_DEV_STATE_AT_INIT ( PQI_DEV_STATE_PQI_STATUS_AVAILABLE | \ 248 PQI_DEV_STATE_ALL_REGISTERS_READY | \ 249 PQI_DEV_STATE_ADMIN_QUEUE_PAIR_READY ) 250 251 #define PQISRC_PQI_DEVICE_SIGNATURE "PQI DREG" 252 #define PQI_ADMINQ_ELEM_ARRAY_ALIGN 64 253 #define PQI_ADMINQ_CI_PI_ALIGN 64 254 #define PQI_OPQ_ELEM_ARRAY_ALIGN 64 255 #define PQI_OPQ_CI_PI_ALIGN 4 256 #define PQI_ADDR_ALIGN_MASK_64 0x3F /* lsb 6 bits */ 257 #define PQI_ADDR_ALIGN_MASK_4 0x3 /* lsb 2 bits */ 258 259 #define PQISRC_PQIMODE_READY_TIMEOUT (30 * 1000 ) /* 30 secs */ 260 #define PQISRC_MODE_READY_POLL_INTERVAL 1000 /* 1 msec */ 261 262 #define PRINT_PQI_SIGNATURE(sign) { int i = 0; \ 263 char si[9]; \ 264 for(i=0;i<8;i++) \ 265 si[i] = *((char *)&(sign)+i); \ 266 si[i] = '\0'; \ 267 DBG_INFO("Signature is %s",si); \ 268 } 269 #define PQI_CONF_TABLE_MAX_LEN ((uint16_t)~0) 270 #define PQI_CONF_TABLE_SIGNATURE "CFGTABLE" 271 272 /* PQI configuration table section IDs */ 273 #define PQI_CONF_TABLE_ALL_SECTIONS (-1) 274 #define PQI_CONF_TABLE_SECTION_GENERAL_INFO 0 275 #define PQI_CONF_TABLE_SECTION_FIRMWARE_FEATURES 1 276 #define PQI_CONF_TABLE_SECTION_FIRMWARE_ERRATA 2 277 #define PQI_CONF_TABLE_SECTION_DEBUG 3 278 #define PQI_CONF_TABLE_SECTION_HEARTBEAT 4 279 280 281 #define PQI_FIRMWARE_FEATURE_OFA 0 282 #define PQI_FIRMWARE_FEATURE_SMP 1 283 #define PQI_FIRMWARE_FEATURE_MAX_KNOWN 2 284 #define PQI_FIRMWARE_FEATURE_AIO_READ_RAID_0 3 285 #define PQI_FIRMWARE_FEATURE_AIO_READ_RAID_1_10 4 286 #define PQI_FIRMWARE_FEATURE_AIO_READ_RAID_5_50 5 287 #define PQI_FIRMWARE_FEATURE_AIO_READ_RAID_6_60 6 288 #define PQI_FIRMWARE_FEATURE_AIO_WRITE_RAID_0 7 289 #define PQI_FIRMWARE_FEATURE_AIO_WRITE_RAID_1_10 8 290 #define PQI_FIRMWARE_FEATURE_AIO_WRITE_RAID_5_50 9 291 #define PQI_FIRMWARE_FEATURE_AIO_WRITE_RAID_6_60 10 292 #define PQI_FIRMWARE_FEATURE_SOFT_RESET_HANDSHAKE 11 293 #define PQI_FIRMWARE_FEATURE_SATA_WWN_FOR_DEV_UNIQUE_ID 12 294 #define PQI_FIRMWARE_FEATURE_TIMEOUT_IN_RAID_IU_SUPPORT 13 295 #define PQI_FIRMWARE_FEATURE_TIMEOUT_IN_TMF_IU_SUPPORT 14 296 #define PQI_FIRMWARE_FEATURE_MAXIMUM 14 297 298 #define CTRLR_HEARTBEAT_CNT(softs) \ 299 LE_64(PCI_MEM_GET64(softs, softs->heartbeat_counter_abs_addr, softs->heartbeat_counter_off)) 300 #define PQI_HEARTBEAT_TIMEOUT_SEC (10) /* 10 sec interval */ 301 #define PQI_HOST_WELLNESS_TIMEOUT_SEC (24*3600) 302 303 /* pqi-2r00a table 36 */ 304 #define PQI_ADMIN_QUEUE_MSIX_DISABLE (0x80000000) 305 #define PQI_ADMIN_QUEUE_MSIX_ENABLE (0 << 31) 306 307 #define PQI_ADMIN_QUEUE_CONF_FUNC_CREATE_Q_PAIR 0x01 308 #define PQI_ADMIN_QUEUE_CONF_FUNC_DEL_Q_PAIR 0x02 309 #define PQI_ADMIN_QUEUE_CONF_FUNC_STATUS_IDLE 0x00 310 #define PQISRC_ADMIN_QUEUE_CREATE_TIMEOUT 1000 /* in miLLI sec, 1 sec, 100 ms is standard */ 311 #define PQISRC_ADMIN_QUEUE_DELETE_TIMEOUT 100 /* 100 ms is standard */ 312 #define PQISRC_ADMIN_CMD_RESP_TIMEOUT 3000 /* 3 sec */ 313 #define PQISRC_RAIDPATH_CMD_TIMEOUT 30000 /* 30 sec */ 314 315 #define REPORT_PQI_DEV_CAP_DATA_BUF_SIZE sizeof(pqi_dev_cap_t) 316 #define REPORT_MANUFACTURER_INFO_DATA_BUF_SIZE 0x80 /* Data buffer size specified in bytes 0-1 of data buffer. 128 bytes. */ 317 /* PQI IUs */ 318 /* Admin IU request length not including header. */ 319 #define PQI_STANDARD_IU_LENGTH 0x003C /* 60 bytes. */ 320 #define PQI_IU_TYPE_GENERAL_ADMIN_REQUEST 0x60 321 #define PQI_IU_TYPE_GENERAL_ADMIN_RESPONSE 0xe0 322 323 /* PQI / Vendor specific IU */ 324 #define PQI_FUNCTION_REPORT_DEV_CAP 0x00 325 #define PQI_REQUEST_IU_RAID_TASK_MANAGEMENT 0x13 326 #define PQI_IU_TYPE_RAID_PATH_IO_REQUEST 0x14 327 #define PQI_IU_TYPE_AIO_PATH_IO_REQUEST 0x15 328 #define PQI_REQUEST_IU_AIO_TASK_MANAGEMENT 0x16 329 #define PQI_REQUEST_IU_GENERAL_ADMIN 0x60 330 #define PQI_REQUEST_IU_REPORT_VENDOR_EVENT_CONFIG 0x72 331 #define PQI_REQUEST_IU_SET_VENDOR_EVENT_CONFIG 0x73 332 #define PQI_REQUEST_IU_VENDOR_GENERAL 0x75 333 #define PQI_RESPONSE_IU_GENERAL_MANAGEMENT 0x81 334 #define PQI_RESPONSE_IU_TASK_MANAGEMENT 0x93 335 #define PQI_RESPONSE_IU_GENERAL_ADMIN 0xe0 336 337 #define PQI_RESPONSE_IU_RAID_PATH_IO_SUCCESS 0xf0 338 #define PQI_RESPONSE_IU_AIO_PATH_IO_SUCCESS 0xf1 339 #define PQI_RESPONSE_IU_RAID_PATH_IO_ERROR 0xf2 340 #define PQI_RESPONSE_IU_AIO_PATH_IO_ERROR 0xf3 341 #define PQI_RESPONSE_IU_AIO_PATH_IS_OFF 0xf4 342 #define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT 0xf6 343 #define PQI_RESPONSE_IU_VENDOR_GENERAL 0xf7 344 #define PQI_REQUEST_HEADER_LENGTH 4 345 #define PQI_FUNCTION_CREATE_OPERATIONAL_IQ 0x10 346 #define PQI_FUNCTION_CREATE_OPERATIONAL_OQ 0x11 347 #define PQI_FUNCTION_DELETE_OPERATIONAL_IQ 0x12 348 #define PQI_FUNCTION_DELETE_OPERATIONAL_OQ 0x13 349 #define PQI_FUNCTION_CHANGE_OPERATIONAL_IQ_PROP 0x14 350 #define PQI_CHANGE_OP_IQ_PROP_ASSIGN_AIO 1 351 352 #define PQI_DEFAULT_IB_QUEUE 0 353 #define PQI_VENDOR_GENERAL_CONFIG_TABLE_UPDATE 0 354 355 #define PQI_VENDOR_RESPONSE_IU_SUCCESS 0 356 #define PQI_VENDOR_RESPONSE_IU_UNSUCCESS 1 357 #define PQI_VENDOR_RESPONSE_IU_INVALID_PARAM 2 358 #define PQI_VENDOR_RESPONSE_IU_INSUFF_RESRC 3 359 360 /* Interface macros */ 361 362 #define GET_FW_STATUS(softs) \ 363 (PCI_MEM_GET32(softs, &softs->ioa_reg->scratchpad3_fw_status, LEGACY_SIS_OMR)) 364 365 #define SIS_IS_KERNEL_PANIC(softs) \ 366 (GET_FW_STATUS(softs) & PQI_CTRL_KERNEL_PANIC) 367 368 #define SIS_IS_KERNEL_UP(softs) \ 369 (GET_FW_STATUS(softs) & PQI_CTRL_KERNEL_UP_AND_RUNNING) 370 371 #define PQI_GET_CTRL_MODE(softs) \ 372 (PCI_MEM_GET32(softs, &softs->ioa_reg->scratchpad0, LEGACY_SIS_SCR0)) 373 374 #define PQI_SAVE_CTRL_MODE(softs, mode) \ 375 PCI_MEM_PUT32(softs, &softs->ioa_reg->scratchpad0, LEGACY_SIS_SCR0, mode) 376 377 #define PQISRC_MAX_TARGETID 1024 378 #define PQISRC_MAX_TARGETLUN 64 379 380 /* Vendor specific IU Type for Event config Cmds */ 381 #define PQI_REQUEST_IU_REPORT_EVENT_CONFIG 0x72 382 #define PQI_REQUEST_IU_SET_EVENT_CONFIG 0x73 383 #define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT 0xf6 384 385 #define PQI_RESPONSE_IU_GENERAL_MANAGEMENT 0x81 386 #define PQI_MANAGEMENT_CMD_RESP_TIMEOUT 3000 387 #define PQISRC_EVENT_ACK_RESP_TIMEOUT 1000 388 389 390 /* Supported Event types by controller */ 391 392 #define PQI_NUM_SUPPORTED_EVENTS 6 393 394 #define PQI_EVENT_TYPE_HOTPLUG 0x1 395 #define PQI_EVENT_TYPE_HARDWARE 0x2 396 #define PQI_EVENT_TYPE_PHYSICAL_DEVICE 0x4 397 #define PQI_EVENT_TYPE_LOGICAL_DEVICE 0x5 398 #define PQI_EVENT_TYPE_AIO_STATE_CHANGE 0xfd 399 #define PQI_EVENT_TYPE_AIO_CONFIG_CHANGE 0xfe 400 401 /* for indexing into the pending_events[] field of struct pqisrc_softstate */ 402 #define PQI_EVENT_HOTPLUG 0 403 #define PQI_EVENT_HARDWARE 1 404 #define PQI_EVENT_PHYSICAL_DEVICE 2 405 #define PQI_EVENT_LOGICAL_DEVICE 3 406 #define PQI_EVENT_AIO_STATE_CHANGE 4 407 #define PQI_EVENT_AIO_CONFIG_CHANGE 5 408 409 410 411 /* Device flags */ 412 #define PQISRC_DFLAG_VALID (1 << 0) 413 #define PQISRC_DFLAG_CONFIGURING (1 << 1) 414 415 #define MAX_EMBEDDED_SG_IN_FIRST_IU 4 416 #define MAX_EMBEDDED_SG_IN_IU 8 417 #define SG_FLAG_LAST 0x40000000 418 #define SG_FLAG_CHAIN 0x80000000 419 420 #define IN_PQI_RESET(softs) (softs->ctlr_state & PQI_BUS_RESET) 421 #define DEV_GONE(dev) (!dev || (dev->invalid == true)) 422 #define IS_AIO_PATH(dev) (dev->aio_enabled) 423 #define IS_RAID_PATH(dev) (!dev->aio_enabled) 424 425 #define DEVICE_RESET(dvp) (dvp->reset_in_progress) 426 427 /* SOP data direction flags */ 428 #define SOP_DATA_DIR_NONE 0x00 429 #define SOP_DATA_DIR_FROM_DEVICE 0x01 430 #define SOP_DATA_DIR_TO_DEVICE 0x02 431 #define SOP_DATA_DIR_BIDIRECTIONAL 0x03 432 #define SOP_PARTIAL_DATA_BUFFER 0x04 433 434 #define PQISRC_DMA_VALID (1 << 0) 435 #define PQISRC_CMD_NO_INTR (1 << 1) 436 437 #define SOP_TASK_ATTRIBUTE_SIMPLE 0 438 #define SOP_TASK_ATTRIBUTE_HEAD_OF_QUEUE 1 439 #define SOP_TASK_ATTRIBUTE_ORDERED 2 440 #define SOP_TASK_ATTRIBUTE_ACA 4 441 442 #define SOP_TASK_MANAGEMENT_FUNCTION_COMPLETE 0x0 443 #define SOP_TASK_MANAGEMENT_FUNCTION_REJECTED 0x4 444 #define SOP_TASK_MANAGEMENT_FUNCTION_FAILED 0x5 445 #define SOP_TASK_MANAGEMENT_FUNCTION_SUCCEEDED 0x8 446 #define SOP_TASK_MANAGEMENT_FUNCTION_ABORT_TASK 0x01 447 #define SOP_TASK_MANAGEMENT_FUNCTION_ABORT_TASK_SET 0x02 448 #define SOP_TASK_MANAGEMENT_LUN_RESET 0x8 449 450 451 /* Additional CDB bytes */ 452 #define PQI_ADDITIONAL_CDB_BYTES_0 0 /* 16 byte CDB */ 453 #define PQI_ADDITIONAL_CDB_BYTES_4 1 /* 20 byte CDB */ 454 #define PQI_ADDITIONAL_CDB_BYTES_8 2 /* 24 byte CDB */ 455 #define PQI_ADDITIONAL_CDB_BYTES_12 3 /* 28 byte CDB */ 456 #define PQI_ADDITIONAL_CDB_BYTES_16 4 /* 32 byte CDB */ 457 458 #define PQI_PROTOCOL_SOP 0x0 459 460 #define PQI_AIO_STATUS_GOOD 0x0 461 #define PQI_AIO_STATUS_CHECK_CONDITION 0x2 462 #define PQI_AIO_STATUS_CONDITION_MET 0x4 463 #define PQI_AIO_STATUS_DEVICE_BUSY 0x8 464 #define PQI_AIO_STATUS_INT_GOOD 0x10 465 #define PQI_AIO_STATUS_INT_COND_MET 0x14 466 #define PQI_AIO_STATUS_RESERV_CONFLICT 0x18 467 #define PQI_AIO_STATUS_CMD_TERMINATED 0x22 468 #define PQI_AIO_STATUS_QUEUE_FULL 0x28 469 #define PQI_AIO_STATUS_TASK_ABORTED 0x40 470 #define PQI_AIO_STATUS_UNDERRUN 0x51 471 #define PQI_AIO_STATUS_OVERRUN 0x75 472 /* Status when Target Failure */ 473 #define PQI_AIO_STATUS_IO_ERROR 0x1 474 #define PQI_AIO_STATUS_IO_ABORTED 0x2 475 #define PQI_AIO_STATUS_IO_NO_DEVICE 0x3 476 #define PQI_AIO_STATUS_INVALID_DEVICE 0x4 477 #define PQI_AIO_STATUS_AIO_PATH_DISABLED 0xe 478 479 /* Service Response */ 480 #define PQI_AIO_SERV_RESPONSE_COMPLETE 0 481 #define PQI_AIO_SERV_RESPONSE_FAILURE 1 482 #define PQI_AIO_SERV_RESPONSE_TMF_COMPLETE 2 483 #define PQI_AIO_SERV_RESPONSE_TMF_SUCCEEDED 3 484 #define PQI_AIO_SERV_RESPONSE_TMF_REJECTED 4 485 #define PQI_AIO_SERV_RESPONSE_TMF_INCORRECT_LUN 5 486 487 #define PQI_TMF_WAIT_DELAY 10000000 /* 10 seconds */ 488 489 #define PQI_RAID_STATUS_GOOD PQI_AIO_STATUS_GOOD 490 #define PQI_RAID_STATUS_CHECK_CONDITION PQI_AIO_STATUS_CHECK_CONDITION 491 #define PQI_RAID_STATUS_CONDITION_MET PQI_AIO_STATUS_CONDITION_MET 492 #define PQI_RAID_STATUS_DEVICE_BUSY PQI_AIO_STATUS_DEVICE_BUSY 493 #define PQI_RAID_STATUS_INT_GOOD PQI_AIO_STATUS_INT_GOOD 494 #define PQI_RAID_STATUS_INT_COND_MET PQI_AIO_STATUS_INT_COND_MET 495 #define PQI_RAID_STATUS_RESERV_CONFLICT PQI_AIO_STATUS_RESERV_CONFLICT 496 #define PQI_RAID_STATUS_CMD_TERMINATED PQI_AIO_STATUS_CMD_TERMINATED 497 #define PQI_RAID_STATUS_QUEUE_FULL PQI_AIO_STATUS_QUEUE_FULL 498 #define PQI_RAID_STATUS_TASK_ABORTED PQI_AIO_STATUS_TASK_ABORTED 499 #define PQI_RAID_STATUS_UNDERRUN PQI_AIO_STATUS_UNDERRUN 500 #define PQI_RAID_STATUS_OVERRUN PQI_AIO_STATUS_OVERRUN 501 502 /* VPD inquiry pages */ 503 #define SCSI_VPD_SUPPORTED_PAGES 0x0 /* standard page */ 504 #define SCSI_VPD_DEVICE_ID 0x83 /* standard page */ 505 #define SA_VPD_PHYS_DEVICE_ID 0xc0 /* vendor-specific page */ 506 #define SA_VPD_LV_DEVICE_GEOMETRY 0xc1 /* vendor-specific page */ 507 #define SA_VPD_LV_IOACCEL_STATUS 0xc2 /* vendor-specific page */ 508 #define SA_VPD_LV_STATUS 0xc3 /* vendor-specific page */ 509 510 #define VPD_PAGE (1 << 8) 511 512 513 /* logical volume states */ 514 #define SA_LV_OK 0x0 515 #define SA_LV_FAILED 0x1 516 #define SA_LV_NOT_CONFIGURED 0x2 517 #define SA_LV_DEGRADED 0x3 518 #define SA_LV_READY_FOR_RECOVERY 0x4 519 #define SA_LV_UNDERGOING_RECOVERY 0x5 520 #define SA_LV_WRONG_PHYSICAL_DRIVE_REPLACED 0x6 521 #define SA_LV_PHYSICAL_DRIVE_CONNECTION_PROBLEM 0x7 522 #define SA_LV_HARDWARE_OVERHEATING 0x8 523 #define SA_LV_HARDWARE_HAS_OVERHEATED 0x9 524 #define SA_LV_UNDERGOING_EXPANSION 0xA 525 #define SA_LV_NOT_AVAILABLE 0xb 526 #define SA_LV_QUEUED_FOR_EXPANSION 0xc 527 #define SA_LV_DISABLED_SCSI_ID_CONFLICT 0xd 528 #define SA_LV_EJECTED 0xe 529 #define SA_LV_UNDERGOING_ERASE 0xf 530 #define SA_LV_UNDERGOING_RPI 0x12 531 #define SA_LV_PENDING_RPI 0x13 532 #define SA_LV_ENCRYPTED_NO_KEY 0x14 533 #define SA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER 0x15 534 #define SA_LV_UNDERGOING_ENCRYPTION 0x16 535 #define SA_LV_UNDERGOING_ENCRYPTION_REKEYING 0x17 536 #define SA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER 0x18 537 #define SA_LV_PENDING_ENCRYPTION 0x19 538 #define SA_LV_PENDING_ENCRYPTION_REKEYING 0x1a 539 #define SA_LV_STATUS_VPD_UNSUPPORTED 0xff 540 541 542 /* constants for flags field of ciss_vpd_logical_volume_status */ 543 #define SA_LV_FLAGS_NO_HOST_IO 0x1 /* volume not available for */ 544 545 /* 546 * assume worst case: SATA queue depth of 31 minus 4 internal firmware commands 547 */ 548 #define PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 27 549 550 /* 0 = no limit */ 551 #define PQI_LOGICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 0 552 #define PQI_LOG_EXT_QUEUE_DEPTH_ENABLED 0x20 553 #define PQI_LOG_EXT_QUEUE_ENABLE 0x56 554 #define MAX_RAW_M256_QDEPTH 32512 555 #define MAX_RAW_M16_QDEPTH 2032 556 #define PQI_PTRAID_UPDATE_ON_RESCAN_LUNS 0x80000000 557 558 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" 559 560 #define SA_CACHE_FLUSH 0x1 561 #define PQISRC_INQUIRY_TIMEOUT 30 562 #define SA_INQUIRY 0x12 563 #define SA_REPORT_LOG 0xc2 /* Report Logical LUNs */ 564 #define SA_REPORT_PHYS 0xc3 /* Report Physical LUNs */ 565 #define SA_CISS_READ 0xc0 566 #define SA_GET_RAID_MAP 0xc8 567 568 #define SCSI_SENSE_RESPONSE_70 0x70 569 #define SCSI_SENSE_RESPONSE_71 0x71 570 #define SCSI_SENSE_RESPONSE_72 0x72 571 #define SCSI_SENSE_RESPONSE_73 0x73 572 573 #define SA_REPORT_LOG_EXTENDED 0x1 574 #define SA_REPORT_PHYS_EXTENDED 0x2 575 576 #define SA_CACHE_FLUSH_BUF_LEN 4 577 578 #define GET_SCSI_SNO(cmd) (cmd->cmdId.serialNumber) 579 580 #define REPORT_LUN_DEV_FLAG_AIO_ENABLED 0x8 581 #define PQI_MAX_TRANSFER_SIZE (4 * 1024U * 1024U) 582 #define RAID_MAP_MAX_ENTRIES 1024 583 #define RAID_MAP_ENCRYPTION_ENABLED 0x1 584 #define PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 27 585 586 #define ASC_LUN_NOT_READY 0x4 587 #define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x4 588 #define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x2 589 590 591 #define OBDR_SIG_OFFSET 43 592 #define OBDR_TAPE_SIG "$DR-10" 593 #define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1) 594 #define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN) 595 596 597 #define IOACCEL_STATUS_BYTE 4 598 #define OFFLOAD_CONFIGURED_BIT 0x1 599 #define OFFLOAD_ENABLED_BIT 0x2 600 601 #define PQI_RAID_DATA_IN_OUT_GOOD 0x0 602 #define PQI_RAID_DATA_IN_OUT_UNDERFLOW 0x1 603 #define PQI_RAID_DATA_IN_OUT_BUFFER_ERROR 0x40 604 #define PQI_RAID_DATA_IN_OUT_BUFFER_OVERFLOW 0x41 605 #define PQI_RAID_DATA_IN_OUT_BUFFER_OVERFLOW_DESCRIPTOR_AREA 0x42 606 #define PQI_RAID_DATA_IN_OUT_BUFFER_OVERFLOW_BRIDGE 0x43 607 #define PQI_RAID_DATA_IN_OUT_PCIE_FABRIC_ERROR 0x60 608 #define PQI_RAID_DATA_IN_OUT_PCIE_COMPLETION_TIMEOUT 0x61 609 #define PQI_RAID_DATA_IN_OUT_PCIE_COMPLETER_ABORT_RECEIVED 0x62 610 #define PQI_RAID_DATA_IN_OUT_PCIE_POISONED_MEMORY_READ 0x63 611 #define PQI_RAID_DATA_IN_OUT_PCIE_ECRC_CHECK_FAILED 0x64 612 #define PQI_RAID_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST 0x65 613 #define PQI_RAID_DATA_IN_OUT_PCIE_ACS_VIOLATION 0x66 614 #define PQI_RAID_DATA_IN_OUT_PCIE_TLP_PREFIX_BLOCKED 0x67 615 #define PQI_RAID_DATA_IN_OUT_ERROR 0xf0 616 #define PQI_RAID_DATA_IN_OUT_PROTOCOL_ERROR 0xf1 617 #define PQI_RAID_DATA_IN_OUT_HARDWARE_ERROR 0xf2 618 #define PQI_RAID_DATA_IN_OUT_UNSOLICITED_ABORT 0xf3 619 #define PQI_RAID_DATA_IN_OUT_ABORTED 0xf4 620 #define PQI_RAID_DATA_IN_OUT_TIMEOUT 0xf5 621 622 623 #define PQI_PHYSICAL_DEVICE_BUS 0 624 #define PQI_RAID_VOLUME_BUS 1 625 #define PQI_HBA_BUS 2 626 #define PQI_EXTERNAL_RAID_VOLUME_BUS 3 627 #define PQI_MAX_BUS PQI_EXTERNAL_RAID_VOLUME_BUS 628 629 #define TEST_UNIT_READY 0x00 630 #define SCSI_VPD_HEADER_LENGTH 64 631 632 633 #define PQI_MAX_MULTILUN 256 634 #define PQI_MAX_LOGICALS 64 635 #define PQI_MAX_PHYSICALS 1024 636 #define PQI_MAX_DEVICES (PQI_MAX_LOGICALS + PQI_MAX_PHYSICALS + 1) /* 1 for controller device entry */ 637 #define PQI_MAX_EXT_TARGETS 32 638 639 #define PQI_CTLR_INDEX (PQI_MAX_DEVICES - 1) 640 #define PQI_PD_INDEX(t) (t + PQI_MAX_LOGICALS) 641 642 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 643 #define MAX_TARGET_DEVICES 1024 644 645 #define PQI_NO_MEM 2 646 647 typedef enum pqisrc_device_status { 648 DEVICE_NOT_FOUND, 649 DEVICE_CHANGED, 650 DEVICE_UNCHANGED, 651 } device_status_t; 652 653 #define SA_RAID_0 0 654 #define SA_RAID_4 1 655 #define SA_RAID_1 2 /* also used for RAID 10 */ 656 #define SA_RAID_5 3 /* also used for RAID 50 */ 657 #define SA_RAID_51 4 658 #define SA_RAID_6 5 /* also used for RAID 60 */ 659 #define SA_RAID_ADM 6 /* also used for RAID 1+0 ADM */ 660 #define SA_RAID_MAX SA_RAID_ADM 661 #define SA_RAID_UNKNOWN 0xff 662 663 #define BIT0 (1 << 0) 664 #define BIT1 (1 << 1) 665 #define BIT2 (1 << 2) 666 #define BIT3 (1 << 3) 667 668 #define BITS_PER_BYTE 8 669 /* BMIC commands */ 670 #define BMIC_IDENTIFY_CONTROLLER 0x11 671 #define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15 672 #define BMIC_READ 0x26 673 #define BMIC_WRITE 0x27 674 #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64 675 #define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66 676 #define BMIC_CACHE_FLUSH 0xc2 677 #define BMIC_FLASH_FIRMWARE 0xf7 678 #define BMIC_WRITE_HOST_WELLNESS 0xa5 679 #define BMIC_SET_DIAGS_OPTIONS 0xf4 680 #define BMIC_SENSE_DIAGS_OPTIONS 0xf5 681 682 683 #define MASKED_DEVICE(lunid) ((lunid)[3] & 0xC0) 684 #define BMIC_GET_LEVEL_2_BUS(lunid) ((lunid)[7] & 0x3F) 685 #define BMIC_GET_LEVEL_TWO_TARGET(lunid) ((lunid)[6]) 686 #define BMIC_GET_DRIVE_NUMBER(lunid) \ 687 (((BMIC_GET_LEVEL_2_BUS((lunid)) - 1) << 8) + \ 688 BMIC_GET_LEVEL_TWO_TARGET((lunid))) 689 #define NON_DISK_PHYS_DEV(rle) \ 690 (((reportlun_ext_entry_t *)(rle))->device_flags & 0x1) 691 692 #define NO_TIMEOUT ((unsigned long) -1) 693 694 #define BMIC_DEVICE_TYPE_SATA 0x1 695 696 /* No of IO slots required for internal requests */ 697 #define PQI_RESERVED_IO_SLOTS_SYNC_REQUESTS 3 698 #define PQI_RESERVED_IO_SLOTS_TMF 1 699 #define PQI_RESERVED_IO_SLOTS_CNT (PQI_NUM_SUPPORTED_EVENTS + \ 700 PQI_RESERVED_IO_SLOTS_TMF + \ 701 PQI_RESERVED_IO_SLOTS_SYNC_REQUESTS) 702 703 /* Defines for print flags */ 704 #define PRINT_FLAG_HDR_COLUMN 0x0001 705 706 707 static inline uint16_t GET_LE16(const uint8_t *p) 708 { 709 return p[0] | p[1] << 8; 710 } 711 712 static inline uint32_t GET_LE32(const uint8_t *p) 713 { 714 return p[0] | p[1] << 8 | p[2] << 16 | p[3] << 24; 715 } 716 717 static inline uint64_t GET_LE64(const uint8_t *p) 718 { 719 return (((uint64_t)GET_LE32(p + 4) << 32) | 720 GET_LE32(p)); 721 } 722 723 static inline uint16_t GET_BE16(const uint8_t *p) 724 { 725 return p[0] << 8 | p[1]; 726 } 727 728 static inline uint32_t GET_BE32(const uint8_t *p) 729 { 730 return p[0] << 24 | p[1] << 16 | p[2] << 8 | p[3]; 731 } 732 733 static inline uint64_t GET_BE64(const uint8_t *p) 734 { 735 return (((uint64_t)GET_BE32(p) << 32) | 736 GET_BE32(p + 4)); 737 } 738 739 static inline void PUT_BE16(uint16_t val, uint8_t *p) 740 { 741 *p++ = val >> 8; 742 *p++ = val; 743 } 744 745 static inline void PUT_BE32(uint32_t val, uint8_t *p) 746 { 747 PUT_BE16(val >> 16, p); 748 PUT_BE16(val, p + 2); 749 } 750 751 static inline void PUT_BE64(uint64_t val, uint8_t *p) 752 { 753 PUT_BE32(val >> 32, p); 754 PUT_BE32(val, p + 4); 755 } 756 757 #define OS_FREEBSD 758 #define SIS_POLL_WAIT 759 760 #define OS_ATTRIBUTE_PACKED __attribute__((__packed__)) 761 #define OS_ATTRIBUTE_ALIGNED(n) __attribute__((aligned(n))) 762 763 764 /* Management Interface */ 765 #define CCISS_IOC_MAGIC 'C' 766 #define SMARTPQI_IOCTL_BASE 'M' 767 #define CCISS_GETDRIVVER _IOWR(SMARTPQI_IOCTL_BASE, 0, driver_info) 768 #define CCISS_GETPCIINFO _IOWR(SMARTPQI_IOCTL_BASE, 1, pqi_pci_info_t) 769 #define SMARTPQI_PASS_THRU _IOWR(SMARTPQI_IOCTL_BASE, 2, IOCTL_Command_struct) 770 #define CCISS_PASSTHRU _IOWR('C', 210, IOCTL_Command_struct) 771 #define CCISS_REGNEWD _IO(CCISS_IOC_MAGIC, 14) 772 773 /*IOCTL pci_info structure */ 774 typedef struct pqi_pci_info 775 { 776 unsigned char bus; 777 unsigned char dev_fn; 778 unsigned short domain; 779 uint32_t board_id; 780 uint32_t chip_id; 781 }pqi_pci_info_t; 782 783 typedef struct _driver_info 784 { 785 unsigned char major_version; 786 unsigned long minor_version; 787 unsigned char release_version; 788 unsigned long build_revision; 789 unsigned long max_targets; 790 unsigned long max_io; 791 unsigned long max_transfer_length; 792 }driver_info, *pdriver_info; 793 794 typedef uint8_t *passthru_buf_type_t; 795 796 797 #define PQISRC_OS_VERSION 1 798 #define PQISRC_FEATURE_VERSION 4014 799 #define PQISRC_PATCH_VERSION 0 800 #define PQISRC_BUILD_VERSION 105 801 802 #define STR(s) # s 803 #define PQISRC_VERSION(a, b, c, d) STR(a.b.c.d) 804 #define PQISRC_DRIVER_VERSION PQISRC_VERSION(PQISRC_OS_VERSION, \ 805 PQISRC_FEATURE_VERSION, \ 806 PQISRC_PATCH_VERSION, \ 807 PQISRC_BUILD_VERSION) 808 809 /* End Management interface */ 810 811 #ifdef ASSERT 812 #undef ASSERT 813 #endif 814 815 /* 816 *os_atomic64_cas-- 817 * 818 *Atomically read, compare, and conditionally write. 819 *i.e. compare and swap. 820 *retval True On Success 821 *retval False On Failure 822 * 823 */ 824 static inline boolean_t 825 os_atomic64_cas(volatile uint64_t* var, uint64_t old_val, uint64_t new_val) 826 { 827 return (atomic_cmpset_64(var, old_val, new_val)); 828 } 829 830 #define ASSERT(cond) {\ 831 if (!(cond)) { \ 832 printf("Assertion failed at file %s line %d\n",__FILE__,__LINE__); \ 833 } \ 834 } 835 836 /* Atomic */ 837 typedef volatile uint64_t OS_ATOMIC64_T; 838 #define OS_ATOMIC64_READ(p) atomic_load_acq_64(p) 839 #define OS_ATOMIC64_INIT(p,val) atomic_store_rel_64(p, val) 840 841 /* 64-bit post atomic increment and decrement operations on value in pointer.*/ 842 #define OS_ATOMIC64_DEC(p) (atomic_fetchadd_64(p, -1) - 1) 843 #define OS_ATOMIC64_INC(p) (atomic_fetchadd_64(p, 1) + 1) 844 845 846 #define PQI_MAX_MSIX 64 /* vectors */ 847 #define PQI_MSI_CTX_SIZE sizeof(pqi_intr_ctx)+1 848 #define IS_POLLING_REQUIRED(softs) if (cold) {\ 849 pqisrc_process_event_intr_src(softs, 0);\ 850 pqisrc_process_response_queue(softs, 1);\ 851 } 852 853 #define OS_GET_TASK_ATTR(rcb) os_get_task_attr(rcb) 854 #define OS_FW_HEARTBEAT_TIMER_INTERVAL (5) 855 856 typedef struct PCI_ACC_HANDLE { 857 bus_space_tag_t pqi_btag; 858 bus_space_handle_t pqi_bhandle; 859 } PCI_ACC_HANDLE_T; 860 861 /* 862 * Legacy SIS Register definitions for the Adaptec PMC SRC/SRCv/smartraid adapters. 863 */ 864 /* accessible via BAR0 */ 865 #define LEGACY_SIS_IOAR 0x18 /* IOA->host interrupt register */ 866 #define LEGACY_SIS_IDBR 0x20 /* inbound doorbell register */ 867 #define LEGACY_SIS_IISR 0x24 /* inbound interrupt status register */ 868 #define LEGACY_SIS_OIMR 0x34 /* outbound interrupt mask register */ 869 #define LEGACY_SIS_ODBR_R 0x9c /* outbound doorbell register read */ 870 #define LEGACY_SIS_ODBR_C 0xa0 /* outbound doorbell register clear */ 871 872 #define LEGACY_SIS_SCR0 0xb0 /* scratchpad 0 */ 873 #define LEGACY_SIS_OMR 0xbc /* outbound message register */ 874 #define LEGACY_SIS_IQUE64_L 0xc0 /* inbound queue address 64-bit (low) */ 875 #define LEGACY_SIS_IQUE64_H 0xc4 /* inbound queue address 64-bit (high)*/ 876 #define LEGACY_SIS_ODBR_MSI 0xc8 /* MSI register for sync./AIF */ 877 #define LEGACY_SIS_IQN_L 0xd0 /* inbound queue native mode (low) */ 878 #define LEGACY_SIS_IQN_H 0xd4 /* inbound queue native mode (high)*/ 879 #define LEGACY_SIS_MAILBOX 0x7fc60 /* mailbox (20 bytes) */ 880 #define LEGACY_SIS_SRCV_MAILBOX 0x1000 /* mailbox (20 bytes) */ 881 #define LEGACY_SIS_SRCV_OFFSET_MAILBOX_7 0x101C /* mailbox 7 register offset */ 882 883 884 #define LEGACY_SIS_ODR_SHIFT 12 /* outbound doorbell shift */ 885 #define LEGACY_SIS_IDR_SHIFT 9 /* inbound doorbell shift */ 886 887 888 /* 889 * PQI Register definitions for the smartraid adapters 890 */ 891 /* accessible via BAR0 */ 892 #define PQI_SIGNATURE 0x4000 893 #define PQI_ADMINQ_CONFIG 0x4008 894 #define PQI_ADMINQ_CAP 0x4010 895 #define PQI_LEGACY_INTR_STATUS 0x4018 896 #define PQI_LEGACY_INTR_MASK_SET 0x401C 897 #define PQI_LEGACY_INTR_MASK_CLR 0x4020 898 #define PQI_DEV_STATUS 0x4040 899 #define PQI_ADMIN_IBQ_PI_OFFSET 0x4048 900 #define PQI_ADMIN_OBQ_CI_OFFSET 0x4050 901 #define PQI_ADMIN_IBQ_ELEM_ARRAY_ADDR 0x4058 902 #define PQI_ADMIN_OBQ_ELEM_ARRAY_ADDR 0x4060 903 #define PQI_ADMIN_IBQ_CI_ADDR 0x4068 904 #define PQI_ADMIN_OBQ_PI_ADDR 0x4070 905 #define PQI_ADMINQ_PARAM 0x4078 906 #define PQI_DEV_ERR 0x4080 907 #define PQI_DEV_ERR_DETAILS 0x4088 908 #define PQI_DEV_RESET 0x4090 909 #define PQI_POWER_ACTION 0x4094 910 911 /* Busy wait micro seconds */ 912 #define OS_BUSYWAIT(x) DELAY(x) 913 #define OS_SLEEP(timeout) \ 914 DELAY(timeout); 915 916 /* TMF request timeout is 600 Sec */ 917 #define OS_TMF_TIMEOUT_SEC (10 * 60) 918 919 #define LE_16(x) htole16(x) 920 #define LE_32(x) htole32(x) 921 #define LE_64(x) htole64(x) 922 #define BE_16(x) htobe16(x) 923 #define BE_32(x) htobe32(x) 924 #define BE_64(x) htobe64(x) 925 926 #define PQI_HWIF_SRCV 0 927 #define PQI_HWIF_UNKNOWN -1 928 929 930 #define SMART_STATE_SUSPEND (1<<0) 931 #define SMART_STATE_UNUSED0 (1<<1) 932 #define SMART_STATE_INTERRUPTS_ON (1<<2) 933 #define SMART_STATE_AIF_SLEEPER (1<<3) 934 #define SMART_STATE_RESET (1<<4) 935 936 #define PQI_FLAG_BUSY (1<<0) 937 #define PQI_MSI_ENABLED (1<<1) 938 #define PQI_SIM_REGISTERED (1<<2) 939 #define PQI_MTX_INIT (1<<3) 940 941 942 #define PQI_CMD_MAPPED (1<<2) 943 944 /* Interrupt context to get oq_id */ 945 typedef struct pqi_intr_ctx { 946 int oq_id; 947 device_t pqi_dev; 948 }pqi_intr_ctx_t; 949 950 typedef uint8_t os_dev_info_t; 951 952 typedef struct OS_SPECIFIC { 953 device_t pqi_dev; 954 struct resource *pqi_regs_res0; /* reg. if. window */ 955 int pqi_regs_rid0; /* resource ID */ 956 bus_dma_tag_t pqi_parent_dmat; /* parent DMA tag */ 957 bus_dma_tag_t pqi_buffer_dmat; 958 959 /* controller hardware interface */ 960 int pqi_hwif; 961 struct resource *pqi_irq[PQI_MAX_MSIX]; /* interrupt */ 962 int pqi_irq_rid[PQI_MAX_MSIX]; 963 void *intrcookie[PQI_MAX_MSIX]; 964 bool intr_registered[PQI_MAX_MSIX]; 965 bool msi_enabled; /* MSI/MSI-X enabled */ 966 pqi_intr_ctx_t *msi_ctx; 967 int oq_id; 968 int pqi_state; 969 uint32_t pqi_flags; 970 struct mtx cam_lock; 971 struct mtx map_lock; 972 int mtx_init; 973 int sim_registered; 974 struct cam_devq *devq; 975 struct cam_sim *sim; 976 struct cam_path *path; 977 struct task event_task; 978 struct cdev *cdev; 979 struct callout wellness_periodic; /* periodic event handling */ 980 struct callout heartbeat_timeout_id; /* heart beat event handling */ 981 } OS_SPECIFIC_T; 982 983 typedef bus_addr_t dma_addr_t; 984 985 986 /* Register access macros */ 987 #define PCI_MEM_GET32( _softs, _absaddr, _offset ) \ 988 bus_space_read_4(_softs->pci_mem_handle.pqi_btag, \ 989 _softs->pci_mem_handle.pqi_bhandle, _offset) 990 991 992 #if defined(__i386__) 993 #define PCI_MEM_GET64( _softs, _absaddr, _offset ) ({ \ 994 (uint64_t)bus_space_read_4(_softs->pci_mem_handle.pqi_btag, \ 995 _softs->pci_mem_handle.pqi_bhandle, _offset) + \ 996 ((uint64_t)bus_space_read_4(_softs->pci_mem_handle.pqi_btag, \ 997 _softs->pci_mem_handle.pqi_bhandle, _offset + 4) << 32); \ 998 }) 999 #else 1000 #define PCI_MEM_GET64(_softs, _absaddr, _offset ) \ 1001 bus_space_read_8(_softs->pci_mem_handle.pqi_btag, \ 1002 _softs->pci_mem_handle.pqi_bhandle, _offset) 1003 #endif 1004 1005 #define PCI_MEM_PUT32( _softs, _absaddr, _offset, _val ) \ 1006 bus_space_write_4(_softs->pci_mem_handle.pqi_btag, \ 1007 _softs->pci_mem_handle.pqi_bhandle, _offset, _val) 1008 1009 #if defined(__i386__) 1010 #define PCI_MEM_PUT64( _softs, _absaddr, _offset, _val ) \ 1011 bus_space_write_4(_softs->pci_mem_handle.pqi_btag, \ 1012 _softs->pci_mem_handle.pqi_bhandle, _offset, _val); \ 1013 bus_space_write_4(_softs->pci_mem_handle.pqi_btag, \ 1014 _softs->pci_mem_handle.pqi_bhandle, _offset + 4, _val >> 32); 1015 #else 1016 #define PCI_MEM_PUT64( _softs, _absaddr, _offset, _val ) \ 1017 bus_space_write_8(_softs->pci_mem_handle.pqi_btag, \ 1018 _softs->pci_mem_handle.pqi_bhandle, _offset, _val) 1019 #endif 1020 1021 1022 #define PCI_MEM_GET_BUF(_softs, _absaddr, _offset, buf, size) \ 1023 bus_space_read_region_1(_softs->pci_mem_handle.pqi_btag,\ 1024 _softs->pci_mem_handle.pqi_bhandle, _offset, buf, size) 1025 1026 /* Lock */ 1027 typedef struct mtx OS_LOCK_T; 1028 typedef struct sema OS_SEMA_LOCK_T; 1029 1030 #define OS_PQILOCK_T OS_LOCK_T 1031 1032 #define OS_ACQUIRE_SPINLOCK(_lock) mtx_lock_spin(_lock) 1033 #define OS_RELEASE_SPINLOCK(_lock) mtx_unlock_spin(_lock) 1034 1035 #define OS_INIT_PQILOCK(_softs,_lock,_lockname) os_init_spinlock(_softs,_lock,_lockname) 1036 #define OS_UNINIT_PQILOCK(_lock) os_uninit_spinlock(_lock) 1037 1038 #define PQI_LOCK(_lock) OS_ACQUIRE_SPINLOCK(_lock) 1039 #define PQI_UNLOCK(_lock) OS_RELEASE_SPINLOCK(_lock) 1040 1041 #define OS_GET_CDBP(rcb) \ 1042 ((rcb->cm_ccb->ccb_h.flags & CAM_CDB_POINTER) ? rcb->cm_ccb->csio.cdb_io.cdb_ptr : rcb->cm_ccb->csio.cdb_io.cdb_bytes) 1043 #define GET_SCSI_BUFFLEN(rcb) (rcb->cm_ccb->csio.dxfer_len) 1044 #define IS_OS_SCSICMD(rcb) (rcb && !rcb->tm_req && rcb->cm_ccb) 1045 1046 #define OS_GET_IO_QINDEX(softs,rcb) curcpu % softs->num_op_obq 1047 #define OS_GET_IO_RESP_QID(softs,rcb) (softs->op_ob_q[(OS_GET_IO_QINDEX(softs,rcb))].q_id) 1048 #define OS_GET_IO_REQ_QINDEX(softs,rcb) OS_GET_IO_QINDEX(softs,rcb) 1049 #define OS_GET_TMF_RESP_QID OS_GET_IO_RESP_QID 1050 #define OS_GET_TMF_REQ_QINDEX OS_GET_IO_REQ_QINDEX 1051 1052 /* check request type */ 1053 #define is_internal_req(rcb) (!(rcb->cm_ccb)) 1054 1055 #define os_io_memcpy(dest, src, len) memcpy(dest, src, len) 1056 1057 /* sg elements addr, len, flags */ 1058 #define OS_GET_IO_SG_COUNT(rcb) rcb->nseg 1059 #define OS_GET_IO_SG_ADDR(rcb,i) rcb->sgt[i].addr 1060 #define OS_GET_IO_SG_LEN(rcb,i) rcb->sgt[i].len 1061 1062 /* scsi commands used in pqilib for RAID bypass*/ 1063 #define SCMD_READ_6 READ_6 1064 #define SCMD_WRITE_6 WRITE_6 1065 #define SCMD_READ_10 READ_10 1066 #define SCMD_WRITE_10 WRITE_10 1067 #define SCMD_READ_12 READ_12 1068 #define SCMD_WRITE_12 WRITE_12 1069 #define SCMD_READ_16 READ_16 1070 #define SCMD_WRITE_16 WRITE_16 1071 1072 /* FreeBSD status macros */ 1073 #define BSD_SUCCESS 0 1074 1075 1076 /* Debug facility */ 1077 1078 #define PQISRC_FLAGS_MASK 0x0000ffff 1079 #define PQISRC_FLAGS_INIT 0x00000001 1080 #define PQISRC_FLAGS_INFO 0x00000002 1081 #define PQISRC_FLAGS_FUNC 0x00000004 1082 #define PQISRC_FLAGS_TRACEIO 0x00000008 1083 #define PQISRC_FLAGS_DISC 0x00000010 1084 #define PQISRC_FLAGS_WARN 0x00000020 1085 #define PQISRC_FLAGS_ERROR 0x00000040 1086 #define PQISRC_FLAGS_NOTE 0x00000080 1087 1088 #define PQISRC_LOG_LEVEL (PQISRC_FLAGS_WARN | PQISRC_FLAGS_ERROR | PQISRC_FLAGS_NOTE) 1089 1090 static int logging_level = PQISRC_LOG_LEVEL; 1091 1092 #define DBG_INIT(fmt,args...) \ 1093 do { \ 1094 if (logging_level & PQISRC_FLAGS_INIT) { \ 1095 printf("[INIT]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \ 1096 } \ 1097 }while(0); 1098 1099 #define DBG_INFO(fmt,args...) \ 1100 do { \ 1101 if (logging_level & PQISRC_FLAGS_INFO) { \ 1102 printf("[INFO]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \ 1103 } \ 1104 }while(0); 1105 1106 #define DBG_FUNC(fmt,args...) \ 1107 do { \ 1108 if (logging_level & PQISRC_FLAGS_FUNC) { \ 1109 printf("[FUNC]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \ 1110 } \ 1111 }while(0); 1112 1113 #define DBG_TRACEIO(fmt,args...) \ 1114 do { \ 1115 if (logging_level & PQISRC_FLAGS_TRACEIO) { \ 1116 printf("[TRACEIO]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \ 1117 } \ 1118 }while(0); 1119 1120 #define DBG_DISC(fmt,args...) \ 1121 do { \ 1122 if (logging_level & PQISRC_FLAGS_DISC) { \ 1123 printf("[DISC]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \ 1124 } \ 1125 }while(0); 1126 1127 #define DBG_WARN(fmt,args...) \ 1128 do { \ 1129 if (logging_level & PQISRC_FLAGS_WARN) { \ 1130 printf("[WARN]:[%u:%u.%u][CPU %d][%s][%d]:"fmt,softs->bus_id,softs->device_id,softs->func_id,curcpu,__func__,__LINE__,##args);\ 1131 } \ 1132 }while(0); 1133 1134 #define DBG_ERR(fmt,args...) \ 1135 do { \ 1136 if (logging_level & PQISRC_FLAGS_ERROR) { \ 1137 printf("[ERROR]::[%u:%u.%u][CPU %d][%s][%d]:"fmt,softs->bus_id,softs->device_id,softs->func_id,curcpu,__func__,__LINE__,##args); \ 1138 } \ 1139 }while(0); 1140 #define DBG_IO(fmt,args...) \ 1141 do { \ 1142 if (logging_level & PQISRC_FLAGS_TRACEIO) { \ 1143 printf("[IO]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \ 1144 } \ 1145 }while(0); 1146 1147 #define DBG_ERR_BTL(device,fmt,args...) \ 1148 do { \ 1149 if (logging_level & PQISRC_FLAGS_ERROR) { \ 1150 printf("[ERROR]::[%u:%u.%u][%u,%u,%u][CPU %d][%s][%d]:"fmt, softs->bus_id, softs->device_id, softs->func_id, device->bus, device->target, device->lun,curcpu,__func__,__LINE__,##args); \ 1151 } \ 1152 }while(0); 1153 1154 #define DBG_WARN_BTL(device,fmt,args...) \ 1155 do { \ 1156 if (logging_level & PQISRC_FLAGS_WARN) { \ 1157 printf("[WARN]:[%u:%u.%u][%u,%u,%u][CPU %d][%s][%d]:"fmt, softs->bus_id, softs->device_id, softs->func_id, device->bus, device->target, device->lun,curcpu,__func__,__LINE__,##args);\ 1158 } \ 1159 }while(0); 1160 1161 #define DBG_NOTE(fmt,args...) \ 1162 do { \ 1163 if (logging_level & PQISRC_FLAGS_NOTE) { \ 1164 printf("[INFO]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \ 1165 } \ 1166 }while(0); 1167 1168 #endif /* _PQI_DEFINES_H */ 1169