1 /*- 2 * Copyright (c) 2018 Microsemi Corporation. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* $FreeBSD$ */ 28 29 #ifndef _PQI_DEFINES_H 30 #define _PQI_DEFINES_H 31 32 #define PQI_STATUS_FAILURE -1 33 #define PQI_STATUS_TIMEOUT -2 34 #define PQI_STATUS_QFULL -3 35 #define PQI_STATUS_SUCCESS 0 36 37 #define PQISRC_CMD_TIMEOUT_CNT 1200000 /* 500usec * 1200000 = 5 min */ 38 #define PQI_CMND_COMPLETE_TMO 1000 /* in millisecond */ 39 40 #define INVALID_ELEM 0xffff 41 #ifndef MIN 42 #define MIN(a,b) ((a) < (b) ? (a) : (b)) 43 #endif 44 45 #ifndef MAX 46 #define MAX(a,b) ((a) > (b) ? (a) : (b)) 47 #endif 48 49 #define PQISRC_ROUNDUP(x, y) (((x) + (y) - 1) / (y) * (y)) 50 #define PQISRC_DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) 51 52 #define ALIGN_BOUNDARY(a, n) { \ 53 if (a % n) \ 54 a = a + (n - a % n); \ 55 } 56 57 /* Busy wait timeout on a condition */ 58 #define COND_BUSYWAIT(cond, timeout /* in millisecond */) { \ 59 if (!(cond)) { \ 60 while (timeout) { \ 61 OS_BUSYWAIT(1000); \ 62 if (cond) \ 63 break; \ 64 timeout--; \ 65 } \ 66 } \ 67 } 68 69 /* Wait timeout on a condition*/ 70 #define COND_WAIT(cond, timeout /* in millisecond */) { \ 71 if (!(cond)) { \ 72 while (timeout) { \ 73 OS_SLEEP(1000); \ 74 if (cond) \ 75 break; \ 76 timeout--; \ 77 } \ 78 } \ 79 } 80 81 #define FILL_QUEUE_ARRAY_ADDR(q,virt,dma) { \ 82 q->array_virt_addr = virt; \ 83 q->array_dma_addr = dma; \ 84 } 85 86 #define true 1 87 #define false 0 88 89 enum INTR_TYPE { 90 LOCK_INTR, 91 LOCK_SLEEP 92 }; 93 94 #define LOCKNAME_SIZE 32 95 96 #define INTR_TYPE_NONE 0x0 97 #define INTR_TYPE_FIXED 0x1 98 #define INTR_TYPE_MSI 0x2 99 #define INTR_TYPE_MSIX 0x4 100 #define SIS_ENABLE_MSIX 0x40 101 #define SIS_ENABLE_INTX 0x80 102 #define PQISRC_LEGACY_INTX_MASK 0x1 103 104 #define DMA_TO_VIRT(mem) ((mem)->virt_addr) 105 #define DMA_PHYS_LOW(mem) (((mem)->dma_addr) & 0x00000000ffffffff) 106 #define DMA_PHYS_HIGH(mem) ((((mem)->dma_addr) & 0xffffffff00000000) >> 32) 107 108 109 typedef enum REQUEST_STATUS { 110 REQUEST_SUCCESS = 0, 111 REQUEST_PENDING = -1, 112 REQUEST_FAILED = -2, 113 }REQUEST_STATUS_T; 114 115 typedef enum IO_PATH { 116 AIO_PATH, 117 RAID_PATH 118 }IO_PATH_T; 119 120 typedef enum device_type 121 { 122 DISK_DEVICE, 123 TAPE_DEVICE, 124 ROM_DEVICE = 5, 125 SES_DEVICE, 126 CONTROLLER_DEVICE, 127 MEDIUM_CHANGER_DEVICE, 128 RAID_DEVICE = 0x0c, 129 ENCLOSURE_DEVICE, 130 ZBC_DEVICE = 0x14 131 } device_type_t; 132 133 typedef enum controller_state { 134 PQI_UP_RUNNING, 135 PQI_BUS_RESET, 136 }controller_state_t; 137 138 139 #define PQISRC_MAX_MSIX_SUPPORTED 64 140 141 /* SIS Specific */ 142 #define PQISRC_INIT_STRUCT_REVISION 9 143 #define PQISRC_SECTOR_SIZE 512 144 #define PQISRC_BLK_SIZE PQISRC_SECTOR_SIZE 145 #define PQISRC_DEFAULT_DMA_ALIGN 4 146 #define PQISRC_DMA_ALIGN_MASK (PQISRC_DEFAULT_DMA_ALIGN - 1) 147 #define PQISRC_ERR_BUF_DMA_ALIGN 32 148 #define PQISRC_ERR_BUF_ELEM_SIZE MAX(sizeof(raid_path_error_info_elem_t),sizeof(aio_path_error_info_elem_t)) 149 #define PQISRC_INIT_STRUCT_DMA_ALIGN 16 150 151 #define SIS_CMD_GET_ADAPTER_PROPERTIES 0x19 152 #define SIS_CMD_GET_COMM_PREFERRED_SETTINGS 0x26 153 #define SIS_CMD_GET_PQI_CAPABILITIES 0x3000 154 #define SIS_CMD_INIT_BASE_STRUCT_ADDRESS 0x1b 155 156 #define SIS_SUPPORT_EXT_OPT 0x00800000 157 #define SIS_SUPPORT_PQI 0x00000004 158 #define SIS_SUPPORT_PQI_RESET_QUIESCE 0x00000008 159 160 #define SIS_PQI_RESET_QUIESCE 0x1000000 161 162 #define SIS_STATUS_OK_TIMEOUT 120000 /* in milli sec, 5 sec */ 163 164 #define SIS_CMD_COMPLETE_TIMEOUT 30000 /* in milli sec, 30 secs */ 165 #define SIS_POLL_START_WAIT_TIME 20000 /* in micro sec, 20 milli sec */ 166 #define SIS_DB_BIT_CLEAR_TIMEOUT_CNT 120000 /* 500usec * 120000 = 60 sec */ 167 168 #define SIS_ENABLE_TIMEOUT 3000 169 #define REENABLE_SIS 0x1 170 #define TRIGGER_NMI_SIS 0x800000 171 /*SIS Register status defines */ 172 173 #define PQI_CTRL_KERNEL_UP_AND_RUNNING 0x80 174 #define PQI_CTRL_KERNEL_PANIC 0x100 175 176 #define SIS_CTL_TO_HOST_DB_DISABLE_ALL 0xFFFFFFFF 177 #define SIS_CTL_TO_HOST_DB_CLEAR 0x00001000 178 #define SIS_CMD_SUBMIT 0x00000200 /* Bit 9 */ 179 #define SIS_CMD_COMPLETE 0x00001000 /* Bit 12 */ 180 #define SIS_CMD_STATUS_SUCCESS 0x1 181 182 /* PQI specific */ 183 184 /* defines */ 185 #define PQISRC_PQI_REG_OFFSET 0x4000 186 #define PQISRC_MAX_OUTSTANDING_REQ 4096 187 #define PQISRC_MAX_ADMIN_IB_QUEUE_ELEM_NUM 16 188 #define PQISRC_MAX_ADMIN_OB_QUEUE_ELEM_NUM 16 189 190 191 192 #define PQI_MIN_OP_IB_QUEUE_ID 1 193 #define PQI_OP_EVENT_QUEUE_ID 1 194 #define PQI_MIN_OP_OB_QUEUE_ID 2 195 196 #define PQISRC_MAX_SUPPORTED_OP_IB_Q 128 197 #define PQISRC_MAX_SUPPORTED_OP_RAID_IB_Q (PQISRC_MAX_SUPPORTED_OP_IB_Q / 2) 198 #define PQISRC_MAX_SUPPORTED_OP_AIO_IB_Q (PQISRC_MAX_SUPPORTED_OP_RAID_IB_Q) 199 #define PQISRC_MAX_OP_IB_QUEUE_ELEM_NUM (PQISRC_MAX_OUTSTANDING_REQ / PQISRC_MAX_SUPPORTED_OP_IB_Q) 200 #define PQISRC_MAX_OP_OB_QUEUE_ELEM_NUM PQISRC_MAX_OUTSTANDING_REQ 201 #define PQISRC_MIN_OP_OB_QUEUE_ELEM_NUM 2 202 #define PQISRC_MAX_SUPPORTED_OP_OB_Q 64 203 #define PQISRC_OP_MAX_IBQ_ELEM_SIZE 8 /* 8 * 16 = 128 bytes */ 204 #define PQISRC_OP_MIN_IBQ_ELEM_SIZE 2 /* 2 * 16 = 32 bytes */ 205 #define PQISRC_OP_OBQ_ELEM_SIZE 1 /* 16 bytes */ 206 #define PQISRC_ADMIN_IBQ_ELEM_SIZE 2 /* 2 * 16 = 32 bytes */ 207 #define PQISRC_INTR_COALSC_GRAN 0 208 #define PQISRC_PROTO_BIT_MASK 0 209 #define PQISRC_SGL_SUPPORTED_BIT_MASK 0 210 211 #define PQISRC_NUM_EVENT_Q_ELEM 32 212 #define PQISRC_EVENT_Q_ELEM_SIZE 32 213 214 /* PQI Registers state status */ 215 216 #define PQI_RESET_ACTION_RESET 0x1 217 #define PQI_RESET_ACTION_COMPLETED 0x2 218 #define PQI_RESET_TYPE_NO_RESET 0x0 219 #define PQI_RESET_TYPE_SOFT_RESET 0x1 220 #define PQI_RESET_TYPE_FIRM_RESET 0x2 221 #define PQI_RESET_TYPE_HARD_RESET 0x3 222 223 #define PQI_RESET_POLL_INTERVAL 100000 /*100 msec*/ 224 225 enum pqisrc_ctrl_mode{ 226 CTRL_SIS_MODE = 0, 227 CTRL_PQI_MODE 228 }; 229 230 /* PQI device performing internal initialization (e.g., POST). */ 231 #define PQI_DEV_STATE_POWER_ON_AND_RESET 0x0 232 /* Upon entry to this state PQI device initialization begins. */ 233 #define PQI_DEV_STATE_PQI_STATUS_AVAILABLE 0x1 234 /* PQI device Standard registers are available to the driver. */ 235 #define PQI_DEV_STATE_ALL_REGISTERS_READY 0x2 236 /* PQI device is initialized and ready to process any PCI transactions. */ 237 #define PQI_DEV_STATE_ADMIN_QUEUE_PAIR_READY 0x3 238 /* The PQI Device Error register indicates the error. */ 239 #define PQI_DEV_STATE_ERROR 0x4 240 241 #define PQI_DEV_STATE_AT_INIT ( PQI_DEV_STATE_PQI_STATUS_AVAILABLE | \ 242 PQI_DEV_STATE_ALL_REGISTERS_READY | \ 243 PQI_DEV_STATE_ADMIN_QUEUE_PAIR_READY ) 244 245 #define PQISRC_PQI_DEVICE_SIGNATURE "PQI DREG" 246 #define PQI_ADMINQ_ELEM_ARRAY_ALIGN 64 247 #define PQI_ADMINQ_CI_PI_ALIGN 64 248 #define PQI_OPQ_ELEM_ARRAY_ALIGN 64 249 #define PQI_OPQ_CI_PI_ALIGN 4 250 #define PQI_ADDR_ALIGN_MASK_64 0x3F /* lsb 6 bits */ 251 #define PQI_ADDR_ALIGN_MASK_4 0x3 /* lsb 2 bits */ 252 253 #define PQISRC_PQIMODE_READY_TIMEOUT (30 * 1000 ) /* 30 secs */ 254 #define PQISRC_MODE_READY_POLL_INTERVAL 1000 /* 1 msec */ 255 256 #define PRINT_PQI_SIGNATURE(sign) { int i = 0; \ 257 char si[9]; \ 258 for(i=0;i<8;i++) \ 259 si[i] = *((char *)&(sign)+i); \ 260 si[i] = '\0'; \ 261 DBG_INFO("Signature is %s",si); \ 262 } 263 #define PQI_CONF_TABLE_MAX_LEN ((uint16_t)~0) 264 #define PQI_CONF_TABLE_SIGNATURE "CFGTABLE" 265 266 /* PQI configuration table section IDs */ 267 #define PQI_CONF_TABLE_SECTION_GENERAL_INFO 0 268 #define PQI_CONF_TABLE_SECTION_FIRMWARE_FEATURES 1 269 #define PQI_CONF_TABLE_SECTION_FIRMWARE_ERRATA 2 270 #define PQI_CONF_TABLE_SECTION_DEBUG 3 271 #define PQI_CONF_TABLE_SECTION_HEARTBEAT 4 272 273 #define CTRLR_HEARTBEAT_CNT(softs) LE_64(PCI_MEM_GET64(softs, softs->heartbeat_counter_abs_addr, softs->heartbeat_counter_off)) 274 #define PQI_NEW_HEARTBEAT_MECHANISM(softs) 1 275 276 /* pqi-2r00a table 36 */ 277 #define PQI_ADMIN_QUEUE_MSIX_DISABLE (0x80000000) 278 #define PQI_ADMIN_QUEUE_MSIX_ENABLE (0 << 31) 279 280 #define PQI_ADMIN_QUEUE_CONF_FUNC_CREATE_Q_PAIR 0x01 281 #define PQI_ADMIN_QUEUE_CONF_FUNC_DEL_Q_PAIR 0x02 282 #define PQI_ADMIN_QUEUE_CONF_FUNC_STATUS_IDLE 0x00 283 #define PQISRC_ADMIN_QUEUE_CREATE_TIMEOUT 1000 /* in miLLI sec, 1 sec, 100 ms is standard */ 284 #define PQISRC_ADMIN_QUEUE_DELETE_TIMEOUT 100 /* 100 ms is standard */ 285 #define PQISRC_ADMIN_CMD_RESP_TIMEOUT 3000 /* 3 sec */ 286 #define PQISRC_RAIDPATH_CMD_TIMEOUT 30000 /* 30 sec */ 287 288 #define REPORT_PQI_DEV_CAP_DATA_BUF_SIZE sizeof(pqi_dev_cap_t) 289 #define REPORT_MANUFACTURER_INFO_DATA_BUF_SIZE 0x80 /* Data buffer size specified in bytes 0-1 of data buffer. 128 bytes. */ 290 /* PQI IUs */ 291 /* Admin IU request length not including header. */ 292 #define PQI_STANDARD_IU_LENGTH 0x003C /* 60 bytes. */ 293 #define PQI_IU_TYPE_GENERAL_ADMIN_REQUEST 0x60 294 #define PQI_IU_TYPE_GENERAL_ADMIN_RESPONSE 0xe0 295 296 /* PQI / Vendor specific IU */ 297 #define PQI_FUNCTION_REPORT_DEV_CAP 0x00 298 #define PQI_REQUEST_IU_TASK_MANAGEMENT 0x13 299 #define PQI_IU_TYPE_RAID_PATH_IO_REQUEST 0x14 300 #define PQI_IU_TYPE_AIO_PATH_IO_REQUEST 0x15 301 #define PQI_REQUEST_IU_GENERAL_ADMIN 0x60 302 #define PQI_REQUEST_IU_REPORT_VENDOR_EVENT_CONFIG 0x72 303 #define PQI_REQUEST_IU_SET_VENDOR_EVENT_CONFIG 0x73 304 #define PQI_RESPONSE_IU_GENERAL_MANAGEMENT 0x81 305 #define PQI_RESPONSE_IU_TASK_MANAGEMENT 0x93 306 #define PQI_RESPONSE_IU_GENERAL_ADMIN 0xe0 307 308 #define PQI_RESPONSE_IU_RAID_PATH_IO_SUCCESS 0xf0 309 #define PQI_RESPONSE_IU_AIO_PATH_IO_SUCCESS 0xf1 310 #define PQI_RESPONSE_IU_RAID_PATH_IO_ERROR 0xf2 311 #define PQI_RESPONSE_IU_AIO_PATH_IO_ERROR 0xf3 312 #define PQI_RESPONSE_IU_AIO_PATH_IS_OFF 0xf4 313 #define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT 0xf6 314 #define PQI_REQUEST_HEADER_LENGTH 4 315 #define PQI_FUNCTION_CREATE_OPERATIONAL_IQ 0x10 316 #define PQI_FUNCTION_CREATE_OPERATIONAL_OQ 0x11 317 #define PQI_FUNCTION_DELETE_OPERATIONAL_IQ 0x12 318 #define PQI_FUNCTION_DELETE_OPERATIONAL_OQ 0x13 319 #define PQI_FUNCTION_CHANGE_OPERATIONAL_IQ_PROP 0x14 320 #define PQI_CHANGE_OP_IQ_PROP_ASSIGN_AIO 1 321 322 #define PQI_DEFAULT_IB_QUEUE 0 323 /* Interface macros */ 324 325 #define GET_FW_STATUS(softs) \ 326 (PCI_MEM_GET32(softs, &softs->ioa_reg->scratchpad3_fw_status, LEGACY_SIS_OMR)) 327 328 #define SIS_IS_KERNEL_PANIC(softs) \ 329 (GET_FW_STATUS(softs) & PQI_CTRL_KERNEL_PANIC) 330 331 #define SIS_IS_KERNEL_UP(softs) \ 332 (GET_FW_STATUS(softs) & PQI_CTRL_KERNEL_UP_AND_RUNNING) 333 334 #define PQI_GET_CTRL_MODE(softs) \ 335 (PCI_MEM_GET32(softs, &softs->ioa_reg->scratchpad0, LEGACY_SIS_SCR0)) 336 337 #define PQI_SAVE_CTRL_MODE(softs, mode) \ 338 PCI_MEM_PUT32(softs, &softs->ioa_reg->scratchpad0, LEGACY_SIS_SCR0, mode) 339 340 #define PQISRC_MAX_TARGETID 1024 341 #define PQISRC_MAX_TARGETLUN 64 342 343 /* Vendor specific IU Type for Event config Cmds */ 344 #define PQI_REQUEST_IU_REPORT_EVENT_CONFIG 0x72 345 #define PQI_REQUEST_IU_SET_EVENT_CONFIG 0x73 346 #define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT 0xf6 347 #define PQI_RESPONSE_IU_GENERAL_MANAGEMENT 0x81 348 #define PQI_MANAGEMENT_CMD_RESP_TIMEOUT 3000 349 #define PQISRC_EVENT_ACK_RESP_TIMEOUT 1000 350 351 352 /* Supported Event types by controller */ 353 #define PQI_NUM_SUPPORTED_EVENTS 7 354 355 #define PQI_EVENT_TYPE_HOTPLUG 0x1 356 #define PQI_EVENT_TYPE_HARDWARE 0x2 357 #define PQI_EVENT_TYPE_PHYSICAL_DEVICE 0x4 358 #define PQI_EVENT_TYPE_LOGICAL_DEVICE 0x5 359 #define PQI_EVENT_TYPE_AIO_STATE_CHANGE 0xfd 360 #define PQI_EVENT_TYPE_AIO_CONFIG_CHANGE 0xfe 361 #define PQI_EVENT_TYPE_HEARTBEAT 0xff 362 363 /* for indexing into the pending_events[] field of struct pqisrc_softstate */ 364 #define PQI_EVENT_HEARTBEAT 0 365 #define PQI_EVENT_HOTPLUG 1 366 #define PQI_EVENT_HARDWARE 2 367 #define PQI_EVENT_PHYSICAL_DEVICE 3 368 #define PQI_EVENT_LOGICAL_DEVICE 4 369 #define PQI_EVENT_AIO_STATE_CHANGE 5 370 #define PQI_EVENT_AIO_CONFIG_CHANGE 6 371 372 #define PQI_MAX_HEARTBEAT_REQUESTS 5 373 374 375 /* Device flags */ 376 #define PQISRC_DFLAG_VALID (1 << 0) 377 #define PQISRC_DFLAG_CONFIGURING (1 << 1) 378 379 #define MAX_EMBEDDED_SG_IN_FIRST_IU 4 380 #define MAX_EMBEDDED_SG_IN_IU 8 381 #define SG_FLAG_LAST 0x40000000 382 #define SG_FLAG_CHAIN 0x80000000 383 384 #define IN_PQI_RESET(softs) (softs->ctlr_state & PQI_BUS_RESET) 385 #define DEV_GONE(dev) (!dev || (dev->invalid == true)) 386 #define IS_AIO_PATH(dev) (dev->aio_enabled) 387 #define IS_RAID_PATH(dev) (!dev->aio_enabled) 388 389 /* SOP data direction flags */ 390 #define SOP_DATA_DIR_NONE 0x00 391 #define SOP_DATA_DIR_FROM_DEVICE 0x01 392 #define SOP_DATA_DIR_TO_DEVICE 0x02 393 #define SOP_DATA_DIR_BIDIRECTIONAL 0x03 394 #define SOP_PARTIAL_DATA_BUFFER 0x04 395 396 #define PQISRC_DMA_VALID (1 << 0) 397 #define PQISRC_CMD_NO_INTR (1 << 1) 398 399 #define SOP_TASK_ATTRIBUTE_SIMPLE 0 400 #define SOP_TASK_ATTRIBUTE_HEAD_OF_QUEUE 1 401 #define SOP_TASK_ATTRIBUTE_ORDERED 2 402 #define SOP_TASK_ATTRIBUTE_ACA 4 403 404 #define SOP_TASK_MANAGEMENT_FUNCTION_COMPLETE 0x0 405 #define SOP_TASK_MANAGEMENT_FUNCTION_REJECTED 0x4 406 #define SOP_TASK_MANAGEMENT_FUNCTION_FAILED 0x5 407 #define SOP_TASK_MANAGEMENT_FUNCTION_SUCCEEDED 0x8 408 #define SOP_TASK_MANAGEMENT_FUNCTION_ABORT_TASK 0x01 409 #define SOP_TASK_MANAGEMENT_FUNCTION_ABORT_TASK_SET 0x02 410 #define SOP_TASK_MANAGEMENT_LUN_RESET 0x8 411 412 413 /* Additional CDB bytes */ 414 #define PQI_ADDITIONAL_CDB_BYTES_0 0 /* 16 byte CDB */ 415 #define PQI_ADDITIONAL_CDB_BYTES_4 1 /* 20 byte CDB */ 416 #define PQI_ADDITIONAL_CDB_BYTES_8 2 /* 24 byte CDB */ 417 #define PQI_ADDITIONAL_CDB_BYTES_12 3 /* 28 byte CDB */ 418 #define PQI_ADDITIONAL_CDB_BYTES_16 4 /* 32 byte CDB */ 419 420 #define PQI_PROTOCOL_SOP 0x0 421 422 #define PQI_AIO_STATUS_GOOD 0x0 423 #define PQI_AIO_STATUS_CHECK_CONDITION 0x2 424 #define PQI_AIO_STATUS_CONDITION_MET 0x4 425 #define PQI_AIO_STATUS_DEVICE_BUSY 0x8 426 #define PQI_AIO_STATUS_INT_GOOD 0x10 427 #define PQI_AIO_STATUS_INT_COND_MET 0x14 428 #define PQI_AIO_STATUS_RESERV_CONFLICT 0x18 429 #define PQI_AIO_STATUS_CMD_TERMINATED 0x22 430 #define PQI_AIO_STATUS_QUEUE_FULL 0x28 431 #define PQI_AIO_STATUS_TASK_ABORTED 0x40 432 #define PQI_AIO_STATUS_UNDERRUN 0x51 433 #define PQI_AIO_STATUS_OVERRUN 0x75 434 /* Status when Target Failure */ 435 #define PQI_AIO_STATUS_IO_ERROR 0x1 436 #define PQI_AIO_STATUS_IO_ABORTED 0x2 437 #define PQI_AIO_STATUS_IO_NO_DEVICE 0x3 438 #define PQI_AIO_STATUS_INVALID_DEVICE 0x4 439 #define PQI_AIO_STATUS_AIO_PATH_DISABLED 0xe 440 441 /* Service Response */ 442 #define PQI_AIO_SERV_RESPONSE_COMPLETE 0 443 #define PQI_AIO_SERV_RESPONSE_FAILURE 1 444 #define PQI_AIO_SERV_RESPONSE_TMF_COMPLETE 2 445 #define PQI_AIO_SERV_RESPONSE_TMF_SUCCEEDED 3 446 #define PQI_AIO_SERV_RESPONSE_TMF_REJECTED 4 447 #define PQI_AIO_SERV_RESPONSE_TMF_INCORRECT_LUN 5 448 449 #define PQI_TMF_WAIT_DELAY 10000000 /* 10 seconds */ 450 451 #define PQI_RAID_STATUS_GOOD PQI_AIO_STATUS_GOOD 452 #define PQI_RAID_STATUS_CHECK_CONDITION PQI_AIO_STATUS_CHECK_CONDITION 453 #define PQI_RAID_STATUS_CONDITION_MET PQI_AIO_STATUS_CONDITION_MET 454 #define PQI_RAID_STATUS_DEVICE_BUSY PQI_AIO_STATUS_DEVICE_BUSY 455 #define PQI_RAID_STATUS_INT_GOOD PQI_AIO_STATUS_INT_GOOD 456 #define PQI_RAID_STATUS_INT_COND_MET PQI_AIO_STATUS_INT_COND_MET 457 #define PQI_RAID_STATUS_RESERV_CONFLICT PQI_AIO_STATUS_RESERV_CONFLICT 458 #define PQI_RAID_STATUS_CMD_TERMINATED PQI_AIO_STATUS_CMD_TERMINATED 459 #define PQI_RAID_STATUS_QUEUE_FULL PQI_AIO_STATUS_QUEUE_FULL 460 #define PQI_RAID_STATUS_TASK_ABORTED PQI_AIO_STATUS_TASK_ABORTED 461 #define PQI_RAID_STATUS_UNDERRUN PQI_AIO_STATUS_UNDERRUN 462 #define PQI_RAID_STATUS_OVERRUN PQI_AIO_STATUS_OVERRUN 463 464 /* VPD inquiry pages */ 465 #define SCSI_VPD_SUPPORTED_PAGES 0x0 /* standard page */ 466 #define SCSI_VPD_DEVICE_ID 0x83 /* standard page */ 467 #define SA_VPD_PHYS_DEVICE_ID 0xc0 /* vendor-specific page */ 468 #define SA_VPD_LV_DEVICE_GEOMETRY 0xc1 /* vendor-specific page */ 469 #define SA_VPD_LV_IOACCEL_STATUS 0xc2 /* vendor-specific page */ 470 #define SA_VPD_LV_STATUS 0xc3 /* vendor-specific page */ 471 472 #define VPD_PAGE (1 << 8) 473 474 475 /* logical volume states */ 476 #define SA_LV_OK 0x0 477 #define SA_LV_NOT_AVAILABLE 0xb 478 #define SA_LV_UNDERGOING_ERASE 0xf 479 #define SA_LV_UNDERGOING_RPI 0x12 480 #define SA_LV_PENDING_RPI 0x13 481 #define SA_LV_ENCRYPTED_NO_KEY 0x14 482 #define SA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER 0x15 483 #define SA_LV_UNDERGOING_ENCRYPTION 0x16 484 #define SA_LV_UNDERGOING_ENCRYPTION_REKEYING 0x17 485 #define SA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER 0x18 486 #define SA_LV_PENDING_ENCRYPTION 0x19 487 #define SA_LV_PENDING_ENCRYPTION_REKEYING 0x1a 488 #define SA_LV_STATUS_VPD_UNSUPPORTED 0xff 489 490 /* 491 * assume worst case: SATA queue depth of 31 minus 4 internal firmware commands 492 */ 493 #define PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 27 494 495 /* 0 = no limit */ 496 #define PQI_LOGICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 0 497 498 499 500 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" 501 502 #define SA_CACHE_FLUSH 0x1 503 #define SA_INQUIRY 0x12 504 #define SA_REPORT_LOG 0xc2 /* Report Logical LUNs */ 505 #define SA_REPORT_PHYS 0xc3 /* Report Physical LUNs */ 506 #define SA_CISS_READ 0xc0 507 #define SA_GET_RAID_MAP 0xc8 508 509 #define SA_REPORT_LOG_EXTENDED 0x1 510 #define SA_REPORT_PHYS_EXTENDED 0x2 511 512 #define SA_CACHE_FLUSH_BUF_LEN 4 513 514 #define REPORT_LUN_DEV_FLAG_AIO_ENABLED 0x8 515 #define PQI_MAX_TRANSFER_SIZE (4 * 1024U * 1024U) 516 #define RAID_MAP_MAX_ENTRIES 1024 517 #define RAID_MAP_ENCRYPTION_ENABLED 0x1 518 #define PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 27 519 520 #define ASC_LUN_NOT_READY 0x4 521 #define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x4 522 #define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x2 523 524 525 #define OBDR_SIG_OFFSET 43 526 #define OBDR_TAPE_SIG "$DR-10" 527 #define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1) 528 #define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN) 529 530 531 #define IOACCEL_STATUS_BYTE 4 532 #define OFFLOAD_CONFIGURED_BIT 0x1 533 #define OFFLOAD_ENABLED_BIT 0x2 534 535 #define PQI_RAID_DATA_IN_OUT_GOOD 0x0 536 #define PQI_RAID_DATA_IN_OUT_UNDERFLOW 0x1 537 #define PQI_RAID_DATA_IN_OUT_UNSOLICITED_ABORT 0xf3 538 #define PQI_RAID_DATA_IN_OUT_ABORTED 0xf4 539 540 #define PQI_PHYSICAL_DEVICE_BUS 0 541 #define PQI_RAID_VOLUME_BUS 1 542 #define PQI_HBA_BUS 2 543 #define PQI_EXTERNAL_RAID_VOLUME_BUS 3 544 #define PQI_MAX_BUS PQI_EXTERNAL_RAID_VOLUME_BUS 545 546 #define TEST_UNIT_READY 0x00 547 #define SCSI_VPD_HEADER_LENGTH 64 548 549 550 #define PQI_MAX_MULTILUN 256 551 #define PQI_MAX_LOGICALS 64 552 #define PQI_MAX_PHYSICALS 1024 553 #define PQI_MAX_DEVICES (PQI_MAX_LOGICALS + PQI_MAX_PHYSICALS + 1) /* 1 for controller device entry */ 554 #define PQI_MAX_EXT_TARGETS 32 555 556 #define PQI_CTLR_INDEX (PQI_MAX_DEVICES - 1) 557 #define PQI_PD_INDEX(t) (t + PQI_MAX_LOGICALS) 558 559 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 560 #define MAX_TARGET_DEVICES 1024 561 562 #define PQI_NO_MEM 2 563 564 typedef enum pqisrc_device_status { 565 DEVICE_NOT_FOUND, 566 DEVICE_CHANGED, 567 DEVICE_UNCHANGED, 568 } device_status_t; 569 570 #define SA_RAID_0 0 571 #define SA_RAID_4 1 572 #define SA_RAID_1 2 /* also used for RAID 10 */ 573 #define SA_RAID_5 3 /* also used for RAID 50 */ 574 #define SA_RAID_51 4 575 #define SA_RAID_6 5 /* also used for RAID 60 */ 576 #define SA_RAID_ADM 6 /* also used for RAID 1+0 ADM */ 577 #define SA_RAID_MAX SA_RAID_ADM 578 #define SA_RAID_UNKNOWN 0xff 579 580 /* BMIC commands */ 581 #define BMIC_IDENTIFY_CONTROLLER 0x11 582 #define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15 583 #define BMIC_READ 0x26 584 #define BMIC_WRITE 0x27 585 #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64 586 #define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66 587 #define BMIC_CACHE_FLUSH 0xc2 588 #define BMIC_FLASH_FIRMWARE 0xf7 589 #define BMIC_WRITE_HOST_WELLNESS 0xa5 590 591 592 #define MASKED_DEVICE(lunid) ((lunid)[3] & 0xC0) 593 #define BMIC_GET_LEVEL_2_BUS(lunid) ((lunid)[7] & 0x3F) 594 #define BMIC_GET_LEVEL_TWO_TARGET(lunid) ((lunid)[6]) 595 #define BMIC_GET_DRIVE_NUMBER(lunid) \ 596 (((BMIC_GET_LEVEL_2_BUS((lunid)) - 1) << 8) + \ 597 BMIC_GET_LEVEL_TWO_TARGET((lunid))) 598 #define NON_DISK_PHYS_DEV(rle) \ 599 (((reportlun_ext_entry_t *)(rle))->device_flags & 0x1) 600 601 #define NO_TIMEOUT ((unsigned long) -1) 602 603 #define BMIC_DEVICE_TYPE_SATA 0x1 604 605 /* No of IO slots required for internal requests */ 606 #define PQI_RESERVED_IO_SLOTS_SYNC_REQUESTS 3 607 #define PQI_RESERVED_IO_SLOTS_TMF 1 608 #define PQI_RESERVED_IO_SLOTS_CNT (PQI_NUM_SUPPORTED_EVENTS + \ 609 PQI_RESERVED_IO_SLOTS_TMF + \ 610 PQI_RESERVED_IO_SLOTS_SYNC_REQUESTS) 611 612 static inline uint16_t GET_LE16(const uint8_t *p) 613 { 614 return p[0] | p[1] << 8; 615 } 616 617 static inline uint32_t GET_LE32(const uint8_t *p) 618 { 619 return p[0] | p[1] << 8 | p[2] << 16 | p[3] << 24; 620 } 621 622 static inline uint64_t GET_LE64(const uint8_t *p) 623 { 624 return (((uint64_t)GET_LE32(p + 4) << 32) | 625 GET_LE32(p)); 626 } 627 628 static inline uint16_t GET_BE16(const uint8_t *p) 629 { 630 return p[0] << 8 | p[1]; 631 } 632 633 static inline uint32_t GET_BE32(const uint8_t *p) 634 { 635 return p[0] << 24 | p[1] << 16 | p[2] << 8 | p[3]; 636 } 637 638 static inline uint64_t GET_BE64(const uint8_t *p) 639 { 640 return (((uint64_t)GET_BE32(p) << 32) | 641 GET_BE32(p + 4)); 642 } 643 644 static inline void PUT_BE16(uint16_t val, uint8_t *p) 645 { 646 *p++ = val >> 8; 647 *p++ = val; 648 } 649 650 static inline void PUT_BE32(uint32_t val, uint8_t *p) 651 { 652 PUT_BE16(val >> 16, p); 653 PUT_BE16(val, p + 2); 654 } 655 656 static inline void PUT_BE64(uint64_t val, uint8_t *p) 657 { 658 PUT_BE32(val >> 32, p); 659 PUT_BE32(val, p + 4); 660 } 661 662 663 #define OS_FREEBSD 664 #define SIS_POLL_WAIT 665 666 #define OS_ATTRIBUTE_PACKED __attribute__((__packed__)) 667 #define OS_ATTRIBUTE_ALIGNED(n) __attribute__((aligned(n))) 668 669 670 /* Management Interface */ 671 #define CCISS_IOC_MAGIC 'C' 672 #define SMARTPQI_IOCTL_BASE 'M' 673 #define CCISS_GETDRIVVER _IOWR(SMARTPQI_IOCTL_BASE, 0, driver_info) 674 #define CCISS_GETPCIINFO _IOWR(SMARTPQI_IOCTL_BASE, 1, pqi_pci_info_t) 675 #define SMARTPQI_PASS_THRU _IOWR(SMARTPQI_IOCTL_BASE, 2, IOCTL_Command_struct) 676 #define CCISS_PASSTHRU _IOWR('C', 210, IOCTL_Command_struct) 677 #define CCISS_REGNEWD _IO(CCISS_IOC_MAGIC, 14) 678 679 /*IOCTL pci_info structure */ 680 typedef struct pqi_pci_info 681 { 682 unsigned char bus; 683 unsigned char dev_fn; 684 unsigned short domain; 685 uint32_t board_id; 686 uint32_t chip_id; 687 }pqi_pci_info_t; 688 689 typedef struct _driver_info 690 { 691 unsigned char major_version; 692 unsigned char minor_version; 693 unsigned char release_version; 694 unsigned long build_revision; 695 unsigned long max_targets; 696 unsigned long max_io; 697 unsigned long max_transfer_length; 698 }driver_info, *pdriver_info; 699 700 typedef uint8_t *passthru_buf_type_t; 701 702 703 #define PQISRC_DRIVER_MAJOR 1 704 #define PQISRC_DRIVER_MINOR 0 705 #define PQISRC_DRIVER_RELEASE 3 706 #define PQISRC_DRIVER_REVISION 239 707 708 #define STR(s) # s 709 #define PQISRC_VERSION(a, b, c, d) STR(a.b.c-d) 710 #define PQISRC_DRIVER_VERSION PQISRC_VERSION(PQISRC_DRIVER_MAJOR, \ 711 PQISRC_DRIVER_MINOR, \ 712 PQISRC_DRIVER_RELEASE, \ 713 PQISRC_DRIVER_REVISION) 714 715 /* End Management interface */ 716 717 #ifdef ASSERT 718 #undef ASSERT 719 #endif 720 721 #define ASSERT(cond) {\ 722 if (!(cond)) { \ 723 printf("Assertion failed at file %s line %d\n",__FILE__,__LINE__); \ 724 } \ 725 } 726 727 728 #define PQI_MAX_MSIX 64 /* vectors */ 729 #define PQI_MSI_CTX_SIZE sizeof(pqi_intr_ctx)+1 730 #define IS_POLLING_REQUIRED(softs) if (cold) {\ 731 pqisrc_process_event_intr_src(softs, 0);\ 732 pqisrc_process_response_queue(softs, 1);\ 733 } 734 735 #define OS_GET_TASK_ATTR(rcb) os_get_task_attr(rcb) 736 #define OS_FW_HEARTBEAT_TIMER_INTERVAL (5) 737 738 typedef struct PCI_ACC_HANDLE { 739 bus_space_tag_t pqi_btag; 740 bus_space_handle_t pqi_bhandle; 741 } PCI_ACC_HANDLE_T; 742 743 /* 744 * Legacy SIS Register definitions for the Adaptec PMC SRC/SRCv/smartraid adapters. 745 */ 746 /* accessible via BAR0 */ 747 #define LEGACY_SIS_IOAR 0x18 /* IOA->host interrupt register */ 748 #define LEGACY_SIS_IDBR 0x20 /* inbound doorbell register */ 749 #define LEGACY_SIS_IISR 0x24 /* inbound interrupt status register */ 750 #define LEGACY_SIS_OIMR 0x34 /* outbound interrupt mask register */ 751 #define LEGACY_SIS_ODBR_R 0x9c /* outbound doorbell register read */ 752 #define LEGACY_SIS_ODBR_C 0xa0 /* outbound doorbell register clear */ 753 754 #define LEGACY_SIS_SCR0 0xb0 /* scratchpad 0 */ 755 #define LEGACY_SIS_OMR 0xbc /* outbound message register */ 756 #define LEGACY_SIS_IQUE64_L 0xc0 /* inbound queue address 64-bit (low) */ 757 #define LEGACY_SIS_IQUE64_H 0xc4 /* inbound queue address 64-bit (high)*/ 758 #define LEGACY_SIS_ODBR_MSI 0xc8 /* MSI register for sync./AIF */ 759 #define LEGACY_SIS_IQN_L 0xd0 /* inbound queue native mode (low) */ 760 #define LEGACY_SIS_IQN_H 0xd4 /* inbound queue native mode (high)*/ 761 #define LEGACY_SIS_MAILBOX 0x7fc60 /* mailbox (20 bytes) */ 762 #define LEGACY_SIS_SRCV_MAILBOX 0x1000 /* mailbox (20 bytes) */ 763 764 #define LEGACY_SIS_ODR_SHIFT 12 /* outbound doorbell shift */ 765 #define LEGACY_SIS_IDR_SHIFT 9 /* inbound doorbell shift */ 766 767 768 /* 769 * PQI Register definitions for the smartraid adapters 770 */ 771 /* accessible via BAR0 */ 772 #define PQI_SIGNATURE 0x4000 773 #define PQI_ADMINQ_CONFIG 0x4008 774 #define PQI_ADMINQ_CAP 0x4010 775 #define PQI_LEGACY_INTR_STATUS 0x4018 776 #define PQI_LEGACY_INTR_MASK_SET 0x401C 777 #define PQI_LEGACY_INTR_MASK_CLR 0x4020 778 #define PQI_DEV_STATUS 0x4040 779 #define PQI_ADMIN_IBQ_PI_OFFSET 0x4048 780 #define PQI_ADMIN_OBQ_CI_OFFSET 0x4050 781 #define PQI_ADMIN_IBQ_ELEM_ARRAY_ADDR 0x4058 782 #define PQI_ADMIN_OBQ_ELEM_ARRAY_ADDR 0x4060 783 #define PQI_ADMIN_IBQ_CI_ADDR 0x4068 784 #define PQI_ADMIN_OBQ_PI_ADDR 0x4070 785 #define PQI_ADMINQ_PARAM 0x4078 786 #define PQI_DEV_ERR 0x4080 787 #define PQI_DEV_ERR_DETAILS 0x4088 788 #define PQI_DEV_RESET 0x4090 789 #define PQI_POWER_ACTION 0x4094 790 791 /* Busy wait micro seconds */ 792 #define OS_BUSYWAIT(x) DELAY(x) 793 #define OS_SLEEP(timeout) \ 794 DELAY(timeout); 795 796 #define OS_HOST_WELLNESS_TIMEOUT (24 * 3600) 797 798 799 #define LE_16(x) htole16(x) 800 #define LE_32(x) htole32(x) 801 #define LE_64(x) htole64(x) 802 #define BE_16(x) htobe16(x) 803 #define BE_32(x) htobe32(x) 804 #define BE_64(x) htobe64(x) 805 806 #define PQI_HWIF_SRCV 0 807 #define PQI_HWIF_UNKNOWN -1 808 809 810 #define SMART_STATE_SUSPEND (1<<0) 811 #define SMART_STATE_UNUSED0 (1<<1) 812 #define SMART_STATE_INTERRUPTS_ON (1<<2) 813 #define SMART_STATE_AIF_SLEEPER (1<<3) 814 #define SMART_STATE_RESET (1<<4) 815 816 #define PQI_FLAG_BUSY (1<<0) 817 #define PQI_MSI_ENABLED (1<<1) 818 #define PQI_SIM_REGISTERED (1<<2) 819 #define PQI_MTX_INIT (1<<3) 820 821 822 #define PQI_CMD_MAPPED (1<<2) 823 824 /* Interrupt context to get oq_id */ 825 typedef struct pqi_intr_ctx { 826 int oq_id; 827 device_t pqi_dev; 828 }pqi_intr_ctx_t; 829 830 typedef uint8_t os_dev_info_t; 831 832 typedef struct OS_SPECIFIC { 833 device_t pqi_dev; 834 struct resource *pqi_regs_res0; /* reg. if. window */ 835 int pqi_regs_rid0; /* resource ID */ 836 bus_dma_tag_t pqi_parent_dmat; /* parent DMA tag */ 837 bus_dma_tag_t pqi_buffer_dmat; 838 839 /* controller hardware interface */ 840 int pqi_hwif; 841 struct resource *pqi_irq[PQI_MAX_MSIX]; /* interrupt */ 842 int pqi_irq_rid[PQI_MAX_MSIX]; 843 void *intrcookie[PQI_MAX_MSIX]; 844 bool intr_registered[PQI_MAX_MSIX]; 845 bool msi_enabled; /* MSI/MSI-X enabled */ 846 pqi_intr_ctx_t *msi_ctx; 847 int oq_id; 848 int pqi_state; 849 uint32_t pqi_flags; 850 struct mtx cam_lock; 851 struct mtx map_lock; 852 int mtx_init; 853 int sim_registered; 854 struct cam_devq *devq; 855 struct cam_sim *sim; 856 struct cam_path *path; 857 struct task event_task; 858 struct cdev *cdev; 859 struct callout wellness_periodic; /* periodic event handling */ 860 struct callout heartbeat_timeout_id; /* heart beat event handling */ 861 eventhandler_tag eh; 862 } OS_SPECIFIC_T; 863 864 typedef bus_addr_t dma_addr_t; 865 866 /* Atomic */ 867 typedef volatile uint64_t OS_ATOMIC64_T; 868 #define OS_ATOMIC64_SET(_softs, target, val) atomic_set_long(&(_softs)->target, val) 869 #define OS_ATOMIC64_READ(_softs, target) atomic_load_acq_64(&(_softs)->target) 870 #define OS_ATOMIC64_INC(_softs, target) atomic_add_64(&(_softs)->target, 1) 871 872 /* Register access macros */ 873 #define PCI_MEM_GET32( _softs, _absaddr, _offset ) \ 874 bus_space_read_4(_softs->pci_mem_handle.pqi_btag, \ 875 _softs->pci_mem_handle.pqi_bhandle, _offset) 876 877 #define PCI_MEM_GET64( _softs, _absaddr, _offset ) \ 878 bus_space_read_8(_softs->pci_mem_handle.pqi_btag, \ 879 _softs->pci_mem_handle.pqi_bhandle, _offset) 880 881 #define PCI_MEM_PUT32( _softs, _absaddr, _offset, _val ) \ 882 bus_space_write_4(_softs->pci_mem_handle.pqi_btag, \ 883 _softs->pci_mem_handle.pqi_bhandle, _offset, _val) 884 885 #define PCI_MEM_PUT64( _softs, _absaddr, _offset, _val ) \ 886 bus_space_write_8(_softs->pci_mem_handle.pqi_btag, \ 887 _softs->pci_mem_handle.pqi_bhandle, _offset, _val) 888 889 #define PCI_MEM_GET_BUF(_softs, _absaddr, _offset, buf, size) \ 890 bus_space_read_region_1(_softs->pci_mem_handle.pqi_btag,\ 891 _softs->pci_mem_handle.pqi_bhandle, _offset, buf, size) 892 893 /* Lock */ 894 typedef struct mtx OS_LOCK_T; 895 typedef struct sema OS_SEMA_LOCK_T; 896 897 #define OS_PQILOCK_T OS_LOCK_T 898 899 #define OS_ACQUIRE_SPINLOCK(_lock) mtx_lock_spin(_lock) 900 #define OS_RELEASE_SPINLOCK(_lock) mtx_unlock_spin(_lock) 901 902 #define OS_INIT_PQILOCK(_softs,_lock,_lockname) os_init_spinlock(_softs,_lock,_lockname) 903 #define OS_UNINIT_PQILOCK(_lock) os_uninit_spinlock(_lock) 904 905 #define PQI_LOCK(_lock) OS_ACQUIRE_SPINLOCK(_lock) 906 #define PQI_UNLOCK(_lock) OS_RELEASE_SPINLOCK(_lock) 907 908 #define OS_GET_CDBP(rcb) ((rcb->cm_ccb->ccb_h.flags & CAM_CDB_POINTER) ? rcb->cm_ccb->csio.cdb_io.cdb_ptr : rcb->cm_ccb->csio.cdb_io.cdb_bytes) 909 #define GET_SCSI_BUFFLEN(rcb) (rcb->cm_ccb->csio.dxfer_len) 910 911 #define OS_GET_IO_QINDEX(softs,rcb) curcpu % softs->num_op_obq 912 #define OS_GET_IO_RESP_QID(softs,rcb) (softs->op_ob_q[(OS_GET_IO_QINDEX(softs,rcb))].q_id) 913 #define OS_GET_IO_REQ_QINDEX(softs,rcb) OS_GET_IO_QINDEX(softs,rcb) 914 #define OS_GET_TMF_RESP_QID OS_GET_IO_RESP_QID 915 #define OS_GET_TMF_REQ_QINDEX OS_GET_IO_REQ_QINDEX 916 917 /* check request type */ 918 #define is_internal_req(rcb) (!(rcb)->cm_ccb) 919 920 /* sg elements addr, len, flags */ 921 #define OS_GET_IO_SG_COUNT(rcb) rcb->nseg 922 #define OS_GET_IO_SG_ADDR(rcb,i) rcb->sgt[i].addr 923 #define OS_GET_IO_SG_LEN(rcb,i) rcb->sgt[i].len 924 925 /* scsi commands used in pqilib for RAID bypass*/ 926 #define SCMD_READ_6 READ_6 927 #define SCMD_WRITE_6 WRITE_6 928 #define SCMD_READ_10 READ_10 929 #define SCMD_WRITE_10 WRITE_10 930 #define SCMD_READ_12 READ_12 931 #define SCMD_WRITE_12 WRITE_12 932 #define SCMD_READ_16 READ_16 933 #define SCMD_WRITE_16 WRITE_16 934 935 /* Debug facility */ 936 937 #define PQISRC_LOG_LEVEL 0x60 938 939 static int logging_level = PQISRC_LOG_LEVEL; 940 941 #define PQISRC_FLAGS_MASK 0x0000ffff 942 #define PQISRC_FLAGS_INIT 0x00000001 943 #define PQISRC_FLAGS_INFO 0x00000002 944 #define PQISRC_FLAGS_FUNC 0x00000004 945 #define PQISRC_FLAGS_TRACEIO 0x00000008 946 #define PQISRC_FLAGS_DISC 0x00000010 947 #define PQISRC_FLAGS_WARN 0x00000020 948 #define PQISRC_FLAGS_ERROR 0x00000040 949 950 951 #define DBG_INIT(fmt,args...) \ 952 do { \ 953 if (logging_level & PQISRC_FLAGS_INIT) { \ 954 printf("[INIT]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \ 955 } \ 956 }while(0); 957 958 #define DBG_INFO(fmt,args...) \ 959 do { \ 960 if (logging_level & PQISRC_FLAGS_INFO) { \ 961 printf("[INFO]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \ 962 } \ 963 }while(0); 964 965 #define DBG_FUNC(fmt,args...) \ 966 do { \ 967 if (logging_level & PQISRC_FLAGS_FUNC) { \ 968 printf("[FUNC]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \ 969 } \ 970 }while(0); 971 972 #define DBG_TRACEIO(fmt,args...) \ 973 do { \ 974 if (logging_level & PQISRC_FLAGS_TRACEIO) { \ 975 printf("[TRACEIO]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \ 976 } \ 977 }while(0); 978 979 #define DBG_DISC(fmt,args...) \ 980 do { \ 981 if (logging_level & PQISRC_FLAGS_DISC) { \ 982 printf("[DISC]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \ 983 } \ 984 }while(0); 985 986 #define DBG_WARN(fmt,args...) \ 987 do { \ 988 if (logging_level & PQISRC_FLAGS_WARN) { \ 989 printf("[WARN]:[%u:%u.%u][CPU %d][%s][%d]:"fmt,softs->bus_id,softs->device_id,softs->func_id,curcpu,__func__,__LINE__,##args);\ 990 } \ 991 }while(0); 992 993 #define DBG_ERR(fmt,args...) \ 994 do { \ 995 if (logging_level & PQISRC_FLAGS_ERROR) { \ 996 printf("[ERROR]::[%u:%u.%u][CPU %d][%s][%d]:"fmt,softs->bus_id,softs->device_id,softs->func_id,curcpu,__func__,__LINE__,##args); \ 997 } \ 998 }while(0); 999 #define DBG_IO(fmt,args...) \ 1000 do { \ 1001 if (logging_level & PQISRC_FLAGS_TRACEIO) { \ 1002 printf("[IO]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \ 1003 } \ 1004 }while(0); 1005 1006 #define DBG_ERR_BTL(device,fmt,args...) \ 1007 do { \ 1008 if (logging_level & PQISRC_FLAGS_ERROR) { \ 1009 printf("[ERROR]::[%u:%u.%u][%u,%u,%u][CPU %d][%s][%d]:"fmt, softs->bus_id, softs->device_id, softs->func_id, device->bus, device->target, device->lun,curcpu,__func__,__LINE__,##args); \ 1010 } \ 1011 }while(0); 1012 1013 #define DBG_WARN_BTL(device,fmt,args...) \ 1014 do { \ 1015 if (logging_level & PQISRC_FLAGS_WARN) { \ 1016 printf("[WARN]:[%u:%u.%u][%u,%u,%u][CPU %d][%s][%d]:"fmt, softs->bus_id, softs->device_id, softs->func_id, device->bus, device->target, device->lun,curcpu,__func__,__LINE__,##args);\ 1017 } \ 1018 }while(0); 1019 1020 #endif // _PQI_DEFINES_H 1021