1 /*- 2 * Copyright (c) 2018 Microsemi Corporation. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* $FreeBSD$ */ 28 29 /* 30 * Driver for the Microsemi Smart storage controllers 31 */ 32 33 #include "smartpqi_includes.h" 34 #include "smartpqi_prototypes.h" 35 36 /* 37 * Supported devices 38 */ 39 struct pqi_ident 40 { 41 u_int16_t vendor; 42 u_int16_t device; 43 u_int16_t subvendor; 44 u_int16_t subdevice; 45 int hwif; 46 char *desc; 47 } pqi_identifiers[] = { 48 /* (MSCC PM8205 8x12G based) */ 49 {0x9005, 0x028f, 0x103c, 0x600, PQI_HWIF_SRCV, "P408i-p SR Gen10"}, 50 {0x9005, 0x028f, 0x103c, 0x601, PQI_HWIF_SRCV, "P408e-p SR Gen10"}, 51 {0x9005, 0x028f, 0x103c, 0x602, PQI_HWIF_SRCV, "P408i-a SR Gen10"}, 52 {0x9005, 0x028f, 0x103c, 0x603, PQI_HWIF_SRCV, "P408i-c SR Gen10"}, 53 {0x9005, 0x028f, 0x1028, 0x1FE0, PQI_HWIF_SRCV, "SmartRAID 3162-8i/eDell"}, 54 {0x9005, 0x028f, 0x9005, 0x608, PQI_HWIF_SRCV, "SmartRAID 3162-8i/e"}, 55 {0x9005, 0x028f, 0x103c, 0x609, PQI_HWIF_SRCV, "P408i-sb SR G10"}, 56 57 /* (MSCC PM8225 8x12G based) */ 58 {0x9005, 0x028f, 0x103c, 0x650, PQI_HWIF_SRCV, "E208i-p SR Gen10"}, 59 {0x9005, 0x028f, 0x103c, 0x651, PQI_HWIF_SRCV, "E208e-p SR Gen10"}, 60 {0x9005, 0x028f, 0x103c, 0x652, PQI_HWIF_SRCV, "E208i-c SR Gen10"}, 61 {0x9005, 0x028f, 0x103c, 0x654, PQI_HWIF_SRCV, "E208i-a SR Gen10"}, 62 {0x9005, 0x028f, 0x103c, 0x655, PQI_HWIF_SRCV, "P408e-m SR Gen10"}, 63 64 /* (MSCC PM8221 8x12G based) */ 65 {0x9005, 0x028f, 0x103c, 0x700, PQI_HWIF_SRCV, "P204i-c SR Gen10"}, 66 {0x9005, 0x028f, 0x103c, 0x701, PQI_HWIF_SRCV, "P204i-b SR Gen10"}, 67 68 /* (MSCC PM8204 8x12G based) */ 69 {0x9005, 0x028f, 0x9005, 0x800, PQI_HWIF_SRCV, "SmartRAID 3154-8i"}, 70 {0x9005, 0x028f, 0x9005, 0x801, PQI_HWIF_SRCV, "SmartRAID 3152-8i"}, 71 {0x9005, 0x028f, 0x9005, 0x802, PQI_HWIF_SRCV, "SmartRAID 3151-4i"}, 72 {0x9005, 0x028f, 0x9005, 0x803, PQI_HWIF_SRCV, "SmartRAID 3101-4i"}, 73 {0x9005, 0x028f, 0x9005, 0x804, PQI_HWIF_SRCV, "SmartRAID 3154-8e"}, 74 {0x9005, 0x028f, 0x9005, 0x805, PQI_HWIF_SRCV, "SmartRAID 3102-8i"}, 75 {0x9005, 0x028f, 0x9005, 0x806, PQI_HWIF_SRCV, "SmartRAID 3100"}, 76 {0x9005, 0x028f, 0x9005, 0x807, PQI_HWIF_SRCV, "SmartRAID 3162-8i"}, 77 {0x9005, 0x028f, 0x152d, 0x8a22, PQI_HWIF_SRCV, "QS-8204-8i"}, 78 {0x9005, 0x028f, 0x193d, 0xf460, PQI_HWIF_SRCV, "UN RAID P460-M4"}, 79 {0x9005, 0x028f, 0x193d, 0xf461, PQI_HWIF_SRCV, "UN RAID P460-B4"}, 80 {0x9005, 0x028f, 0x1bd4, 0x004b, PQI_HWIF_SRCV, "INSPUR RAID PM8204-2GB"}, 81 {0x9005, 0x028f, 0x1bd4, 0x004c, PQI_HWIF_SRCV, "INSPUR RAID PM8204-4GB"}, 82 83 /* (MSCC PM8222 8x12G based) */ 84 {0x9005, 0x028f, 0x9005, 0x900, PQI_HWIF_SRCV, "SmartHBA 2100-8i"}, 85 {0x9005, 0x028f, 0x9005, 0x901, PQI_HWIF_SRCV, "SmartHBA 2100-4i"}, 86 {0x9005, 0x028f, 0x9005, 0x902, PQI_HWIF_SRCV, "HBA 1100-8i"}, 87 {0x9005, 0x028f, 0x9005, 0x903, PQI_HWIF_SRCV, "HBA 1100-4i"}, 88 {0x9005, 0x028f, 0x9005, 0x904, PQI_HWIF_SRCV, "SmartHBA 2100-8e"}, 89 {0x9005, 0x028f, 0x9005, 0x905, PQI_HWIF_SRCV, "HBA 1100-8e"}, 90 {0x9005, 0x028f, 0x9005, 0x906, PQI_HWIF_SRCV, "SmartHBA 2100-4i4e"}, 91 {0x9005, 0x028f, 0x9005, 0x907, PQI_HWIF_SRCV, "HBA 1100"}, 92 {0x9005, 0x028f, 0x9005, 0x908, PQI_HWIF_SRCV, "SmartHBA 2100"}, 93 {0x9005, 0x028f, 0x9005, 0x90a, PQI_HWIF_SRCV, "SmartHBA 2100A-8i"}, 94 {0x9005, 0x028f, 0x193d, 0x8460, PQI_HWIF_SRCV, "UN HBA H460-M1"}, 95 {0x9005, 0x028f, 0x193d, 0x8461, PQI_HWIF_SRCV, "UN HBA H460-B1"}, 96 {0x9005, 0x028f, 0x1bd4, 0x004a, PQI_HWIF_SRCV, "INSPUR SMART-HBA PM8222-SHBA"}, 97 {0x9005, 0x028f, 0x13fe, 0x8312, PQI_HWIF_SRCV, "MIC-8312BridgeB"}, 98 99 /* (SRCx MSCC FVB 24x12G based) */ 100 {0x9005, 0x028f, 0x103c, 0x1001, PQI_HWIF_SRCV, "MSCC FVB"}, 101 102 /* (MSCC PM8241 24x12G based) */ 103 104 /* (MSCC PM8242 24x12G based) */ 105 {0x9005, 0x028f, 0x152d, 0x8a37, PQI_HWIF_SRCV, "QS-8242-24i"}, 106 {0x9005, 0x028f, 0x9005, 0x1300, PQI_HWIF_SRCV, "HBA 1100-8i8e"}, 107 {0x9005, 0x028f, 0x9005, 0x1301, PQI_HWIF_SRCV, "HBA 1100-24i"}, 108 {0x9005, 0x028f, 0x9005, 0x1302, PQI_HWIF_SRCV, "SmartHBA 2100-8i8e"}, 109 {0x9005, 0x028f, 0x9005, 0x1303, PQI_HWIF_SRCV, "SmartHBA 2100-24i"}, 110 {0x9005, 0x028f, 0x105b, 0x1321, PQI_HWIF_SRCV, "8242-24i"}, 111 {0x9005, 0x028f, 0x1bd4, 0x0045, PQI_HWIF_SRCV, "INSPUR SMART-HBA 8242-24i"}, 112 113 /* (MSCC PM8236 16x12G based) */ 114 {0x9005, 0x028f, 0x152d, 0x8a24, PQI_HWIF_SRCV, "QS-8236-16i"}, 115 {0x9005, 0x028f, 0x9005, 0x1380, PQI_HWIF_SRCV, "SmartRAID 3154-16i"}, 116 {0x9005, 0x028f, 0x1bd4, 0x0046, PQI_HWIF_SRCV, "INSPUR RAID 8236-16i"}, 117 118 /* (MSCC PM8237 24x12G based) */ 119 {0x9005, 0x028f, 0x103c, 0x1100, PQI_HWIF_SRCV, "P816i-a SR Gen10"}, 120 {0x9005, 0x028f, 0x103c, 0x1101, PQI_HWIF_SRCV, "P416ie-m SR G10"}, 121 122 /* (MSCC PM8238 16x12G based) */ 123 {0x9005, 0x028f, 0x152d, 0x8a23, PQI_HWIF_SRCV, "QS-8238-16i"}, 124 {0x9005, 0x028f, 0x9005, 0x1280, PQI_HWIF_SRCV, "HBA 1100-16i"}, 125 {0x9005, 0x028f, 0x9005, 0x1281, PQI_HWIF_SRCV, "HBA 1100-16e"}, 126 {0x9005, 0x028f, 0x105b, 0x1211, PQI_HWIF_SRCV, "8238-16i"}, 127 {0x9005, 0x028f, 0x1bd4, 0x0048, PQI_HWIF_SRCV, "INSPUR SMART-HBA 8238-16i"}, 128 {0x9005, 0x028f, 0x9005, 0x1282, PQI_HWIF_SRCV, "SmartHBA 2100-16i"}, 129 130 /* (MSCC PM8240 24x12G based) */ 131 {0x9005, 0x028f, 0x152d, 0x8a36, PQI_HWIF_SRCV, "QS-8240-24i"}, 132 {0x9005, 0x028f, 0x9005, 0x1200, PQI_HWIF_SRCV, "SmartRAID 3154-24i"}, 133 {0x9005, 0x028f, 0x9005, 0x1201, PQI_HWIF_SRCV, "SmartRAID 3154-8i16e"}, 134 {0x9005, 0x028f, 0x9005, 0x1202, PQI_HWIF_SRCV, "SmartRAID 3154-8i8e"}, 135 {0x9005, 0x028f, 0x1bd4, 0x0047, PQI_HWIF_SRCV, "INSPUR RAID 8240-24i"}, 136 {0, 0, 0, 0, 0, 0} 137 }; 138 139 struct pqi_ident 140 pqi_family_identifiers[] = { 141 {0x9005, 0x028f, 0, 0, PQI_HWIF_SRCV, "Smart Array Storage Controller"}, 142 {0, 0, 0, 0, 0, 0} 143 }; 144 145 /* 146 * Function to identify the installed adapter. 147 */ 148 static struct pqi_ident * 149 pqi_find_ident(device_t dev) 150 { 151 struct pqi_ident *m; 152 u_int16_t vendid, devid, sub_vendid, sub_devid; 153 154 vendid = pci_get_vendor(dev); 155 devid = pci_get_device(dev); 156 sub_vendid = pci_get_subvendor(dev); 157 sub_devid = pci_get_subdevice(dev); 158 159 for (m = pqi_identifiers; m->vendor != 0; m++) { 160 if ((m->vendor == vendid) && (m->device == devid) && 161 (m->subvendor == sub_vendid) && 162 (m->subdevice == sub_devid)) { 163 return (m); 164 } 165 } 166 167 for (m = pqi_family_identifiers; m->vendor != 0; m++) { 168 if ((m->vendor == vendid) && (m->device == devid)) { 169 return (m); 170 } 171 } 172 173 return (NULL); 174 } 175 176 /* 177 * Determine whether this is one of our supported adapters. 178 */ 179 static int 180 smartpqi_probe(device_t dev) 181 { 182 struct pqi_ident *id; 183 184 if ((id = pqi_find_ident(dev)) != NULL) { 185 device_set_desc(dev, id->desc); 186 return(BUS_PROBE_VENDOR); 187 } 188 189 return(ENXIO); 190 } 191 192 /* 193 * Store Bus/Device/Function in softs 194 */ 195 void pqisrc_save_controller_info(struct pqisrc_softstate *softs) 196 { 197 device_t dev = softs->os_specific.pqi_dev; 198 199 softs->bus_id = (uint32_t)pci_get_bus(dev); 200 softs->device_id = (uint32_t)pci_get_device(dev); 201 softs->func_id = (uint32_t)pci_get_function(dev); 202 } 203 204 /* 205 * Allocate resources for our device, set up the bus interface. 206 * Initialize the PQI related functionality, scan devices, register sim to 207 * upper layer, create management interface device node etc. 208 */ 209 static int 210 smartpqi_attach(device_t dev) 211 { 212 struct pqisrc_softstate *softs = NULL; 213 struct pqi_ident *id = NULL; 214 int error = 0; 215 u_int32_t command = 0, i = 0; 216 int card_index = device_get_unit(dev); 217 rcb_t *rcbp = NULL; 218 219 /* 220 * Initialise softc. 221 */ 222 softs = device_get_softc(dev); 223 224 if (!softs) { 225 printf("Could not get softc\n"); 226 error = EINVAL; 227 goto out; 228 } 229 memset(softs, 0, sizeof(*softs)); 230 softs->os_specific.pqi_dev = dev; 231 232 DBG_FUNC("IN\n"); 233 234 /* assume failure is 'not configured' */ 235 error = ENXIO; 236 237 /* 238 * Verify that the adapter is correctly set up in PCI space. 239 */ 240 pci_enable_busmaster(softs->os_specific.pqi_dev); 241 command = pci_read_config(softs->os_specific.pqi_dev, PCIR_COMMAND, 2); 242 if ((command & PCIM_CMD_MEMEN) == 0) { 243 DBG_ERR("memory window not available command = %d\n", command); 244 error = ENXIO; 245 goto out; 246 } 247 248 /* 249 * Detect the hardware interface version, set up the bus interface 250 * indirection. 251 */ 252 id = pqi_find_ident(dev); 253 softs->os_specific.pqi_hwif = id->hwif; 254 255 switch(softs->os_specific.pqi_hwif) { 256 case PQI_HWIF_SRCV: 257 DBG_INFO("set hardware up for PMC SRCv for %p", softs); 258 break; 259 default: 260 softs->os_specific.pqi_hwif = PQI_HWIF_UNKNOWN; 261 DBG_ERR("unknown hardware type\n"); 262 error = ENXIO; 263 goto out; 264 } 265 266 pqisrc_save_controller_info(softs); 267 268 /* 269 * Allocate the PCI register window. 270 */ 271 softs->os_specific.pqi_regs_rid0 = PCIR_BAR(0); 272 if ((softs->os_specific.pqi_regs_res0 = 273 bus_alloc_resource_any(softs->os_specific.pqi_dev, SYS_RES_MEMORY, 274 &softs->os_specific.pqi_regs_rid0, RF_ACTIVE)) == NULL) { 275 DBG_ERR("couldn't allocate register window 0\n"); 276 /* assume failure is 'out of memory' */ 277 error = ENOMEM; 278 goto out; 279 } 280 281 bus_get_resource_start(softs->os_specific.pqi_dev, SYS_RES_MEMORY, 282 softs->os_specific.pqi_regs_rid0); 283 284 softs->pci_mem_handle.pqi_btag = rman_get_bustag(softs->os_specific.pqi_regs_res0); 285 softs->pci_mem_handle.pqi_bhandle = rman_get_bushandle(softs->os_specific.pqi_regs_res0); 286 /* softs->pci_mem_base_vaddr = (uintptr_t)rman_get_virtual(softs->os_specific.pqi_regs_res0); */ 287 softs->pci_mem_base_vaddr = (char *)rman_get_virtual(softs->os_specific.pqi_regs_res0); 288 289 /* 290 * Allocate the parent bus DMA tag appropriate for our PCI interface. 291 * 292 * Note that some of these controllers are 64-bit capable. 293 */ 294 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 295 PAGE_SIZE, 0, /* algnmnt, boundary */ 296 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 297 BUS_SPACE_MAXADDR, /* highaddr */ 298 NULL, NULL, /* filter, filterarg */ 299 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 300 BUS_SPACE_UNRESTRICTED, /* nsegments */ 301 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 302 0, /* flags */ 303 NULL, NULL, /* No locking needed */ 304 &softs->os_specific.pqi_parent_dmat)) { 305 DBG_ERR("can't allocate parent DMA tag\n"); 306 /* assume failure is 'out of memory' */ 307 error = ENOMEM; 308 goto dma_out; 309 } 310 311 softs->os_specific.sim_registered = FALSE; 312 softs->os_name = "FreeBSD "; 313 314 /* Initialize the PQI library */ 315 error = pqisrc_init(softs); 316 if (error) { 317 DBG_ERR("Failed to initialize pqi lib error = %d\n", error); 318 error = PQI_STATUS_FAILURE; 319 goto out; 320 } 321 322 mtx_init(&softs->os_specific.cam_lock, "cam_lock", NULL, MTX_DEF); 323 softs->os_specific.mtx_init = TRUE; 324 mtx_init(&softs->os_specific.map_lock, "map_lock", NULL, MTX_DEF); 325 callout_init(&softs->os_specific.wellness_periodic, 1); 326 callout_init(&softs->os_specific.heartbeat_timeout_id, 1); 327 328 /* 329 * Create DMA tag for mapping buffers into controller-addressable space. 330 */ 331 if (bus_dma_tag_create(softs->os_specific.pqi_parent_dmat,/* parent */ 332 1, 0, /* algnmnt, boundary */ 333 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 334 BUS_SPACE_MAXADDR, /* highaddr */ 335 NULL, NULL, /* filter, filterarg */ 336 softs->pqi_cap.max_sg_elem*PAGE_SIZE,/*maxsize*/ 337 softs->pqi_cap.max_sg_elem, /* nsegments */ 338 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 339 BUS_DMA_ALLOCNOW, /* flags */ 340 busdma_lock_mutex, /* lockfunc */ 341 &softs->os_specific.map_lock, /* lockfuncarg*/ 342 &softs->os_specific.pqi_buffer_dmat)) { 343 DBG_ERR("can't allocate buffer DMA tag for pqi_buffer_dmat\n"); 344 return (ENOMEM); 345 } 346 347 rcbp = &softs->rcb[1]; 348 for( i = 1; i <= softs->pqi_cap.max_outstanding_io; i++, rcbp++ ) { 349 if ((error = bus_dmamap_create(softs->os_specific.pqi_buffer_dmat, 0, &rcbp->cm_datamap)) != 0) { 350 DBG_ERR("Cant create datamap for buf @" 351 "rcbp = %p maxio = %d error = %d\n", 352 rcbp, softs->pqi_cap.max_outstanding_io, error); 353 goto dma_out; 354 } 355 } 356 357 os_start_heartbeat_timer((void *)softs); /* Start the heart-beat timer */ 358 callout_reset(&softs->os_specific.wellness_periodic, 120*hz, 359 os_wellness_periodic, softs); 360 /* Register our shutdown handler. */ 361 softs->os_specific.eh = EVENTHANDLER_REGISTER(shutdown_final, 362 smartpqi_shutdown, softs, SHUTDOWN_PRI_DEFAULT); 363 364 error = pqisrc_scan_devices(softs); 365 if (error) { 366 DBG_ERR("Failed to scan lib error = %d\n", error); 367 error = PQI_STATUS_FAILURE; 368 goto out; 369 } 370 371 error = register_sim(softs, card_index); 372 if (error) { 373 DBG_ERR("Failed to register sim index = %d error = %d\n", 374 card_index, error); 375 goto out; 376 } 377 378 smartpqi_target_rescan(softs); 379 380 TASK_INIT(&softs->os_specific.event_task, 0, pqisrc_event_worker,softs); 381 382 error = create_char_dev(softs, card_index); 383 if (error) { 384 DBG_ERR("Failed to register character device index=%d r=%d\n", 385 card_index, error); 386 goto out; 387 } 388 goto out; 389 390 dma_out: 391 if (softs->os_specific.pqi_regs_res0 != NULL) 392 bus_release_resource(softs->os_specific.pqi_dev, SYS_RES_MEMORY, 393 softs->os_specific.pqi_regs_rid0, 394 softs->os_specific.pqi_regs_res0); 395 out: 396 DBG_FUNC("OUT error = %d\n", error); 397 return(error); 398 } 399 400 /* 401 * Deallocate resources for our device. 402 */ 403 static int 404 smartpqi_detach(device_t dev) 405 { 406 struct pqisrc_softstate *softs = NULL; 407 softs = device_get_softc(dev); 408 DBG_FUNC("IN\n"); 409 410 EVENTHANDLER_DEREGISTER(shutdown_final, softs->os_specific.eh); 411 412 /* kill the periodic event */ 413 callout_drain(&softs->os_specific.wellness_periodic); 414 /* Kill the heart beat event */ 415 callout_drain(&softs->os_specific.heartbeat_timeout_id); 416 417 smartpqi_shutdown(softs); 418 destroy_char_dev(softs); 419 pqisrc_uninit(softs); 420 deregister_sim(softs); 421 pci_release_msi(dev); 422 423 DBG_FUNC("OUT\n"); 424 return 0; 425 } 426 427 /* 428 * Bring the controller to a quiescent state, ready for system suspend. 429 */ 430 static int 431 smartpqi_suspend(device_t dev) 432 { 433 struct pqisrc_softstate *softs; 434 softs = device_get_softc(dev); 435 DBG_FUNC("IN\n"); 436 437 DBG_INFO("Suspending the device %p\n", softs); 438 softs->os_specific.pqi_state |= SMART_STATE_SUSPEND; 439 440 DBG_FUNC("OUT\n"); 441 return(0); 442 } 443 444 /* 445 * Bring the controller back to a state ready for operation. 446 */ 447 static int 448 smartpqi_resume(device_t dev) 449 { 450 struct pqisrc_softstate *softs; 451 softs = device_get_softc(dev); 452 DBG_FUNC("IN\n"); 453 454 softs->os_specific.pqi_state &= ~SMART_STATE_SUSPEND; 455 456 DBG_FUNC("OUT\n"); 457 return(0); 458 } 459 460 /* 461 * Do whatever is needed during a system shutdown. 462 */ 463 int 464 smartpqi_shutdown(void *arg) 465 { 466 struct pqisrc_softstate *softs = NULL; 467 int rval = 0; 468 469 DBG_FUNC("IN\n"); 470 471 softs = (struct pqisrc_softstate *)arg; 472 473 rval = pqisrc_flush_cache(softs, PQISRC_SHUTDOWN); 474 if (rval != PQI_STATUS_SUCCESS) { 475 DBG_ERR("Unable to flush adapter cache! rval = %d", rval); 476 } 477 478 DBG_FUNC("OUT\n"); 479 480 return rval; 481 } 482 483 /* 484 * PCI bus interface. 485 */ 486 static device_method_t pqi_methods[] = { 487 /* Device interface */ 488 DEVMETHOD(device_probe, smartpqi_probe), 489 DEVMETHOD(device_attach, smartpqi_attach), 490 DEVMETHOD(device_detach, smartpqi_detach), 491 DEVMETHOD(device_suspend, smartpqi_suspend), 492 DEVMETHOD(device_resume, smartpqi_resume), 493 { 0, 0 } 494 }; 495 496 static devclass_t pqi_devclass; 497 static driver_t smartpqi_pci_driver = { 498 "smartpqi", 499 pqi_methods, 500 sizeof(struct pqisrc_softstate) 501 }; 502 503 DRIVER_MODULE(smartpqi, pci, smartpqi_pci_driver, pqi_devclass, 0, 0); 504 MODULE_DEPEND(smartpqi, pci, 1, 1, 1); 505